diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005290.v b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005290.v index 580a57c..1191a78 100644 --- a/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005290.v +++ b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005290.v @@ -34,7 +34,7 @@ module K005290 /////////////////////////////////////////////////////////// -////// PIXEL DATA LATCH +////// TILELINE LATCH //// // @@ -64,7 +64,7 @@ wire pixel7_n = ~(i_ABS_2H & ABS_2H_dl & ~i_ABS_n4H); // -// pixel latches +// tileline latches // /* @@ -73,8 +73,8 @@ wire pixel7_n = ~(i_ABS_2H & ABS_2H_dl & ~i_ABS_n4H); DRAM A B C D E F G H */ -reg [31:0] A_LINELATCH; -reg [31:0] B_LINELATCH; +reg [31:0] A_TILELINELATCH; +reg [31:0] B_TILELINELATCH; always @(posedge i_EMU_MCLK) begin @@ -82,7 +82,7 @@ begin begin if(!pixel7_n) //posedge of px7 begin - A_LINELATCH <= i_GFXDATA; + A_TILELINELATCH <= i_GFXDATA; end end end @@ -93,7 +93,7 @@ begin begin if(!pixel3_n) //posedge of px3 begin - B_LINELATCH <= i_GFXDATA; + B_TILELINELATCH <= i_GFXDATA; end end end @@ -162,14 +162,14 @@ begin A_PIXEL7 <= 4'h0; end 2'b11: begin - A_PIXEL0 <= A_LINELATCH[31:28]; - A_PIXEL1 <= A_LINELATCH[27:24]; - A_PIXEL2 <= A_LINELATCH[23:20]; - A_PIXEL3 <= A_LINELATCH[19:16]; - A_PIXEL4 <= A_LINELATCH[15:12]; - A_PIXEL5 <= A_LINELATCH[11:8]; - A_PIXEL6 <= A_LINELATCH[7:4]; - A_PIXEL7 <= A_LINELATCH[3:0]; + A_PIXEL0 <= A_TILELINELATCH[31:28]; + A_PIXEL1 <= A_TILELINELATCH[27:24]; + A_PIXEL2 <= A_TILELINELATCH[23:20]; + A_PIXEL3 <= A_TILELINELATCH[19:16]; + A_PIXEL4 <= A_TILELINELATCH[15:12]; + A_PIXEL5 <= A_TILELINELATCH[11:8]; + A_PIXEL6 <= A_TILELINELATCH[7:4]; + A_PIXEL7 <= A_TILELINELATCH[3:0]; end endcase end @@ -238,14 +238,14 @@ begin B_PIXEL7 <= 4'h0; end 2'b11: begin - B_PIXEL0 <= B_LINELATCH[31:28]; - B_PIXEL1 <= B_LINELATCH[27:24]; - B_PIXEL2 <= B_LINELATCH[23:20]; - B_PIXEL3 <= B_LINELATCH[19:16]; - B_PIXEL4 <= B_LINELATCH[15:12]; - B_PIXEL5 <= B_LINELATCH[11:8]; - B_PIXEL6 <= B_LINELATCH[7:4]; - B_PIXEL7 <= B_LINELATCH[3:0]; + B_PIXEL0 <= B_TILELINELATCH[31:28]; + B_PIXEL1 <= B_TILELINELATCH[27:24]; + B_PIXEL2 <= B_TILELINELATCH[23:20]; + B_PIXEL3 <= B_TILELINELATCH[19:16]; + B_PIXEL4 <= B_TILELINELATCH[15:12]; + B_PIXEL5 <= B_TILELINELATCH[11:8]; + B_PIXEL6 <= B_TILELINELATCH[7:4]; + B_PIXEL7 <= B_TILELINELATCH[3:0]; end endcase end diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005292.v b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005292.v index c5c77c5..816fe9c 100644 --- a/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005292.v +++ b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005292.v @@ -53,12 +53,12 @@ module K005292 output wire o_FLIP_2V, output wire o_FLIP_1V, - output reg o_VCLK = 1'b0, + output reg o_VCLK, output reg o_FRAMEPARITY = 1'b0, output wire o_VSYNC_n, - output wire o_CSYNC_n, + output reg o_CSYNC, output wire [8:0] __REF_HCOUNTER, output wire [8:0] __REF_VCOUNTER @@ -119,84 +119,26 @@ assign { o_FLIP_1V } = vertical_counter[7:0] ^ {8{i_VFLIP}}; -always @(posedge i_EMU_MCLK or negedge i_MRST_n) + +// +// HCOUNTER +// + +always @(posedge i_EMU_MCLK) begin if(!i_MRST_n) //asynchronous reset begin horizontal_counter <= 9'd128; - vertical_counter <= 9'd248; - - o_VBLANK_n <= 1'b0; - o_VBLANKH_n <= 1'b0; - o_FRAMEPARITY <= 1'b0; - __REF_DMA_n <= 1'b1; end else - begin //count up + begin if(!i_EMU_CLK6MPCEN_n) begin if(horizontal_counter < 9'd511) //h count up begin - if(horizontal_counter == 9'd175) //v count up - begin - if(vertical_counter < 9'd511) - begin - //VBLANK - if(vertical_counter > 9'd494 || vertical_counter < 9'd271) - begin - o_VBLANK_n <= 1'b0; - end - else - begin - o_VBLANK_n <= 1'b1; - end - - //VBLANK** - if(vertical_counter > 9'd247 && vertical_counter < 9'd271) - begin - o_VBLANKH_n <= 1'b0; - end - else - begin - o_VBLANKH_n <= 1'b1; - end - - //256V - if(vertical_counter == 9'd495) //flip parity value - begin - o_FRAMEPARITY <= ~o_FRAMEPARITY; - end - - //DMA - if(vertical_counter > 9'd478 && vertical_counter < 9'd495) - begin - __REF_DMA_n <= 1'b0; - end - else - begin - __REF_DMA_n <= 1'b1; - end - - vertical_counter <= vertical_counter + 9'd1; - end - else - begin - vertical_counter <= 9'd248; - end - end - - if(horizontal_counter > 9'd174 && horizontal_counter < 9'd207) - begin - o_VCLK <= 1'b1; - end - else - begin - o_VCLK <= 1'b0; - end - horizontal_counter <= horizontal_counter + 9'd1; end - else //h loop + else //h loop begin horizontal_counter <= 9'd128; end @@ -205,12 +147,262 @@ begin end +// +// SYNC TIP GENERATOR +// + +reg narrow_hsync_on_vsync = 1'b0; //appears on just before vsync period of even frame +reg wide_hsync_on_vsync = 1'b0; //appears on vsync period +reg hsync = 1'b0; //normal vclk + +reg narrow_hsync_on_vsync_clken_n = 1'b1; +reg hsync_clken_n = 1'b1; + +always @(posedge i_EMU_MCLK) +begin + if(!i_MRST_n) //asynchronous reset + begin + narrow_hsync_on_vsync <= 1'b0; + wide_hsync_on_vsync <= 1'b0; + hsync <= 1'b0; + end + else + begin + if(!i_EMU_CLK6MPCEN_n) + begin + //narrow hsync on vsync + if(horizontal_counter == 9'd175) + begin + narrow_hsync_on_vsync <= 1'b1; + end + else if(horizontal_counter == 9'd191) + begin + narrow_hsync_on_vsync <= 1'b0; + end + + else if(horizontal_counter == 9'd367) + begin + narrow_hsync_on_vsync <= 1'b1; + end + else if(horizontal_counter == 9'd383) + begin + narrow_hsync_on_vsync <= 1'b0; + end + + else + begin + narrow_hsync_on_vsync <= narrow_hsync_on_vsync; + end + + + //wide hysnc on vsync + if(horizontal_counter == 9'd143) + begin + wide_hsync_on_vsync <= 1'b1; + end + else if(horizontal_counter == 9'd175) + begin + wide_hsync_on_vsync <= 1'b0; + end + + else if(horizontal_counter == 9'd335) + begin + wide_hsync_on_vsync <= 1'b1; + end + else if(horizontal_counter == 9'd367) + begin + wide_hsync_on_vsync <= 1'b0; + end + + else + begin + wide_hsync_on_vsync <= wide_hsync_on_vsync; + end + + + //hysnc + if(horizontal_counter == 9'd175) + begin + hsync <= 1'b1; + end + else if(horizontal_counter == 9'd207) + begin + hsync <= 1'b0; + end + + else + begin + hsync <= hsync; + end + + + + //narrow hsync on vsync clken + if(horizontal_counter == 9'd366) + begin + narrow_hsync_on_vsync_clken_n <= 1'b0; + end + else + begin + narrow_hsync_on_vsync_clken_n <= 1'b1; + end + + //hsync clken + if(horizontal_counter == 9'd174) + begin + hsync_clken_n <= 1'b0; + end + else + begin + hsync_clken_n <= 1'b1; + end + end + end +end + + +// +// VCLK GENERATOR +// + +//VCLK output +always @(*) +begin + if(o_FRAMEPARITY == 1'b0) //EVEN FRAME + begin + if(vertical_counter > 9'd503 || vertical_counter < 9'd266) + begin + o_VCLK <= narrow_hsync_on_vsync & o_HBLANK_n; + end + else + begin + o_VCLK <= hsync; + end + end + else //ODD FRAME + begin + o_VCLK <= hsync; + end +end + + +//VCLK clken +reg vclk_clken_n; + +always @(*) +begin + if(o_FRAMEPARITY == 1'b0) //EVEN FRAME + begin + if(vertical_counter > 9'd502 || vertical_counter < 9'd265) //not 503 and 266!! clken should be asserted before a posedge of VCLK, so it have to go 1V faster + begin + vclk_clken_n <= narrow_hsync_on_vsync_clken_n; + end + else + begin + vclk_clken_n <= hsync_clken_n; + end + end + else //ODD FRAME + begin + vclk_clken_n <= hsync_clken_n; + end +end + + +// +// VCOUNTER +// + +always @(posedge i_EMU_MCLK) //do not use asynchronous VCLK +begin + if(!i_MRST_n) //asynchronous reset + begin + vertical_counter <= 9'd248; + end + else + begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!vclk_clken_n) + begin + if(vertical_counter < 9'd511) + begin + //VBLANK + if(vertical_counter > 9'd494 || vertical_counter < 9'd271) + begin + o_VBLANK_n <= 1'b0; + end + else + begin + o_VBLANK_n <= 1'b1; + end + + //VBLANK** + if(vertical_counter > 9'd494 || vertical_counter < 9'd271) + begin + o_VBLANKH_n <= 1'b0; + end + else + begin + o_VBLANKH_n <= 1'b1; //VBLANK** goes high when vcounter = 248 + end + + //256V + if(vertical_counter == 9'd495) //flip parity value + begin + o_FRAMEPARITY <= ~o_FRAMEPARITY; + end + + //DMA + if(vertical_counter > 9'd478 && vertical_counter < 9'd495) + begin + __REF_DMA_n <= 1'b0; + end + else + begin + __REF_DMA_n <= 1'b1; + end + + vertical_counter <= vertical_counter + 9'd1; + end + else + begin + vertical_counter <= 9'd248; + + o_VBLANKH_n <= 1'b1; + end + end + end + end +end + + + /////////////////////////////////////////////////////////// ////// SYNC GENERATOR //// assign o_VSYNC_n = vertical_counter[8]; -assign o_CSYNC_n = o_VSYNC_n & ~o_VCLK; + +always @(*) +begin + if(vertical_counter > 9'd503 || vertical_counter < 9'd266) + begin + if(vertical_counter > 9'd247 && vertical_counter < 9'd256) + begin + o_CSYNC <= o_VSYNC_n ^ wide_hsync_on_vsync; + end + else + begin + o_CSYNC <= o_VSYNC_n ^ narrow_hsync_on_vsync; + end + end + else + begin + o_CSYNC <= o_VSYNC_n ^ hsync; + end +end + endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005294.v b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005294.v new file mode 100644 index 0000000..558d628 --- /dev/null +++ b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005294.v @@ -0,0 +1,202 @@ +/* + K005294 "LINELATCH" +*/ + +module K005294 +( + input wire i_EMU_MCLK, + input wire i_EMU_CLK6MPCEN_n, + + input wire [31:0] i_GFXDATA, + input wire [3:0] i_OC, + + input wire i_TILELINELATCH_n, + + output reg [7:0] o_DA, + output reg [7:0] o_DB, + + //005294 control signals + input wire i_WRTIME2, + input wire i_COLORLATCH_n, + input wire i_XPOS_D0, + input wire i_PIXELLATCH_WAIT_n, + input wire i_LATCH_A_D2, + input wire [2:0] i_PIXELSEL +); + + + +/////////////////////////////////////////////////////////// +////// COLORLATCH +//// + +//latches pixel palette data from VRAM +reg [3:0] OBJ_PALETTE; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!i_COLORLATCH_n) + begin + OBJ_PALETTE <= i_OC; + end + end +end + + + + + + + + +/////////////////////////////////////////////////////////// +////// TILELINE LATCH +//// + +reg [31:0] OBJ_TILELINELATCH; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!i_TILELINELATCH_n) //posedge of px7 + begin + OBJ_TILELINELATCH <= i_GFXDATA; + end + end +end + + + + + + + + +/////////////////////////////////////////////////////////// +////// PIXEL SELECT / PIXELLATCH_WAIT / WRTIME2 DELAY +//// + +/* + It's probably intended to delay DRAM writing until a + new tile is copied from CHARRAM. + + What a Konami style mess!! + 005295(internally) -> 005294(internally) total delay + PIXELSEL 0clk dly 4clk dly = 4clk delay + WRTIME2 2clk dly 2clk dly = 4clk delay + PIXELLATCH_WAIT_n 1clk dly 3clk dly = 4clk delay +*/ + +reg [2:0] pixelsel_dly [3:0]; +reg [1:0] wrtime2_dly; +reg [3:0] pixellatch_wait_dly; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + pixelsel_dly[0] <= i_PIXELSEL; + pixelsel_dly[1] <= pixelsel_dly[0]; + pixelsel_dly[2] <= pixelsel_dly[1]; + pixelsel_dly[3] <= pixelsel_dly[2]; + end +end + + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + wrtime2_dly[0] <= i_WRTIME2; + wrtime2_dly[1] <= wrtime2_dly[0]; + end +end + + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + pixellatch_wait_dly[0] <= ~i_PIXELLATCH_WAIT_n; + pixellatch_wait_dly[1] <= pixellatch_wait_dly[0]; + pixellatch_wait_dly[2] <= pixellatch_wait_dly[1]; + pixellatch_wait_dly[3] <= pixellatch_wait_dly[2]; + end +end + + + + + + + + +/////////////////////////////////////////////////////////// +////// PIXEL SELECTOR AND PIXEL LATCH +//// + +wire pixellatch_n = wrtime2_dly[1] | pixellatch_wait_dly[2]; +reg [3:0] OBJ_PIXEL_LATCHED; +reg [3:0] OBJ_PIXEL_UNLATCHED; + +always @(*) +begin + case(pixelsel_dly[3]) + 3'b000: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[31:28]; //pixel 0(A) + 3'b001: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[27:24]; //pixel 1(B) + 3'b010: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[23:20]; + 3'b011: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[19:16]; + 3'b100: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[15:12]; + 3'b101: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[11:8]; + 3'b110: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[7:4]; + 3'b111: OBJ_PIXEL_UNLATCHED <= OBJ_TILELINELATCH[3:0]; + endcase +end + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!pixellatch_n) + begin + OBJ_PIXEL_LATCHED <= OBJ_PIXEL_UNLATCHED; + end + end +end + + + + + + + +/////////////////////////////////////////////////////////// +////// DOUT MUX +//// + +always @(*) +begin + case({pixellatch_wait_dly[2], i_XPOS_D0}) + 2'b00: begin + o_DA <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED}; + o_DB <= {OBJ_PALETTE, OBJ_PIXEL_UNLATCHED}; + end + 2'b01: begin + o_DA <= {OBJ_PALETTE, OBJ_PIXEL_UNLATCHED}; + o_DB <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED}; + end + 2'b10: begin + o_DA <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED}; + o_DB <= {4'b0000, 4'b0000}; + end + 2'b11: begin + o_DA <= {4'b0000, 4'b0000}; + o_DB <= {OBJ_PALETTE, OBJ_PIXEL_LATCHED}; + end + endcase +end + +endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005295.v b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005295.v new file mode 100644 index 0000000..f72e946 --- /dev/null +++ b/BubSysROM_core_ModelSim/BubSysROM_component/asic/K005295.v @@ -0,0 +1,1787 @@ +/* + K005295 SPRITE ENGINE +*/ + +/* + GX400 SPRITES + + Konami GX400 hardware(developed in 1984, released in March 1985) is + equipped with a nice sprite engine. This engine can draw 8 sizes of + sprites: + 32*32, 16*32, 32*16, 64*64, 8*8, 16*8, 8*16, 16*16 + by enabling double height mode(LATCH_A bit 1), it can draw some + additional sizes: + 32*64, 16*64, 64*128, 8*32 + + All sprite data is stored in CHARRAM. 4bpp, big endian. For example, + think about 16*8 sprite. That can be expressed just like this: + + + |----------- HLINE -----------| + |---TILELINE---|---TILELINE---| + O O O O o o o o A A A A a a a a --- + O O O O o o o o A A A A a a a a | + O O O O o o o o A A A A a a a a | + O O O O o o o o A A A A a a a a VTILE + O O O O o o o o A A A A a a a a | + O O O O o o o o A A A A a a a a | + O O O O o o o o A A A A a a a a | + O O O O o o o o A A A A a a a a --- + + Sprite engine can fetch 8 pixels of sprite data from CHARRAM at + a single time. 4bpp*8 = 32bits. I will call this "TILELINE." + + This sprite is 16*8, so there are two TILELINEs in one "HLINE" + To draw ONE HLINE, TWO TILELINEs are needed to be fetched. + + Again, eight HLINEs are needed to complete this 16*8 sprite. + I will call this eight HLINEs, "VTILE". Width doesn't matter. + + Please remember these three terms, TILELINE, HLINE, VTILE. I + use these terms in variable names. +*/ + +module K005295 +#( + parameter __ENABLE_DOUBLE_HEIGHT_MODE = 1'b0, + parameter __SAVE_FRAMEBUFFER_CAPACITY = 1'b1 +) +( + //emulator + input wire i_EMU_MCLK, + input wire i_EMU_CLK6MPCEN_n, + + //timings + input wire i_DMA_n, + input wire i_VBLANKH_n, + input wire i_VBLANK_n, + input wire i_HBLANK_n, + input wire i_ABS_4H, + input wire i_ABS_2H, + input wire i_ABS_1H, + input wire i_CHAMPX, + input wire i_OBJWR, + + //flip + input wire i_FLIP, + + //clocked shift + input wire [7:0] i_OBJDATA, + output wire [2:0] o_ORA, + + //framebuffer CAS + output wire o_CAS, + + //framebuffer + output wire [7:0] o_FA, //ODD BUFFER + output wire [7:0] o_FB, //EVEN BUFFER + + output reg o_XA7, + output reg o_XB7, + + //peripheral control signals + input wire i_OBJHL, + output reg o_CHAOV, + output wire o_ORINC, + + //005294 control signals + output reg o_WRTIME2, + output wire o_COLORLATCH_n, + output wire o_XPOS_D0, + output reg o_PIXELLATCH_WAIT_n, + output wire o_LATCH_A_D2, + output wire [2:0] o_PIXELSEL, + + //CHARRAM address + output wire [7:0] o_OCA +); + + + +/////////////////////////////////////////////////////////// +////// GLOBAL SIGNALS +//// + +reg hsize_parity = 1'b0; +reg pixellatch_wait_n; + + + + + + +/////////////////////////////////////////////////////////// +////// PIXEL3 +//// + +/* + pixel3_n is very important. The most of branches of FSM are occurs + on Pixel 3. +*/ + +wire pixel3_n = ~(i_ABS_1H & i_ABS_2H); + + + + + + +/////////////////////////////////////////////////////////// +////// 4H clocked DMA_n +//// + +/* + Sampling DMA_n at every rising edge of 4H allows FSM to know + the start of a new VBLANK. If the value of sampled DMA_n is 1 + and VBLANK or VBLANKH is 0, it is the beginning of a new VBLANK. +*/ + +reg DMA_4H_CLKD_n = 1'b1; +wire new_vblank_n = DMA_4H_CLKD_n | i_VBLANKH_n; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if({i_ABS_4H, i_ABS_2H, i_ABS_1H} == 3'd3) + begin + DMA_4H_CLKD_n <= i_DMA_n; + end + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// ORA/register enable generation +//// + +//latch enable signal +wire LATCH_A_en_n; //OBJRAM BYTE 2: zoom MSBs[7:6], size[5:3], unknown size bits[2:1], hflip[0] +wire LATCH_B_en_n; //OBJRAM BYTE 4: zoom LSBs[7:0] +wire LATCH_C_en_n; //OBJRAM BYTE 6: sprite code LSBs[7:0] +wire LATCH_D_en_n; //OBJRAM BYTE 8: sprite code MSBs[7:6], vflip[5], obj palette[4:1], xpos MSB[0] +wire LATCH_E_en_n; //OBJRAM BYTE A: xpos LSBs[7:0] +wire LATCH_F_en_n; //OBJRAM BYTE C: ypos[7:0] + +assign o_COLORLATCH_n = LATCH_D_en_n; + +//if /A ORA = 2, if /B ORA = 3, ... ,if /F, ORA = 7 +//MUDA MUDA MUDA MUDA MUDA MUDA +//ORA ORA ORA ORA ORA ORA ORA +assign o_ORA[2] = ~&{ LATCH_C_en_n, LATCH_D_en_n, LATCH_E_en_n, LATCH_F_en_n}; +assign o_ORA[1] = ~&{LATCH_A_en_n, LATCH_B_en_n, LATCH_E_en_n, LATCH_F_en_n}; +assign o_ORA[0] = ~&{ LATCH_B_en_n, LATCH_D_en_n, LATCH_F_en_n}; + +//latch enable shift register +reg latching_start; +reg [6:0] attr_latch_en_sr; +assign {LATCH_A_en_n, LATCH_B_en_n, LATCH_C_en_n, + LATCH_D_en_n, LATCH_E_en_n, LATCH_F_en_n, o_ORINC} = attr_latch_en_sr; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(i_ABS_1H == 1'b0) + begin + attr_latch_en_sr[6] <= ~latching_start; + attr_latch_en_sr[5:0] <= attr_latch_en_sr[6:1]; + end + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// SPRITE ATTRIBUTE LATCHES +//// + +//LATCH_F is not shown here since ypos data is directly loaded into ypos counter +reg [7:0] LATCH_A; //OBJRAM BYTE 2: zoom MSBs[7:6], size[5:3], unknown size bits[2:1], hflip[0] +reg [7:0] LATCH_B; //OBJRAM BYTE 4: zoom LSBs[7:0] +reg [7:0] LATCH_C; //OBJRAM BYTE 6: sprite code LSBs[7:0] +reg [7:0] LATCH_D; //OBJRAM BYTE 8: sprite code MSBs[7:6], vflip[5], obj palette[4:1], xpos MSB[0] +reg [7:0] LATCH_E; //OBJRAM BYTE A: xpos LSBs[7:0] + +assign o_XPOS_D0 = LATCH_E[0]; +assign o_LATCH_A_D2 = LATCH_A[2]; + +//LATCH_A +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!LATCH_A_en_n) + begin + LATCH_A <= i_OBJDATA & {6'b1111_11, __ENABLE_DOUBLE_HEIGHT_MODE, 1'b1}; + end + + if(!LATCH_B_en_n) + begin + LATCH_B <= i_OBJDATA; + end + + if(!LATCH_C_en_n) + begin + LATCH_C <= i_OBJDATA; + end + + if(!LATCH_D_en_n) + begin + LATCH_D <= i_OBJDATA; + end + + if(!LATCH_E_en_n) + begin + LATCH_E <= i_OBJDATA; + end + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// HZOOM FEEDBACK ACCUMULATOR +//// + +/* + FEEDBACK LOOP[9:0] + ┌────────────────────────┐ + │ │ + │ ┌─────┐ ┌─────┐ │ + │ │ A │CLK─►│ D │ │ + └─► │ D │RST─►│ F │ │ + │ D │ │ F │ │ + │ E ├(+)─►│ ├──┴──► FEEDBACK_LOOP[9:7] = PIXELSEL[2:0] + ZOOM FACTOR ──────► │ R │ │ │ + │ │ │ │ + └──┬──┘ └─────┘ + │ CARRY + │ ┌─────┐ + │ CLK─►│ LS │ + | RST─►│ 163 ├─────► TILELINE_ADDR[2:0] + └───────►│ │ + ENP/ENT └─────┘ +*/ + +reg hzoom_cnt_n; +reg hzoom_rst_n; +reg [9:0] hzoom_acc = 10'd0; +wire [10:0] hzoom_nextval = hzoom_acc + {LATCH_A[7:6], LATCH_B}; +reg [2:0] hzoom_tileline_cntr; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!hzoom_rst_n) + begin + hzoom_acc <= 10'd0; + hzoom_tileline_cntr <= 3'd0; + end + else + begin + if(!hzoom_cnt_n) + begin + hzoom_acc <= hzoom_nextval[9:0]; + if(hzoom_nextval[10] == 1'b1) + begin + hzoom_tileline_cntr <= hzoom_tileline_cntr + 3'd1; + end + end + end + end +end + + + +/////////////////////////////////////////////////////////// +////// TILELINE/HLINE COMPLETE FLAG +//// + +/* + "tileline complete" flag is the carry output of hzoom feedback + accumulator. It notifies the end of the current tileline(8 pixels) + + "hline complete" flag notifies the end of current hline. The multiplexer + selects proper complete flag according to the width of the current + sprite. +*/ + +reg hline_complete; +wire tileline0_complete = hzoom_nextval[10]; +wire tileline1_complete = &{hzoom_nextval[10], hzoom_tileline_cntr[0]}; +wire tileline3_complete = &{hzoom_nextval[10], hzoom_tileline_cntr[0], hzoom_tileline_cntr[1]}; +wire tileline7_complete = &{hzoom_nextval[10], hzoom_tileline_cntr[0], hzoom_tileline_cntr[1], hzoom_tileline_cntr[2]}; + +always @(*) +begin + case({LATCH_A[5:3]}) + 4'h0: hline_complete <= tileline3_complete; //32*32 4 horizontal tileline + 4'h1: hline_complete <= tileline1_complete; //16*32 2 horizontal tileline + 4'h2: hline_complete <= tileline3_complete; //32*16 4 horizontal tileline + 4'h3: hline_complete <= tileline7_complete; //64*64 8 horizontal tileline + 4'h4: hline_complete <= tileline0_complete; //8*8 1 horizontal tileline + 4'h5: hline_complete <= tileline1_complete; //16*8 2 horizontal tileline + 4'h6: hline_complete <= tileline0_complete; //8*16 1 horizontal tileline + 4'h7: hline_complete <= tileline1_complete; //16*16 2 horizontal tileline + endcase +end + + + + + +/////////////////////////////////////////////////////////// +////// VZOOM FEEDBACK ACCUMULATOR +//// + +/* + FEEDBACK LOOP[9:0] + ┌────────────────────────┐ + │ │ + │ ┌─────┐ ┌─────┐ │ + │ │ A │CLK─►│ D │ │ + └─► │ D │RST─►│ F │ │ + │ D │ │ F │ │ + │ E ├(+)─►│ ├──┴──► FEEDBACK_LOOP[9:7] = HLINE_ADDR[2:0] + ZOOM FACTOR ──────► │ R │ │ │ + │ │ │ │ + └──┬──┘ └─────┘ + │ CARRY + │ ┌─────┐ + │ CLK─►│ LS │ + | RST─►│ 163 ├─────► VTILE_ADDR[3:0] + └───────►│ │ + ENP/ENT └─────┘ +*/ + +reg vzoom_cnt_n; +reg vzoom_rst_n; +reg [9:0] vzoom_acc = 10'd0; +wire [10:0] vzoom_nextval = vzoom_acc + {LATCH_A[7:6], LATCH_B}; +reg [3:0] vzoom_vtile_cntr; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(!vzoom_rst_n) + begin + vzoom_acc <= 10'd0; + vzoom_vtile_cntr <= 4'd0; + end + else + begin + if(!vzoom_cnt_n) + begin + vzoom_acc <= vzoom_nextval[9:0]; + if(vzoom_nextval[10] == 1'b1) + begin + vzoom_vtile_cntr <= vzoom_vtile_cntr + 4'd1; + end + end + end + end +end + + + + + +/////////////////////////////////////////////////////////// +////// DRAWING COMPLETE FLAG +//// + +/* + "vtile_complete" notifies the last hline of the sprite. It is ANDed with + the carry output of the vzoom feedback accumulator, so the flag only + appears on the drawing cycle of the last hline. Stops sprite drawing + after vtile_complete + hline_complete were asserted. +*/ + +reg vtile_complete_n; +wire vtile0_complete_n = ~vzoom_nextval[10]; +wire vtile1_complete_n = ~&{vzoom_nextval[10], vzoom_vtile_cntr[0]}; +wire vtile3_complete_n = ~&{vzoom_nextval[10], vzoom_vtile_cntr[0], vzoom_vtile_cntr[1]}; +wire vtile7_complete_n = ~&{vzoom_nextval[10], vzoom_vtile_cntr[0], vzoom_vtile_cntr[1], vzoom_vtile_cntr[2]}; +wire vtile15_complete_n = ~&{vzoom_nextval[10], vzoom_vtile_cntr[0], vzoom_vtile_cntr[1], vzoom_vtile_cntr[2], vzoom_vtile_cntr[3]}; + +always @(*) +begin + case({LATCH_A[1], LATCH_A[5:3]}) + 4'h0: vtile_complete_n <= vtile3_complete_n; //32*32 4 vetrical tiles + 4'h1: vtile_complete_n <= vtile3_complete_n; //16*32 4 vetrical tiles + 4'h2: vtile_complete_n <= vtile1_complete_n; //32*16 2 vetrical tiles + 4'h3: vtile_complete_n <= vtile7_complete_n; //64*64 8 vetrical tiles + 4'h4: vtile_complete_n <= vtile0_complete_n; //8*8 1 vetrical tiles + 4'h5: vtile_complete_n <= vtile0_complete_n; //16*8 1 vetrical tiles + 4'h6: vtile_complete_n <= vtile1_complete_n; //8*16 2 vetrical tiles + 4'h7: vtile_complete_n <= vtile1_complete_n; //16*16 2 vetrical tiles + 4'h8: vtile_complete_n <= vtile7_complete_n; //32*64 8 vetrical tiles + 4'h9: vtile_complete_n <= vtile7_complete_n; //16*64 8 vetrical tiles + 4'hA: vtile_complete_n <= vtile3_complete_n; //32*32 4 vetrical tiles + 4'hB: vtile_complete_n <= vtile15_complete_n; //64*128 16 vetrical tiles + 4'hC: vtile_complete_n <= vtile1_complete_n; //8*16 2 vetrical tiles + 4'hD: vtile_complete_n <= vtile1_complete_n; //16*32 2 vetrical tiles + 4'hE: vtile_complete_n <= vtile3_complete_n; //8*32 4 vetrical tiles + 4'hF: vtile_complete_n <= vtile3_complete_n; //16*32 4 vetrical tiles + endcase +end + + + + + + +/////////////////////////////////////////////////////////// +////// FRAMEBUFFER XYPOS COUNTER +//// + +//countup signal delay registers +reg [1:0] xpos_cnt_dly_n; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + xpos_cnt_dly_n[0] <= ~o_WRTIME2; + xpos_cnt_dly_n[1] <= xpos_cnt_dly_n[0]; + end +end + +reg ypos_cnt_n; +reg [3:0] ypos_cnt_dly_n; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + ypos_cnt_dly_n[0] <= ypos_cnt_n; + ypos_cnt_dly_n[3:1] <= ypos_cnt_dly_n[2:0]; + end +end + + +//xpos counter +reg [7:0] evenbuffer_xpos_counter; +reg [7:0] oddbuffer_xpos_counter; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(LATCH_F_en_n == 1'b0) //2clk delay AND LATCH_F_en_n -> preload data before sprite drawing + begin + evenbuffer_xpos_counter <= {LATCH_D[0], LATCH_E[7:1]} + LATCH_E[0]; + oddbuffer_xpos_counter <= {LATCH_D[0], LATCH_E[7:1]}; + end + else if(ypos_cnt_dly_n[3] == 1'b0) + begin + evenbuffer_xpos_counter <= {LATCH_D[0], LATCH_E[7:1]} + LATCH_E[0]; + oddbuffer_xpos_counter <= {LATCH_D[0], LATCH_E[7:1]}; + end + else + begin + if(xpos_cnt_dly_n[1] == 1'b0) + begin + evenbuffer_xpos_counter <= evenbuffer_xpos_counter + 8'd1; + oddbuffer_xpos_counter <= oddbuffer_xpos_counter + 8'd1; + end + end + end +end + + +//ypos counter +reg [7:0] buffer_ypos_counter; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(LATCH_F_en_n == 1'b0) + begin + buffer_ypos_counter <= i_OBJDATA; + end + else + begin + if(ypos_cnt_dly_n[3] == 1'b0) + begin + buffer_ypos_counter <= buffer_ypos_counter + 8'd1; + end + end + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// DRAWING STATUS FLAGS +//// + +wire x_out_of_screen = ~(~oddbuffer_xpos_counter[7] | oddbuffer_xpos_counter[6]); //0-255 or 384-511 +wire y_out_of_screen = (buffer_ypos_counter == 8'd255) ? 1'b1 : 1'b0; + +wire end_of_tileline = tileline0_complete | x_out_of_screen; +wire end_of_hline = hline_complete | x_out_of_screen; +//wire end_of_last_hline_n = ~(~(vtile_complete_n | vzoom_cnt_n) | y_out_of_screen); +wire end_of_last_hline_n = ~(~(vtile_complete_n) | y_out_of_screen); + + + + + + + +/////////////////////////////////////////////////////////// +////// SPRITE ENGINE MegaPAL +//// + +// DIRECT REPLACEMENT OF MegaPAL IMPLEMENTATION + +/* + [Comb] STATUS FLAGS +*/ + +wire [2:0] drawing_status = {end_of_last_hline_n, end_of_hline, end_of_tileline}; + +localparam KEEP_DRAWING = 3'b100; +localparam END_OF_TILELINE = 2'b01; //3'bX01 will not work +localparam END_OF_HLINE = 3'b111; +localparam END_OF_SPRITE = 3'b011; + + + +/* + [4H CLK] FSM SUSPEND AND RESUME +*/ + +reg [1:0] FSM_SUSPEND_DLY; +wire FSM_SUSPEND = ((i_HBLANK_n & i_VBLANKH_n) | FSM_SUSPEND_DLY[1]) | ~DMA_4H_CLKD_n; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if({i_ABS_4H, i_ABS_2H, i_ABS_1H} == 3'd3) + begin + FSM_SUSPEND_DLY[0] <= (i_HBLANK_n & i_VBLANKH_n); + FSM_SUSPEND_DLY[1] <= FSM_SUSPEND_DLY[0]; + end + end +end + + + +/* + [6M CLK] CHA O/V +*/ + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(pixel3_n == 1'b0) + begin + o_CHAOV <= FSM_SUSPEND; + end + end +end + + + +/* + [4H CLK] FOR ATTRIBUTE FETCHING END DETECTION +*/ + +reg LATCH_F_2H_NCLKD_en_n = 1'b1; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(pixel3_n == 1'b0) + begin + LATCH_F_2H_NCLKD_en_n <= LATCH_F_en_n; + end + end +end + + + +/* + [6M CLK] HSIZE PARITY +*/ + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(hzoom_rst_n == 1'b0) //preload, new hline + begin + hsize_parity <= 1'b1; + end + else + begin + if(hzoom_cnt_n == 1'b0) + begin + hsize_parity <= ~hsize_parity; + end + end + end +end + + + +/* + [6M CLK] FINITE STATE MACHINE +*/ + +/* + ATTR_LATCHING_S0: + Put 1 in latching_start for 1 pixel. After that, sprite attributes are latched + sequentially while 1H clocked shift register shifting 0(inverted input) + + ATTR_LATCHING_S1: + FSM does nothing while 1H clocked sr working for 14 pixels. FSM jumps to + HCOUNT_S0 if ORed signal of LATCH_F_2H_NCLKD_en_n(sampled at a rising edge of + 4H) and pixel3_n is 0. Reset HV accumulator at this time. + + HCOUNT_S0: + hcounter_en_n becomes 0 during HCOUNT_S0. If H accumulator's carry is enabled, + FSM controls hcounter_en_n according to the hsize_parity(this is important) + if hsize at the point is odd(=1), put 0 in pixellatch_wait_n(stop K005294 to + latch a pixel). In contrast, if hsize at the point is even(=0), put 1 in + pixellatch_wait_n + + HWAIT_S0: + Current tileline data is always latched at a rising edge (pixel3_n = 0) of + the 2H, so if the tileline drawing is finished before that, insert HWAIT_S0 + cycle to wait for the next data. At a rising edge of 2H, the FSM can branch to: + HCOUNT_S0(hline not completed) + ODDSIZE_S0(current hline is ended with an =odd numbered size 7, 9, 11...) + SUSPEND_S0(active video period) + + ODDSIZE_S0: + If the previous state was HCOUNT_S0 or HWAIT_S0, and if it satisfies the + condition that hsize is odd, FSM goes ODDSIZE_S0 to end current hline drawing + cycle. The reason why this state exists is as follows: + 1. The engine draws sprite two pixels(EVEN+ODD) per one buffer access cycle. + It latches the first pixel from pixel selctor, switches selector to pick + the next pixel. Writes these two pixels to the frame buffer. + 2. If the current tileline's size is an odd number, and should be terminate the + cycle, it can't be done. Because the first pixel is still on the pixel + selector's output without being latched. And, WRTIME has not been asserted. + It(the first pixel) can't be written on the buffer. + 3. This cycle maintained for four pixels(next pixel3_n = next rising edge of 2H) + During this cycle, the first pixel is latched and WRTIME is asserted in + pixel3_n of ODDSIZE_S0. + + SUSPEND_S0: + Branches to this state unconditionally when FSM_SUSPEND is 1. When the FSM is in + ATTR_LATCHING_S1, it moves to this state after attrubute latching. The FSM checks + FSM_SUSPEND at every rising edge of 2H. + Note that WRTIME2 and o_PIXELLATCH_WAIT_n will still be on the lines after a + suspension, since they are just delayed signals from the shift registers. +*/ + +/* + 일단 스프라이트 속성부터 래치시킴 S0을 1픽셀동안 유지시키면 SR이 1H클럭에 맞춰 쭉 + 시프팅, 그동안 S1을 유지하는데 이때는 아무일도 안 함. S1이 끝나면 그리기를 시작하는데, + 만약 서스펜드 플래그가 올라가있으면 대기상태로 들어감. + + 쭉 그리는데, 확대/축소된 스프라이트의 경우 h어큐뮬레이터의 캐리가 픽셀 3에서 정확히 안 + 올라갈 때가 있음. 이럴 경우 캐리가 올라간 엣지의 다음 엣지에서 HWAIT상태로 들어감. + 여기서 중요한 건 HCOUNT에서 캐리가 올라갔을 때(end_of_tileline) K5294쪽 MUX빠져나온 후 + 래치를 잠깐 정지시키는 latch_wait신호가 hsize_parity에 따라 다르다는 것임. 사라만다 + 캡쳐에 이 경우가 없어서 3시간을 날렸다는 걸 잊지 말기 + + HWAIT때는 그냥 latch_wait으로 래칭을 정지. end_of_hline일때 가로사이즈가 홀수라면 먼저 + 들어온 픽셀이 아직 래치되지 않고 기다리는 중이므로 ODDSIZE를 4클럭동안 삽입. 이때 먼저 + 들어온 픽셀이 래치되고 기록됨. +*/ + +//Declare states +localparam ATTR_LATCHING_S0 = 3'd1; +localparam ATTR_LATCHING_S1 = 3'd2; +localparam HCOUNT_S0 = 3'd3; +localparam HWAIT_S0 = 3'd4; +localparam ODDSIZE_S0 = 3'd5; +localparam SUSPEND_S0 = 3'd0; + +//Declare state register +reg [2:0] sprite_engine_state = SUSPEND_S0; //3'd0 = reset state, Quartus always reset FSM as 0 + +//Determine the next state synchronously, based on the current state and the input +always @ (posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + case(sprite_engine_state) + // ATTRIBUTE LATCHING START + ATTR_LATCHING_S0: + sprite_engine_state <= ATTR_LATCHING_S1; + + // WAIT FOR LATCHING COMPLETION + ATTR_LATCHING_S1: + if(pixel3_n == 1'b0) //exit condition: 1 pixel just after end of ORINC(negative logic) + begin + if(LATCH_F_2H_NCLKD_en_n == 1'b0) + begin + if(FSM_SUSPEND == 1'b0) //keep going + begin + sprite_engine_state <= HCOUNT_S0; + end + else //if not, go suspend_s0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else + begin + sprite_engine_state <= ATTR_LATCHING_S1; + end + end + else + begin + sprite_engine_state <= ATTR_LATCHING_S1; + end + + // DRAWING + // IMPORTANCE LEVEL: END_OF_SPRITE > END_OF_HLINE > END_OF_TILELINE > KEEP_DRAWING + HCOUNT_S0: + if(drawing_status == END_OF_SPRITE) + begin + if(pixel3_n == 1'b0) //at pixel 3 + begin + if(FSM_SUSPEND == 1'b0) //keep going + begin + if(hsize_parity == 1'b0) //zoomed horizontal size is even + begin + sprite_engine_state <= ATTR_LATCHING_S0; + end + else + begin + sprite_engine_state <= ODDSIZE_S0; + end + end + else //if not, go suspend_s0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else //at pixel 0, 1, 2 + begin + sprite_engine_state <= HWAIT_S0; + end + end + else if(drawing_status == END_OF_HLINE) + begin + if(pixel3_n == 1'b0) //at pixel 3 + begin + if(FSM_SUSPEND == 1'b0) //keep going + begin + if(hsize_parity == 1'b0) //zoomed horizontal size is even + begin + sprite_engine_state <= HCOUNT_S0; + end + else //zoomed horizontal size is odd + begin + sprite_engine_state <= ODDSIZE_S0; + end + end + else //if not, go SUSPEND_S0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else //at pixel 0, 1, 2 + begin + sprite_engine_state <= HWAIT_S0; + end + end + else if(drawing_status[1:0] == END_OF_TILELINE) + begin + if(pixel3_n == 1'b0) //at pixel 3 + begin + if(FSM_SUSPEND == 1'b0) //keep going + begin + sprite_engine_state <= HCOUNT_S0; + end + else //if not, go suspend_s0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else //at pixel 0, 1, 2 + begin + sprite_engine_state <= HWAIT_S0; + end + end + else // `KEEP_DRAWING + begin + if(pixel3_n == 1'b0) //at pixel 3 + begin + if(FSM_SUSPEND == 1'b0) //keep going + begin + sprite_engine_state <= HCOUNT_S0; + end + else //if not, go SUSPEND_S0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else //at pixel 0, 1, 2 + begin + sprite_engine_state <= HCOUNT_S0; + end + end + + + + // WAIT STATE: WAITING FOR /PX3 + HWAIT_S0: + if(pixel3_n == 1'b0) //exit condition: encounter px3 + begin + if(FSM_SUSPEND == 1'b0) //keep going, return to HCOUNT_S0 or fetch new attributes + begin + if(drawing_status == END_OF_SPRITE) + begin + if(hsize_parity == 1'b0) //zoomed horizontal size is even + begin + sprite_engine_state <= ATTR_LATCHING_S0; + end + else //zoomed horizontal size is odd + begin + sprite_engine_state <= ODDSIZE_S0; + end + end + else if(drawing_status == END_OF_HLINE) + begin + if(hsize_parity == 1'b0) //zoomed horizontal size is even + begin + sprite_engine_state <= HCOUNT_S0; + end + else //zoomed horizontal size is odd + begin + sprite_engine_state <= ODDSIZE_S0; + end + end + else + begin + sprite_engine_state <= HCOUNT_S0; + end + end + else //if not, go suspend_s0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else + begin + sprite_engine_state <= HWAIT_S0; + end + + + // WAIT FOR WRITE ONLY A SINGLE PIXEL + ODDSIZE_S0: + if(pixel3_n == 1'b0) //exit condition: encounter px3 + begin + if(FSM_SUSPEND == 1'b0) //keep going, return to HCOUNT_S0 or fetch new attributes + begin + if(drawing_status == END_OF_SPRITE) + begin + sprite_engine_state <= ATTR_LATCHING_S0; + end + else + begin + sprite_engine_state <= HCOUNT_S0; + end + end + else //if not, go suspend_s0 + begin + sprite_engine_state <= SUSPEND_S0; + end + end + else + begin + sprite_engine_state <= ODDSIZE_S0; + end + + + // SUSPEND STATE: WAITING FOR /PX3 + SUSPEND_S0: begin + if(pixel3_n == 1'b0) //exit condition: encounter px3 + begin + if(new_vblank_n == 1'b0) + begin + sprite_engine_state <= ATTR_LATCHING_S0; //new vblank + end + else if(FSM_SUSPEND == 1'b0) //return to HCOUNT_S0 or fetch new attributes + begin + if(drawing_status == END_OF_SPRITE) + begin + sprite_engine_state <= ATTR_LATCHING_S0; + end + else if(drawing_status == END_OF_HLINE) + begin + if(hsize_parity == 1'b0) //zoomed horizontal size is even + begin + sprite_engine_state <= HCOUNT_S0; + end + else //zoomed horizontal size is odd + begin + sprite_engine_state <= ODDSIZE_S0; + end + end + else + begin + sprite_engine_state <= HCOUNT_S0; + end + end + else + begin + sprite_engine_state <= SUSPEND_S0; + end + end + end + endcase + end +end + +//Determine the output based only on the current state and the input (do not wait for a clock edge) +//signal list: +// latching_start +// hzoom_cnt_n +// hzoom_rst_n +// vzoom_cnt_n +// vzoom_rst_n +// ypos_cnt_n +// pixellatch_wait_n +always @(*) //Quartus +begin + case(sprite_engine_state) + ATTR_LATCHING_S0: begin + latching_start <= 1'b1; + + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + ATTR_LATCHING_S1: begin + if(LATCH_F_2H_NCLKD_en_n == 1'b0 && pixel3_n == 1'b0) + begin + latching_start <= 1'b0; + + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b0; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b0; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + else + begin + latching_start <= 1'b0; + + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + + HCOUNT_S0: begin + /* + HCOUNT_S0 + 대기 상태: 다음 PIXEL3_n까지 기다립니다. + + 1. END_OF_SPRITE가 PIXEL3_n전에 감지되었을 경우 pixellatch_wait_n + 은 0이 되고, hv피드백 카운터를 정지해야 합니다. HWAIT_S0에서 hv피드백 + 카운터를 조작하기 때문입니다. PIXEL3_n에 감지되었을 경우는 + pixellatch_wait_n가 1이고, hv피드백 카운터를 조작해야 합니다. + 2. END_OF_SPRITE가 PIXEL3_n전에 감지되었을 경우 pixellatch_wait_n + 은 0이 되고, hv피드백 카운터를 정지해야 합니다. HWAIT_S0에서 hv피드백 + 카운터를 조작하기 때문입니다. PIXEL3_n에 감지되었을 경우는 + pixellatch_wait_n가 1이고, hv피드백 카운터를 조작해야 합니다. + 3. END_OF_SPRITE가 PIXEL3_n전에 감지되었을 경우 pixellatch_wait_n + 은 0이 되고, hv피드백 카운터를 정지해야 합니다. HWAIT_S0에서 hv피드백 + 카운터를 조작하기 때문입니다. PIXEL3_n에 감지되었을 경우는 + pixellatch_wait_n가 1이고, hv피드백 카운터를 조작해야 합니다. + 4. KEEP_DRAWING에는 pixellatch_wait_n은 1이 되고, hv피드백 카운터를 + 계속 증가시켜야 합니다. + */ + + latching_start <= 1'b0; + + if(drawing_status == END_OF_SPRITE) + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else if(drawing_status == END_OF_HLINE) + begin + if(hsize_parity == 1'b0) //after drawing even pixels + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b0; + + vzoom_cnt_n <= 1'b0; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b0; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else + begin + if(pixel3_n == 1'b0) //pixel 3, after drawing odd pixles: will go to ODDSIZE_S0 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; //latch immediately + end + else + begin //before pixel 3, will go to HWAIT_S0 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; //will be latched on pixel3 of HWAIT_S0 + end + end + + end + else if(drawing_status[1:0] == END_OF_TILELINE) + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; //latch anyway + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= ~hsize_parity; //odd size = wait for the even pixel, + //even size = latch(=do not need to be latched, will be drawn immediately) + end + end + else //`KEEP_DRAWING + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + end + end + + + HWAIT_S0: begin + /* + HWAIT_S0 + 대기 상태: 다음 PIXEL3_n까지 기다립니다. + + 1. END_OF_SPRITE인 경우 hsize_parity에 따라 출력이 달라집니다. + 짝수개를 그린 후라면 스프라이트를 그만 그려도 되지만, 홀수개를 + 그린 후라면 ODDSIZE_S0을 삽입해야 하기 때문에 hv피드백 카운터를 + 조작해서는 안 됩니다. + 2. END_OF_HLINE인 경우 hsize_parity에 따라 출력이 달라집니다. + 짝수개를 그린 후라면 바로 다음 tileline을 그려야 하지만, 홀수개를 + 그린 후라면 ODDSIZE_S0을 삽입해야 하기 때문에 hv피드백 카운터를 + 조작해서는 안 됩니다. + 3. END_OF_TILELINE인 경우 PIXEL3_n이 오면 카운터를 증가시킵니다 + 4. KEEP_DRAWING은 발생할 수 없지만 모든 경우를 기술해야 하므로 + 작성합니다. + */ + + latching_start <= 1'b0; + + if(drawing_status == END_OF_SPRITE) + begin + if(hsize_parity == 1'b0) //after drawing even pixels + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else //after drawing odd pixels: everything will be changed in ODDSIZE_S0 + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + end + else if(drawing_status == END_OF_HLINE) + begin + if(hsize_parity == 1'b0) //after drawing even pixels + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b0; + + vzoom_cnt_n <= 1'b0; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b0; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else //after drawing odd pixels: everything will be changed in ODDSIZE_S0 + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + end + else if(drawing_status[1:0] == END_OF_TILELINE) + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else //`KEEP_DRAWING: WILL NOT HAPPEN + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + end + end + + ODDSIZE_S0: begin + /* + ODDSIZE_S0 + 지금까지 그린 픽셀 갯수가 홀수인 상황에서 짝수 버퍼에 0을 쓰고 한 + 라인 그리기를 마쳐야 하는 경우입니다. 이 상태로 넘어온 경우 hsize_ + parity가 홀수인 것은 확정된 상황입니다. + + 1. END_OF_SPRITE인 경우 스프라이트 그리기를 마쳐야 합니다. + 2. END_OF_HLINE인 경우 ypos와 vzoom을 증가시켜야 합니다. + 3. END_OF_TILELINE은 발생할 수 없지만 모든 경우를 기술해야 하므로 + 작성합니다. + 4. KEEP_DRAWING은 발생할 수 없지만 모든 경우를 기술해야 하므로 + 작성합니다. + */ + + latching_start <= 1'b0; + + if(drawing_status == END_OF_SPRITE) + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b0; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b0; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else if(drawing_status == END_OF_HLINE) + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b0; + + vzoom_cnt_n <= 1'b0; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b0; + + pixellatch_wait_n <= 1'b0; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else if(drawing_status[1:0] == END_OF_TILELINE) //WILL NOT HAPPEN + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + else //`KEEP_DRAWING(WILL NOT HAPPEN) + begin + if(pixel3_n == 1'b0) //pixel 3 + begin + hzoom_cnt_n <= 1'b0; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b1; + end + else + begin //before pixel 3 + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + end + end + + SUSPEND_S0: begin + /* + SUSPEND_S0 + 작업이 재개될 때 까지 기다립니다. + */ + latching_start <= 1'b0; + + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + + default: begin + latching_start <= 1'b0; + + hzoom_cnt_n <= 1'b1; + hzoom_rst_n <= 1'b1; + + vzoom_cnt_n <= 1'b1; + vzoom_rst_n <= 1'b1; + + ypos_cnt_n <= 1'b1; + + pixellatch_wait_n <= 1'b0; + end + endcase +end + + + +/* + [6M CLK] WRTIME DELAY +*/ + +reg wrtime1; +wire oddsize_wrtime0 = (sprite_engine_state == ODDSIZE_S0 && pixel3_n == 1'b0) ? 1'b1 : 1'b0; +wire evensize_wrtime0 = (sprite_engine_state == HCOUNT_S0) ? ~hsize_parity : 1'b0; +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + //feed hsize_parity normally, but it should be 1 when PIXEL3 at ODDSIZE_S0 + wrtime1 <= evensize_wrtime0 | oddsize_wrtime0; + o_WRTIME2 <= wrtime1; + end +end + + + +/* + [6M CLK] o_PIXELLATCH_WAIT_n DELAY +*/ + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + o_PIXELLATCH_WAIT_n <= pixellatch_wait_n; + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// PIXEL SELECT(005294), LINE SELECT, TILE SELECT +//// + +//005294 PIXEL SELECT +assign o_PIXELSEL = hzoom_acc[9:7] ^ {3{LATCH_A[0]}}; //OBJ_HFLIP + +//CHARRAM ADDRESS +wire [2:0] TILELINE_ADDR = hzoom_tileline_cntr ^ {3{LATCH_A[0]}}; +wire [2:0] HLINE_ADDR = vzoom_acc[9:7] ^ {3{LATCH_D[5]}}; +wire [3:0] VTILE_ADDR = vzoom_vtile_cntr ^ {4{LATCH_D[5]}}; +reg [13:0] CHARRAM_ADDR; //unmultiplexed +assign o_OCA = (i_CHAMPX == 1'b0) ? CHARRAM_ADDR[7:0] : {1'b1, CHARRAM_ADDR[13:8], 1'b1}; //RAS : CAS + +always @(*) +begin + case({LATCH_A[1], LATCH_A[5:3]}) + // |-------(OBJ CODE)-------| + 4'h0: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:3], VTILE_ADDR[1:0], HLINE_ADDR[2:0], TILELINE_ADDR[1:0]}; //32*32 4 vetrical tiles + 4'h1: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:2], VTILE_ADDR[1:0], HLINE_ADDR[2:0], TILELINE_ADDR[0:0]}; //16*32 4 vetrical tiles + 4'h2: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:2], VTILE_ADDR[0:0], HLINE_ADDR[2:0], TILELINE_ADDR[1:0]}; //32*16 2 vetrical tiles + 4'h3: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:5], VTILE_ADDR[2:0], HLINE_ADDR[2:0], TILELINE_ADDR[2:0]}; //64*64 8 vetrical tiles + 4'h4: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:0], 1'b0, HLINE_ADDR[2:0] }; //8*8 1 vetrical tiles + 4'h5: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:0], HLINE_ADDR[2:0], TILELINE_ADDR[0:0]}; //16*8 1 vetrical tiles + 4'h6: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:0], VTILE_ADDR[0:0], HLINE_ADDR[2:0] }; //8*16 2 vetrical tiles + 4'h7: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:1], VTILE_ADDR[0:0], HLINE_ADDR[2:0], TILELINE_ADDR[0:0]}; //16*16 2 vetrical tiles + + 4'h8: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:4], VTILE_ADDR[2:0], HLINE_ADDR[2:0], TILELINE_ADDR[1:0]}; //32*64 8 vetrical tiles + 4'h9: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:3], VTILE_ADDR[2:0], HLINE_ADDR[2:0], TILELINE_ADDR[0:0]}; //16*64 8 vetrical tiles + 4'hA: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:4], VTILE_ADDR[1:0], HLINE_ADDR[2:0], TILELINE_ADDR[1:0]}; //32*32 4 vetrical tiles + 4'hB: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:6], VTILE_ADDR[3:0], HLINE_ADDR[2:0], TILELINE_ADDR[2:0]}; //64*128 16 vetrical tiles + 4'hC: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:0], VTILE_ADDR[0:0], HLINE_ADDR[2:0] }; //8*16 2 vetrical tiles + 4'hD: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:1], VTILE_ADDR[0:0], HLINE_ADDR[2:0], TILELINE_ADDR[0:0]}; //16*16 2 vetrical tiles + 4'hE: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:1], VTILE_ADDR[1:0], HLINE_ADDR[2:0] }; //8*32 4 vetrical tiles + 4'hF: CHARRAM_ADDR <= {LATCH_D[7:6], LATCH_C[7:2], VTILE_ADDR[1:0], HLINE_ADDR[2:0], TILELINE_ADDR[0:0]}; //16*32 4 vetrical tiles + endcase +end + + + + + + + + +/////////////////////////////////////////////////////////// +////// SCREEN COUNTER +//// + +//X Screen Counter +reg [6:0] buffer_x_screencounter = 7'd0; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + if(i_ABS_1H == 1'b1) //negedge of 1H + begin + if(i_OBJWR == 1'b1) + begin + buffer_x_screencounter <= 7'd0; + end + else + begin + if(buffer_x_screencounter == 7'd127) + begin + buffer_x_screencounter <= 7'd0; + end + else + begin + buffer_x_screencounter <= buffer_x_screencounter + 7'd1; + end + end + end + end +end + +/* + Y Screen Counter + + This Y Screen Counter increases at a rising edge of i_HBLANK_n, + asynchronously. But we need to synchronize all flip-flops to + the master clock, so there was no choice but to install an edge + detector, and counting was delayed by one clock. However, a rising + edge of HBLANK increases the Y Counter before OBJ WR switches MUX + and the timing is not stern, so this delay is invisible from the + outside and does not affect the behavior. +*/ + +reg prev_hblank; +reg [7:0] buffer_y_screencounter = 8'd15; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + prev_hblank <= i_HBLANK_n; + + if(i_VBLANK_n == 1'b0) //async reset by VBLANK + begin + buffer_y_screencounter <= 8'd15; + + end + else + begin + if(i_HBLANK_n == 1'b1 && prev_hblank == 1'b0) //1 clk after the positive edge of vblank + begin + if(buffer_y_screencounter == 8'd255) + begin + buffer_y_screencounter <= 8'd0; + end + else + begin + buffer_y_screencounter <= buffer_y_screencounter + 8'd1; + end + end + end + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// BUFFER MUX +//// + +/* + GX400 uses 1Mb of frame buffer, but 256*256 size sprite field consumes + only 512kb. I think Konami engineers designed the hardware that can + support interlaced mode that was never been used. +*/ + +reg buffer_frame_parity = 1'b0; +reg prev_vblank; + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + prev_vblank <= i_VBLANK_n; + + if(i_VBLANK_n == 1'b0 && prev_vblank == 1'b1) //async reset by VBLANK + begin + buffer_frame_parity <= ~buffer_frame_parity; + end + end +end + + +reg [15:0] EVENBUFFER_ADDR; //unmultiplexed, buffer A on the Nemesis schematics +reg [15:0] ODDBUFFER_ADDR; //unmultiplexed, buffer B on the Nemesis schematics +assign o_FA = (o_CAS == 1'b0) ? EVENBUFFER_ADDR[7:0] : EVENBUFFER_ADDR[15:8]; //RAS : CAS +assign o_FB = (o_CAS == 1'b0) ? ODDBUFFER_ADDR[7:0] : ODDBUFFER_ADDR[15:8]; //RAS : CAS + +always @(*) +begin + case(i_OBJWR) + 1'b1: begin //sprite drawing period + EVENBUFFER_ADDR <= {buffer_frame_parity | __SAVE_FRAMEBUFFER_CAPACITY, + buffer_ypos_counter, evenbuffer_xpos_counter[6:0]}; + ODDBUFFER_ADDR <= {buffer_frame_parity | __SAVE_FRAMEBUFFER_CAPACITY, + buffer_ypos_counter, oddbuffer_xpos_counter[6:0]}; + end + 1'b0: begin //active video period + EVENBUFFER_ADDR <= {buffer_frame_parity | __SAVE_FRAMEBUFFER_CAPACITY, + buffer_y_screencounter ^ {8{i_FLIP}}, buffer_x_screencounter ^ {7{i_FLIP}}}; + ODDBUFFER_ADDR <= {buffer_frame_parity | __SAVE_FRAMEBUFFER_CAPACITY, + buffer_y_screencounter ^ {8{i_FLIP}}, buffer_x_screencounter ^ {7{i_FLIP}}}; + end + endcase +end + + + + + + +/////////////////////////////////////////////////////////// +////// XA7 XB7 +//// + +/* + When the X coordinate goes out of the screen (xpos>255), the xpos counter + value wraps around, which can damage the sprite drawn before, so make XA/XB + as 1 and overwrite it with the existing data without updating the value. + + Need to delay 1 clk. + + Note that Konami swapped the name of two signals on the Nemesis schematics. + XA is on the ODD(B) buffer, and vice versa. +*/ + +always @(posedge i_EMU_MCLK) +begin + if(!i_EMU_CLK6MPCEN_n) + begin + o_XA7 <= evenbuffer_xpos_counter[7]; + o_XB7 <= oddbuffer_xpos_counter[7]; + end +end + + + + + + +/////////////////////////////////////////////////////////// +////// CAS +//// + +assign o_CAS = i_OBJHL; + + +endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px3.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM.v similarity index 58% rename from BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px3.v rename to BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM.v index 546f35a..62cf9df 100644 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px3.v +++ b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM.v @@ -1,23 +1,34 @@ /* - 4416 DRAM + DRAM */ -module DRAM16k4_charram_px3 +module DRAM #( parameter + dw=8, // data width + aw=8, // address bus width (number of pins) + rw=aw, // row width (usually address but width) + cw=aw, // column width (address but width or shorter) + ctop=cw-1, // index in address where MSB of col is + cbot=0, // index in address where LSB of col is + simhexfile="", + init=0 +) ( input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, + input wire [aw-1:0] i_ADDR, + input wire [dw-1:0] i_DIN, + output reg [dw-1:0] o_DOUT, input wire i_RAS_n, input wire i_CAS_n, input wire i_WR_n, input wire i_RD_n ); -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; +reg [dw-1:0] RAM [0:(2**(rw+cw))-1]; +reg prev_ras; +reg prev_cas; +reg [rw-1:0] ROW_ADDR; +reg [cw-1:0] COL_ADDR; +wire [rw+cw-1:0] ADDR = {COL_ADDR, ROW_ADDR}; /* MCLK 1 1 @@ -32,21 +43,24 @@ wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; >column >launch >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ + CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯ /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ */ always @(posedge i_MCLK) begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) + prev_ras <= i_RAS_n; + prev_cas <= i_CAS_n; + + if(i_RAS_n == 1'b0 && prev_ras == 1'b1) begin - __ROW_ADDR <= i_ADDR; + ROW_ADDR <= i_ADDR; end - if(i_CAS_n == 1'b0) + if(i_CAS_n == 1'b0 && prev_cas == 1'b1) begin - __COL_ADDR <= i_ADDR[6:1]; + COL_ADDR <= i_ADDR[ctop:cbot]; end end @@ -55,7 +69,7 @@ always @(posedge i_MCLK) begin if(i_WR_n == 1'b0) begin - RAM16k4[__ADDR] <= i_DIN; + RAM[ADDR] <= i_DIN; end end @@ -63,13 +77,25 @@ always @(posedge i_MCLK) //read begin if(i_RD_n == 1'b0) begin - o_DOUT <= RAM16k4[__ADDR]; + o_DOUT <= RAM[ADDR]; end end +integer i; + initial begin - $readmemh("init_charram_px3.txt", RAM16k4); + if( simhexfile != "" ) + begin + $readmemh(simhexfile, RAM); + end + else if( init != 0 ) + begin + for(i = 0; i < 2**(rw+cw); i = i + 1) + begin + RAM[i] <= {dw{1'b0}}; + end + end end -endmodule \ No newline at end of file +endmodule diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4.v deleted file mode 100644 index 5f40e08..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4.v +++ /dev/null @@ -1,70 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px0.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px0.v deleted file mode 100644 index b262660..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px0.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px0 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px0.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px1.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px1.v deleted file mode 100644 index ed7e7b5..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px1.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px1 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px1.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px2.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px2.v deleted file mode 100644 index 158c476..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px2.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px2 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px2.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px4.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px4.v deleted file mode 100644 index 909f9a2..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px4.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px4 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px4.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px5.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px5.v deleted file mode 100644 index 47ba9ff..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px5.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px5 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px5.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px6.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px6.v deleted file mode 100644 index 7ba7fb0..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px6.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px6 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px6.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px7.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px7.v deleted file mode 100644 index 5283daa..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/DRAM16k4_charram_px7.v +++ /dev/null @@ -1,75 +0,0 @@ -/* - 4416 DRAM -*/ - -module DRAM16k4_charram_px7 -( - input wire i_MCLK, - input wire [7:0] i_ADDR, - input wire [3:0] i_DIN, - output reg [3:0] o_DOUT, - input wire i_RAS_n, - input wire i_CAS_n, - input wire i_WR_n, - input wire i_RD_n -); - -reg [3:0] RAM16k4 [16383:0]; -reg [7:0] __ROW_ADDR; -reg [5:0] __COL_ADDR; -wire [13:0] __ADDR = {__COL_ADDR, __ROW_ADDR}; - -/* - MCLK 1 1 - 0 1 2 3 4 5 6 7 8 9 0 1 - CLK18M _|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯| - CLK9M ¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯|___|¯¯¯| - CLK6M ¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯|___| - PIXEL ----(3)----|----(4)----|----(5)----|----(6)----|----(7)----|----(0)----|----(1)----|----(2)----|----(3)----| - /DTACK ¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯S0¯¯S1¯¯S2¯¯S3¯¯S4¯|_w___w__S5__S6|¯S7¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - |-----------| = access time = 162.75ns - >row - >column - >launch - >CPU acquisition - CHAMPX1 ¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ - /RAS ___________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|________________ - /CAS _______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯|____________ -*/ - -always @(posedge i_MCLK) -begin - if(i_RAS_n == 1'b0 && i_CAS_n == 1'b1) - begin - __ROW_ADDR <= i_ADDR; - end - - if(i_CAS_n == 1'b0) - begin - __COL_ADDR <= i_ADDR[6:1]; - end -end - - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM16k4[__ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM16k4[__ADDR]; - end -end - -initial -begin - $readmemh("init_charram_px7.txt", RAM16k4); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM.v new file mode 100644 index 0000000..f8a7d12 --- /dev/null +++ b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM.v @@ -0,0 +1,44 @@ +/* + SRAM +*/ + +module SRAM #(parameter + dw=8, + aw=10, + simhexfile="" +) +( + input wire i_MCLK, + input wire [aw-1:0] i_ADDR, + input wire [dw-1:0] i_DIN, + output reg [dw-1:0] o_DOUT, + input wire i_WR_n, + input wire i_RD_n +); + +reg [dw-1:0] RAM [0:(2**aw)-1]; + +always @(posedge i_MCLK) +begin + if(i_WR_n == 1'b0) + begin + RAM[i_ADDR] <= i_DIN; + end +end + +always @(posedge i_MCLK) //read +begin + if(i_RD_n == 1'b0) + begin + o_DOUT <= RAM[i_ADDR]; + end +end + +initial +begin + if( simhexfile != "" ) begin + $readmemh(simhexfile, RAM); + end +end + +endmodule diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8.v deleted file mode 100644 index 0a2036e..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8.v +++ /dev/null @@ -1,33 +0,0 @@ -/* - 6116 SRAM -*/ - -module SRAM2k8 -( - input wire i_MCLK, - input wire [10:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM2k8 [2047:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM2k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM2k8[i_ADDR]; - end -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_high.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_high.v deleted file mode 100644 index a9cadaf..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_high.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - 6116 SRAM -*/ - -module SRAM2k8_color_high -( - input wire i_MCLK, - input wire [10:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM2k8 [2047:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM2k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM2k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_colorram_high.txt", RAM2k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_low.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_low.v deleted file mode 100644 index 8b9df7f..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_color_low.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - 6116 SRAM -*/ - -module SRAM2k8_color_low -( - input wire i_MCLK, - input wire [10:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM2k8 [2047:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM2k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM2k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_colorram_low.txt", RAM2k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_obj.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_obj.v deleted file mode 100644 index 213bf97..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_obj.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - 6116 SRAM -*/ - -module SRAM2k8_obj -( - input wire i_MCLK, - input wire [10:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM2k8 [2047:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM2k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM2k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_objram.txt", RAM2k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_scroll.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_scroll.v deleted file mode 100644 index 4ef95cd..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM2k8_scroll.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - 6116 SRAM -*/ - -module SRAM2k8_scroll -( - input wire i_MCLK, - input wire [10:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM2k8 [2047:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM2k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM2k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_scrollram.txt", RAM2k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8.v deleted file mode 100644 index 89d75a6..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8.v +++ /dev/null @@ -1,33 +0,0 @@ -/* - TC5533P SRAM -*/ - -module SRAM4k8 -( - input wire i_MCLK, - input wire [11:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM4k8 [4095:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM4k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM4k8[i_ADDR]; - end -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_high.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_high.v deleted file mode 100644 index 8a0e803..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_high.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - TC5533P SRAM -*/ - -module SRAM4k8_vram1_high -( - input wire i_MCLK, - input wire [11:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM4k8 [4095:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM4k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM4k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_vram1_high.txt", RAM4k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_low.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_low.v deleted file mode 100644 index df67803..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram1_low.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - TC5533P SRAM -*/ - -module SRAM4k8_vram1_low -( - input wire i_MCLK, - input wire [11:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM4k8 [4095:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM4k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM4k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_vram1_low.txt", RAM4k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram2.v b/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram2.v deleted file mode 100644 index 6a37d5b..0000000 --- a/BubSysROM_core_ModelSim/BubSysROM_component/ram/SRAM4k8_vram2.v +++ /dev/null @@ -1,38 +0,0 @@ -/* - TC5533P SRAM -*/ - -module SRAM4k8_vram2 -( - input wire i_MCLK, - input wire [11:0] i_ADDR, - input wire [7:0] i_DIN, - output reg [7:0] o_DOUT, - input wire i_WR_n, - input wire i_RD_n -); - -reg [7:0] RAM4k8 [4095:0]; - -always @(posedge i_MCLK) -begin - if(i_WR_n == 1'b0) - begin - RAM4k8[i_ADDR] <= i_DIN; - end -end - -always @(posedge i_MCLK) //read -begin - if(i_RD_n == 1'b0) - begin - o_DOUT <= RAM4k8[i_ADDR]; - end -end - -initial -begin - $readmemh("init_vram2.txt", RAM4k8); -end - -endmodule \ No newline at end of file diff --git a/BubSysROM_core_ModelSim/BubSysROM_screensim.v b/BubSysROM_core_ModelSim/BubSysROM_screensim.v index 05934ce..03ced61 100644 --- a/BubSysROM_core_ModelSim/BubSysROM_screensim.v +++ b/BubSysROM_core_ModelSim/BubSysROM_screensim.v @@ -44,7 +44,7 @@ always @(posedge i_EMU_MCLK) begin end $display("Start of frame %d", frame); //debug message - frame = frame + 16'd1; + end else if(i_HCOUNTER == 9'd277) begin $fseek(fd, BITMAP_LINE_ADDRESS, 0); //set current line address @@ -57,6 +57,9 @@ always @(posedge i_EMU_MCLK) begin end else if(i_VCOUNTER == 9'd495 && i_HCOUNTER == 9'd151) begin $fclose(fd); //close this frame + $display("Frame %d saved", frame); //debug message + + frame = frame + 16'd1; end else begin diff --git a/BubSysROM_core_ModelSim/BubSysROM_video/BubSysROM_video.v b/BubSysROM_core_ModelSim/BubSysROM_video/BubSysROM_video.v index 8425848..8aeb2e0 100644 --- a/BubSysROM_core_ModelSim/BubSysROM_video/BubSysROM_video.v +++ b/BubSysROM_core_ModelSim/BubSysROM_video/BubSysROM_video.v @@ -124,51 +124,33 @@ wire HBLANK_n; wire VBLANK_n; assign o_VBLANK_n = VBLANK_n; wire VBLANKH_n; +wire VCLK; +wire CSYNC_n; -wire ABS_256H; +//hcounter +wire ABS_256H, + ABS_128H, ABS_64H, ABS_32H, ABS_16H, + ABS_8H, ABS_4H, ABS_2H, ABS_1H; + +wire FLIP_128H, FLIP_64H, FLIP_32H, FLIP_16H, + FLIP_8H, FLIP_4H, FLIP_2H, FLIP_1H; + +//vcounter +wire ABS_128V, ABS_64V, ABS_32V, ABS_16V, + ABS_8V, ABS_4V, ABS_2V, ABS_1V; + +wire FLIP_128V, FLIP_64V, FLIP_32V, FLIP_16V, + FLIP_8V, FLIP_4V, FLIP_2V, FLIP_1V; + +//misc wire ABS_n256H = ~ABS_256H; -wire ABS_128H; -wire ABS_64H; -wire ABS_32H; -wire ABS_16H; -wire ABS_8H; -wire ABS_4H; -wire ABS_2H; -wire ABS_1H; wire ABS_n1H = ~ABS_1H; wire ABS_128HA = (ABS_256H & ABS_128H) | (ABS_n256H & ABS_32H); -wire ABS_128V; -wire ABS_64V; -wire ABS_32V; -wire ABS_16V; -wire ABS_8V; -wire ABS_4V; -wire ABS_2V; -wire ABS_1V; - wire FLIP_n256H = ABS_n256H ^ i_HFLIP; -wire FLIP_128H; -wire FLIP_64H; -wire FLIP_32H; -wire FLIP_16H; -wire FLIP_8H; -wire FLIP_4H; -wire FLIP_2H; -wire FLIP_1H; -wire FLIP_128V; -wire FLIP_64V; -wire FLIP_32V; -wire FLIP_16V; -wire FLIP_8V; -wire FLIP_4V; -wire FLIP_2V; -wire FLIP_1V; +wire DMA_n = ~&{ABS_128V, ABS_64V, ABS_32V, ~ABS_16V}; //16C NAND; vcounter 480-495 -wire VCLK; - -wire CSYNC_n; //declare K005292 core: this core does not have LS393 sprite code up counter K005292 K005292_main @@ -227,12 +209,39 @@ K005292 K005292_main .o_FRAMEPARITY ( ), //256V .o_VSYNC_n (o_VSYNC_n ), - .o_CSYNC_n (CSYNC_n ), + .o_CSYNC (CSYNC_n ), .__REF_HCOUNTER (__REF_HCOUNTER ), .__REF_VCOUNTER (__REF_VCOUNTER ) ); +//fully asynchronous shit in K005292(modded) +wire ORINC; +reg [7:0] OBJ; +wire objcntr_tick = ORINC | (&{OBJ[7:4]}); + +always @(posedge i_EMU_MCLK) +begin + if(!o_EMU_CLK6MPCEN_n) + begin + if(ABS_1H == 1'b0) //posedge of 1H + begin + if(DMA_n == 1'b0) + begin + OBJ <= 8'd0; + end + else + begin + if(objcntr_tick == 1'b0) + begin + OBJ <= OBJ + 8'd1; + end + end + end + end +end + + // // CSYNC DFF @@ -313,7 +322,7 @@ always @(posedge i_EMU_MCLK) begin if(!i_EMU_CLK18MNCEN_n) begin - CHAMPX2 = CHAMPX; + CHAMPX2 <= CHAMPX; end end @@ -323,7 +332,7 @@ end // //timing singals -wire OBJRW; //switches mux between active display+buffer clear/005295 write +wire OBJWR; //switches mux between active display+buffer clear/005295 write wire OBJCLR; //fix mux output as 0 when clearing the buffer by writing 0s //19H LS74A @@ -343,9 +352,9 @@ end reg DFF_19H_B; always @(posedge i_EMU_MCLK) begin - if(!o_EMU_CLK6MNCEN_n) //negedge cen + if(!o_EMU_CLK6MPCEN_n) //negedge cen begin - if(ABS_1H == 1'b0) //every EVEN pixel + if(ABS_1H == 1'b1) //every ODD pixel begin DFF_19H_B <= DFF_19H_A; end @@ -385,7 +394,7 @@ begin end end -assign OBJRW = DFF_19H_B; +assign OBJWR = DFF_19H_B; assign OBJCLR = ~DFF_19H_B; assign o_BLK = DFF_17A_A; @@ -477,7 +486,8 @@ wire scrollram_wr = (i_VZCS_n | i_CPU_RW | i_CPU_LDS_n | TIME2); //declare SCROLLRAM wire [7:0] scrollram_dout; -SRAM2k8_scroll SCROLLRAM_LOW +SRAM #(.aw( 11 ), .dw( 8 ), .simhexfile("init_scrollram.txt")) +SCROLLRAM_LOW ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (scrollram_addr ), @@ -585,7 +595,8 @@ wire vram2l_wr = (i_VCS2_n | i_CPU_RW | i_CPU_LDS_n | ABS_1H | ABS_2H //declare vram1 wire [15:0] vram1_dout; -SRAM4k8_vram1_high VRAM1_HIGH +SRAM #(.aw( 12 ), .dw( 8 ), .simhexfile("init_vram1_high.txt")) +VRAM1_HIGH ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (vram_addr ), @@ -595,7 +606,8 @@ SRAM4k8_vram1_high VRAM1_HIGH .i_RD_n (VRTIME ) ); -SRAM4k8_vram1_low VRAM1_LOW +SRAM #(.aw( 12 ), .dw( 8 ), .simhexfile("init_vram1_low.txt")) +VRAM1_LOW ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (vram_addr ), @@ -607,7 +619,8 @@ SRAM4k8_vram1_low VRAM1_LOW //declare vram2 wire [7:0] vram2_dout; -SRAM4k8_vram2 VRAM2_LOW +SRAM #(.aw( 12 ), .dw( 8 ), .simhexfile("init_vram2.txt")) +VRAM2_LOW ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (vram_addr ), @@ -653,28 +666,7 @@ wire [3:0] PR = vram1_dout[15:12]; wire [7:0] VCA; wire [13:0] __REF_VCA_ORIGINAL = {tile_code, line_addr ^ {3{VVFF}}}; assign VCA = (CHAMPX2 == 1'b0) ? - { //RAS - tile_code[4], - tile_code[3], - tile_code[2], - tile_code[1], - tile_code[0], - line_addr[2] ^ VVFF, - line_addr[1] ^ VVFF, - line_addr[0] ^ VVFF - } : - { //CAS - 1'b1, - tile_code[10], - tile_code[9], - tile_code[8], - tile_code[7], - tile_code[6], - tile_code[5], - 1'b1 - }; - - + {tile_code[4:0], line_addr[2:0] ^ {3{VVFF}}} : {1'b1, tile_code[10:5], 1'b1}; //RAS : CAS @@ -686,7 +678,7 @@ assign VCA = (CHAMPX2 == 1'b0) ? //// // -// SPRITE NAMETABLE SECTION +// OBJRAM SECTION // //make objram address @@ -700,7 +692,8 @@ wire objram_wr = |{i_OBJRAM_n, i_CPU_RW, i_CPU_LDS_n, TIME2}; //LS32* //declare OBJRAM wire [7:0] objram_dout; -SRAM2k8_obj OBJRAM_LOW +SRAM #(.aw( 11 ), .dw( 8 ), .simhexfile("init_objram.txt")) +OBJRAM_LOW ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (objram_addr ), @@ -725,8 +718,7 @@ LOGIC373 OBJRAM_CPULATCH // SPRITE DMA SECTION // -wire dma = ~&{ABS_128V, ABS_64V, ABS_32V, ~ABS_16V}; //16C NAND; vcounter 480-495 - +//19G LS273 reg [7:0] obj_priority; always @(posedge i_EMU_MCLK) begin @@ -739,22 +731,107 @@ begin end end +//17G LS374 reg [7:0] obj_attr; always @(posedge i_EMU_MCLK) begin if(!o_EMU_CLK6MPCEN_n) begin - if(ABS_1H == 1'b0) //posedge of 1H + if(ABS_1H == 1'b1) //posedge of /px1 begin obj_attr <= objram_dout; end end end +//make objtable address +wire [2:0] ORA; +wire [10:0] objtable_addr; +assign objtable_addr = (DMA_n == 1'b0) ? + {obj_priority, ABS_8H, ABS_4H, ABS_2H} : + {OBJ, ORA}; +//make objtable_wr +wire objtable_wr = ~(ABS_1H & ~DMA_n); + +//declare objtable ram +wire [7:0] objtable_dout; +SRAM #(.aw( 11 ), .dw( 8 )) +OBJTABLE +( + .i_MCLK (i_EMU_MCLK ), + .i_ADDR (objtable_addr ), + .i_DIN (obj_attr ), + .o_DOUT (objtable_dout ), + .i_WR_n (objtable_wr ), + .i_RD_n (1'b0 ) +); +// +// asic section +// + +wire [7:0] OCA; +wire CHAOV; +reg OBJHL; + +wire [7:0] FA, FB; +wire XA7, XB7; +wire OBJBUF_CAS; + +wire WRTIME2; +wire COLORLATCH_n; +wire XPOS_D0; +wire PIXELLATCH_WAIT_n; +wire LATCH_A_D2; +wire [2:0] PIXELSEL; + + +//declare K005295 core +K005295 #(.__ENABLE_DOUBLE_HEIGHT_MODE(1'b0), .__SAVE_FRAMEBUFFER_CAPACITY(1'b1)) +K005295_main +( + .i_EMU_MCLK (i_EMU_MCLK ), + .i_EMU_CLK6MPCEN_n (o_EMU_CLK6MPCEN_n ), + + .i_DMA_n (DMA_n ), + .i_VBLANKH_n (VBLANKH_n ), + .i_VBLANK_n (VBLANK_n ), + .i_HBLANK_n (HBLANK_n ), + .i_ABS_4H (ABS_4H ), + .i_ABS_2H (ABS_2H ), + .i_ABS_1H (ABS_1H ), + .i_CHAMPX (CHAMPX2 ), + .i_OBJWR (OBJWR ), + + .i_FLIP (i_HFLIP ), + + .i_OBJDATA (objtable_dout ), + .o_ORA (ORA ), + + .o_CAS (OBJBUF_CAS ), + + .o_FA (FA ), + .o_FB (FB ), + + .o_XA7 (XA7 ), + .o_XB7 (XB7 ), + + .i_OBJHL (OBJHL ), + .o_CHAOV (CHAOV ), + .o_ORINC (ORINC ), + + .o_WRTIME2 (WRTIME2 ), + .o_COLORLATCH_n (COLORLATCH_n ), + .o_XPOS_D0 (XPOS_D0 ), + .o_PIXELLATCH_WAIT_n (PIXELLATCH_WAIT_n ), + .o_LATCH_A_D2 (LATCH_A_D2 ), + .o_PIXELSEL (PIXELSEL ), + + .o_OCA (OCA ) +); @@ -799,31 +876,11 @@ wire [7:0] cpu_addr; assign cpu_addr = (i_CHACS_n == 1'b1) ? refresh_addr : (CHAMPX2 == 1'b0) ? - { //RAS - i_CPU_ADDR[8], //A9 - i_CPU_ADDR[7], //A8 - i_CPU_ADDR[6], //A7 - i_CPU_ADDR[5], //A6 - i_CPU_ADDR[4], //A5 - i_CPU_ADDR[3], //A4 - i_CPU_ADDR[2], //A3 - i_CPU_ADDR[1] //A2 - } : - { //CAS - 1'b1, //HIGH - i_CPU_ADDR[14], //A15 - i_CPU_ADDR[13], //A14 - i_CPU_ADDR[12], //A13 - i_CPU_ADDR[11], //A12 - i_CPU_ADDR[10], //A11 - i_CPU_ADDR[9], //A10 - 1'b1 //HIGH - }; + i_CPU_ADDR[8:1] : {1'b1, i_CPU_ADDR[14:9], 1'b1}; //RAS(A9-A2) : CAS(1, A15-A10, 1) //LS157*2 11A/B MUX wire [7:0] gfx_addr; -assign gfx_addr = VCA; -//assign gfx_addr = (CHAOV_n == 1'b0) ? VCA : OCA; +assign gfx_addr = (CHAOV == 1'b0) ? OCA : VCA; //LS157*2 10A/B MUX wire [7:0] charram_addr; @@ -836,7 +893,7 @@ assign charram_addr = (~ABS_2H == 1'b0) ? gfx_addr : cpu_addr; //RAS/CAS wire charram_ras_n = ~CHAMPX; -reg charram_cas_n = 1'b1; //54.25ns delayed RAS +reg charram_cas_n = 1'b1; //54.25ns delayed RAS, same as CHAMPX2 always @(posedge i_EMU_MCLK) begin if(!i_EMU_CLK18MNCEN_n) @@ -870,13 +927,15 @@ wire charram2_rd = ~charram2_rw; //disables output when reading wire charram1u_wr = charramu_en | charram1_rw; wire charram1l_wr = charraml_en | charram1_rw; wire charram2u_wr = charramu_en | charram2_rw; -wire charram2l_wr = charramu_en | charram2_rw; +wire charram2l_wr = charraml_en | charram2_rw; //declare charram wire [15:0] charram1_dout; //A1=0 wire [15:0] charram2_dout; //A1=1 -DRAM16k4_charram_px0 CHARRAM_PX0 //6B +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px0.txt")) +CHARRAM_PX0 //6B ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -887,7 +946,10 @@ DRAM16k4_charram_px0 CHARRAM_PX0 //6B .i_WR_n (charram1u_wr ), .i_RD_n (charram1_rd ) ); -DRAM16k4_charram_px1 CHARRAM_PX1 //6A + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px1.txt")) +CHARRAM_PX1 //6A ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -898,7 +960,10 @@ DRAM16k4_charram_px1 CHARRAM_PX1 //6A .i_WR_n (charram1u_wr ), .i_RD_n (charram1_rd ) ); -DRAM16k4_charram_px2 CHARRAM_PX2 //2B + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px2.txt")) +CHARRAM_PX2 //2B ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -909,7 +974,10 @@ DRAM16k4_charram_px2 CHARRAM_PX2 //2B .i_WR_n (charram1l_wr ), .i_RD_n (charram1_rd ) ); -DRAM16k4_charram_px3 CHARRAM_PX3 //2A + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px3.txt")) +CHARRAM_PX3 //2A ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -920,7 +988,10 @@ DRAM16k4_charram_px3 CHARRAM_PX3 //2A .i_WR_n (charram1l_wr ), .i_RD_n (charram1_rd ) ); -DRAM16k4_charram_px4 CHARRAM_PX4 //7B + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px4.txt")) +CHARRAM_PX4 //7B ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -931,7 +1002,10 @@ DRAM16k4_charram_px4 CHARRAM_PX4 //7B .i_WR_n (charram2u_wr ), .i_RD_n (charram2_rd ) ); -DRAM16k4_charram_px5 CHARRAM_PX5 //7A + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px5.txt")) +CHARRAM_PX5 //7A ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -942,7 +1016,10 @@ DRAM16k4_charram_px5 CHARRAM_PX5 //7A .i_WR_n (charram2u_wr ), .i_RD_n (charram2_rd ) ); -DRAM16k4_charram_px6 CHARRAM_PX6 //4B + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px6.txt")) +CHARRAM_PX6 //4B ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -953,7 +1030,10 @@ DRAM16k4_charram_px6 CHARRAM_PX6 //4B .i_WR_n (charram2l_wr ), .i_RD_n (charram2_rd ) ); -DRAM16k4_charram_px7 CHARRAM_PX7 //4A + +DRAM #(.dw( 4 ), .aw( 8 ), .rw( 8 ), .cw( 6 ), .ctop( 6 ), .cbot( 1 ), + .simhexfile("init_charram_px7.txt")) +CHARRAM_PX7 //4A ( .i_MCLK (i_EMU_MCLK ), .i_ADDR (charram_addr ), @@ -1028,6 +1108,128 @@ K005290 K005290_main +/////////////////////////////////////////////////////////// +////// K005294 +//// + +wire TILELINELATCH_n = ~(ABS_1H & ABS_2H); +wire [7:0] DA; +wire [7:0] DB; + + +K005294 K005294_main +( + .i_EMU_MCLK (i_EMU_MCLK ), + .i_EMU_CLK6MPCEN_n (o_EMU_CLK6MPCEN_n ), + + .i_GFXDATA ({charram1_dout, charram2_dout}), + .i_OC (objtable_dout[4:1] ), + + .i_TILELINELATCH_n (TILELINELATCH_n ), + + .o_DA (DA ), + .o_DB (DB ), + + .i_WRTIME2 (WRTIME2 ), + .i_COLORLATCH_n (COLORLATCH_n ), + .i_XPOS_D0 (XPOS_D0 ), + .i_PIXELLATCH_WAIT_n (PIXELLATCH_WAIT_n ), + .i_LATCH_A_D2 (LATCH_A_D2 ), + .i_PIXELSEL (PIXELSEL ) +); + + + + + + +/////////////////////////////////////////////////////////// +////// FRAME BUFFER +//// + + +reg DFF_18H_A; +always @(posedge i_EMU_MCLK) +begin + if(!o_EMU_CLK6MPCEN_n) + begin + DFF_18H_A <= WRTIME2; + end +end + +reg DFF_18H_B; +always @(posedge i_EMU_MCLK) +begin + if(!o_EMU_CLK6MNCEN_n) //negative edge of CLK6M + begin + DFF_18H_B <= DFF_18H_A; + end +end + +wire wrtime2_buf_ras_n = DFF_18H_A & ~DFF_18H_B; //21H LS08 AND +wire objbuf_ras_n = (OBJWR == 1'b0) ? ~CHAMPX : wrtime2_buf_ras_n; //13H LS157 + + + +reg DFF_17H_B; +always @(posedge i_EMU_MCLK) +begin + if(!o_EMU_CLK6MPCEN_n) //positive edge of CLK6M + begin + DFF_17H_B <= DFF_18H_A; + end +end + +wire wrtime2_buf_we_n = __REF_CLK6M | ~DFF_17H_B; //14H LS32 OR +wire objbuf_we_n = (OBJWR == 1'b0) ? OBJCLRWE : wrtime2_buf_we_n; //13H LS157 + + + +reg objbuf_ras_dly_n; + +always @(posedge i_EMU_MCLK) +begin + OBJHL <= ~objbuf_ras_n; + + objbuf_ras_dly_n <= objbuf_ras_n; +end + + +wire evenbuf_overwrite_disable = ~(~XA7 & |{DA[3:0]}); +wire [7:0] evenbuf_dout; +wire [7:0] evenbuf_din = (OBJCLR == 1'b1) ? 8'h00 : + (evenbuf_overwrite_disable == 1'b0) ? DA : evenbuf_dout; + +wire oddbuf_overwrite_disable = ~(~XB7 & |{DB[3:0]}); +wire [7:0] oddbuf_dout; +wire [7:0] oddbuf_din = (OBJCLR == 1'b1) ? 8'h00 : + (oddbuf_overwrite_disable == 1'b0) ? DB : oddbuf_dout; + + +//EVEN +DRAM #(.dw( 8 ), .aw( 8 ), .init( 1 )) +EVENBUF +( + .i_MCLK (i_EMU_MCLK), .i_ADDR (FA), + .i_DIN (evenbuf_din), .o_DOUT (evenbuf_dout), + .i_RAS_n (objbuf_ras_n), .i_CAS_n (~OBJBUF_CAS), .i_WR_n (objbuf_we_n), .i_RD_n (1'b0) +); + + +//ODD +DRAM #(.dw( 8 ), .aw( 8 ), .init( 1 )) +ODDBUF +( + .i_MCLK (i_EMU_MCLK), .i_ADDR (FB), + .i_DIN (oddbuf_din), .o_DOUT (oddbuf_dout), + .i_RAS_n (objbuf_ras_n), .i_CAS_n (~OBJBUF_CAS), .i_WR_n (objbuf_we_n), .i_RD_n (1'b0) +); + + + + + + /////////////////////////////////////////////////////////// ////// K005293 @@ -1057,7 +1259,7 @@ K005293 K005293_main .i_A_PIXEL (A_PIXEL ), .i_B_PIXEL (B_PIXEL ), - .i_OBJBUF_DATA (16'h0000 ), + .i_OBJBUF_DATA ({oddbuf_dout, evenbuf_dout}), .i_A_TRN_n (A_TRN_n ), .i_B_TRN_n (B_TRN_n ), @@ -1077,8 +1279,6 @@ K005293 K005293_main - - /////////////////////////////////////////////////////////// ////// DATA OUTPUT MUX //// diff --git a/BubSysROM_core_ModelSim/wave.do b/BubSysROM_core_ModelSim/wave.do index bed2d6d..ab990a0 100644 --- a/BubSysROM_core_ModelSim/wave.do +++ b/BubSysROM_core_ModelSim/wave.do @@ -1,94 +1,91 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate /BubSysROM_video_tb/main/i_EMU_MCLK -add wave -noupdate /BubSysROM_video_tb/main/__REF_CLK9M -add wave -noupdate /BubSysROM_video_tb/main/__REF_CLK6M -add wave -noupdate -radix unsigned {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[2]} -add wave -noupdate -radix unsigned {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[1]} -add wave -noupdate /BubSysROM_video_tb/main/K005290_main/ABS_2H_dl -add wave -noupdate -radix unsigned {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[0]} -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VCLK -add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/K005292_main/vertical_counter -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_HBLANK_n -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VBLANK_n -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VBLANKH_n -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_FRAMEPARITY -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_VSYNC_n -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/o_CSYNC_n -add wave -noupdate /BubSysROM_video_tb/main/TIME1 -add wave -noupdate /BubSysROM_video_tb/main/TIME2 -add wave -noupdate /BubSysROM_video_tb/main/CHAMPX -add wave -noupdate /BubSysROM_video_tb/main/VRTIME -add wave -noupdate /BubSysROM_video_tb/main/OBJCLRWE -add wave -noupdate /BubSysROM_video_tb/main/OBJRW -add wave -noupdate /BubSysROM_video_tb/main/OBJCLR -add wave -noupdate /BubSysROM_video_tb/main/BLK -add wave -noupdate -radix unsigned -childformat {{{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[8]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[7]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[6]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[5]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[4]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[3]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[2]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[1]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[0]} -radix unsigned}} -subitemconfig {{/BubSysROM_video_tb/main/K005292_main/horizontal_counter[8]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[7]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[6]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[5]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[4]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[3]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[2]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[1]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/horizontal_counter[0]} {-height 15 -radix unsigned}} /BubSysROM_video_tb/main/K005292_main/horizontal_counter -add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_video_tb/main/scrollram_addr[10]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[9]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[8]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[7]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[6]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[5]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[4]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[3]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[2]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[1]} -radix hexadecimal} {{/BubSysROM_video_tb/main/scrollram_addr[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_video_tb/main/scrollram_addr[10]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[9]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[8]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[7]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[6]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[5]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[4]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[3]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[2]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[1]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/scrollram_addr[0]} {-height 15 -radix hexadecimal}} /BubSysROM_video_tb/main/scrollram_addr -add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/scrollram_dout -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005291_main/TMA_HSCROLL_VALUE -add wave -noupdate /BubSysROM_video_tb/main/K005291_main/o_SHIFTA1 -add wave -noupdate /BubSysROM_video_tb/main/K005291_main/o_SHIFTA2 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005291_main/TMB_HSCROLL_VALUE -add wave -noupdate /BubSysROM_video_tb/main/K005291_main/o_SHIFTB -add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/K005291_main/TMAB_VSCROLL_VALUE -add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[11]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[10]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[9]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[8]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[7]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[6]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[5]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[4]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[3]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[2]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[1]} -radix hexadecimal} {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[11]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[10]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[9]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[8]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[7]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[6]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[5]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[4]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[3]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[2]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[1]} {-height 15 -radix hexadecimal} {/BubSysROM_video_tb/main/K005291_main/o_VRAMADDR[0]} {-height 15 -radix hexadecimal}} /BubSysROM_video_tb/main/K005291_main/o_VRAMADDR -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/tile_code -add wave -noupdate /BubSysROM_video_tb/main/VVFF -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005291_main/o_TILELINEADDR -add wave -noupdate -radix decimal /BubSysROM_video_tb/main/__REF_VCA_ORIGINAL -add wave -noupdate /BubSysROM_video_tb/main/CHAMPX2 -add wave -noupdate /BubSysROM_video_tb/main/VCA -add wave -noupdate /BubSysROM_video_tb/main/charram_ras_n -add wave -noupdate /BubSysROM_video_tb/main/charram_cas_n -add wave -noupdate -radix decimal /BubSysROM_video_tb/main/CHARRAM_PX0/__ADDR -add wave -noupdate /BubSysROM_video_tb/main/charram1_rd -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/charram1_dout -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/charram2_dout -add wave -noupdate /BubSysROM_video_tb/main/__REF_CLK6M -add wave -noupdate /BubSysROM_video_tb/main/K005290_main/pixel7_n -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_LINELATCH -add wave -noupdate /BubSysROM_video_tb/main/K005290_main/i_A_MODE -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_PIXEL_DELAY1 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_PIXEL_DELAY2 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/A_PIXEL_DELAY3 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/o_A_PIXEL -add wave -noupdate /BubSysROM_video_tb/main/K005290_main/pixel3_n -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/B_LINELATCH -add wave -noupdate /BubSysROM_video_tb/main/K005290_main/i_B_MODE -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005290_main/o_B_PIXEL -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/PR -add wave -noupdate /BubSysROM_video_tb/main/VHFF -add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/VC -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY1 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY2 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY3 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/A_PROPERTY_DELAY4 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/B_PROPERTY_DELAY1 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/B_PROPERTY_DELAY2 -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/B_PROPERTY_DELAY3 -add wave -noupdate /BubSysROM_video_tb/main/K005293_main/a_pr -add wave -noupdate /BubSysROM_video_tb/main/K005293_main/b_pr -add wave -noupdate /BubSysROM_video_tb/main/K005293_main/priority_mode -add wave -noupdate /BubSysROM_video_tb/main/K005293_main/transparency -add wave -noupdate /BubSysROM_video_tb/main/K005293_main/layer -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/i_A_PIXEL -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/i_B_PIXEL -add wave -noupdate /BubSysROM_video_tb/main/K005293_main/a_palette -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/b_palette -add wave -noupdate -radix hexadecimal /BubSysROM_video_tb/main/K005293_main/o_CD -add wave -noupdate /BubSysROM_video_tb/main/ABS_8H -add wave -noupdate /BubSysROM_video_tb/main/ABS_4H -add wave -noupdate /BubSysROM_video_tb/main/ABS_2H -add wave -noupdate /BubSysROM_video_tb/main/ABS_1H -add wave -noupdate -radix unsigned /BubSysROM_video_tb/main/K005292_main/horizontal_counter -add wave -noupdate -radix unsigned -childformat {{{/BubSysROM_video_tb/main/K005292_main/vertical_counter[8]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[7]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[6]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[5]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[4]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[3]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[2]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[1]} -radix unsigned} {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[0]} -radix unsigned}} -expand -subitemconfig {{/BubSysROM_video_tb/main/K005292_main/vertical_counter[8]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[7]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[6]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[5]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[4]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[3]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[2]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[1]} {-height 15 -radix unsigned} {/BubSysROM_video_tb/main/K005292_main/vertical_counter[0]} {-height 15 -radix unsigned}} /BubSysROM_video_tb/main/K005292_main/vertical_counter -add wave -noupdate /BubSysROM_video_tb/main/dma -add wave -noupdate /BubSysROM_video_tb/main/K005292_main/__REF_DMA_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_HBLANK_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_VBLANK_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_VBLANKH_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_ABS_4H +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_ABS_2H +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_ABS_1H +add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJCLR +add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJWR +add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJCLRWE +add wave -noupdate /BubSysROM_top_tb/main/video_main/CHAMPX +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/buffer_frame_parity +add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/OBJ +add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/ORA +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/objtable_addr +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/objtable_dout +add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M +add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/sprite_engine_state +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/drawing_status +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hzoom_acc +add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005295_main/xpos_cnt_dly_n[1]} +add wave -noupdate -color {Blue Violet} -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/TILELINE_ADDR +add wave -noupdate -color {Blue Violet} -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/HLINE_ADDR +add wave -noupdate -color Cyan -radix unsigned -childformat {{{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[7]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[6]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[5]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[4]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[3]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[2]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[1]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[0]} -radix unsigned}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[7]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[6]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[5]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[4]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[3]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[2]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[1]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter[0]} {-color Cyan -height 15 -radix unsigned}} /BubSysROM_top_tb/main/video_main/K005295_main/evenbuffer_xpos_counter +add wave -noupdate -color Cyan -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/oddbuffer_xpos_counter +add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005295_main/ypos_cnt_dly_n[3]} +add wave -noupdate -color {Blue Violet} -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/VTILE_ADDR +add wave -noupdate -color Cyan -radix unsigned -childformat {{{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[7]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[6]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[5]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[4]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[3]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[2]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[1]} -radix unsigned} {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[0]} -radix unsigned}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[7]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[6]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[5]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[4]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[3]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[2]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[1]} {-color Cyan -height 15 -radix unsigned} {/BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter[0]} {-color Cyan -height 15 -radix unsigned}} /BubSysROM_top_tb/main/video_main/K005295_main/buffer_ypos_counter +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/x_out_of_screen +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/y_out_of_screen +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hsize_parity +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/oddsize_wrtime0 +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/evensize_wrtime0 +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/o_PIXELLATCH_WAIT_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/CHAOV +add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[13]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[12]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[11]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[10]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[9]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[8]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[7]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[6]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[5]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[4]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[3]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[2]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[1]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[13]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[12]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[11]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[10]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[9]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[8]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[7]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[6]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[5]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[4]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[3]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[2]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[1]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR[0]} {-height 15 -radix hexadecimal}} /BubSysROM_top_tb/main/video_main/K005295_main/CHARRAM_ADDR +add wave -noupdate -radix hexadecimal -childformat {{{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[13]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[12]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[11]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[10]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[9]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[8]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[7]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[6]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[5]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[4]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[3]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[2]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[1]} -radix hexadecimal} {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[0]} -radix hexadecimal}} -subitemconfig {{/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[13]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[12]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[11]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[10]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[9]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[8]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[7]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[6]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[5]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[4]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[3]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[2]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[1]} {-height 15 -radix hexadecimal} {/BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR[0]} {-height 15 -radix hexadecimal}} /BubSysROM_top_tb/main/video_main/CHARRAM_PX1/ADDR +add wave -noupdate /BubSysROM_top_tb/main/video_main/CHARRAM_PX3/i_RAS_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/CHARRAM_PX3/i_CAS_n +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/i_GFXDATA +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/i_TILELINELATCH_n +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_TILELINELATCH +add wave -noupdate /BubSysROM_top_tb/main/video_main/COLORLATCH_n +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_PALETTE +add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hsize_parity +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/pixellatch_wait_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/PIXELLATCH_WAIT_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/WRTIME2 +add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005294_main/wrtime2_dly[1]} +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/hzoom_acc +add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/PIXELSEL +add wave -noupdate -radix unsigned {/BubSysROM_top_tb/main/video_main/K005294_main/pixelsel_dly[3]} +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005294_main/pixellatch_n +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_PIXEL_LATCHED +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/OBJ_PIXEL_UNLATCHED +add wave -noupdate -color Coral -radix unsigned /BubSysROM_top_tb/main/video_main/XPOS_D0 +add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/buffer_x_screencounter +add wave -noupdate -radix unsigned /BubSysROM_top_tb/main/video_main/K005295_main/buffer_y_screencounter +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005295_main/EVENBUFFER_ADDR +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005295_main/ODDBUFFER_ADDR +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/EVENBUF/ADDR +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/ODDBUF/ADDR +add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005294_main/pixellatch_wait_dly[2]} +add wave -noupdate {/BubSysROM_top_tb/main/video_main/K005294_main/pixellatch_wait_dly[3]} +add wave -noupdate /BubSysROM_top_tb/main/video_main/K005295_main/i_EMU_MCLK +add wave -noupdate -color Magenta -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/o_DA +add wave -noupdate -color Magenta -radix hexadecimal /BubSysROM_top_tb/main/video_main/K005294_main/o_DB +add wave -noupdate /BubSysROM_top_tb/main/video_main/objbuf_ras_n +add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJBUF_CAS +add wave -noupdate /BubSysROM_top_tb/main/video_main/objbuf_we_n +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/evenbuffer_din +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/oddbuffer_din +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/evenbuffer_dout +add wave -noupdate -radix hexadecimal /BubSysROM_top_tb/main/video_main/oddbuffer_dout +add wave -noupdate /BubSysROM_top_tb/main/video_main/evenbuffer_overwrite_disable +add wave -noupdate /BubSysROM_top_tb/main/video_main/oddbuffer_overwrite_disable +add wave -noupdate /BubSysROM_top_tb/main/video_main/i_EMU_MCLK +add wave -noupdate /BubSysROM_top_tb/main/video_main/__REF_CLK6M +add wave -noupdate /BubSysROM_top_tb/main/video_main/ABS_1H +add wave -noupdate /BubSysROM_top_tb/main/video_main/o_BLK +add wave -noupdate /BubSysROM_top_tb/main/video_main/OBJWR TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {5273950 ns} 0} +WaveRestoreCursors {{Cursor 1} {6539470 ns} 0} quietly wave cursor active 1 -configure wave -namecolwidth 179 +configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 1 @@ -102,4 +99,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1025200 ns} {6261840 ns} +WaveRestoreZoom {29998270 ns} {30000100 ns} diff --git a/README.md b/README.md index 8864992..c31ce4c 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,2 @@ -# MiSTer_BubSysROM_core -Bubble System ROM core for MiSTer FPGA +# ikacore_BubSysROM +Bubble System revised ROM version core for MiSTer FPGA diff --git a/GX400_datasplitter/GX400_datasplitter.cpp b/resources/GX400_datasplitter/GX400_datasplitter.cpp similarity index 100% rename from GX400_datasplitter/GX400_datasplitter.cpp rename to resources/GX400_datasplitter/GX400_datasplitter.cpp diff --git a/GX400_datasplitter/GX400_datasplitter.exe b/resources/GX400_datasplitter/GX400_datasplitter.exe similarity index 100% rename from GX400_datasplitter/GX400_datasplitter.exe rename to resources/GX400_datasplitter/GX400_datasplitter.exe diff --git a/resources/waveform_captures.zip b/resources/waveform_captures.zip new file mode 100644 index 0000000..300a879 Binary files /dev/null and b/resources/waveform_captures.zip differ