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Updates for v2.1 board

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This commit is contained in:
Philip Smart
2020-07-29 13:46:31 +01:00
parent 7c657c8f40
commit 585b047e08
19 changed files with 4246 additions and 896 deletions
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6
.gitignore vendored
View File

@@ -27,6 +27,7 @@
*.pof
*.qdf
*.srf
*.swo
c5_pin_model_dump.txt
build/db/
build/incremental_db/
@@ -124,4 +125,7 @@ schematics/tranZPUter-SW/
schematics/tranZPUter/
software/asm/.cbiosII.asm.swo
software/roms/SA1510.orig
CPLD/build/tranZPUterSW_constraints.sdc.clk
CPLD/tranZPUterSW.vhd.clk
CPLD/tranZPUterSW.vhd.presweep
software/asm/include/Definitions.asm.swo

29
CPLD/build/tranZPUterSW.qsf
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@@ -116,8 +116,6 @@ set_location_assignment PIN_128 -to CTLCLK
set_location_assignment PIN_45 -to CTL_M1n
set_location_assignment PIN_55 -to CTL_BUSACKn
set_location_assignment PIN_70 -to CTL_BUSRQn
set_location_assignment PIN_37 -to TZ_BUSACKn
set_location_assignment PIN_34 -to ENIOWAIT
set_location_assignment PIN_32 -to Z80_MEM[4]
set_location_assignment PIN_42 -to Z80_MEM[3]
set_location_assignment PIN_44 -to Z80_MEM[2]
@@ -125,15 +123,18 @@ set_location_assignment PIN_40 -to Z80_MEM[1]
set_location_assignment PIN_39 -to Z80_MEM[0]
set_location_assignment PIN_36 -to CFG_MZ80A
set_location_assignment PIN_35 -to CFG_MZ700
set_location_assignment PIN_30 -to TBA[0]
set_location_assignment PIN_29 -to TBA[1]
set_location_assignment PIN_28 -to TBA[2]
set_location_assignment PIN_27 -to TBA[3]
set_location_assignment PIN_26 -to TBA[4]
set_location_assignment PIN_25 -to TBA[5]
set_location_assignment PIN_23 -to TBA[6]
set_location_assignment PIN_22 -to TBA[7]
set_location_assignment PIN_21 -to TBA[8]
# Spare connected pins to be assigned if needed.
#set_location_assignment PIN_30 -to TBA[0]
#set_location_assignment PIN_29 -to TBA[1]
#set_location_assignment PIN_28 -to TBA[2]
#set_location_assignment PIN_27 -to TBA[3]
#set_location_assignment PIN_26 -to TBA[4]
#set_location_assignment PIN_25 -to TBA[5]
#set_location_assignment PIN_23 -to TBA[6]
#set_location_assignment PIN_22 -to TBA[7]
#set_location_assignment PIN_21 -to TBA[8]
#set_location_assignment PIN_37 -to TBA[9]
#set_location_assignment PIN_34 -to TBA[10]
# Z80 Control signals.
# ====================
@@ -167,3 +168,9 @@ set_global_assignment -name SDC_FILE tranZPUterSW_constraints.sdc
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF

230
CPLD/build/tranZPUterSW_constraints.sdc
View File

@@ -38,9 +38,16 @@ set_time_format -unit ns -decimal_places 3
# Create Clock
#**************************************************************
# Standard mainboard clock. If using tranZPUter on a different host then set to the host frequency.
create_clock -name {SYSCLK} -period 500.000 -waveform { 0.000 250.000 } [get_ports { SYSCLK }]
#create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
# For K64F
create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [ get_ports { CTLCLK }]
# For basic board with oscillator.
#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }]
#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ]
##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
#**************************************************************
@@ -65,110 +72,113 @@ create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_port
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CFG_MZ80A}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CFG_MZ700}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {SYS_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {SYS_WAITn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_HALTn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_M1n}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RESETn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RFSHn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_WRn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CFG_MZ80A}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CFG_MZ700}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_CLKSLCT}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_HALTn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_M1n}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_RFSHn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {ENIOWAIT}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_CSn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_OEn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_WEn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SVCREQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SYSREQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SYS_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {TZ_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_BUSRQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_CLK}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[0]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[1]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[2]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[3]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[4]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[5]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[6]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[7]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[8]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[9]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[10]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[14]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[0]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[1]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[2]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[3]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[4]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_INTn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_WRn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_CLKSLCT}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYSREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[4]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[5]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[6]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[7]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[8]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[9]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[10]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[14]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[4]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WRn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RDn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}]
# For K64F
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}]
# For basic board with oscillator.
#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}]
#**************************************************************
# Set Clock Groups
@@ -180,6 +190,23 @@ set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z8
# Set False Path
#**************************************************************
# For K64F
set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}]
set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For basic board with oscillator.
#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}]
#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For both configurations.
set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[4]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[3]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[2]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[1]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[0]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
#**************************************************************
@@ -187,7 +214,6 @@ set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z8
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************

784
CPLD/tranZPUterSW.vhd
View File

File diff suppressed because it is too large Load Diff

12
CPLD/tranZPUterSW_Toplevel.vhd
View File

@@ -66,8 +66,6 @@ entity tranZPUterSW is
CTL_WAITn : in std_logic;
SVCREQn : out std_logic;
SYSREQn : out std_logic;
TZ_BUSACKn : out std_logic;
ENIOWAIT : out std_logic;
Z80_MEM : out std_logic_vector(4 downto 0);
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
@@ -90,10 +88,10 @@ entity tranZPUterSW is
-- Mode signals.
CFG_MZ80A : in std_logic;
CFG_MZ700 : in std_logic;
CFG_MZ700 : in std_logic
-- Reserved.
TBA : in std_logic_vector(8 downto 0)
--TBA : in std_logic_vector(10 downto 0)
-- JTAG / ISP
--TCK : in std_logic;
@@ -143,8 +141,6 @@ begin
CTL_WAITn => CTL_WAITn,
SVCREQn => SVCREQn,
SYSREQn => SYSREQn,
TZ_BUSACKn => TZ_BUSACKn,
ENIOWAIT => ENIOWAIT,
Z80_MEM => Z80_MEM,
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
@@ -167,10 +163,10 @@ begin
-- Mode signals.
CFG_MZ80A => CFG_MZ80A,
CFG_MZ700 => CFG_MZ700,
CFG_MZ700 => CFG_MZ700
-- Reserved.
TBA => TBA
--TBA => TBA
);
end architecture;

14
CPLD/tranZPUterSW_pkg.vhd
View File

@@ -34,6 +34,17 @@ use ieee.numeric_std.all;
use ieee.math_real.all;
package tranZPUterSW_pkg is
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
@@ -59,9 +70,6 @@ package tranZPUterSW_pkg is
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
------------------------------------------------------------
-- Records
------------------------------------------------------------

3303
software/asm/1Z-013A-KM.asm Normal file
View File

File diff suppressed because it is too large Load Diff

728
software/asm/1Z-013A.asm
View File

@@ -146,11 +146,11 @@ QER: CP 02H ; A=02H
JR Z,ST1
LD DE,MSGE1 ; CHECK SUM ERROR
RST 18H ; CALL MSGX
L010F: JR ST1
L010F: JR ST1
; LOAD COMMAND
LOAD: CALL QRDI
LOAD: CALL QRDI
JR C,QER
LOA0: CALL NL
LD DE,MSGQ2 ; LOADING
@@ -2374,382 +2374,386 @@ DACN1: OR A
;
; KEY MATRIX TO DISPLAY CODE TABL
;
KTBL: ;S0 00 - 07 ;
DB 0F0H ; NULL
DB 0F0H ; NULL
DB 040H ; CURSOR DOWN
DB 0F0H ; NULL
DB 0F0H ; NULL
DB 04FH ; :
DB 02CH ; ;
DB 0CDH ; CR
;S1 08 - 0F ;
DB 022H ; 2
DB 021H ; 1
DB 017H ; W
DB 011H ; Q
DB 001H ; A
DB 0C7H ; DEL
DB 000H ; NULL
DB 01AH ; Z
;S2 10 - 17 ;
DB 024H ; 4
DB 023H ; 3
DB 012H ; R
DB 005H ; E
DB 004H ; D
DB 013H ; S
DB 018H ; X
DB 003H ; C
;S3 18 - 1F ;
DB 026H ; 6
DB 025H ; 5
DB 019H ; Y
DB 014H ; T
DB 007H ; G
DB 006H ; F
DB 016H ; V
DB 002H ; B
;S4 20 - 27 ;
DB 028H ; 8
DB 027H ; 7
DB 009H ; I
DB 015H ; U
DB 00AH ; J
DB 008H ; H
DB 00EH ; N
DB 000H ; SPACE
;S5 28 - 2F ;
DB 020H ; 0
DB 029H ; 9
DB 010H ; P
DB 00FH ; O
DB 00CH ; L
DB 00BH ; K
DB 02FH ; ,
DB 00DH ; M
;S6 30 - 37 ;
DB 0BEH ; ^
DB 02AH ; -
DB 052H ; [
DB 055H ; @
DB 04FH ; :
DB 02CH ; ;
DB 02DH ; /
DB 02EH ; .
;S7 38 - 3F ;
DB 0C5H ; HOME
DB 059H ; \
DB 0C3H ; CURSOR RIGHT
DB 0C2H ; CURSOR UP
DB 0CDH ; CR
DB 054H ; ]
DB 000H ; NULL
DB 049H ; ?
KTBL:
;S0 00 - 07
DB 0BFH ; SPARE
DB 0CAH ; GRAPH
DB 58H ;
DB 0C9H ; ALPHA
DB 0F0H ; NO
DB 2CH ; ;
DB 4FH ; :
DB 0CDH ; CR
;S1 08 - 0F
DB 19H ; Y
DB 1AH ; Z
DB 55H ; @
DB 52H ; [
DB 54H ; ]
DB 0F0H ; NULL
DB 0F0H ; NULL
DB 0F0H ; NULL
;S2 10 - 17
DB 11H ; Q
DB 12H ; R
DB 13H ; S
DB 14H ; T
DB 15H ; U
DB 16H ; V
DB 17H ; W
DB 18H ; X
;S3 18 - 1F
DB 09H ; I
DB 0AH ; J
DB 0BH ; K
DB 0CH ; L
DB 0DH ; M
DB 0EH ; N
DB 0FH ; O
DB 10H ; P
;S4 20 - 27
DB 01H ; A
DB 02H ; B
DB 03H ; C
DB 04H ; D
DB 05H ; E
DB 06H ; F
DB 07H ; G
DB 08H ; H
;S5 28 - 2F
DB 21H ; 1
DB 22H ; 2
DB 23H ; 3
DB 24H ; 4
DB 25H ; 5
DB 26H ; 6
DB 27H ; 7
DB 28H ; 8
;S6 30 - 37
DB 59H ; \
DB 50H ;
DB 2AH ; -
DB 00H ; SPACE
DB 20H ; 0
DB 29H ; 9
DB 2FH ; ,
DB 2EH ; .
;S7 38 - 3F
DB 0C8H ; INST.
DB 0C7H ; DEL.
DB 0C2H ; CURSOR UP
DB 0C1H ; CURSOR DOWN
DB 0C3H ; CURSOR RIGHT
DB 0C4H ; CURSOR LEFT
DB 49H ; ?
DB 2DH ; /
;
;
; KTBL SHIFT ON
;
KTBLS: ;S0 00 - 07
DB 0F0H ; NULL
DB 0F0H ; NULL
DB 040H ; CURSOR DOWN
DB 0F0H ; NULL
DB 0F0H ; NULL
DB 04FH ; :
DB 02CH ; ;
DB 0CDH ; CR
;S1 08 - 0F
DB 062H ; "
DB 061H ; !
DB 097H ; w
DB 091H ; q
DB 081H ; a
DB 0C8H ; INSERT
DB 000H ; NULL
DB 09AH ; z
;S2 10 - 17
DB 064H ; $
DB 063H ; #
DB 092H ; r
DB 085H ; e
DB 084H ; d
DB 093H ; s
DB 098H ; x
DB 083H ; c
;S3 18 - 1F ;
DB 066H ; &
DB 065H ; %
DB 099H ; y
DB 094H ; t
DB 087H ; g
DB 086H ; f
DB 096H ; v
DB 082H ; b
;S4 20 - 27
DB 068H ; (
DB 067H ; '
DB 089H ; i
DB 095H ; u
DB 08AH ; j
DB 088H ; h
DB 08EH ; n
DB 000H ; SPACE
;S5 28 - 2F
DB 0BFH ; _
DB 069H ; )
DB 090H ; p
DB 08FH ; o
DB 08CH ; l
DB 08BH ; k
DB 051H ; <
DB 08DH ; m
;S6 30 - 37
DB 0A5H ; ~
DB 02BH ; =
DB 0BCH ; (
DB 0A4H ; '
DB 06BH ; #
DB 06AH ; +
DB 045H ; <-
DB 057H ; >
;S7 38 - 3F
DB 0C6H ; CLR
DB 080H ; |
DB 0C4H ; CURSOR LEFT
DB 0C1H ; CURSOR DOWN
DB 0CDH ; CR
DB 040H ; )
DB 000H ; NULL
DB 050H ; UP^
KTBLS:
;S0 00 - 07
DB 0BFH ; SPARE
DB 0CAH ; GRAPH
DB 1BH ; POND
DB 0C9H ; ALPHA
DB 0F0H ; NO
DB 6AH ; +
DB 6BH ; *
DB 0CDH ; CR
;S1 08 - 0F
DB 99H ; y
DB 9AH ; z
DB 0A4H ; `
DB 0BCH ; {
DB 40H ; }
DB 0F0H ; NULL
DB 0F0H ; NULL
DB 0F0H ; NULL
;S2 10 - 17
DB 91H ; q
DB 92H ; r
DB 93H ; s
DB 94H ; t
DB 95H ; u
DB 96H ; v
DB 97H ; w
DB 98H ; x
;S3 18 - 1F
DB 89H ; i
DB 8AH ; j
DB 8BH ; k
DB 8CH ; l
DB 8DH ; m
DB 8EH ; n
DB 8FH ; o
DB 90H ; p
;S4 20 - 27
DB 81H ; a
DB 82H ; b
DB 83H ; c
DB 84H ; d
DB 85H ; e
DB 86H ; f
DB 87H ; g
DB 88H ; h
;S5 28 - 2F
DB 61H ; !
DB 62H ; "
DB 63H ; #
DB 64H ; $
DB 65H ; %
DB 66H ; &
DB 67H ; '
DB 68H ; (
;S6 30 - 37
DB 80H ; \
DB 0A5H ; POND MARK
DB 2BH ; YEN
DB 00H ; SPACE
DB 60H ;
DB 69H ; )
DB 51H ; <
DB 57H ; >
;S7 38 - 3F
DB 0C6H ; CLR
DB 0C5H ; HOME
DB 0C2H ; CURSOR UP
DB 0C1H ; CURSOR DOWN
DB 0C3H ; CURSOR RIGHT
DB 0C4H ; CURSOR LEFT
DB 5AH ;
DB 45H ;
;
;
; GRAPHIC
;
KTBLG: ;S0 00 - 07 ; ;S0 00 - 07
DB 03EH ; DB 0BFH ; SPARE
DB 037H ; DB 0F0H ; GRAPH BUT NULL
DB 038H ; DB 0E5H ; #
DB 03CH ; DB 0C9H ; ALPHA
DB 053H ; DB 0F0H ; NO
DB 0C7H ; DB 42H ; # ;
DB 000H ; DB 0B6H ; #:
DB 076H ; DB 0CDH ; CR
;S1 08 - 0F ; ;S1 08 - 0F
DB 03EH ; #2
DB 037H ; #1
DB 038H ; #W
DB 03CH ; #Q
DB 053H ; #A
DB 0C7H ; #DEL
DB 000H ; #NULL
DB 076H ; #Z
;S2 10 - 17
DB 07BH ; #4
DB 07FH ; #3
DB 030H ; #R
DB 034H ; #E
DB 047H ; #D
DB 044H ; #S
DB 06DH ; #X
DB 0DEH ; #C
;S3 18 - 1F
DB 05EH ; #6
DB 03AH ; #5
DB 075H ; #Y
DB 071H ; #T
DB 04BH ; #G
DB 04AH ; #F
DB 0DAH ; #V
DB 06FH ; #B
;S4 20 - 27
DB 0BDH ; #8
DB 01FH ; #7
DB 07DH ; #I
DB 079H ; #U
DB 05CH ; #J
DB 072H ; #H
DB 032H ; #N
DB 000H ; SPACE
;S5 28 - 2F
DB 09CH ; #0
DB 0A1H ; #9
DB 0D6H ; #P
DB 0B0H ; #O
DB 0B4H ; #L
DB 05BH ; #K
DB 060H ; #,
DB 01CH ; #M
;S6 30 - 37
DB 09EH ; #^
DB 0D2H ; #-
DB 0D8H ; #[
DB 0B2H ; #@
DB 0B6H ; ##:
DB 042H ; #;
DB 0DBH ; #/
DB 0B8H ; #.
;S7 38 - 3F
DB 0C5H ; HOME
DB 0D4H ; #\
DB 0C3H ; CURSOR RIGHT
DB 0C2H ; CURSOR UP
DB 0CDH ; CR
DB 04EH ; #J
DB 000H ; NULL
DB 0BAH ; #?
KTBLGS:
;S0 00 - 07
DB 0BFH ; SPARE
DB 0F0H ; GRAPH BUT NULL
DB 0E5H ; #
DB 0C9H ; ALPHA
DB 0F0H ; NO
DB 42H ; # ;
DB 0B6H ; #:
DB 0CDH ; CR
;S1 08 - 0F
DB 75H ; #Y
DB 76H ; #Z
DB 0B2H ; #@
DB 0D8H ; #[
DB 4EH ; #]
DB 0F0H ; #NULL
DB 0F0H ; #NULL
DB 0F0H ; #NULL
;S2 10 - 17
DB 3CH ; #Q
DB 30H ; #R
DB 44H ; #S
DB 71H ; #T
DB 79H ; #U
DB 0DAH ; #V
DB 38H ; #W
DB 6DH ; #X
;S3 18 - 1F
DB 7DH ; #I
DB 5CH ; #J
DB 5BH ; #K
DB 0B4H ; #L
DB 1CH ; #M
DB 32H ; #N
DB 0B0H ; #O
DB 0D6H ; #P
;S4 20 - 27
DB 53H ; #A
DB 6FH ; #B
DB 0DEH ; #C
DB 47H ; #D
DB 34H ; #E
DB 4AH ; #F
DB 4BH ; #G
DB 72H ; #H
;S5 28 - 2F
DB 37H ; #1
DB 3EH ; #2
DB 7FH ; #3
DB 7BH ; #4
DB 3AH ; #5
DB 5EH ; #6
DB 1FH ; #7
DB 0BDH ; #8
;S6 30 - 37
DB 0D4H ; #YEN
DB 9EH ; #+
DB 0D2H ; #-
DB 00H ; SPACE
DB 9CH ; #0
DB 0A1H ; #9
DB 0CAH ; #,
DB 0B8H ; #.
;S7 38 - 3F
DB 0C8H ; INST
DB 0C7H ; DEL.
DB 0C2H ; CURSOR UP
DB 0C1H ; CURSOR DOWN
DB 0C3H ; CURSOR RIGHT
DB 0C4H ; CURSOR LEFT
DB 0BAH ; #?
DB 0DBH ; #/
;
;
; CONTROL CODE
;
KTBLGS: ;S0 00 - 07 ; ;S0 00 - 07
DB 036H ; DB 0F0H
DB 03FH ; DB 0F0H
DB 078H ; DB 0F0H ; ^
DB 07CH ; DB 0F0H
DB 046H ; DB 0F0H
DB 0C8H ; DB 0F0H
DB 000H ; DB 0F0H
DB 077H ; DB 0F0H
;S1 08 - 0F ; ;S1 08 - 0F
DB 036H ; ?2
DB 03FH ; ?1
DB 078H ; ?W
DB 07CH ; ?Q
DB 046H ; ?A
DB 0C8H ; INST
DB 000H ; NULL
DB 077H ; ?Z
;S2 10 - 17
DB 03BH ; ?4
DB 07EH ; ?3
DB 070H ; ?R
DB 074H ; ?E
DB 048H ; ?D
DB 041H ; ?S
DB 0DDH ; ?X
DB 0D9H ; C
;S3 18 - 1F
DB 01EH ; ?6
DB 07AH ; ?5
DB 035H ; ?Y
DB 031H ; ?T
DB 04CH ; ?G
DB 043H ; ?F
DB 0A6H ; ?V
DB 06EH ; ?B
;S4 20 - 27
DB 0A2H ; ?8
DB 05FH ; ?7
DB 03DH ; ?I
DB 039H ; ?U
DB 05DH ; ?J
DB 073H ; ?H
DB 033H ; ?N
DB 000H ; SPACE
;S5 28 - 2F
DB 09DH ; ?0
DB 0A3H ; ?9
DB 0B1H ; ?P
DB 0D5H ; ?O
DB 056H ; ?L
DB 06CH ; ?K
DB 0D0H ; ?,
DB 01DH ; ?M
;S6 30 - 37
DB 09FH ; ?^
DB 0D1H ; ?-
DB 0B3H ; ?[
DB 0D7H ; ?@
DB 04DH ; ?:
DB 0B5H ; ?;
DB 01BH ; ?/
DB 0B9H ; ?.
KTBLC:
;S0 00 - 07
DB 0F0H
DB 0F0H
DB 0F0H ; ^
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
;S1 08 - 0F
DB 0F0H ; ^Y E3
DB 5AH ; ^Z E4 (CHECKER)
DB 0F0H ; ^@
DB 0F0H ; ^[ EB/E5
DB 0F0H ; ^] EA/E7
DB 0F0H ; #NULL
DB 0F0H ; #NULL
DB 0F0H ; #NULL
;S2 10 - 17
DB 0C1H ; ^Q
DB 0C2H ; ^R
DB 0C3H ; ^S
DB 0C4H ; ^T
DB 0C5H ; ^U
DB 0C6H ; ^V
DB 0F0H ; ^W E1
DB 0F0H ; ^X E2
;S3 18 - 1F
DB 0F0H ; ^I F9
DB 0F0H ; ^J FA
DB 0F0H ; ^K FB
DB 0F0H ; ^L FC
DB 0F0H ; ^M CD
DB 0F0H ; ^N FE
DB 0F0H ; ^O FF
DB 0F0H ; ^P E0
;S4 20 - 27
DB 0F0H ; ^A F1
DB 0F0H ; ^B F2
DB 0F0H ; ^C F3
DB 0F0H ; ^D F4
DB 0F0H ; ^E F5
DB 0F0H ; ^F F6
DB 0F0H ; ^G F7
DB 0F0H ; ^H F8
;S5 28 - 2F
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
;S6 30 - 37 (ERROR? 7 VALUES ONLY!!)
DB 0F0H ; ^YEN E6
DB 0F0H ; ^ EF
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H ; ^,
DB 0F0H
;S7 38 - 3F
DB 0C6H ; CLR
DB 0D3H ; ?\
DB 0C4H ; CURSOR RIGHT
DB 0C1H ; CURSOR UP
DB 0CDH ; CR
DB 0B7H ; ?J
DB 000H ; NULL
DB 0BBH ; ??
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H ; ^/ EE
;
;
; KANA
;
KTBLC: ;S0 00 - 07 ; ;S0 00 - 07
DB 0F0H ; DB 0BFH ; SPARE
DB 0F0H ; DB 0F0H ; GRAPH BUT NULL
DB 0E2H ; DB 0CFH ; NIKO WH.
DB 0C1H ; DB 0C9H ; ALPHA
DB 0E0H ; DB 0F0H ; NO
DB 0F0H ; DB 0B5H ; MO
DB 000H ; DB 4DH ; DAKU TEN
DB 0E5H ; DB 0CDH ; CR
;S1 08 - 0F ; ;S1 08 - 0F
DB 0F0H ; CODE 80H=NOT KEY
DB 0F0H ;
DB 0E2H ; CTRL + W
DB 0C1H ; CTRL + Q
DB 0E0H ; CTRL + A SHIFT LOCK
DB 0F0H ;
DB 000H ;
DB 0E5H ; CTRL + Z
;S2 10 - 17 ; ;S2 10 - 17
DB 0F0H ;
DB 0F0H ;
DB 0C2H ; CTRL + R
DB 0CFH ; CTRL + E ROLL DOWN
DB 0CEH ; CTRL + D ROLL UP
DB 0C3H ; CTRL + S
DB 0E3H ; CTRL + X
DB 0F3H ; CTRL + C
;S3 18 - 1F ; ;S3 18 - 1F
DB 0F0H ;
DB 0F0H ;
DB 0E4H ; CTRL + Y
DB 0C4H ; CTRL + T
DB 0F7H ; CTRL + G
DB 0F6H ; CTRL + F
DB 0C6H ; CTRL + V CLR
DB 0F2H ; CTRL + B
;S4 20 - 27 ; ;S4 20 - 27
DB 0F0H ;
DB 0F0H ;
DB 0F9H ; CTRL + I
DB 0C5H ; CTRL + U HOME
DB 0FAH ; CTRL + J
DB 0F8H ; CTRL + H
DB 0FEH ; CTRL + N
DB 0F0H ;
;S5 28 - 2F ; ;S5 28 - 2F
DB 0F0H ;
DB 0F0H ;
DB 0E1H ; CTRL + P
DB 0FFH ; CTRL + O
DB 0FCH ; CTRL + L
DB 0FBH ; CTRL + K
DB 0F0H ;
DB 0FDH ; CTRL + M
;S6 30 - 37 ; ;S6 30 - 37
DB 0EFH ; CTRL + ^
DB 0F4H ; CTRL + -
DB 0E6H ; CTRL + [
DB 0CCH ; CTRL + @ REVERSE
DB 0F0H ;
DB 0F0H ;
DB 0F0H ;
DB 0F0H ;
;S7 38 - 3F ; ;S7 38 - 3F
DB 0F0H ;
DB 0EBH ; CTRL + \
DB 0F0H ;
DB 0F0H ;
DB 0F0H ;
DB 0EEH ; CTRL + ]
DB 0F0H ;
KTBLG:
;S0 00 - 07
DB 0BFH ; SPARE
DB 0F0H ; GRAPH BUT NULL
DB 0CFH ; NIKO WH.
DB 0C9H ; ALPHA
DB 0F0H ; NO
DB 0B5H ; MO
DB 4DH ; DAKU TEN
DB 0CDH ; CR
;S1 08 - 0F
DB 35H ; HA
DB 77H ; TA
DB 0D7H ; WA
DB 0B3H ; YO
DB 0B7H ; HANDAKU
DB 0F0H
DB 0F0H
DB 0F0H
;S2 10 - 17
DB 7CH ; KA
DB 70H ; KE
DB 41H ; SHI
DB 31H ; KO
DB 39H ; HI
DB 0A6H ; TE
DB 78H ; KI
DB 0DDH ; CHI
;S3 18 - 1F
DB 3DH ; FU
DB 5DH ; MI
DB 6CH ; MU
DB 56H ; ME
DB 1DH ; RHI
DB 33H ; RA
DB 0D5H ; HE
DB 0B1H ; HO
;S4 20 - 27
DB 46H ; SA
DB 6EH ; TO
DB 0D9H ; THU
DB 48H ; SU
DB 74H ; KU
DB 43H ; SE
DB 4CH ; SO
DB 73H ; MA
;S5 28 - 2F
DB 3FH ; A
DB 36H ; I
DB 7EH ; U
DB 3BH ; E
DB 7AH ; O
DB 1EH ; NA
DB 5FH ; NI
DB 0A2H ; NU
;S6 30 - 37
DB 0D3H ; YO
DB 9FH ; YU
DB 0D1H ; YA
DB 00H ; SPACE
DB 9DH ; NO
DB 0A3H ; NE
DB 0D0H ; RU
DB 0B9H ; RE
;S7 38 - 3F
DB 0C6H ; ?CLR
DB 0C5H ; ?HOME
DB 0C2H ; ?CURSOR UP
DB 0C1H ; ?CURSOR DOWN
DB 0C3H ; ?CURSOR RIGHT
DB 0C4H ; ?CURSOR LEFT
DB 0BBH ; DASH
DB 0BEH ; RO
; MEMORY DUMP COMMAND "D"

6
software/asm/include/TZFS_Definitions.asm
View File

@@ -194,6 +194,12 @@ CPLDCFG EQU 06EH ; Versi
CPLDSTATUS EQU 06EH ; Version 2.1 CPLD status register.
CPLDINFO EQU 06FH ; Version 2.1 CPLD version information register.
;-----------------------------------------------
; CPLD Configuration constants.
;-----------------------------------------------
SET_MODE_MZ80A EQU 1 ; Set to original unmodified hardware.
SET_MODE_MZ700 EQU 2 ; Map keyboard and memory mode settings to MZ700 mode.
;-----------------------------------------------
; tranZPUter SW Memory Management modes
;-----------------------------------------------

7
software/asm/monitor_1Z-013A-KM.asm Normal file
View File

@@ -0,0 +1,7 @@
; Configurable parameters.
COLW: EQU 40 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 0
INCLUDE "1Z-013A-KM.asm"

7
software/asm/monitor_80c_1Z-013A-KM.asm Normal file
View File

@@ -0,0 +1,7 @@
; Configurable parameters.
COLW: EQU 80 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 1
INCLUDE "1Z-013A-KM.asm"

12
software/asm/tzfs.asm
View File

@@ -533,21 +533,27 @@ SETMODE80: LD A, 128
LD A,TZSVC_CMD_LOAD80BIOS ; Request the I/O processor loads the SA1510 80column BIOS into memory.
JR SETBIOS
; Commands to switch into MZ-700 compatible mode. This involves loading the original (but patched for keyboard use) 1Z-013A BIOS
; and changing the frequency, also enabling of additional traps to detect and change memory mode.
; Commands to switch into MZ-700 compatible mode. This involves loading the original (but patched for keyboard use for v1.1) 1Z-013A BIOS
; and changing the frequency, and on the v1.1 board also enabling of additional traps to detect and change memory mode which are catered for in
; hardware on v2+ boards..
SETMODE700: LD A, 0
LD (DSPCTL), A
LD (SCRNMODE),A ; 0 = 40char mode on reset.
;
LD A,SET_MODE_MZ700
OUT (CPLDCFG),A ; Set the CPLD compatibility mode.
LD A,TZSVC_CMD_LOAD700BIOS40 ; Request the I/O processor loads the MZ700 1Z-013A 40column BIOS into memory.
JR SETBIOS
SETMODE7008:LD A, 128
LD (DSPCTL), A
LD A,1
LD (SCRNMODE),A
LD A,SET_MODE_MZ700
OUT (CPLDCFG),A ; Set the CPLD compatibility mode.
LD A,TZSVC_CMD_LOAD700BIOS80 ; Request the I/O processor loads the SA1510 80column BIOS into memory.
JR SETBIOS
; Command to switch into the Sharp MZ-80B compatible mode. This involves loading the IPL, switching
; the frequency to 4MHz and enabling of additional traps to detect and change memory mode.
SETMODE80B: LD A, 128

2
software/asm/tzfs_bank2.asm
View File

@@ -350,7 +350,9 @@ HELPSCR: ; "--------- 40 column width -------------"
DB "700 - Select MZ-700 Mode.", 00DH
DB "7008 - Select MZ-700 80 col Mode.", 00DH
DB "B - toggle keyboard bell.", 00DH
DB "BASIC - Load BASIC SA-5510.", 00DH
DB "C[b] - clear memory $1200-$D000.", 00DH
DB "CPM - Load CPM.", 00DH
DB "DXXXX[YYYY] - dump mem XXXX to YYYY.", 00DH
DB "EC[fn]- erase file, fn=No or Filename", 00DH
DB "F[x] - boot fd drive x.", 00DH

BIN
software/roms/monitor_1Z-013A-KM.rom Normal file
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BIN
software/roms/monitor_1Z-013A.rom
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BIN
software/roms/monitor_80c_1Z-013A-KM.rom Normal file
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BIN
software/roms/monitor_80c_1Z-013A.rom
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BIN
software/roms/tzfs.rom
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2
software/tools/assemble_roms.sh
View File

@@ -32,7 +32,7 @@ ROOTDIR=../../tranZPUter
TOOLDIR=${ROOTDIR}/software/tools
JARDIR=${ROOTDIR}/software/tools
ASM=glass-0.5.jar
BUILDROMLIST="MZ80AFI monitor_SA1510 monitor_80c_SA1510 monitor_1Z-013A monitor_80c_1Z-013A MZ80B_IPL"
BUILDROMLIST="MZ80AFI monitor_SA1510 monitor_80c_SA1510 monitor_1Z-013A monitor_80c_1Z-013A monitor_1Z-013A-KM monitor_80c_1Z-013A-KM MZ80B_IPL"
#BUILDMZFLIST="hi-ramcheck sharpmz-test"
BUILDMZFLIST="BASIC sharpmz-test"
ASMDIR=${ROOTDIR}/software/asm