From 585b047e0873e0349eff2f23f4b33a4a149ce3dc Mon Sep 17 00:00:00 2001 From: Philip Smart Date: Wed, 29 Jul 2020 13:46:31 +0100 Subject: [PATCH] Updates for v2.1 board --- .gitignore | 6 +- CPLD/build/tranZPUterSW.qsf | 29 +- CPLD/build/tranZPUterSW_constraints.sdc | 230 +- CPLD/tranZPUterSW.vhd | 784 +++-- CPLD/tranZPUterSW_Toplevel.vhd | 12 +- CPLD/tranZPUterSW_pkg.vhd | 14 +- software/asm/1Z-013A-KM.asm | 3303 +++++++++++++++++++++ software/asm/1Z-013A.asm | 728 ++--- software/asm/include/TZFS_Definitions.asm | 6 + software/asm/monitor_1Z-013A-KM.asm | 7 + software/asm/monitor_80c_1Z-013A-KM.asm | 7 + software/asm/tzfs.asm | 12 +- software/asm/tzfs_bank2.asm | 2 + software/roms/monitor_1Z-013A-KM.rom | Bin 0 -> 4096 bytes software/roms/monitor_1Z-013A.rom | Bin 4096 -> 4096 bytes software/roms/monitor_80c_1Z-013A-KM.rom | Bin 0 -> 4096 bytes software/roms/monitor_80c_1Z-013A.rom | Bin 4096 -> 4096 bytes software/roms/tzfs.rom | Bin 18432 -> 18432 bytes software/tools/assemble_roms.sh | 2 +- 19 files changed, 4246 insertions(+), 896 deletions(-) create mode 100644 software/asm/1Z-013A-KM.asm create mode 100644 software/asm/monitor_1Z-013A-KM.asm create mode 100644 software/asm/monitor_80c_1Z-013A-KM.asm create mode 100644 software/roms/monitor_1Z-013A-KM.rom create mode 100644 software/roms/monitor_80c_1Z-013A-KM.rom diff --git a/.gitignore b/.gitignore index 31f0a0d..68f4ff2 100644 --- a/.gitignore +++ b/.gitignore @@ -27,6 +27,7 @@ *.pof *.qdf *.srf +*.swo c5_pin_model_dump.txt build/db/ build/incremental_db/ @@ -124,4 +125,7 @@ schematics/tranZPUter-SW/ schematics/tranZPUter/ software/asm/.cbiosII.asm.swo software/roms/SA1510.orig - +CPLD/build/tranZPUterSW_constraints.sdc.clk +CPLD/tranZPUterSW.vhd.clk +CPLD/tranZPUterSW.vhd.presweep +software/asm/include/Definitions.asm.swo diff --git a/CPLD/build/tranZPUterSW.qsf b/CPLD/build/tranZPUterSW.qsf index 88045bf..3d0fb55 100644 --- a/CPLD/build/tranZPUterSW.qsf +++ b/CPLD/build/tranZPUterSW.qsf @@ -116,8 +116,6 @@ set_location_assignment PIN_128 -to CTLCLK set_location_assignment PIN_45 -to CTL_M1n set_location_assignment PIN_55 -to CTL_BUSACKn set_location_assignment PIN_70 -to CTL_BUSRQn -set_location_assignment PIN_37 -to TZ_BUSACKn -set_location_assignment PIN_34 -to ENIOWAIT set_location_assignment PIN_32 -to Z80_MEM[4] set_location_assignment PIN_42 -to Z80_MEM[3] set_location_assignment PIN_44 -to Z80_MEM[2] @@ -125,15 +123,18 @@ set_location_assignment PIN_40 -to Z80_MEM[1] set_location_assignment PIN_39 -to Z80_MEM[0] set_location_assignment PIN_36 -to CFG_MZ80A set_location_assignment PIN_35 -to CFG_MZ700 -set_location_assignment PIN_30 -to TBA[0] -set_location_assignment PIN_29 -to TBA[1] -set_location_assignment PIN_28 -to TBA[2] -set_location_assignment PIN_27 -to TBA[3] -set_location_assignment PIN_26 -to TBA[4] -set_location_assignment PIN_25 -to TBA[5] -set_location_assignment PIN_23 -to TBA[6] -set_location_assignment PIN_22 -to TBA[7] -set_location_assignment PIN_21 -to TBA[8] +# Spare connected pins to be assigned if needed. +#set_location_assignment PIN_30 -to TBA[0] +#set_location_assignment PIN_29 -to TBA[1] +#set_location_assignment PIN_28 -to TBA[2] +#set_location_assignment PIN_27 -to TBA[3] +#set_location_assignment PIN_26 -to TBA[4] +#set_location_assignment PIN_25 -to TBA[5] +#set_location_assignment PIN_23 -to TBA[6] +#set_location_assignment PIN_22 -to TBA[7] +#set_location_assignment PIN_21 -to TBA[8] +#set_location_assignment PIN_37 -to TBA[9] +#set_location_assignment PIN_34 -to TBA[10] # Z80 Control signals. # ==================== @@ -167,3 +168,9 @@ set_global_assignment -name SDC_FILE tranZPUterSW_constraints.sdc set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name AUTO_RESOURCE_SHARING OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF diff --git a/CPLD/build/tranZPUterSW_constraints.sdc b/CPLD/build/tranZPUterSW_constraints.sdc index be75629..9523b8a 100644 --- a/CPLD/build/tranZPUterSW_constraints.sdc +++ b/CPLD/build/tranZPUterSW_constraints.sdc @@ -38,9 +38,16 @@ set_time_format -unit ns -decimal_places 3 # Create Clock #************************************************************** +# Standard mainboard clock. If using tranZPUter on a different host then set to the host frequency. create_clock -name {SYSCLK} -period 500.000 -waveform { 0.000 250.000 } [get_ports { SYSCLK }] -#create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] -create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] + +# For K64F +create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [ get_ports { CTLCLK }] + +# For basic board with oscillator. +#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }] +#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ] +##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }] #************************************************************** @@ -65,110 +72,113 @@ create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_port # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CFG_MZ80A}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CFG_MZ700}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_BUSACKn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_BUSRQn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_WAITn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {SYS_BUSRQn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {SYS_WAITn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[0]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[1]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[2]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[3]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[4]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[5]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[6]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[7]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[8]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[9]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[10]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[11]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[12]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[13]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[14]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[15]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_BUSACKn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[0]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[1]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[2]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[3]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[4]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[5]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[6]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[7]}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_HALTn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_IORQn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_M1n}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_MREQn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RESETn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RFSHn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_WRn}] -set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RDn}] - - - +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CFG_MZ80A}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CFG_MZ700}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSACKn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[0]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[1]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[2]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[3]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[4]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[5]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[6]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[7]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[8]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[9]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[10]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[11]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[12]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[13]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[14]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[15]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[0]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[1]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[2]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[3]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[4]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[5]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[6]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[7]}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}] +set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}] #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_CLKSLCT}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_HALTn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_M1n}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_RFSHn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {ENIOWAIT}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_CSn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_OEn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_WEn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SVCREQn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SYSREQn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SYS_BUSACKn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {TZ_BUSACKn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[11]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[12]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[13]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VMEM_CSn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_BUSRQn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_CLK}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[0]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[1]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[2]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[3]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[4]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[5]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[6]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[7]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[0]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[1]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[2]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[3]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[4]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[5]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[6]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[7]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[8]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[9]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[10]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[11]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[12]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[13]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[14]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[15]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[15]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[0]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[1]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[2]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[3]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[4]}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_WAITn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_INTn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MREQn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_WRn}] -set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_RDn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_CLKSLCT}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYSREQn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[11]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[12]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[13]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VMEM_CSn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[0]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[1]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[2]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[3]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[4]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[5]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[6]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[7]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[0]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[1]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[2]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[3]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[4]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[5]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[6]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[7]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[8]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[9]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[10]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[11]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[12]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[13]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[14]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[15]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[15]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[0]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[1]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[2]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[3]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[4]}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WRn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RDn}] +set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}] + +# For K64F +set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}] + +# For basic board with oscillator. +#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}] + #************************************************************** # Set Clock Groups @@ -180,6 +190,23 @@ set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z8 # Set False Path #************************************************************** +# For K64F +set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}] +set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For basic board with oscillator. +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}] +#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] +#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}] + +# For both configurations. +set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[4]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[3]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[2]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[1]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} +set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[0]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} #************************************************************** @@ -187,7 +214,6 @@ set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z8 #************************************************************** - #************************************************************** # Set Maximum Delay #************************************************************** diff --git a/CPLD/tranZPUterSW.vhd b/CPLD/tranZPUterSW.vhd index 77f8e7d..f95b967 100644 --- a/CPLD/tranZPUterSW.vhd +++ b/CPLD/tranZPUterSW.vhd @@ -13,15 +13,23 @@ -- History: June 2020 - Initial creation. -- July 2020 - Updated and fixed logic, removed the MZ80B compatibility logic as there -- are not enough resources in the CPLD to fully implement. --- July 2020 - Changed the keyboard mapping logic to be more compatible. A scan is made --- periodically of the underlying keyboard and the key data is stored in --- the key matrix. When the running software accesses the keyboard it reads +-- July 2020 - Changed the keyboard mapping logic to be more compatible. A full swepp +-- is made if a read is made to the keyboard data twice in a row as this +-- signifies a game or program reading BREAK. When the software scans the +-- keyboard the data is stored into a matrix which is then used for mapping +-- of the keys. When the running software accesses the keyboard it reads -- from the key matrix and not the PPI. This allows for better compatibility -- and a functioning SHIFT+BREAK key. The MZ80A keyboard layout is mapped -- as though the keyboard was a real MZ700 keyboard, ie. BREAK key is CLR/HOME -- and INST/DEL is CTRL etc. The numeric keypad on the MZ80A is mapped to the -- cursor key layout with 7 and 9 acting as INST/DEL. The function keys are -- mapped to 1, 0, 00, . and 3 on the numeric keypad. +-- July 2020 - Making RFS updates I decided that a basic board (ie. no K64F) which would +-- be used in conjunction with the RFS board needs a secondary clock, +-- more especially for the MZ700 3.58MHz mode. I thus added a 50MHz clock +-- onto the output that would normally be driven by a K64F. This output +-- is then divided down to act as the secondary clock. When a mode switch +-- is made to MZ700 mode the frequency automatically changes. -- -- --------------------------------------------------------------------------------------------------------- @@ -80,8 +88,6 @@ entity cpld512 is CTL_WAITn : in std_logic; SVCREQn : out std_logic; SYSREQn : out std_logic; - TZ_BUSACKn : out std_logic; - ENIOWAIT : out std_logic; Z80_MEM : out std_logic_vector(4 downto 0); -- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality. @@ -104,10 +110,10 @@ entity cpld512 is -- Mode signals. CFG_MZ80A : in std_logic; - CFG_MZ700 : in std_logic; + CFG_MZ700 : in std_logic -- Reserved. - TBA : in std_logic_vector(8 downto 0) + --TBA : in std_logic_vector(10 downto 0) ); end entity; @@ -122,7 +128,9 @@ architecture rtl of cpld512 is signal KEY_MATRIX : KeyMatrixType; signal KEYMAP_DATA : std_logic_vector(7 downto 0); signal KEY_STROBE : std_logic_vector(3 downto 0); + signal KEY_STROBE_LAST : std_logic_vector(3 downto 0); signal KEY_SUBSTITUTE : std_logic; + signal KEY_SWEEP : std_logic; signal MB_KEY_STROBE : std_logic_vector(3 downto 0); signal MB_WRITE_STROBE : std_logic; signal MB_READ_KEYS : std_logic; @@ -130,6 +138,7 @@ architecture rtl of cpld512 is -- CPLD configuration signals. signal MODE_MZ80A : std_logic; signal MODE_MZ700 : std_logic; + signal MODE_SWITCH : std_logic; signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- IO Decode signals. @@ -140,26 +149,22 @@ architecture rtl of cpld512 is signal SCK_RDn : std_logic := '0'; signal CPLD_CFGn : std_logic := '0'; signal CPLD_INFOn : std_logic := '0'; - signal MEM_MODE_LATCH : std_logic_vector(7 downto 0); + signal MEM_MODE_LATCH : std_logic_vector(4 downto 0); -- SR (LS279) state symbols. - signal SYSCLK_D : std_logic; signal SYSCLK_Q : std_logic; - signal CTLCLK_D : std_logic; signal CTLCLK_Q : std_logic; -- - signal TZ_BUSACKni : std_logic; signal DISABLE_BUSn : std_logic; - signal ENABLE_BUSn : std_logic; -- CPU Frequency select logic based on Flip Flops and gates. - signal CTL_CLKSLCTi : std_logic; signal SCK_CTLSELn : std_logic; signal Z80_CLKi : std_logic; + signal CTLCLKi : std_logic; -- Z80 Wait Insert generator when I/O ports in region > 0XE0 are accessed to give the K64F time to proces them. -- - --signal REQ_WAIT : std_logic; + --signal REQ_WAITn : std_logic; -- RAM select and write signals. signal RAM_OEni : std_logic; @@ -171,8 +176,10 @@ architecture rtl of cpld512 is signal MB_BUSRQn : std_logic; signal MB_ADDR : std_logic_vector(15 downto 0); signal MB_DATA : std_logic_vector(7 downto 0); - signal MB_DELAY : unsigned(15 downto 0); + signal MB_DELAY_TICKS : unsigned(11 downto 0); + signal MB_DELAY_MS : unsigned(7 downto 0); signal MB_STATE : integer range 0 to 7; + signal MB_WAITn : std_logic; function to_std_logic(L: boolean) return std_logic is begin @@ -189,45 +196,52 @@ begin -- The mode can be changed either by a Z80 transaction write into the register or setting of the external signals. The Z80 write is typically used -- by host software such as RFS, the external signals by the K64F I/O processor. -- - process( SYSCLK, Z80_RESETn, CPLD_CFGn, CPLD_INFOn, Z80_ADDR, Z80_DATA ) + MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CPLD_CFGn, CPLD_INFOn, Z80_ADDR, Z80_DATA ) begin if(Z80_RESETn = '0') then - MODE_MZ80A <= '1'; - MODE_MZ700 <= '0'; + MODE_MZ80A <= '1'; + MODE_MZ700 <= '0'; + MODE_SWITCH <= '0'; - elsif(SYSCLK'event and SYSCLK = '1') then - --- Potential, if RFS available, reset to correct mode. + elsif(Z80_CLKi'event and Z80_CLKi = '1') then -- Write to register. if(CPLD_CFGn = '0' and Z80_WRn = '0') then -- Set mode, default to MZ80A if no valid combination given. - MODE_MZ80A <= '0'; - MODE_MZ700 <= '0'; - if(Z80_DATA(2 downto 0) = "010") then - MODE_MZ700 <= '1'; - else - MODE_MZ80A <= '1'; - end if; - - -- Read current register settings. - elsif(CPLD_CFGn = '0' and Z80_RDn = '0') then - CPLD_CFG_DATA <= "000000" & MODE_MZ700 & MODE_MZ80A; - - -- Read version information. - elsif(CPLD_INFOn = '0' and Z80_RDn = '0') then - CPLD_CFG_DATA <= "1010" & std_logic_vector(to_unsigned(CPLD_VERSION, 4)); - + case Z80_DATA(2 downto 0) is + when "010" => + MODE_MZ700 <= '1'; + MODE_MZ80A <= '0'; + if MODE_MZ700 = '0' then + MODE_SWITCH <= '1'; + end if; + when others => + MODE_MZ80A <= '1'; + MODE_MZ700 <= '0'; + if MODE_MZ80A = '0' then + MODE_SWITCH <= '1'; + end if; + end case; else - null; + MODE_SWITCH <= '0'; end if; -- The external signals override the register settings if applied. -- if(CFG_MZ700 = '0' and CFG_MZ80A = '1') then MODE_MZ80A <= '1'; + + if MODE_MZ80A = '0' then + MODE_SWITCH <= '1'; + end if; + elsif(CFG_MZ700 = '1' and CFG_MZ80A = '0') then MODE_MZ700 <= '1'; + + if MODE_MZ700 = '0' then + MODE_SWITCH <= '1'; + end if; else null; end if; @@ -238,27 +252,25 @@ begin -- Memory mode latch. This latch stores the current memory mode (or Bank Paging Scheme) according to the running software. -- - process( SYSCLK, Z80_RESETn, MEM_CFGn, Z80_IORQn, Z80_ADDR, Z80_DATA ) + MEMORYMODE: process( Z80_CLKi, Z80_RESETn, MEM_CFGn, Z80_IORQn, Z80_WRn, Z80_ADDR, Z80_DATA ) variable mz700_LOWER_RAM : std_logic; variable mz700_UPPER_RAM : std_logic; variable mz700_INHIBIT : std_logic; begin if(Z80_RESETn = '0') then - --MEM_MODE_LATCH <= "00001000"; - MEM_MODE_LATCH <= "00000000"; + MEM_MODE_LATCH <= "00000"; mz700_LOWER_RAM := '0'; mz700_UPPER_RAM := '0'; mz700_INHIBIT := '0'; - elsif(SYSCLK'event and SYSCLK = '1') then + elsif (MEM_CFGn = '0' and Z80_WRn = '0') then + MEM_MODE_LATCH <= Z80_DATA(4 downto 0); - if(MEM_CFGn = '0' and Z80_WRn = '0') then - MEM_MODE_LATCH <= Z80_DATA; + elsif(Z80_CLKi'event and Z80_CLKi = '1') then -- Check for MZ700 Mode memory changes and adjust current memory mode setting. - elsif(MODE_MZ700 = '1' and Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 3) = "11100") then - + if(MODE_MZ700 = '1' and Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 3) = "11100") then -- MZ700 memory mode switch? -- 0x0000:0x0FFF 0xD000:0xFFFF @@ -323,7 +335,6 @@ begin else null; end if; - else null; end if; @@ -332,33 +343,48 @@ begin -- Process to map host keyboard to realise compatibility with other Sharp machines. -- Currently the host is the Sharp MZ-80A and a mapping exists for the MZ-700. - process( SYSCLK, Z80_RESETn, MEM_CFGn, Z80_IORQn, Z80_ADDR, Z80_DATA ) + KEYMAPPER: process( Z80_CLKi, Z80_RESETn, MEM_CFGn, Z80_IORQn, Z80_ADDR, Z80_DATA ) begin if Z80_RESETn = '0' then + KEY_SUBSTITUTE <= '0'; + KEY_SWEEP <= '0'; + MB_STATE <= 0; MB_BUSRQn <= '1'; MB_MREQn <= '1'; - MB_ADDR <= (others => '0'); - MB_DELAY <= (others => '1'); - MB_KEY_STROBE <= (others => '0'); MB_WRITE_STROBE <= '0'; MB_READ_KEYS <= '0'; - MB_STATE <= 0; + MB_WAITn <= '1'; + MB_ADDR <= (others => '0'); + MB_DELAY_TICKS <= (others => '1'); + MB_DELAY_MS <= (others => '0'); + MB_KEY_STROBE <= (others => '0'); KEY_STROBE <= (others => '0'); - KEY_SUBSTITUTE <= '0'; + KEY_STROBE_LAST <= (others => '0'); - elsif SYSCLK'event and SYSCLK = '1' then + elsif Z80_CLKi'event and Z80_CLKi = '1' then -- When inactive, wait for a Z80 I/O transaction that needs writeback. -- if MODE_MZ700 = '1' then - -- Configurable delay, halts all actions whilst the timer > 0. - if MB_DELAY /= 0 then - MB_DELAY <= MB_DELAY - 1; + -- Auto scanning state machine. When the MZ700 isnt scanning the keys this FSM scans them to be ready + -- to respond to events such as BREAK key detection. Normally the FSM wont run as the MZ700 scans the keys in + -- software but when the MZ700 runs some kinds of software the scans stop and occasionally the BREAK/SHIFT line 9 is scanned. + -- Under these circumstances the FSM will make a full sweep of the keys. + -- + -- Configurable delay, a tick by tick timer and a millisecond timer, halts all actions whilst the timer > 0. + if MB_DELAY_TICKS /= 0 or MB_DELAY_MS /= 0 then - -- If the Z80 Bus has not been requested, request it for the next transaction. - elsif MB_BUSRQn = '1' and KEY_SUBSTITUTE = '0' then + if MB_DELAY_TICKS = 0 and MB_DELAY_MS /= 0 then + MB_DELAY_TICKS <= X"DFC"; -- 1ms with a 3.58MHz clock. + MB_DELAY_MS <= MB_DELAY_MS - 1; + else + MB_DELAY_TICKS <= MB_DELAY_TICKS - 1; + end if; + + -- If the Z80 Bus has not been requested and we need to make a key sweep, request the bus and start the sweep. + elsif Z80_MREQn = '1' and MB_BUSRQn = '1' and KEY_SWEEP = '1' and KEY_SUBSTITUTE = '0' then MB_BUSRQn <= '0'; -- When the Z80 bus is available, run the FSM. @@ -366,7 +392,7 @@ begin -- Move along the state machine, next state can be overriden if required. -- - if MB_STATE = 5 then + if MB_STATE = 6 then MB_STATE <= 0; else MB_STATE <= MB_STATE+1; @@ -379,37 +405,42 @@ begin MB_ADDR <= X"E000"; MB_DATA <= "1111" & MB_KEY_STROBE; - -- Allow at least 2 cycles for the write pulse. + -- Allow at least 1 cycles for the MREQ signal to settle. when 1 => MB_MREQn <= '0'; + MB_DELAY_TICKS <= X"001"; + + -- Allow at least 1 cycle for the write pulse. + when 2 => MB_WRITE_STROBE <= '1'; - MB_DELAY <= X"0001"; + MB_DELAY_TICKS <= X"001"; -- Terminate write pulse. - when 2 => + when 3 => MB_MREQn <= '1'; MB_WRITE_STROBE <= '0'; -- Setup for a read of the key data from PPI B. - when 3 => + when 4 => MB_ADDR <= X"E001"; -- Allow at least 2 cycles for the data to become available. - when 4 => + when 5 => MB_MREQn <= '0'; MB_READ_KEYS <= '1'; - MB_DELAY <= X"0001"; + MB_DELAY_TICKS <= X"002"; -- Read the key data into the matrix for later mapping. - when 5 => + when 6 => KEY_MATRIX(to_integer(unsigned(MB_KEY_STROBE))) <= Z80_DATA; MB_MREQn <= '1'; MB_READ_KEYS <= '0'; - MB_DELAY <= X"0DFC"; -- 1ms delay between key sweeps with a 3.58MHz clock. - MB_BUSRQn <= '1'; if unsigned(MB_KEY_STROBE) = 9 then MB_KEY_STROBE <= (others => '0'); + MB_DELAY_MS <= X"32"; -- 50ms delay between key sweeps with a 3.58MHz clock to prevent excessive scanning. + KEY_SWEEP <= '0'; + MB_BUSRQn <= '1'; else MB_KEY_STROBE <= MB_KEY_STROBE + 1; end if; @@ -420,95 +451,136 @@ begin end if; - -- When the Z80 isnt tri-stated process normally. + -- When the Z80 isnt tri-stated process the memory operations and act on required triggers. -- if MB_BUSRQn = '1' and Z80_BUSACKn = '1' then - -- Detect a strobe output write and store it - this is used as the index into the key matrix for each read operation on the . + -- Detect a strobe output write and store it - this is used as the index into the key matrix for each read operation. if(Z80_MREQn = '0' and Z80_ADDR(15 downto 0) = X"E000") then - KEY_STROBE <= Z80_DATA(3 downto 0); + KEY_STROBE <= Z80_DATA(3 downto 0); end if; -- On a keyscan read data into the matrix and raise the substitue flag. This flag will disable the mainboard (tri-state it) so that the data lines are not driven. The mapped - -- data is the output on the data bus by the CPLD which the Z80 reads. + -- data is then output on the data bus by the CPLD which the Z80 reads. if(Z80_MREQn = '0' and Z80_ADDR(15 downto 0) = X"E001") then - if((unsigned(MEM_MODE_LATCH(4 downto 0)) = 2 or unsigned(MEM_MODE_LATCH(4 downto 0)) = 8 or (unsigned(MEM_MODE_LATCH(4 downto 0)) >= 10 and unsigned(MEM_MODE_LATCH(4 downto 0)) < 15))) then - KEY_SUBSTITUTE <= '1'; - MB_BUSRQn <= '1'; + + -- If this is the first loop, set a 1 cycle wait to allow us to read in the scanned data before overriding with the mapped data. The Z80 cycle is short so without the wait + -- we cant reliably read the data being output from the 8255. + if MB_WAITn = '1' and KEY_SUBSTITUTE = '0' then + MB_WAITn <= '0'; + MB_BUSRQn <= '1'; + else + -- 2nd cycle we release the WAIT state and override the data being output by the 8255 with the mapped equivalent. + MB_WAITn <= '1'; + KEY_SUBSTITUTE <= '1'; + + -- On the 2nd loop the data from the 8255 key scan has settled on the bus so can be captured. + if KEY_SUBSTITUTE = '0' then + KEY_MATRIX(to_integer(unsigned(KEY_STROBE))) <= Z80_DATA; + end if; + + -- Remember last key strobe as we need to detect a scan to the same row more than once, this is typically used for BREAK detection or single key detection. + -- In these cases we make an automated sweep of the entire keyboard as keys on the host are spread out on different strobe lines whereas the machine we are mapping to + -- has them on one strobe line. + KEY_STROBE_LAST <= KEY_STROBE; + if KEY_STROBE_LAST = KEY_STROBE then + KEY_SWEEP <= '1'; + end if; end if; - end if; - - -- Actual keyboard mapping. The Sharp MZ-80A key codes are scanned into a 10x8 matrix and then this matrix is indexed to extract the keycodes for the machine we - -- are being compatible with. - -- - if(KEY_SUBSTITUTE = '1') then + -- Actual keyboard mapping. The Sharp MZ-80A key codes are scanned into a 10x8 matrix and then this matrix is indexed to extract the keycodes for the machine we + -- are being compatible with. + -- -- MZ-80A Keyboard -> MZ-700 mapping. case KEY_STROBE is -- D7 D6 D5 D4 D3 D2 D1 D0 when "0000" => - KEYMAP_DATA <= '1' & KEY_MATRIX(0)(7) & KEY_MATRIX(7)(4) & KEY_MATRIX(0)(1) & '1' & KEY_MATRIX(6)(2) & KEY_MATRIX(6)(3) & KEY_MATRIX(7)(3); -- 1 + KEYMAP_DATA <= '1' & KEY_MATRIX(0)(7) & KEY_MATRIX(7)(4) & KEY_MATRIX(0)(1) & '1' & KEY_MATRIX(6)(2) & KEY_MATRIX(6)(3) & KEY_MATRIX(7)(3); -- 1 when "0001" => - KEYMAP_DATA <= KEY_MATRIX(3)(5) & KEY_MATRIX(1)(0) & KEY_MATRIX(6)(4) & KEY_MATRIX(6)(5) & KEY_MATRIX(7)(2) & '1' & '1' & '1' ; -- 2 + KEYMAP_DATA <= KEY_MATRIX(3)(5) & KEY_MATRIX(1)(0) & KEY_MATRIX(6)(4) & KEY_MATRIX(6)(5) & KEY_MATRIX(7)(2) & '1' & '1' & '1' ; -- 2 when "0010" => - KEYMAP_DATA <= KEY_MATRIX(1)(4) & KEY_MATRIX(2)(5) & KEY_MATRIX(2)(2) & KEY_MATRIX(3)(4) & KEY_MATRIX(4)(4) & KEY_MATRIX(3)(1) & KEY_MATRIX(1)(5) & KEY_MATRIX(2)(1); -- 3 + KEYMAP_DATA <= KEY_MATRIX(1)(4) & KEY_MATRIX(2)(5) & KEY_MATRIX(2)(2) & KEY_MATRIX(3)(4) & KEY_MATRIX(4)(4) & KEY_MATRIX(3)(1) & KEY_MATRIX(1)(5) & KEY_MATRIX(2)(1); -- 3 when "0011" => - KEYMAP_DATA <= KEY_MATRIX(4)(5) & KEY_MATRIX(4)(3) & KEY_MATRIX(5)(2) & KEY_MATRIX(5)(3) & KEY_MATRIX(5)(0) & KEY_MATRIX(4)(1) & KEY_MATRIX(5)(4) & KEY_MATRIX(5)(5); -- 4 + KEYMAP_DATA <= KEY_MATRIX(4)(5) & KEY_MATRIX(4)(3) & KEY_MATRIX(5)(2) & KEY_MATRIX(5)(3) & KEY_MATRIX(5)(0) & KEY_MATRIX(4)(1) & KEY_MATRIX(5)(4) & KEY_MATRIX(5)(5); -- 4 when "0100" => - KEYMAP_DATA <= KEY_MATRIX(1)(3) & KEY_MATRIX(3)(0) & KEY_MATRIX(2)(0) & KEY_MATRIX(2)(3) & KEY_MATRIX(2)(4) & KEY_MATRIX(3)(2) & KEY_MATRIX(3)(3) & KEY_MATRIX(4)(2); -- 5 + KEYMAP_DATA <= KEY_MATRIX(1)(3) & KEY_MATRIX(3)(0) & KEY_MATRIX(2)(0) & KEY_MATRIX(2)(3) & KEY_MATRIX(2)(4) & KEY_MATRIX(3)(2) & KEY_MATRIX(3)(3) & KEY_MATRIX(4)(2); -- 5 when "0101" => - KEYMAP_DATA <= KEY_MATRIX(1)(6) & KEY_MATRIX(1)(7) & KEY_MATRIX(2)(6) & KEY_MATRIX(2)(7) & KEY_MATRIX(3)(6) & KEY_MATRIX(3)(7) & KEY_MATRIX(4)(6) & KEY_MATRIX(4)(7); -- 6 + KEYMAP_DATA <= KEY_MATRIX(1)(6) & KEY_MATRIX(1)(7) & KEY_MATRIX(2)(6) & KEY_MATRIX(2)(7) & KEY_MATRIX(3)(6) & KEY_MATRIX(3)(7) & KEY_MATRIX(4)(6) & KEY_MATRIX(4)(7); -- 6 when "0110" => - KEYMAP_DATA <= KEY_MATRIX(7)(6) & KEY_MATRIX(6)(7) & KEY_MATRIX(6)(6) & KEY_MATRIX(4)(0) & KEY_MATRIX(5)(7) & KEY_MATRIX(5)(6) & KEY_MATRIX(5)(1) & KEY_MATRIX(6)(0); -- 7 + KEYMAP_DATA <= KEY_MATRIX(7)(6) & KEY_MATRIX(6)(7) & KEY_MATRIX(6)(6) & KEY_MATRIX(4)(0) & KEY_MATRIX(5)(7) & KEY_MATRIX(5)(6) & KEY_MATRIX(5)(1) & KEY_MATRIX(6)(0); -- 7 when "0111" => - KEYMAP_DATA <= KEY_MATRIX(8)(6) & KEY_MATRIX(9)(6) & KEY_MATRIX(8)(7) & KEY_MATRIX(8)(3) & KEY_MATRIX(9)(4) & KEY_MATRIX(8)(4) & KEY_MATRIX(7)(0) & KEY_MATRIX(6)(1); -- 8 + KEYMAP_DATA <= KEY_MATRIX(8)(6) & KEY_MATRIX(9)(6) & KEY_MATRIX(8)(7) & KEY_MATRIX(8)(3) & KEY_MATRIX(9)(4) & KEY_MATRIX(8)(4) & KEY_MATRIX(7)(0) & KEY_MATRIX(6)(1); -- 8 when "1000" => - KEYMAP_DATA <= KEY_MATRIX(7)(7) & KEY_MATRIX(1)(2) & '1' & '1' & '1' & '1' & '1' & KEY_MATRIX(0)(0); -- 9 + KEYMAP_DATA <= KEY_MATRIX(7)(7) & KEY_MATRIX(1)(2) & '1' & '1' & '1' & '1' & '1' & KEY_MATRIX(0)(0); -- 9 when "1001" => - KEYMAP_DATA <= KEY_MATRIX(8)(2) & KEY_MATRIX(8)(0) & KEY_MATRIX(8)(1) & KEY_MATRIX(9)(0) & KEY_MATRIX(9)(2) & '1' & '1' & '1' ; -- 10 + KEYMAP_DATA <= KEY_MATRIX(8)(2) & KEY_MATRIX(8)(0) & KEY_MATRIX(8)(1) & KEY_MATRIX(9)(0) & KEY_MATRIX(9)(2) & '1' & '1' & '1' ; -- 10 when others => - KEYMAP_DATA <= "11111111"; + KEYMAP_DATA <= "11111111"; end case; end if; -- When the Z80_MREQn goes inactive, the keyboard read has completed so clear the substitute flag which in turn allows normal bus operations. -- if(KEY_SUBSTITUTE = '1' and Z80_MREQn = '1') then - KEY_SUBSTITUTE <= '0'; + KEY_SUBSTITUTE <= '0'; end if; end if; - else + -- Standard mode we dont use the MB logic so set to default. MB_BUSRQn <= '1'; MB_STATE <= 0; end if; - end if; end process; + -- Secondary clock source. If the K64F processor is installed, then use its clock output as the secondary clock as it is more finely programmable. If the K64F + -- is not available, use the onboard oscillator. + -- + CTLCLKSRC: if USE_K64F_CTL_CLOCK = 1 generate + CTLCLKi <= CTLCLK; + else generate + process(Z80_RESETn, CTLCLK) + variable FREQDIVCTR : unsigned(3 downto 0); + begin + if Z80_RESETn = '0' then + FREQDIVCTR := (others => '0'); + CTLCLKi <= '0'; + + elsif CTLCLK'event and CTLCLK = '1' then + + FREQDIVCTR := FREQDIVCTR + 1; + + -- MZ700 => 3.58MHz, MZ80A => 12.5MHz + if (FREQDIVCTR = 7 and MODE_MZ700 = '1') or (FREQDIVCTR = 2 and MODE_MZ80A = '1') then + CTLCLKi <= not CTLCLKi; + FREQDIVCTR := (others => '0'); + end if; + end if; + end process; + end generate; + -- D type Flip Flops used for the CPU frequency switching circuit. The changeover of frequencies occurs on the high level, the output clock remaining -- high until the falling edge of the clock being switched into. FFCLK1: process( SYSCLK, Z80_RESETn ) begin - if Z80_RESETn = '0' then SYSCLK_Q <= '0'; -- If the system clock goes active high, process the inputs and set the D-type output. elsif( rising_edge(SYSCLK) ) then - if ((TZ_BUSACKni = '0' and SCK_CTLSELn = '0') or CTLCLK_Q = '1') then + if ((DISABLE_BUSn = '1' or MB_BUSRQn = '0' or SCK_CTLSELn = '1') and CTLCLK_Q = '1') then SYSCLK_Q <= '0'; else SYSCLK_Q <= '1'; end if; end if; end process; - FFCLK2: process( CTLCLK, Z80_RESETn ) begin + FFCLK2: process( CTLCLKi, Z80_RESETn ) begin if Z80_RESETn = '0' then CTLCLK_Q <= '1'; -- If the control clock goes active high, process the inputs and set the D-type output. - elsif( rising_edge(CTLCLK) ) then - if ((TZ_BUSACKni = '1' or SCK_CTLSELn = '1') and SYSCLK_Q = '1') then + elsif( rising_edge(CTLCLKi) ) then + if ((DISABLE_BUSn = '0' and SCK_CTLSELn = '0') and SYSCLK_Q = '1') then CTLCLK_Q <= '0'; else CTLCLK_Q <= '1'; @@ -516,166 +588,21 @@ begin end if; end process; - -- Latch output so the K64F can determine current status. - Z80_MEM <= MEM_MODE_LATCH(4 downto 0); - ENIOWAIT <= MEM_MODE_LATCH(5); - - -- Clock frequency switching. Depending on the state of the flip flops either the system (mainboard) clocks is selected (default and selected when accessing - -- the mainboard) and the programmable frequency generated by the K64F timers. - Z80_CLKi <= CTLCLK when CTLCLK_Q = '0' - else SYSCLK; - CTL_CLKSLCTi<= '1' when (TZ_BUSACKni = '0' and SCK_CTLSELn = '0') - else '0'; - CTL_CLKSLCT <= CTL_CLKSLCTi; - Z80_CLK <= Z80_CLKi; - - -- Mainboard BUS Request S-R latch 1. - MBBUSREQ: process(SYSCLK) - variable tmp : std_logic; - begin - if(SYSCLK='1' and SYSCLK'event) then - if((ENABLE_BUSn = '1' and Z80_RESETn = '1') and DISABLE_BUSn = '1') then - tmp := tmp; - elsif((ENABLE_BUSn = '0' or Z80_RESETn = '0') and DISABLE_BUSn = '0') then - tmp := 'Z'; - elsif((ENABLE_BUSn = '0' or Z80_RESETn = '0') and DISABLE_BUSn = '1') then - tmp := '1'; - else - tmp := '0'; - end if; - end if; - - TZ_BUSACKni <= tmp; - end PROCESS; - -- Mainboard Clock Select S-R latch 3. - MBCLKSEL: process(SYSCLK) - variable tmp : std_logic; + MBCLKSEL: process(Z80_CLKi, SCK_SYSCLKn, SCK_CTLCLKn, Z80_RESETn) begin - if(SYSCLK='1' and SYSCLK'event) then - if((SCK_SYSCLKn = '1' and Z80_RESETn = '1') and SCK_CTLCLKn = '1') then - tmp := tmp; - elsif((SCK_SYSCLKn = '0' or Z80_RESETn = '0') and SCK_CTLCLKn = '0') then - tmp := 'Z'; - elsif((SCK_SYSCLKn = '0' or Z80_RESETn = '0') and SCK_CTLCLKn = '1') then - tmp := '1'; + if Z80_RESETn = '0' then + SCK_CTLSELn <= '1'; + elsif (Z80_CLKi='1' and Z80_CLKi'event) then + if SCK_SYSCLKn = '0' or (MODE_SWITCH = '1' and MODE_MZ80A = '1') then + SCK_CTLSELn <= '1'; + elsif SCK_CTLCLKn = '0' or (MODE_SWITCH = '1' and MODE_MZ700 = '1') then + SCK_CTLSELn <= '0'; else - tmp := '0'; + null; end if; end if; - - SCK_CTLSELn <= tmp; - end PROCESS; - - - -- Mainboard WAIT State Generator S-R latch 4. - -- NB: V2.1 design doesnt need the wait state generator as the mapping is done in hardware. - -- - --MBWAITGEN: process(SYSCLK, Z80_ADDR, Z80_M1n, CTL_BUSRQn, MEM_MODE_LATCH, Z80_IORQn) - -- variable tmp : std_logic; - -- variable iowait : std_logic; - --begin - -- - -- -- IO Wait select active when an IO operation is made in range 0xE0-0xFF. - -- if (Z80_ADDR(7 downto 5) = "111" and Z80_M1n = '1' and CTL_BUSRQn = '1' and MEM_MODE_LATCH(5) = '1' and Z80_IORQn = '0') then - -- iowait := '0'; - -- else - -- iowait := '1'; - -- end if; - -- - -- if(SYSCLK='1' and SYSCLK'event) then - -- if((CTL_BUSRQn = '1' and Z80_RESETn = '1') and iowait = '1') then - -- tmp := tmp; - -- elsif((CTL_BUSRQn = '0' or Z80_RESETn = '0') and iowait = '0') then - -- tmp := 'Z'; - -- elsif((CTL_BUSRQn = '0' or Z80_RESETn = '0') and iowait = '1') then - -- tmp := '1'; - -- else - -- tmp := '0'; - -- end if; - -- end if; - -- - -- REQ_WAIT <= tmp; - --end PROCESS; - - -- Wait states, added by the video circuitry or the K64F. - Z80_WAITn <= '0' when SYS_WAITn = '0' or CTL_WAITn = '0' --or REQ_WAITn = '0' - else '1'; - - -- Z80 signals passed to the mainboard, if the K64F has control of the bus then the Z80 signals are disabled as they are not tri-stated during a BUSRQ state. - CTL_M1n <= Z80_M1n when Z80_BUSACKn = '1' - else 'Z'; - CTL_RFSHn <= Z80_RFSHn when Z80_BUSACKn = '1' - else 'Z'; - CTL_HALTn <= Z80_HALTn when Z80_BUSACKn = '1' - else 'Z'; - - -- Bus control logic. - TZ_BUSACKn <= TZ_BUSACKni; - SYS_BUSACKn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' - else - '0' when TZ_BUSACKni = '0' or (Z80_BUSACKn = '0' and CTL_BUSACKn = '0') - else '1'; - Z80_BUSRQn <= '0' when SYS_BUSRQn = '0' or CTL_BUSRQn = '0' or MB_BUSRQn = '0' - else '1'; - - -- - -- Data Bus Multiplexing, plex the output devices onto the Z80 data bus. - -- - Z80_DATA <= "0000000" & CTL_CLKSLCTi when SCK_RDn = '0' - else - MEM_MODE_LATCH(7 downto 0) when MEM_CFGn = '0' and Z80_RDn = '0' - else - KEYMAP_DATA when MB_BUSRQn = '1' and Z80_BUSACKn = '1' and KEY_SUBSTITUTE = '1' - else - CPLD_CFG_DATA when (CPLD_CFGn = '0' or CPLD_INFOn = '0') and Z80_RDn = '0' - else - MB_DATA when MB_BUSRQn = '0' and Z80_BUSACKn = '0' and MB_READ_KEYS = '0' -- add read signals inactive state here. - else - (others => 'Z'); - - -- - -- Address Bus Multiplexing. - -- - Z80_ADDR <= MB_ADDR when MB_BUSRQn = '0' and Z80_BUSACKn = '0' - else (others => 'Z'); - - Z80_WRn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_WRITE_STROBE = '1') -- and (write1 or write2...) signals active here - else - '1' when Z80_BUSACKn = '0' - else 'Z'; - - Z80_RDn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_READ_KEYS = '1') -- and (read1 or read2...) signals active here - else - '1' when Z80_BUSACKn = '0' - else 'Z'; - - Z80_MREQn <= MB_MREQn when Z80_BUSACKn = '0' - else 'Z'; - - -- The tranZPUter SW board adds upgrades for the Z80 processor and host. These upgrades are controlled through an IO port which - -- in v1.0 - v1.1 was either at 0x2-=0x2f, 0x60-0x6f, 0xA0-0xAf, 0xF0-0xFF, the default being 0x60. This logic mimcs the 74HCT138 and - -- FlashRAM decoder which produces the Io port select signals. - -- - TZIO_CSn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "0110" - else '1'; - MEM_CFGn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "000" -- IO 60 - else '1'; - SCK_CTLCLKn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "001" -- IO 62 - else '1'; - SCK_SYSCLKn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "010" -- IO 64 - else '1'; - SCK_RDn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "011" -- IO 66 - else '1'; - SVCREQn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "100" -- IO 68 - else '1'; - SYSREQn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "101" -- IO 6A - else '1'; - CPLD_CFGn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 0) = "1110" -- IO 6E - else '1'; - CPLD_INFOn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 0) = "1111" -- IO 6F - else '1'; - + end process; -- Memory decoding, taken directly from the definitions coded into the flashcfg tool in v1.1. The CPLD adds greater flexibility and mapping down to the byte level where needed. @@ -710,14 +637,16 @@ begin -- 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected. -- 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected. -- 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected. - process(Z80_ADDR, Z80_WRn, Z80_RDn, Z80_IORQn, Z80_MREQn, Z80_M1n, MEM_MODE_LATCH, KEY_SUBSTITUTE) begin + MEMORYMGMT: process(Z80_ADDR, Z80_WRn, Z80_RDn, Z80_IORQn, Z80_MREQn, Z80_M1n, MEM_MODE_LATCH) + begin + -- Memory action according to the set memory mode. Not synchronous as we need to detect and act on address or signals long before a rising edge. + -- case MEM_MODE_LATCH(4 downto 0) is -- Set 0 - default, no tranZPUter RAM access so just pulse the ENABLE_BUS signal for safety to ensure the CPU has continuous access to the -- mainboard resources, especially for Refresh of DRAM. when "00000" => - ENABLE_BUSn <= '0'; DISABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 16) <= "000"; RAM_CSni <= '1'; @@ -728,14 +657,16 @@ begin when "00001" => RAM_CSni <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); - if( Z80_MREQn = '0' and unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000") then + if( unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000") then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; RAM_OEni <= Z80_RDn; - RAM_WEni <= Z80_WRn; + if unsigned(Z80_ADDR(15 downto 0)) >= X"EC00" then + RAM_WEni <= Z80_WRn; + else + RAM_WEni <= '1'; + end if; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; RAM_WEni <= '1'; RAM_OEni <= '1'; end if; @@ -746,42 +677,40 @@ begin when "00010" => RAM_CSni <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F3C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F400" and unsigned(Z80_ADDR(15 downto 0)) < X"F7C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F800" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + if( (unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F3FF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F7FF")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; RAM_OEni <= Z80_RDn; - RAM_WEni <= Z80_WRn; + if unsigned(Z80_ADDR(15 downto 0)) = X"E800" then + RAM_WEni <= '1'; + else + RAM_WEni <= Z80_WRn; + end if; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 3 - Monitor ROM 0000-0FFF, Main RAM area 0x1000-0xD000, User ROM 0xE800-EFFF are in tranZPUter memory block 0, Floppy ROM F000-FFFF are in tranZPUter memory block 1. -- NB: Main DRAM will not be refreshed so cannot be used to store data in this mode. when "00011" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then + if(((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; - RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) < X"F3C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F400" and unsigned(Z80_ADDR(15 downto 0)) < X"F7C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + if unsigned(Z80_ADDR(15 downto 0)) = X"E800" then + RAM_WEni <= '1'; + else + RAM_WEni <= Z80_WRn; + end if; + elsif (unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F3FF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F7FF") then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "001" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; @@ -791,22 +720,25 @@ begin -- NB: Main DRAM will not be refreshed so cannot be used to store data in this mode. when "00100" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then + if( ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; - RAM_WEni <= Z80_WRn; + Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); + RAM_OEni <= Z80_RDn; + if unsigned(Z80_ADDR(15 downto 0)) = X"E800" then + RAM_WEni <= '1'; + else + RAM_WEni <= Z80_WRn; + end if; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "010" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; @@ -816,22 +748,23 @@ begin -- NB: Main DRAM will not be refreshed so cannot be used to store data in this mode. when "00101" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then + if( ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; - RAM_WEni <= Z80_WRn; + if unsigned(Z80_ADDR(15 downto 0)) = X"E800" then + RAM_WEni <= '1'; + else + RAM_WEni <= Z80_WRn; + end if; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "011" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; @@ -841,22 +774,14 @@ begin -- Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. when "00110" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) < X"F3C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F400" and unsigned(Z80_ADDR(15 downto 0)) < X"F7C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F800" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + if ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F3FF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F7FF")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - Z80_HI_ADDR(18 downto 15) <= "001" & Z80_ADDR(15); + Z80_HI_ADDR(18 downto 15) <= "100" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0100" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - Z80_HI_ADDR(18 downto 15) <= "101" & Z80_ADDR(15); - RAM_OEni <= Z80_RDn; - RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; @@ -866,23 +791,20 @@ begin -- Special case for 0000:00FF (interrupt vectors) which resides in block 4 and CPM vectors, F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. when "00111" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"0100") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) < X"F3C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F400" and unsigned(Z80_ADDR(15 downto 0)) < X"F7C0") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F800" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + if ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"0100") or (unsigned(Z80_ADDR(15 downto 0)) >= X"F000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F3FF" and unsigned(Z80_ADDR(15 downto 0)) /= X"F7FF")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "100" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0100" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then + elsif(((unsigned(Z80_ADDR(15 downto 0)) >= X"0100" and unsigned(Z80_ADDR(15 downto 0)) < X"D000") or (unsigned(Z80_ADDR(15 downto 0)) >= X"E800" and unsigned(Z80_ADDR(15 downto 0)) < X"F000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "101" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; @@ -893,205 +815,153 @@ begin when "01000" => RAM_CSni <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); - if( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then + if((unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 10 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard. when "01010" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then + if(((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "110" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 11 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. when "01011" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then + if(((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + elsif(((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "110" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 12 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. when "01100" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then + if(((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "110" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + elsif(((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "110" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 13 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. when "01101" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then + if(((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + elsif(((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 14 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. when "01110" => RAM_CSni <= '0'; - if( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then + if(((unsigned(Z80_ADDR(15 downto 0)) >= X"0000" and unsigned(Z80_ADDR(15 downto 0)) < X"1000"))) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "110" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and (unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then + elsif((unsigned(Z80_ADDR(15 downto 0)) >= X"1000" and unsigned(Z80_ADDR(15 downto 0)) < X"D000")) then DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_OEni <= Z80_RDn; RAM_WEni <= Z80_WRn; - elsif( Z80_MREQn = '0' and ((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then + elsif(((unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"))) then DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; else DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_WEni <= '1'; RAM_OEni <= '1'; end if; - if KEY_SUBSTITUTE = '1' then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - end if; - -- Set 24 - All memory and IO are on the tranZPUter board, 64K block 0 selected. when "11000" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "000" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1100,7 +970,6 @@ begin -- Set 25 - All memory and IO are on the tranZPUter board, 64K block 1 selected. when "11001" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "001" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1109,7 +978,6 @@ begin -- Set 26 - All memory and IO are on the tranZPUter board, 64K block 2 selected. when "11010" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "010" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1118,7 +986,6 @@ begin -- Set 27 - All memory and IO are on the tranZPUter board, 64K block 3 selected. when "11011" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "011" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1127,7 +994,6 @@ begin -- Set 28 - All memory and IO are on the tranZPUter board, 64K block 4 selected. when "11100" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "100" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1136,7 +1002,6 @@ begin -- Set 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected. when "11101" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "101" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1145,7 +1010,6 @@ begin -- Set 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected. when "11110" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "110" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1154,7 +1018,6 @@ begin -- Set 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected. when "11111" => DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; Z80_HI_ADDR(18 downto 15) <= "111" & Z80_ADDR(15); RAM_CSni <= '0'; RAM_OEni <= Z80_RDn; @@ -1163,49 +1026,160 @@ begin when others => end case; - -- If the non-standard case of Z80 RD and Z80 WR being set low occurs, enable the ENABLE_BUS signal as the K64F is requesting access to the MZ80A motherboard. - if(Z80_RDn = '0' and Z80_WRn = '0' and Z80_MREQn = '1' and Z80_IORQn = '1') then - DISABLE_BUSn <= '0'; - ENABLE_BUSn <= '1'; - RAM_OEni <= '1'; - RAM_CSni <= '1'; - RAM_WEni <= '1'; - end if; - -- Defaults for IO operations, can be overriden for a specific set but should be present in all other sets. if((Z80_WRn = '0' or Z80_RDn = '0') and Z80_IORQn = '0') then - -- If the address is within configured IO control register range, activate the IODECODE signal. - if(unsigned(Z80_ADDR(7 downto 0)) >= X"60" and unsigned(Z80_ADDR(7 downto 0)) < X"79") then + -- If the address is within configured IO control register range then disable the mainboard. Only allow I/O operations to pass through to the mainboard + -- when not processed by the CPLD. + if(unsigned(Z80_ADDR(7 downto 0)) >= X"60" and unsigned(Z80_ADDR(7 downto 0)) < X"6F") then - if(unsigned(MEM_MODE_LATCH(4 downto 0)) >= 10 and unsigned(MEM_MODE_LATCH(4 downto 0)) < 15) then - DISABLE_BUSn<= '1'; - ENABLE_BUSn <= '1'; - else - DISABLE_BUSn<= '0'; - ENABLE_BUSn <= '1'; - end if; - - elsif(unsigned(Z80_ADDR(7 downto 0)) >= X"E0" and unsigned(Z80_ADDR(7 downto 0)) < X"EF") then - DISABLE_BUSn<= '0'; - ENABLE_BUSn <= '1'; + DISABLE_BUSn <= '0'; else - DISABLE_BUSn <= '1'; - ENABLE_BUSn <= '0'; + DISABLE_BUSn <= '1'; end if; end if; end process; + -- Latch output so the K64F can determine current status. + Z80_MEM <= MEM_MODE_LATCH(4 downto 0); + + -- Clock frequency switching. Depending on the state of the flip flops either the system (mainboard) clocks is selected (default and selected when accessing + -- the mainboard) and the programmable frequency generated by the K64F timers. + Z80_CLKi <= (SYSCLK or SYSCLK_Q) and (CTLCLKi or CTLCLK_Q); + CTL_CLKSLCT <= SYSCLK_Q; + Z80_CLK <= Z80_CLKi; + + + -- Wait states, added by the video circuitry or the K64F. + Z80_WAITn <= '0' when SYS_WAITn = '0' or CTL_WAITn = '0' or MB_WAITn = '0' + else '1'; + + -- Z80 signals passed to the mainboard, if the K64F has control of the bus then the Z80 signals are disabled as they are not tri-stated during a BUSRQ state. + CTL_M1n <= Z80_M1n when Z80_BUSACKn = '1' + else 'Z'; + CTL_RFSHn <= Z80_RFSHn when Z80_BUSACKn = '1' + else 'Z'; + CTL_HALTn <= Z80_HALTn when Z80_BUSACKn = '1' + else 'Z'; + + -- Bus control logic. + SYS_BUSACKn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else + '0' when DISABLE_BUSn = '0' or (KEY_SUBSTITUTE = '1' and Z80_MREQn = '0') or (Z80_BUSACKn = '0' and CTL_BUSACKn = '0') + else '1'; + Z80_BUSRQn <= '0' when SYS_BUSRQn = '0' or CTL_BUSRQn = '0' or MB_BUSRQn = '0' + else '1'; + + -- + -- Data Bus Multiplexing, plex the output devices onto the Z80 data bus. + -- + Z80_DATA <= (others => 'Z') when Z80_BUSACKn = '0' and CTL_BUSACKn = '0' -- Tristate bus when Z80 tristated and the K64F is requesting all devices to tristate. + else + "0000000" & SYSCLK_Q when SCK_RDn = '0' -- Read the clock select status. + else + "000" & MEM_MODE_LATCH(4 downto 0) when MEM_CFGn = '0' and Z80_RDn = '0' -- Read the memory mode latch. + else + KEYMAP_DATA when MB_BUSRQn = '1' and Z80_BUSACKn = '1' and KEY_SUBSTITUTE = '1' and Z80_MREQn = '0' -- Read mapped keyboard data. + else + "000000" & MODE_MZ700 & MODE_MZ80A when CPLD_CFGn = '0' and Z80_RDn = '0' -- Read current register settings. + else + "1010" & std_logic_vector(to_unsigned(CPLD_VERSION, 4)) when CPLD_INFOn = '0' and Z80_RDn = '0' -- Read version information. + else + MB_DATA when MB_BUSRQn = '0' and Z80_BUSACKn = '0' and MB_READ_KEYS = '0' -- add read signals inactive state here. + else + (others => 'Z'); -- Default is to tristate the CPLD data bus output when not being used. + + -- + -- Address Bus Multiplexing. + -- + Z80_ADDR <= MB_ADDR when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else + (others => 'Z'); + + Z80_WRn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_WRITE_STROBE = '1') -- and (write1 or write2...) signals active here + else + '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else 'Z'; + + Z80_RDn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_READ_KEYS = '1') -- and (read1 or read2...) signals active here + else + '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else 'Z'; + + Z80_MREQn <= MB_MREQn when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else 'Z'; + + Z80_INTn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else 'Z'; + + Z80_NMIn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0' + else 'Z'; + + -- The tranZPUter SW board adds upgrades for the Z80 processor and host. These upgrades are controlled through an IO port which + -- in v1.0 - v1.1 was either at 0x2-=0x2f, 0x60-0x6f, 0xA0-0xAf, 0xF0-0xFF, the default being 0x60. This logic mimcs the 74HCT138 and + -- FlashRAM decoder which produces the Io port select signals. + -- + TZIO_CSn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "0110" + else '1'; + MEM_CFGn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "000" -- IO 60 + else '1'; + SCK_CTLCLKn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "001" -- IO 62 + else '1'; + SCK_SYSCLKn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "010" -- IO 64 + else '1'; + SCK_RDn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "011" -- IO 66 + else '1'; + SVCREQn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "100" -- IO 68 + else '1'; + SYSREQn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 1) = "101" -- IO 6A + else '1'; + CPLD_CFGn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 0) = "1110" -- IO 6E + else '1'; + CPLD_INFOn <= '0' when TZIO_CSn = '0' and Z80_ADDR(3 downto 0) = "1111" -- IO 6F + else '1'; + -- Assign the RAM select signals to their external pins. RAM_CSn <= RAM_CSni; - RAM_OEn <= RAM_OEni; - RAM_WEn <= RAM_WEni; + RAM_OEn <= RAM_OEni when Z80_MREQn = '0' + else '1'; + RAM_WEn <= RAM_WEni when Z80_MREQn = '0' + else '1'; -- For the video card, additional address lines are needed to address the banked video memory. The CPLD is acting as a buffer for these lines. - VADDR <= Z80_ADDR(13 downto 11) when Z80_BUSACKn = '1' + VADDR <= Z80_ADDR(13 downto 11) when Z80_BUSACKn = '1' else (others => 'Z'); - VMEM_CSn <= '0' when unsigned(Z80_ADDR(15 downto 0)) >= X"E000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF" and Z80_MREQn = '0' and Z80_RFSHn = '1' + VMEM_CSn <= '0' when unsigned(Z80_ADDR(15 downto 0)) >= X"E000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF" and Z80_MREQn = '0' and Z80_RFSHn = '1' else '1'; + -- Mainboard WAIT State Generator S-R latch 4. + -- NB: V2.1 design doesnt need the wait state generator as the mapping is done in hardware. + -- + --MBWAITGEN: process(SYSCLK, Z80_ADDR, Z80_M1n, CTL_BUSRQn, MEM_MODE_LATCH, Z80_IORQn) + -- variable tmp : std_logic; + -- variable iowait : std_logic; + --begin + -- + -- -- IO Wait select active when an IO operation is made in range 0xE0-0xFF. + -- if (Z80_ADDR(7 downto 5) = "111" and Z80_M1n = '1' and CTL_BUSRQn = '1' and MEM_MODE_LATCH(5) = '1' and Z80_IORQn = '0') then + -- iowait := '0'; + -- else + -- iowait := '1'; + -- end if; + -- + -- if(SYSCLK='1' and SYSCLK'event) then + -- if((CTL_BUSRQn = '1' and Z80_RESETn = '1') and iowait = '1') then + -- tmp := tmp; + -- elsif((CTL_BUSRQn = '0' or Z80_RESETn = '0') and iowait = '0') then + -- tmp := 'Z'; + -- elsif((CTL_BUSRQn = '0' or Z80_RESETn = '0') and iowait = '1') then + -- tmp := '1'; + -- else + -- tmp := '0'; + -- end if; + -- end if; + -- + -- REQ_WAIT <= tmp; + --end PROCESS; + end architecture; diff --git a/CPLD/tranZPUterSW_Toplevel.vhd b/CPLD/tranZPUterSW_Toplevel.vhd index 05a641c..6a74155 100644 --- a/CPLD/tranZPUterSW_Toplevel.vhd +++ b/CPLD/tranZPUterSW_Toplevel.vhd @@ -66,8 +66,6 @@ entity tranZPUterSW is CTL_WAITn : in std_logic; SVCREQn : out std_logic; SYSREQn : out std_logic; - TZ_BUSACKn : out std_logic; - ENIOWAIT : out std_logic; Z80_MEM : out std_logic_vector(4 downto 0); -- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality. @@ -90,10 +88,10 @@ entity tranZPUterSW is -- Mode signals. CFG_MZ80A : in std_logic; - CFG_MZ700 : in std_logic; + CFG_MZ700 : in std_logic -- Reserved. - TBA : in std_logic_vector(8 downto 0) + --TBA : in std_logic_vector(10 downto 0) -- JTAG / ISP --TCK : in std_logic; @@ -143,8 +141,6 @@ begin CTL_WAITn => CTL_WAITn, SVCREQn => SVCREQn, SYSREQn => SYSREQn, - TZ_BUSACKn => TZ_BUSACKn, - ENIOWAIT => ENIOWAIT, Z80_MEM => Z80_MEM, -- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality. @@ -167,10 +163,10 @@ begin -- Mode signals. CFG_MZ80A => CFG_MZ80A, - CFG_MZ700 => CFG_MZ700, + CFG_MZ700 => CFG_MZ700 -- Reserved. - TBA => TBA + --TBA => TBA ); end architecture; diff --git a/CPLD/tranZPUterSW_pkg.vhd b/CPLD/tranZPUterSW_pkg.vhd index d7b95da..3c0dbeb 100644 --- a/CPLD/tranZPUterSW_pkg.vhd +++ b/CPLD/tranZPUterSW_pkg.vhd @@ -34,6 +34,17 @@ use ieee.numeric_std.all; use ieee.math_real.all; package tranZPUterSW_pkg is + ------------------------------------------------------------ + -- Configurable parameters. + ------------------------------------------------------------ + + -- Version of hdl. + constant CPLD_VERSION : integer := 1; + + -- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator. + -- + constant USE_K64F_CTL_CLOCK : integer := 1; + ------------------------------------------------------------ -- Function prototypes ------------------------------------------------------------ @@ -59,9 +70,6 @@ package tranZPUterSW_pkg is constant ZERO : std_logic := '0'; constant HIZ : std_logic := 'Z'; - -- Version of hdl. - constant CPLD_VERSION : integer := 1; - ------------------------------------------------------------ -- Records ------------------------------------------------------------ diff --git a/software/asm/1Z-013A-KM.asm b/software/asm/1Z-013A-KM.asm new file mode 100644 index 0000000..d644405 --- /dev/null +++ b/software/asm/1Z-013A-KM.asm @@ -0,0 +1,3303 @@ + ; MONITOR PROGRAM 1Z-013A + ; (MZ700) FOR PAL + ; REV. 83.4.7 + ; Tuesday, 02 of June 1998 at 10:02 PM + ; Tuesday, 09 of June 1998 at 07:17 AM +; Configurable parameters. These are set in the wrapper file, ie monitor_SA1510.asm +; +;COLW: EQU 40 ; Width of the display screen (ie. columns). +;ROW: EQU 25 ; Number of rows on display screen. +;SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. + + ORG 0000h ; 0000h Entrypoint +MONIT: JP START ; MONITOR ON +GETL: JP QGETL ; GET LINE (END "CR") +LETNL: JP QLTNL ; NEW LINE +NL: JP QNL ; +PRNTS: JP QPRTS ; PRINT SPACE +PRNTT: JP QPRTT ; PRINT TAB +PRNT: JP QPRNT ; 1 CHARACTER PRINT +MSG: JP QMSG ; 1 LINE PRINT (END "0DH") +MSGX: JP QMSGX ; RST 18H +GETKY: JP QGET ; GET KEY +BRKEY: JP QBRK ; GET BREAK +WRINF: JP QWRI ; WRITE INFORMATION +WRDAT: JP QWRD ; WRITE DATA +RDINF: JP QRDI ; READ INFORMATION +RDDAT: JP QRDD ; READ DATA +VERFY: JP QVRFY ; VERIFYING CMT +MELDY: JP QMLDY ; RST 30H +TIMST: JP QTMST ; TIME SET + NOP + NOP + JP 1038H ; INTERRUPT ROUTINE (8253) +TIMRD: JP QTMRD ; TIME READ +BELL: JP QBEL ; BELL ON +XTEMP: JP QTEMP ; TEMPO SET (1 - 7) +MSTA: JP MLDST ; MELODY START +MSTP: JP MLDSP ; MELODY STOP + +START: LD SP,SPV ; STACK SET (10F0H) + IM 1 ; IM 1 SET + CALL QMODE ; 8255 MODE SET + CALL QBRK ; CTRL ? + JR NC,ST0 + CP 20H ; KEY IS CTRL KEY + JR NZ,ST0 +CMY0: OUT (0E1H),A ; D000-FFFFH IS DRAM + LD DE,0FFF0H ; TRANS. ADR. + LD HL,DMCP ; MEMORY CHANG PROGRAM + LD BC,05H ; BYTE SIZE + LDIR + JP 0FFF0H ; JUMP $FFF0 + +DMCP: OUT (0E0H),A ; 0000H-0FFFH IS DRAM + JP 0000H + +ST0: LD B,0FFH ; BUFFER CLEAR + LD HL,NAME ; 10F1H-11F0H CLEAR + CALL QCLER + LD A,16H ; LASTER CLR. + CALL PRNT + IF MODE80C = 0 + LD A,017H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode. + ELSE + LD A,017H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode. + ENDIF + ; LD A,71H ; BACK:BLUE CHA.:WRITE + LD HL,0D800H ; COLOR ADDRESS + CALL NCLR8 + LD HL,TIMIN ; INTERRUPT JUMP ROUTINE + LD A,0C3H + LD (1038H),A + LD (1039H),HL + LD A,04H ; NORMAL TEMPO + LD (TEMPW),A + CALL MLDSP ; MELODY STOP + CALL NL + LD DE,MSGQ3 ; ** MONITOR 1Z-013A ** + RST 18H ; CALL MGX + CALL QBEL +SS: LD A,01H + LD (SWRK),A ; KEY IN SILENT + LD HL,0E800H ; USR ROM? + LD (HL),A ; ROM CHECK + JR FD2 + +ST1: CALL NL + LD A,2AH ; "*" PRINT + CALL PRNT + LD DE,BUFER ; GET LINE WORK (11A3H) + CALL GETL +ST2: LD A,(DE) + INC DE + CP 0DH + JR Z,ST1 + CP 'J' ; JUMP + JR Z,GOTO + CP 'L' ; LOAD PROGRAM + JR Z,LOAD + CP 'F' ; FLOPPY ACCESS + JR Z,FD + CP 'B' ; KEY IN BELL + JR Z,SG + CP '#' ; CHANG MEMORY + JR Z,CMY0 + CP 'P' ; PRINTER TEST + JR Z,PTEST + CP 'M' ; MEMORY CORRECTION + JP Z,MCOR + CP 'S' ; SAVE DATA + JP Z,SAVE + CP 'V' ; VERIFYING DATA + JP Z,VRFY + CP 'D' ; DUMP DATA + JP Z,DUMP + NOP + NOP + NOP + NOP + JR ST2 ; NO COMMAND + + ; JUMP COMMAND + +GOTO: CALL HEXIY + JP (HL) + + ; KEY SOUND ON/OFF + +SG: LD A,(SWRK) ; D0=SOUND WORK + RRA + CCF ; CHANGE MODE + RLA + JR SS+2 + + ; FLOPPY + +FD: LD HL,0F000H ; FLOPPY I/O CHECK +FD2: LD A,(HL) + OR A + JR NZ,ST1 +FD1: JP (HL) + + ; ERROR (LOADING) + +QER: CP 02H ; A=02H : BREAK IN + JR Z,ST1 + LD DE,MSGE1 ; CHECK SUM ERROR + RST 18H ; CALL MSGX +L010F: JR ST1 + + ; LOAD COMMAND + +LOAD: CALL QRDI + JR C,QER +LOA0: CALL NL + LD DE,MSGQ2 ; LOADING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + CALL QRDD + JR C,QER + LD HL,(EXADR) ; EXECUTE ADDRESS + LD A,H + CP 12H ; EXECUTE CHECK + JR C,L010F + JP (HL) + + ; GETLINE AND BREAK IN CHECK + ; + ; EXIT BREAK IN THEN JUMP (ST1) + ; ACC=TOP OF LINE DATA + +BGETL: EX (SP),HL + POP BC ; STACK LOAD + LD DE,BUFER ; MONITOR GETLINE BUFF + CALL GETL + LD A,(DE) + CP 1BH ; BREAK CODE + JR Z,L010F ; JP Z,ST1 + JP (HL) + + ; ASCII TO HEX CONVERT + ; INPUT (DE)=ASCII + ; CY=1 THEN JUMP (ST1) + +HEXIY: EX (SP),IY + POP AF + CALL HLHEX + JR C,L010F ; JP C,ST1 + JP (IY) + +MSGE1: DB "CHECK SUM ER.\r" + + ; PLOTTER PRINTER TEST COMMAND + ; (DPG23) + ; &=CONTROL COMMANDS GROUP + ; C=PEN CHANGE + ; G=GRAPH MODE + ; S=80 CHA. IN 1 LINE + ; L=40 CHA. IN 1 LINE + ; T=PLOTTER TEST + ; IN (DE)=PRINT DATA + +PTEST: LD A,(DE) + CP '&' + JR NZ,PTST1 +PTST0: INC DE + LD A,(DE) + CP 'L' ; 40 IN 1 LINE + JR Z,PLPT + CP 'S' ; 80 IN 1 LINE + JR Z,PPLPT + CP 'C' ; PEN CHANGE + JR Z,PEN + CP 'G' ; GRAPH MODE + JR Z,PLOT + CP 'T' ; TEST + JR Z,PTRN +PTST1: CALL PMSG ; PLOT MESSAGE + JP ST1 + +PLPT: LD DE,LLPT ; 01-09-09-0B-0D + JR PTST1 + +PPLPT: LD DE,SLPT ; 01-09-09-09-0D + JR PTST1 + +PTRN: LD A,04H ; TEST PATTERN + JR PLOT+2 + +PLOT: LD A,02H ; GRAPH CODE + CALL LPRNT + JR PTST0 + +PEN: LD A,1DH ; 1 CHANGE CODE (TEXT MODE) + JR PLOT+2 + + ; 1CHA. PRINT TO $LPT + ; IN: ACC PRINT DATA + +LPRNT: LD C,0 ; RDA TEST (READY? RDA=0) + LD B,A ; PRINT DATA STORE + CALL RDA + LD A,B + OUT (0FFH),A ; DATA OUT + LD A,80H ; RDP HIGH + OUT (0FEH),A + LD C,01H ; RDA TEST + CALL RDA + XOR A ; RDP LOW + OUT (0FEH),A + RET + + ; $LPT MSG + ; IN: DE DATA LOW ADDRESS + ; 0DH MSG END + +PMSG: PUSH DE + PUSH BC + PUSH AF +PMSG1: LD A,(DE) ; ACC=DATA + CALL LPRNT + LD A,(DE) + INC DE + CP 0DH ; END? + JR NZ,PMSG1 + POP AF + POP BC + POP DE + RET + + ; RDA CHECK + ; BRKEY IN TO MONITOR RETURN + ; IN: C RDA CODE + +RDA: IN A,(0FEH) + AND 0DH ; RDA ONLY + CP C + RET Z + CALL BRKEY + JR NZ,RDA + LD SP,SPV + JP ST1 + + ; MELODY + ; DE=DATA LOW ADDRESS + ; EXIT CF=1 BREAK + ; CF=0 OK + +QMLDY: PUSH BC + PUSH DE + PUSH HL + LD A,02H + LD (OCTV),A + LD B,01H +MLD1: LD A,(DE) + CP 0DH ; CR + JR Z,MLD4 + CP 0C8H ; END MARK + JR Z,MLD4 + CP 0CFH ; UNDER OCTAVE + JR Z,MLD2 + CP 2DH ; "-" + JR Z,MLD2 + CP 2BH ; "+" + JR Z,MLD3 + CP 0D7H ; UPPER OCTAVE + JR Z,MLD3 + CP 23H ; "#" HANON + LD HL,MTBL + JR NZ,L01F5 + LD HL,MNTBL + INC DE +L01F5: CALL ONPU ; ONTYO SET + JR C,MLD1 + CALL RYTHM + JR C,MLD5 + CALL MLDST ; MELODY START + LD B,C + JR MLD1 + +MLD2: LD A,3 +L0207: LD (OCTV),A + INC DE + JR MLD1 + +MLD3: LD A,01H + JR L0207 + +MLD4: CALL RYTHM +MLD5: PUSH AF + CALL MLDSP + POP AF + JP RET3 + + ; ONPU TO RATIO CONV + ; EXIT (RATIO)=RATIO VALUE + ; C=ONTYO*TEMPO + +ONPU: PUSH BC + LD B,8 +ONP1: LD A,(DE) +L0220: CP (HL) + JR Z,ONP2 + INC HL + INC HL + INC HL + DJNZ L0220 + SCF + INC DE + POP BC + RET + +ONP2: INC HL + PUSH DE + LD E,(HL) + INC HL + LD D,(HL) + EX DE,HL + LD A,H + OR A + JR Z,L023F + LD A,(OCTV) ; 11A0H OCTAVE WORK +L0239: DEC A + JR Z,L023F + ADD HL,HL + JR L0239 + +L023F: LD (RATIO),HL ; 11A1H ONPU RATIO + LD HL,OCTV + LD (HL),02H + DEC HL + POP DE + INC DE + LD A,(DE) + LD B,A + AND 0F0H ; ONTYO ? + CP 30H + JR Z,L0255 + LD A,(HL) ; HL=ONTYO + JR L025A + +L0255: INC DE + LD A,B + AND 0FH + LD (HL),A ; HL=ONTYO +L025A: LD HL,OPTBL + ADD A,L + LD L,A + LD C,(HL) + LD A,(TEMPW) + LD B,A + XOR A +ONP3: ADD A,C + DJNZ ONP3 + POP BC + LD C,A + XOR A + RET + +MTBL: DB "C" + DW 0846H + DB "D" + DW 075FH + DB "E" + DW 0691H + DB "F" + DW 0633H + DB "G" + DW 0586H + DB "A" + DW 04ECH + DB "B" + DW 0464H + DB "R" + DW 0000H +MNTBL: DB "C" ; #C + DW 07CFH + DB "D" ; #D + DW 06F5H + DB "E" ; #E + DW 0633H + DB "F" ; #F + DW 05DAH + DB "G" ; #G + DW 0537H + DB "A" ; #A + DW 04A5H + DB "B" ; #B + DW 0423H + DB "R" ; #R + DW 0000H +OPTBL: DB 01H + DB 02H + DB 03H + DB 04H + DB 06H + DB 08H + DB 0CH + DB 10H + DB 18H + DB 20H + + ; INCREMENT DE REG. + +P4DE: INC DE + INC DE + INC DE + INC DE + RET + + ; MELODY START & STOP + +MLDST: LD HL,(RATIO) + LD A,H + OR A + JR Z,MLDSP + PUSH DE + EX DE,HL + LD HL,CONT0 + LD (HL),E + LD (HL),D + LD A,01H + POP DE + JR MLDS1 + +MLDSP: LD A,36H ; MODE SET (8253 C0) + LD (CONTF),A ; E007H + XOR A +MLDS1: LD (SUNDG),A ; E008H + RET ; TEHRO SET + + ; RHYTHM + ; B=COUNT DATA + ; IN + ; EXIT CF=1 BREAK + ; CF=0 OK + +RYTHM: LD HL,KEYPA ; E000H + LD (HL),0F8H + INC HL + LD A,(HL) + AND 81H ; BREAK IN CHECK + JR NZ,L02D5 + SCF + RET + +L02D5: LD A,(TEMP) ; E008H + RRCA ; TEMPO OUT + JR C,L02D5 +L02DB: LD A,(TEMP) + RRCA + JR NC,L02DB + DJNZ L02D5 + XOR A + RET + + ; TEMPO SET + ; ACC=VALUE (1-7) + +QTEMP: PUSH AF + PUSH BC + AND 0FH + LD B,A + LD A,8 + SUB B + LD (TEMPW),A + POP BC + POP AF + RET + + ; CRT MANAGEMENT + ; EXIT HL:DSPXY H=Y,L=X + ; DE:MANG ADR. (ON DSPXY) + ; A :MANG DATA + ; CY:MANG=1 + +PMANG: LD HL,MANG ; CRT MANG POINTER + LD A,(1172H) ; DSPXY+1 + ADD A,L + LD L,A + LD A,(HL) + INC HL + RL (HL) + OR (HL) + RR (HL) + RRCA + EX DE,HL + LD HL,(DSPXY) + RET + + ; TIME SET + ; ACC=0 : AM + ; =1 : PM + ; DE=SEC: BINARY + +QTMST: DI + PUSH BC + PUSH DE + PUSH HL + LD (AMPM),A ; AMPM DATA + LD A,0F0H + LD (TIMFG),A ; TIME FLAG + LD HL,0A8C0H ; 12 HOURS (43200 SECONDS) + XOR A + SBC HL,DE ; COUNT DATA = 12H-IN DATA + PUSH HL + NOP + EX DE,HL + LD HL,CONTF ; E007H + LD (HL),74H ; C1 + LD (HL),0B0H ; C2 + DEC HL ; CONT2 + LD (HL),E ; E006H + LD (HL),D + DEC HL ; CONT1 + LD (HL),0AH ; E005H STROBE 640,6µSECONDS COUNT2 + LD (HL),0 + INC HL + INC HL ; CONTF + LD (HL),80H ; E007H + DEC HL ; CONT2 +QTMS1: LD C,(HL) ; E006H + LD A,(HL) + CP D + JR NZ,QTMS1 + LD A,C + CP E + JR NZ,QTMS1 + DEC HL ; E005H + NOP + NOP + NOP + LD (HL),0FBH ; 1 SECOND (15611HZ) E005H + LD (HL),3CH + INC HL + POP DE +QTMS2: LD C,(HL) ; E006H + LD A,(HL) + CP D + JR NZ,QTMS2 + LD A,C + CP E + JR NZ,QTMS2 + POP HL + POP DE + POP BC + EI + RET + + ; BELL DATA + ; +QBELD: DB 0D7H + DB "A0" + DB 0DH + NOP + NOP + + ; TIME READ + ; EXIT ACC=0 :AM + ; =1 :PM + ; DE=SEC. BINARY + +QTMRD: PUSH HL + LD HL,CONTF + LD (HL),80H ; E007H C2 + DEC HL ; CONT2 + DI + LD E,(HL) + LD D,(HL) ; e006H C2 MODE0 + EI +L0363: LD A,E + OR D + JR Z,QTMR1 + XOR A + LD HL,0A8C0H ; 12 HOURS + SBC HL,DE + JR C,QTMR2 + EX DE,HL + LD A,(AMPM) + POP HL + RET + +QTMR1: LD DE,0A8C0H +L0378: LD A,(AMPM) + XOR 01H + POP HL + RET + +QTMR2: DI + LD HL,CONT2 + LD A,(HL) + CPL + LD E,A + LD A,(HL) + CPL + LD D,A + EI + INC DE + JR L0378 + + ; TIME INTERRUPT + +TIMIN: PUSH AF + PUSH BC + PUSH DE + PUSH HL + LD HL,AMPM + LD A,(HL) + XOR 01H + LD (HL),A + LD HL,CONTF + LD (HL),80H ; CONT2 + DEC HL + PUSH HL + LD E,(HL) + LD D,(HL) + LD HL,0A8C0H + ADD HL,DE + DEC HL + DEC HL + EX DE,HL + POP HL + LD (HL),E + LD (HL),D + POP HL + POP DE + POP BC + POP AF + EI + RET + + ; SPACE PRINT AND DISP ACC + ; INPUT:HL=DISP. ADR. + +SPHEX: CALL QPRTS ; SPACE PRINT + LD A,(HL) + CALL PRTHX ; DSP OF ACC (ASCII) + LD A,(HL) + RET + + ; (ASCII PRINT) FOR HL + +PRTHL: LD A,H + CALL PRTHX + LD A,L + JR PRTHX + + NOP + NOP + + ; (ASCII PRINT) FOR ACC + +PRTHX: PUSH AF + RRCA + RRCA + RRCA + RRCA + CALL ASC + CALL PRNT + POP AF + CALL ASC + JP PRNT + + ; 80 CHA. 1 LINE CODE (DATA) + +SLPT: DB 01H ; TEXT MODE + DB 09H + DB 09H + DB 09H + DB 0DH + + ; HEXADECIMAL TO ASCII + ; IN : ACC (D3-D0)=HEXADECIMAL + ; EXIT: ACC = ASCII +ASC: AND 0FH + CP 0AH + JR C,NOADD + ADD A,07H +NOADD: ADD A,30H + RET + + ; ASCII TO HEXADECIMAL + ; IN : ACC = ASCII + ; EXIT: ACC = HEXADECIMAL + ; CY = 1 ERROR + +HEXJ: SUB 30H + RET C ; <0 + CP 0AH + CCF + RET NC ; 0-9 + SUB 07H + CP 10H + CCF + RET C + CP 0AH + RET + + NOP + NOP + NOP + NOP + +HEX: JR HEXJ + + ; PRESS PLAY MESSAGE + +MSGN1: DW 207FH +MSGN2: DB "PLAY\r" +MSGN3: DW 207FH + DB "RECORD.\r" ; PRESS RECORD + + NOP + NOP + NOP + NOP + + ; 4 ASCII TO (HL) + ; IN DE=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : OUT + +HLHEX: PUSH DE + CALL L2HEX + JR C,L041D + LD H,A + CALL L2HEX + JR C,L041D + LD L,A +L041D: POP DE + RET + + ; 2 ASCII TO (ACC) + ; IN DE=DATA LOW ADRRESS + ; EXIT CF=0 : OK + ; =1 : OUT + +L2HEX: PUSH BC + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + RRCA + RRCA + RRCA + RRCA + LD C,A + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + OR C +L0434: POP BC + RET + + ; WRITE INFORMATION + +QWRI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,0CCH ; "L" + LD HL,IBUFE ; 10F0H + LD BC,80H ; WRITE BYTE SIZE +WRI1: CALL CKSUM ; CHECK SUM + CALL MOTOR ; MOTOR ON + JR C,WRI3 + LD A,E + CP 0CCH ; "L" + JR NZ,WRI2 + CALL NL + PUSH DE + LD DE,MSGN7 ; WRITING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + POP DE +WRI2: CALL GAP + CALL WTAPE +WRI3: JP RET2 + +MSGN7: DB "WRITING \r" + + ; 40 CHA. IN 1 LINE CODE (DATA) + +LLPT: DB 01H ; TEXT MODE + DB 09H + DB 09H + DB 0BH + DB 0DH + + ; WRITE DATA + ; EXIT CF=0 : OK + ; =1 : BREAK + +QWRD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,53H ; "S" +L047D: LD BC,(SIZE) ; WRITE DATA BYTE SIZE + LD HL,(DTADR) ; WRITE DATA ADDRESS + LD A,B + OR C + JR Z,RET1 + JR WRI1 + + ; TAPE WRITE + ; BC=BYTE SIZE + ; HL=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : BREAK + +WTAPE: PUSH DE + PUSH BC + PUSH HL + LD D,02H + LD A,0F8H ; 88H WOULD BE BETTER!! + LD (KEYPA),A ; E000H +WTAP1: LD A,(HL) + CALL WBYTE ; 1 BYTE WRITE + LD A,(KEYPB) ; E001H + AND 81H ; SHIFT & BREAK + JP NZ,WTAP2 + LD A,02H ; BREAK IN CODE + SCF + JR WTAP3 + +WTAP2: INC HL + DEC BC + LD A,B + OR C + JP NZ,WTAP1 + LD HL,(SUMDT) ; SUM DATA SET + LD A,H + CALL WBYTE + LD A,L + CALL WBYTE + CALL LONG + DEC D + JP NZ,L04C2 + OR A + JP WTAP3 + +L04C2: LD B,0 +L04C4: CALL SHORT + DEC B + JP NZ,L04C4 + POP HL + POP BC + PUSH BC + PUSH HL + JP WTAP1 + +WTAP3: +RET1: POP HL + POP BC + POP DE + RET + + DB 2FH + DB 4EH + + ; READ INFORMATION (FROM $CMT) + ; EXIT ACC=0: OK CF=0 + ; =1: ER CF=1 + ; =2: BREAK CF=1 + +QRDI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H ; "R" + LD E,0CCH ; "L" + LD BC,80H + LD HL,IBUFE +RD1: CALL MOTOR + JP C,RTP6 + CALL TMARK + JP C,RTP6 + CALL RTAPE + JP RTP4 + + ; READ DATA (FROM $CMT) + ; EXIT SAME UP + +QRDD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H ; "R" + LD E,53H ; "S" + LD BC,(SIZE) + LD HL,(DTADR) + LD A,B + OR C + JP Z,RTP4 + JR RD1 + + ; READ TAPE + ; IN BC=SIZE + ; DE=LOAD ADDRESS + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK=1 + +RTAPE: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; TWICE WRITE +RTP1: LD BC,KEYPB + LD DE,CSTR +RTP2: CALL EDGE ; 1-->0 EDGE DETECT + JR C,RTP6 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) ; DATA (1 BIT) READ + AND 20H + JP Z,RTP2 + LD D,H + LD HL,0 + LD (SUMDT),HL + POP HL + POP BC + PUSH BC + PUSH HL +RTP3: CALL RBYTE ; 1 BYTE READ + JR C,RTP6 + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JR NZ,RTP3 + LD HL,(SUMDT) ; CHECK SUM + CALL RBYTE ; CHECK SUM DATA + JR C,RTP6 + LD E,A + CALL RBYTE ; CHECK SUM DATA + JR C,RTP6 + CP L + JR NZ,RTP5 + LD A,E + CP H + JR NZ,RTP5 +RTP8: XOR A +RTP4: +RET2: POP HL + POP BC + POP DE + CALL MSTOP + PUSH AF + LD A,(TIMFG) ; INT. CHECK + CP 0F0H + JR NZ,L0563 + EI +L0563: POP AF + RET + +RTP5: DEC D + JR Z,RTP7 + LD H,D + CALL GAPCK + JR RTP1 + +RTP7: LD A,01H + JR RTP9 + +RTP6: LD A,02H +RTP9: SCF + JR RTP4 + + ; BELL + +QBEL: PUSH DE + LD DE,QBELD + RST 30H ; CALL MELODY + POP DE + RET + + ; FLASHING AND KEYIN + ; EXIT: ACC INPUT KEY DATA (DSP.CODE) + ; H=F0H THEN NO KEYIN (Z FLAG) + +FLKEY: CALL QFLAS + CALL QKEY + CP 0F0H + RET + + NOP + + ; VERIFY (FROM $CMT) + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER CF=1 + ; =2 : BREAK CF=1 + +QVRFY: DI + PUSH DE + PUSH BC + PUSH HL + LD BC,(SIZE) + LD HL,(DTADR) + LD D,0D2H ; "R" + LD E,53H ; "S" + LD A,B + OR C + JR Z,RTP4 ; END + CALL CKSUM + CALL MOTOR + JR C,RTP6 ; BRK + CALL TMARK ; TAPE MARK DETECT + JR C,RTP6 ; BRK + CALL TVRFY + JR RTP4 + + ; DATA VERIFY + ; BC=SIZE + ; HL=DATA LOW ADDRESS + ; CSMDT=CHECK SUM + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK =1 + +TVRFY: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; COMPARE TWICE +TVF1: LD BC,KEYPB + LD DE,CSTR +TVF2: CALL EDGE + JP C,RTP6 ; BRK + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JP Z,TVF2 + LD D,H + POP HL + POP BC + PUSH BC + PUSH HL + ; COMPARE TAPE DATA AND STORAGE +TVF3: CALL RBYTE + JR C,RTP6 ; BRK + CP (HL) + JR NZ,RTP7 ; ERROR, NOT EQUAL + INC HL ; STORAGE ADDRESS + 1 + DEC BC ; SIZE - 1 + LD A,B + OR C + JR NZ,TVF3 + ; COMPARE CHECK SUM (1199H/CSMDT) AND TAPE + LD HL,(CSMDT) + CALL RBYTE + CP H + JR NZ,RTP7 ; ERROR, NOT EQUAL + CALL RBYTE + CP L + JR NZ,RTP7 ; ERROR, NOT EQUAL + DEC D ; NUMBER OF COMPARES (2) - 1 + JP Z,RTP8 ; OK, 2 COMPARES + LD H,D ; (-->05C7H), SAVE NUMBER OF COMPARES + JR TVF1 ; NEXT COMPARE + + ; FLASHING DATA LOAD + +QLOAD: PUSH AF + LD A,(FLASH) + CALL QPONT + LD (HL),A + POP AF + RET + + ; NEW LINE AND PRINT HL REG (ASCII) + +NLPHL: CALL NL + CALL PRTHL + RET + + ; EDGE (TAPE DATA EDGE DETECT) + ; BC=KEYPB (E001H) + ; DE=CSTR (E002H) + ; EXIT CF=0 OK CF=1 BREAK + +EDGE: LD A,0F8H ; BREAK KEY IN (88H WOULD BE BETTER!!) + LD (KEYPA),A + NOP +EDG1: LD A,(BC) + AND 81H ; SHIFT & BREAK + JR NZ,L060E + SCF + RET + +L060E: LD A,(DE) + AND 20H + JR NZ,EDG1 ; CSTR D5 = 0 +EDG2: LD A,(BC) ; 8 + AND 81H ; 9 + JR NZ,L061A ; 10/14 + SCF + RET + +L061A: LD A,(DE) ; 8 + AND 20H ; 9 + JR Z,EDG2 ; CSTR D5 = 1 10/14 + RET ; 11 + + NOP + NOP + NOP + NOP + ; 1 BYTE READ + ; EXIT SUMDT=STORE + ; CF=1 : BREAK + ; CF=0 : DATA=ACC + +RBYTE: PUSH BC + PUSH DE + PUSH HL + LD HL,0800H ; 8 BITS + LD BC,KEYPB ; KEY DATA E001H + LD DE,CSTR ; $TAPE DATA E002H +RBY1: CALL EDGE ; 41 OR 101 + JP C,RBY3 ; 13 (SHIFT & BREAK) + CALL DLY3 ; 20+18*63+33 + LD A,(DE) ; DATA READ :8 + AND 20H + JP Z,RBY2 ; 0 + PUSH HL + LD HL,(SUMDT) + INC HL ; CHECK SUM ; COUNT HIGH BITS ON TAPE + LD (SUMDT),HL + POP HL + SCF +RBY2: LD A,L ; BUILD CHAR + RLA + LD L,A + DEC H ; BITCOUNT-1 + JP NZ,RBY1 + CALL EDGE + LD A,L ; CHAR READ +RBY3: POP HL + POP DE + POP BC + RET + + NOP + NOP + NOP + + ; TAPE MARK DETECT + ; E=@L@ : INFORMATION + ; =@S@ : DATA + ; EXIT CF=0 OK + ; =1 BREAK + +TMARK: CALL GAPCK + PUSH BC + PUSH DE + PUSH HL + LD HL,2828H + LD A,E + CP 0CCH ; "L" + JR Z,L066C + LD HL,1414H +L066C: LD (TMCNT),HL + LD BC,KEYPB + LD DE,CSTR +TM1: LD HL,(TMCNT) +TM2: CALL EDGE + JR C,TM4 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR Z,TM1 + DEC H + JR NZ,TM2 +TM3: CALL EDGE + JR C,TM4 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR NZ,TM1 + DEC L + JR NZ,TM3 + CALL EDGE +TM4: +RET3: POP HL + POP DE + POP BC + RET + + ; MOTOR ON + ; IN D=@W@ :WRITE + ; =@R@ :READ + ; EXIT CF=0 OK + ; =1 BREAK + ; + ; If the button is pressed, + +MOTOR: PUSH BC + PUSH DE + PUSH HL + LD B,0AH ; Pulse motor upto 10 times if sense is low. Each pulse flips on->off or off->on +MOT1: LD A,(CSTR) ; Check sense, if low then pulse motor to switch it on. + AND 10H + JR Z,MOT4 ; If NZ (bit PC4 is high), then wait a bit and return, motor running. + ; If Z then pulse the motor on circuit. +MOT2: LD B,0FFH ; 2 SEC DELAY +L06AD: CALL DLY12 ; 7 MSEC DELAY + JR L06B4 ; MOTOR ENTRY ADJUST + + JR MOTOR ; ORG 06B2H + +L06B4: DJNZ L06AD + XOR A +MOT7: JR RET3 + +MOT4: LD A,06H ; + LD HL,CSTPT ; 8255 Control register + LD (HL),A ; Set PC3 low + INC A + LD (HL),A ; Set PC3 high + DJNZ MOT1 ; Check to see if sense now active. + CALL NL ; Sense not active so play button hasnt been pressed. + LD A,D ; Determine if we are Loading or Saving, display correct message. + CP 0D7H ; "W" + JR Z,MOT8 + LD DE,MSGN1 ; PLAY MARK + JR MOT9 + +MOT8: LD DE,MSGN3 ; "RECORD." + RST 18H ; CALL MSGX + LD DE,MSGN2 ; "PLAY" +MOT9: RST 18H ; CALL MSGX +MOT5: LD A,(CSTR) ; Check sense input and wait until it is high. + AND 10H + JR NZ,MOT2 + CALL QBRK ; If sense is low, check for User Key Break entry. + JR NZ,MOT5 + SCF + JR MOT7 + + ; INITIAL MESSAGE + +MSGQ3: DB "** MONITOR 1Z-013A **\r" + NOP + + ; MOTOR STOP + +MSTOP: PUSH AF + PUSH BC + PUSH DE + LD B,0AH +MST1: LD A,(CSTR) + AND 10H + JR Z,MST3 + LD A,06H + LD (CSTPT),A + INC A + LD (CSTPT),A + DJNZ MST1 +MST3: JP QRSTR1 + + ; CHECK SUM + ; IN BC=SIZE + ; HL=DATA ADDRESS + ; EXIT SUMDT=STORE + ; CSMDT=STORE + +CKSUM: PUSH BC + PUSH DE +L071C: PUSH HL + LD DE,0 +CKS1: LD A,B + OR C + JR NZ,CKS2 + EX DE,HL +L0725: LD (SUMDT),HL ; NUMBER OF HIGHBITS IN DATA + LD (CSMDT),HL + POP HL + POP DE + POP BC + RET + +CKS2: LD A,(HL) + PUSH BC + LD B,8 +CKS3: RLCA + JR NC,L0737 + INC DE +L0737: DJNZ CKS3 +L0739: POP BC + INC HL + DEC BC + JR CKS1 + + ; MODE SET OF KEYPORT + +QMODE: LD HL,KEYPF + LD (HL),8AH ; 10001010 CTRL WORD MODE0 + LD (HL),07H ; PC3=1 M-ON + LD (HL),05H ; PC2=1 INTMSK + LD (HL),01H ; TZ: Enable VGATE (2xNOP removed below to keep ROM consistency). + RET + + ;NOP + ;NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; 107 MICRO SEC DELAY + +DLY1: LD A,15H ; 18*21+20 +L075B: DEC A + JP NZ,L075B + RET + +DLY2: LD A,13H ; 18*19+20 +L0762: DEC A + JP NZ,L0762 + RET + + ; 1 BYTE WRITE + +WBYTE: PUSH BC + LD B,8 + CALL LONG +WBY1: RLCA + CALL C,LONG + CALL NC,SHORT + DEC B + JP NZ,WBY1 + POP BC + RET + + ; GAP + TAPEMARK + ; E=@L@ LONG GAP + ; =@s@ SHORT GAP + +GAP: PUSH BC + PUSH DE + LD A,E + LD BC,55F0H + LD DE,2828H + CP 0CCH ; "L" + JP Z,GAP1 + LD BC,2AF8H + LD DE,1414H +GAP1: CALL SHORT + DEC BC + LD A,B + OR C + JR NZ,GAP1 +GAP2: CALL LONG + DEC D + JR NZ,GAP2 +GAP3: CALL SHORT + DEC E + JR NZ,GAP3 + CALL LONG + POP DE + POP BC + RET + + ; MEMORY CORRECTION + ; COMMAND "M" + +MCOR: CALL HEXIY ; CORRECTION ADDRESS +MCR1: CALL NLPHL ; CORRECTION ADDRESS PRINT + CALL SPHEX ; ACC-->ASCII DISP. + CALL QPRTS ; SPACE PRINT + CALL BGETL ; GET DATA & CHECK DATA + CALL HLHEX ; HL<--ASCII(DE) + JR C,MCR3 + CALL P4DE ; (INC DE)*4 + INC DE + CALL L2HEX ; DATA CHECK + JR C,MCR1 + CP (HL) + JR NZ,MCR1 + INC DE + LD A,(DE) + CP 0DH ; NOT CORRECTION ? + JR Z,MCR2 + CALL L2HEX ; ACC<--HL(ASCII) + JR C,MCR1 + LD (HL),A ; DATA CORRECT +MCR2: INC HL + JR MCR1 + +MCR3: LD H,B ; MEMORY ADDRESS + LD L,C + JR MCR1 + + DB "(HL)" + DB 0F1H + DB 9EH + DB "SUB (" + + ; GET 1 LINE STATEMENT * + ; DE=DATA STORE LOW ADDRESS + ; (END=CR) + +QGETL: PUSH AF + PUSH BC + PUSH HL + PUSH DE +GETL1: CALL QQKEY ; ENTRY KEY +AUTO3: PUSH AF ; IN KEY DATA SAVE + LD B,A + LD A,(SWRK) ; BELL WORK + RRCA + CALL NC,QBEL ; ENTRY BELL + LD A,B + LD HL,KANAF ; KANA & GRAPH FLAGS + AND 0F0H + CP 0C0H + POP DE ; EREG=FLAGREG + LD A,B + JR NZ,GETL2 ; NOT C0H + CP 0CDH ; CR + JR Z,GETL3 + CP 0CBH ; BREAK + JP Z,GETLC + CP 0CFH ; NIKO MARK WH. + JR Z,GETL2 + CP 0C7H ; CRT EDITION + JR NC,GETL5 ; <=C7H + RR E ; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL. + LD A,B + JR NC,GETL5 +GETL2: CALL QDSP ; DISPL. + JR GETL1 + +GETL5: CALL QDPCT ; CRT CONTROL + JR GETL1 + + ; BREAK IN + +GETLC: POP HL + PUSH HL + LD (HL),1BH ; BREAK CODE + INC HL + LD (HL),0DH + JR GETLR + + ; GETLA + +GETLA: RRCA ; CY<--D7 + JR NC,GETL6 + JR GETLB + + ; DELAY 7 MSEC AND SWEP + +DSWEP: CALL DLY12 + CALL QSWEP + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +GETL3: CALL PMANG ; CR + LD B,COLW ; 1 LINE + JR NC,GETLA + DEC H ; BEFORE LINE +GETLB: LD B,COLW*2 ; 2 LINE +GETL6: LD L,0 + CALL QPNT1 + POP DE ; STORE TOP ADDRESS + PUSH DE +GETLZ: LD A,(HL) + CALL QDACN + LD (DE),A + INC HL + INC DE + DJNZ GETLZ + EX DE,HL +GETLU: LD (HL),0DH + DEC HL + LD A,(HL) + CP 20H ; SPACE THEN CR + + ; CR AND NEW LINE + + JR Z,GETLU + + ; NEW LINE RETURN + +GETLR: CALL QLTNL + POP DE + POP HL + POP BC + POP AF + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; MESSAGE PRINT + ; DE PRINT DATA LOW ADDRESS + ; END=CR + +QMSG: PUSH AF + PUSH BC + PUSH DE +MSG1: LD A,(DE) + CP 0DH ; CR + JR Z,MSGX2 + CALL QPRNT + INC DE + JR MSG1 + + ; ALL PRINT MESSAGE + +QMSGX: PUSH AF + PUSH BC + PUSH DE +MSGX1: LD A,(DE) + CP 0DH +MSGX2: JP Z,QRSTR1 + CALL QADCN + CALL PRNT3 + INC DE + JR MSGX1 + + ; TOP OF KEYTBLS + +QKYSM: LD DE,KTBLS ; SHIFT ALSO + JR QKY5 + + ; BREAK CODE IN + +NBRK: LD A,0CBH ; BREAK CODE + OR A + JR QKY1 + + ; GETKEY + ; NO ECHO BACK + ; EXIT ACC=ASCII CODE + +QGET: CALL QKEY ; KEY IN (DISPLAY CODE) + SUB 0F0H ; NOT KEYIN CODE + RET Z + ADD A,0F0H + JP QDACN ; DISPLAY TO ASCII CODE + + NOP + NOP + + ; 1 KEY INPUT + ; IN B=KEY MODE (SHIFT, CTRL, BREAK) + ; C=KEY DATA (COLUMN & ROW) + ; EXIT ACC=DISPLAY CODE + ; IF NO KEY ACC=F0H + ; IF CY=1 THEN ATTRIBUTE ON + ; (SMALL, HIRAKANA) + +QKEY: PUSH BC + PUSH DE + PUSH HL + CALL DSWEP ; DELAY AND KEY SWEP + LD A,B + RLCA + JR C,QKY2 + LD A,0F0H ; SHIFT OR CTRL HERE +QKY1: POP HL + POP DE + POP BC + RET + +QKY2: LD DE,KTBL ; NORMAL KEY TABLE + LD A,B + CP 88H ; BREAK IN (SHIFT & BRK) + JR Z,NBRK + LD H,0 ; HL=ROW & COLUMN + LD L,C + BIT 5,A ; CTRL CHECK + JR NZ,L08F7 ; YES, CTRL + LD A,(KANAF) ; 0=NR., 1=GRAPH + RRCA + JP C,QKYGRP ; GRAPH MODE + LD A,B ; CTRL KEY CHECK + RLA + RLA + JR C,QKYSM + JR QKY5 + +L08F7: LD DE,KTBLC ; CONTROL KEY TABLE +QKY5: ADD HL,DE ; TABLE +QKY55: LD A,(HL) + JR QKY1 + +QKYGRP: BIT 6,B + JR Z,QKYGRS + LD DE,KTBLG + ADD HL,DE + SCF + JR QKY55 + +QKYGRS: LD DE,KTBLGS + JR QKY5 + + ; NEWLINE + +QLTNL: XOR A + LD (DPRNT),A ; ROW POINTER + LD A,0CDH ; CR + JR PRNT5 + + NOP + NOP + +QNL: LD A,(DPRNT) + OR A + RET Z + JR QLTNL + + NOP + + ; PRINT SPACE + +QPRTS: LD A,20H + JR QPRNT + + ; PRINT TAB + +QPRTT: CALL PRNTS + LD A,(DPRNT) + OR A + RET Z +L092C: SUB 10 + JR C,QPRTT + JR NZ,L092C + NOP + NOP + NOP + + ; PRINT + ; IN ACC=PRINT DATA (ASCII) + +QPRNT: CP 0DH ; CR + JR Z,QLTNL + PUSH BC + LD C,A + LD B,A + CALL QPRT + LD A,B + POP BC + RET + +MSGOK: DB "OK!\r" + + ; PRINT ROUTINE + ; 1 CHARACTER + ; INPUT:C=ASCII DATA (QDSP+QDPCT) + +QPRT: LD A,C + CALL QADCN ; ASCII TO DSPLAY + LD C,A + CP 0F0H + RET Z ; ZERO=ILLEGAL DATA + AND 0F0H ; MSD CHECK + CP 0C0H + LD A,C + JR NZ,PRNT3 + CP 0C7H + JR NC,PRNT3 ; CRT EDITOR +PRNT5: CALL QDPCT + CP 0C3H ; "->" + JR Z,PRNT4 + CP 0C5H ; HOME + JR Z,PRNT2 + CP 0C6H ; CLR + RET NZ +PRNT2: XOR A +L0968: LD (DPRNT),A + RET + +PRNT3: CALL QDSP +PRNT4: LD A,(DPRNT) ; TAB POINT+1 + INC A + CP COLW*2 + JR C,L0968 + SUB COLW*2 + JR L0968 + + ; FLASHING BYPASS 1 + +FLAS1: LD A,(FLASH) + JR FLAS2 + + ; BREAK SUBROUTINE BYPASS 1 + ; CTRL OR NOT KEY + +QBRK2: BIT 5,A ; NOT OR CTRL + JR Z,QBRK3 ; CTRL + OR A ; NOTKEY A=7FH + RET + +QBRK3: LD A,20H ; CTRL D5=1 + OR A ; ZERO FLG CLR + SCF + RET + +MSGSV: DB "FILENAME? " + DB 0DH + + ; DLY 7 MSEC +DLY12: PUSH BC + LD B,15H +L0999: CALL DLY3 + DJNZ L0999 + POP BC + RET + + ; LOADING MESSAGE + +MSGQ2: DB "LOADING \r" + + ; DELAY FOR LONG PULSE + +DLY4: LD A,59H ; 18*89+20 +L09AB: DEC A + JP NZ,L09AB + RET + + NOP + NOP + NOP + + ; KEY BOARD SEARCH + ; & DISPLAY CODE CONVERSION + ; EXIT A=DISPLAY CODE + ; CY=GRAPH MODE + ; WITH CURSOR DISPLAY + +QQKEY: PUSH HL + CALL QSAVE +KSL1: CALL FLKEY ; KEY + JR NZ,KSL1 ; KEY IN THEN JUMP +KSL2: CALL FLKEY + JR Z,KSL2 ; NOT KEY IN THEN JUMP + LD H,A + CALL DLY12 ; DELAY CHATTER + CALL QKEY + PUSH AF + CP H ; CHATTER CHECK + POP HL + JR NZ,KSL2 + PUSH HL + POP AF ; IN KEY DATA + CALL QLOAD ; FLASHING DATA LOAD + POP HL + RET + + ; CLEAR 2 + +NCLR08: XOR A ; CY FLAG +NCLR8: LD BC,0800H +CLEAR: PUSH DE ; BC=CLR BYTE SIZE, A=CLR DATA + LD D,A +CLEAR1: LD (HL),D + INC HL + DEC BC + LD A,B + OR C + JR NZ,CLEAR1 + POP DE + RET + + ; FLASHING 2 + +QFLS: PUSH AF + PUSH HL + LD A,(KEYPC) + RLCA + RLCA + JR C,FLAS1 + LD A,(FLSDT) +FLAS2: CALL QPONT ; DISPLAY POSITION + LD (HL),A + POP HL + POP AF + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +QFLAS: JR QFLS + + ; SHORT AND LONG PULSE FOR 1 BIT WRITE + +SHORT: PUSH AF ; 12 + LD A,03H ; 9 + LD (CSTPT),A ; E003H PC3=1:16 + CALL DLY1 ; 20+18*21+20 + CALL DLY1 ; 20+18*21+20 + LD A,02H ; 9 + LD (CSTPT),A ; E003H PC3=0:16 + CALL DLY1 ; 20+18*21+20 + CALL DLY1 ; 20+18*21+20 + POP AF ; 11 + RET ; 11 + +LONG: PUSH AF ; 11 + LD A,03H ; 9 + LD (CSTPT),A ; 16 + CALL DLY4 ; 20+18*89+20 + LD A,02H ; 9 + LD (CSTPT),A ; 16 + CALL DLY4 ; 20+18*89+20 + POP AF ; 11 + RET ; 11 + + NOP + NOP + NOP + NOP + NOP + + ; BREAK KEY CHECK + ; AND SHIFT, CTRL KEY CHECK + ; EXIT BREAK ON : ZERO=1 + ; OFF: ZERO=0 + ; NO KEY : CY =0 + ; KEY IN : CY =1 + ; A D6=1 : SHIFT ON + ; =0 : OFF + ; D5=1 : CTRL ON + ; =0 : OFF + ; D4=1 : SHIFT+CNT ON + ; =0 : OFF + +QBRK: LD A,0F8H ; LINE 8SWEEP + LD (KEYPA),A + NOP + LD A,(KEYPB) + OR A + RRA + JP C,QBRK2 ; SHIFT ? + RLA + RLA + JR NC,QBRK1 ; BREAK ? + LD A,40H ; SHIFT D6=1 + SCF + RET + +QBRK1: XOR A ; SHIFT ? + RET + + ; 320 U SEC DELAY + +DLY3: LD A,3FH ; 18*63+33 + JP L0762 ; JP DLY2+2 + + NOP + + ; KEY BOARD SWEEP + ; EXIT B,D7=0 NO DATA + ; =1 DATA + ; D6=0 SHIFT OFF + ; =1 SHIFT ON + ; D5=0 CTRL OFF + ; =1 CTRL ON + ; D4=0 SHIFT+CTRL OFF + ; =1 SHIFT+CTRL ON + ; C = ROW & COLUMN + ; 7 6 5 4 3 2 1 0 + ; * * ^ ^ ^ < < < + +QSWEP: PUSH DE + PUSH HL + XOR A + LD B,0F8H + LD D,A + CALL QBRK + JR NZ,SWEP6 + LD D,88H ; BREAK ON + JR SWEP9 + +SWEP6: JR NC,SWEP0 + LD D,A + JR SWEP0 + +SWEP01: SET 7,D +SWEP0: DEC B + LD A,B + LD (KEYPA),A + CP 0EFH ; MAP SWEEP END ? + JR NZ,SWEP3 + CP 0F8H ; BREAK KEY ROW + JR Z,SWEP0 +SWEP9: LD B,D + POP HL + POP DE + RET + +SWEP3: LD A,(KEYPB) + CPL + OR A + JR Z,SWEP0 + LD E,A +SWEP2: LD H,8 + LD A,B + AND 0FH + RLCA + RLCA + RLCA + LD C,A + LD A,E +L0A89: DEC H + RRCA + JR NC,L0A89 + LD A,H + ADD A,C + LD C,A + JR SWEP01 + ; + ; + ; ASCII TO DISPLAY CODE TABL + ; +ATBL: + ; 00 - 0F + DB 0F0H ; ^ @ + DB 0F0H ; ^ A + DB 0F0H ; ^ B + DB 0F3H ; ^ C + DB 0F0H ; ^ D + DB 0F5H ; ^ E + DB 0F0H ; ^ F + DB 0F0H ; ^ G + DB 0F0H ; ^ H + DB 0F0H ; ^ I + DB 0F0H ; ^ J + DB 0F0H ; ^ K + DB 0F0H ; ^ L + DB 0F0H ; ^ M + DB 0F0H ; ^ N + DB 0F0H ; ^ O + ; 10 - 1F + DB 0F0H ; ^ P + DB 0C1H ; ^ Q CUR. DOWN + DB 0C2H ; ^ R CUR. UP + DB 0C3H ; ^ S CUR. RIGHT + DB 0C4H ; ^ T CUR. LEFT + DB 0C5H ; ^ U HOME + DB 0C6H ; ^ V CLEAR + DB 0F0H ; ^ W + DB 0F0H ; ^ X + DB 0F0H ; ^ Y + DB 0F0H ; ^ Z SEP. + DB 0F0H ; ^ [ + DB 0F0H ; ^ \ + DB 0F0H ; ^ ] + DB 0F0H ; ^ ^ + DB 0F0H ; ^ - + ; 20 - 2F + DB 00H ; SPACE + DB 61H ; ! + DB 62H ; " + DB 63H ; # + DB 64H ; $ + DB 65H ; % + DB 66H ; & + DB 67H ; ' + DB 68H ; ( + DB 69H ; ) + DB 6BH ; * + DB 6AH ; + + DB 2FH ; , + DB 2AH ; - + DB 2EH ; . + DB 2DH ; / + ; 30 - 3F + DB 20H ; 0 + DB 21H ; 1 + DB 22H ; 2 + DB 23H ; 3 + DB 24H ; 4 + DB 25H ; 5 + DB 26H ; 6 + DB 27H ; 7 + DB 28H ; 8 + DB 29H ; 9 + DB 4FH ; : + DB 2CH ; ; + DB 51H ; < + DB 2BH ; = + DB 57H ; > + DB 49H ; ? + ; 40 - 4F + DB 55H ; @ + DB 01H ; A + DB 02H ; B + DB 03H ; C + DB 04H ; D + DB 05H ; E + DB 06H ; F + DB 07H ; G + DB 08H ; H + DB 09H ; I + DB 0AH ; J + DB 0BH ; K + DB 0CH ; L + DB 0DH ; M + DB 0EH ; N + DB 0FH ; O + ; 50 - 5F + DB 10H ; P + DB 11H ; Q + DB 12H ; R + DB 13H ; S + DB 14H ; T + DB 15H ; U + DB 16H ; V + DB 17H ; W + DB 18H ; X + DB 19H ; Y + DB 1AH ; Z + DB 52H ; [ + DB 59H ; \ + DB 54H ; ] + DB 50H ; + DB 45H ; + ; 60 - 6F + DB 0C7H ; UFO + DB 0C8H + DB 0C9H + DB 0CAH + DB 0CBH + DB 0CCH + DB 0CDH + DB 0CEH + DB 0CFH + DB 0DFH + DB 0E7H + DB 0E8H + DB 0E5H + DB 0E9H + DB 0ECH + DB 0EDH + ; 70 - 7F + DB 0D0H + DB 0D1H + DB 0D2H + DB 0D3H + DB 0D4H + DB 0D5H + DB 0D6H + DB 0D7H + DB 0D8H + DB 0D9H + DB 0DAH + DB 0DBH + DB 0DCH + DB 0DDH + DB 0DEH + DB 0C0H + ; 80 - 8F + DB 80H ; } + DB 0BDH + DB 9DH + DB 0B1H + DB 0B5H + DB 0B9H + DB 0B4H + DB 9EH + DB 0B2H + DB 0B6H + DB 0BAH + DB 0BEH + DB 9FH + DB 0B3H + DB 0B7H + DB 0BBH + ; 90 - 9F + DB 0BFH ; _ + DB 0A3H + DB 85H + DB 0A4H ; ` + DB 0A5H ; ~ + DB 0A6H + DB 94H + DB 87H + DB 88H + DB 9CH + DB 82H + DB 98H + DB 84H + DB 92H + DB 90H + DB 83H + ; A0 - AF + DB 91H + DB 81H + DB 9AH + DB 97H + DB 93H + DB 95H + DB 89H + DB 0A1H + DB 0AFH + DB 8BH + DB 86H + DB 96H + DB 0A2H + DB 0ABH + DB 0AAH + DB 8AH + ; B0 - BF + DB 8EH + DB 0B0H + DB 0ADH + DB 8DH + DB 0A7H + DB 0A8H + DB 0A9H + DB 8FH + DB 8CH + DB 0AEH + DB 0ACH + DB 9BH + DB 0A0H + DB 99H + DB 0BCH ; { + DB 0B8H + ; C0 - CF + DB 40H + DB 3BH + DB 3AH + DB 70H + DB 3CH + DB 71H + DB 5AH + DB 3DH + DB 43H + DB 56H + DB 3FH + DB 1EH + DB 4AH + DB 1CH + DB 5DH + DB 3EH + ; D0 - DF + DB 5CH + DB 1FH + DB 5FH + DB 5EH + DB 37H + DB 7BH + DB 7FH + DB 36H + DB 7AH + DB 7EH + DB 33H + DB 4BH + DB 4CH + DB 1DH + DB 6CH + DB 5BH + ; E0 - EF + DB 78H + DB 41H + DB 35H + DB 34H + DB 74H + DB 30H + DB 38H + DB 75H + DB 39H + DB 4DH + DB 6FH + DB 6EH + DB 32H + DB 77H + DB 76H + DB 72H + ; F0 - FF + DB 73H + DB 47H + DB 7CH + DB 53H + DB 31H + DB 4EH + DB 6DH + DB 48H + DB 46H + DB 7DH + DB 44H + DB 1BH + DB 58H + DB 79H + DB 42H + DB 60H + + ; FLASHING DATA SAVE + +QSAVE: LD HL,FLSDT + LD (HL),0EFH ; NORMAL CURSOR + LD A,(KANAF) + RRCA + JR C,L0BA0 ; GRAPH MODE + RRCA + JR NC,SV0 ; NORMAL MODE +L0BA0: LD (HL),0FFH ; GRAPH CURSOR +SV0: LD A,(HL) + PUSH AF + CALL QPONT ; FLASHING POSITION + LD A,(HL) + LD (FLASH),A + POP AF + LD (HL),A + XOR A + LD HL,KEYPA +L0BB1: LD (HL),A + CPL ; OH NO! UNUSED BITS WERE TOUCHED TOO!!! + LD (HL),A + RET + +SV1: LD (HL),43H ; KANA CURSOR + JR SV0 + + ; ASCII TO DISPLAY CODE CONVERT + ; IN ACC:ASCII + ; EXIT ACC:DISPLAY CODE + +QADCN: PUSH BC + PUSH HL + LD HL,ATBL + LD C,A + LD B,0 + ADD HL,BC + LD A,(HL) + JR DACN3 + +VRNS: DB "V1.0A\r" ; VERSION MANAGEMENT + NOP + NOP + NOP + + ; DISPLAY CODE TO ASCII CONVERSION + ; IN ACC=DISPLAY CODE + ; EXIT ACC=ASCII + +QDACN: PUSH BC + PUSH HL + PUSH DE + LD HL,ATBL + LD D,H + LD E,L + LD BC,0100H + CPIR + JR Z,DACN1 + LD A,0F0H +DACN2: POP DE +DACN3: POP HL + POP BC + RET + +DACN1: OR A + DEC HL + SBC HL,DE + LD A,L + JR DACN2 + + ; + ; + ; KEY MATRIX TO DISPLAY CODE TABL + ; + +KTBL: ;S0 00 - 07 ; + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 040H ; CURSOR DOWN + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 04FH ; : + DB 02CH ; ; + DB 0CDH ; CR + ;S1 08 - 0F ; + DB 022H ; 2 + DB 021H ; 1 + DB 017H ; W + DB 011H ; Q + DB 001H ; A + DB 0C7H ; DEL + DB 000H ; NULL + DB 01AH ; Z + ;S2 10 - 17 ; + DB 024H ; 4 + DB 023H ; 3 + DB 012H ; R + DB 005H ; E + DB 004H ; D + DB 013H ; S + DB 018H ; X + DB 003H ; C + ;S3 18 - 1F ; + DB 026H ; 6 + DB 025H ; 5 + DB 019H ; Y + DB 014H ; T + DB 007H ; G + DB 006H ; F + DB 016H ; V + DB 002H ; B + ;S4 20 - 27 ; + DB 028H ; 8 + DB 027H ; 7 + DB 009H ; I + DB 015H ; U + DB 00AH ; J + DB 008H ; H + DB 00EH ; N + DB 000H ; SPACE + ;S5 28 - 2F ; + DB 020H ; 0 + DB 029H ; 9 + DB 010H ; P + DB 00FH ; O + DB 00CH ; L + DB 00BH ; K + DB 02FH ; , + DB 00DH ; M + ;S6 30 - 37 ; + DB 0BEH ; ^ + DB 02AH ; - + DB 052H ; [ + DB 055H ; @ + DB 04FH ; : + DB 02CH ; ; + DB 02DH ; / + DB 02EH ; . + ;S7 38 - 3F ; + DB 0C5H ; HOME + DB 059H ; \ + DB 0C3H ; CURSOR RIGHT + DB 0C2H ; CURSOR UP + DB 0CDH ; CR + DB 054H ; ] + DB 000H ; NULL + DB 049H ; ? + + ; + ; + ; KTBL SHIFT ON + ; +KTBLS: ;S0 00 - 07 + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 040H ; CURSOR DOWN + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 04FH ; : + DB 02CH ; ; + DB 0CDH ; CR + ;S1 08 - 0F + DB 062H ; " + DB 061H ; ! + DB 097H ; w + DB 091H ; q + DB 081H ; a + DB 0C8H ; INSERT + DB 000H ; NULL + DB 09AH ; z + ;S2 10 - 17 + DB 064H ; $ + DB 063H ; # + DB 092H ; r + DB 085H ; e + DB 084H ; d + DB 093H ; s + DB 098H ; x + DB 083H ; c + ;S3 18 - 1F ; + DB 066H ; & + DB 065H ; % + DB 099H ; y + DB 094H ; t + DB 087H ; g + DB 086H ; f + DB 096H ; v + DB 082H ; b + ;S4 20 - 27 + DB 068H ; ( + DB 067H ; ' + DB 089H ; i + DB 095H ; u + DB 08AH ; j + DB 088H ; h + DB 08EH ; n + DB 000H ; SPACE + ;S5 28 - 2F + DB 0BFH ; _ + DB 069H ; ) + DB 090H ; p + DB 08FH ; o + DB 08CH ; l + DB 08BH ; k + DB 051H ; < + DB 08DH ; m + ;S6 30 - 37 + DB 0A5H ; ~ + DB 02BH ; = + DB 0BCH ; ( + DB 0A4H ; ' + DB 06BH ; # + DB 06AH ; + + DB 045H ; <- + DB 057H ; > + ;S7 38 - 3F + DB 0C6H ; CLR + DB 080H ; | + DB 0C4H ; CURSOR LEFT + DB 0C1H ; CURSOR DOWN + DB 0CDH ; CR + DB 040H ; ) + DB 000H ; NULL + DB 050H ; UP^ + ; + ; + ; GRAPHIC + ; +KTBLG: ;S0 00 - 07 ; ;S0 00 - 07 + DB 03EH ; DB 0BFH ; SPARE + DB 037H ; DB 0F0H ; GRAPH BUT NULL + DB 038H ; DB 0E5H ; # + DB 03CH ; DB 0C9H ; ALPHA + DB 053H ; DB 0F0H ; NO + DB 0C7H ; DB 42H ; # ; + DB 000H ; DB 0B6H ; #: + DB 076H ; DB 0CDH ; CR + ;S1 08 - 0F ; ;S1 08 - 0F + DB 03EH ; #2 + DB 037H ; #1 + DB 038H ; #W + DB 03CH ; #Q + DB 053H ; #A + DB 0C7H ; #DEL + DB 000H ; #NULL + DB 076H ; #Z + ;S2 10 - 17 + DB 07BH ; #4 + DB 07FH ; #3 + DB 030H ; #R + DB 034H ; #E + DB 047H ; #D + DB 044H ; #S + DB 06DH ; #X + DB 0DEH ; #C + ;S3 18 - 1F + DB 05EH ; #6 + DB 03AH ; #5 + DB 075H ; #Y + DB 071H ; #T + DB 04BH ; #G + DB 04AH ; #F + DB 0DAH ; #V + DB 06FH ; #B + ;S4 20 - 27 + DB 0BDH ; #8 + DB 01FH ; #7 + DB 07DH ; #I + DB 079H ; #U + DB 05CH ; #J + DB 072H ; #H + DB 032H ; #N + DB 000H ; SPACE + ;S5 28 - 2F + DB 09CH ; #0 + DB 0A1H ; #9 + DB 0D6H ; #P + DB 0B0H ; #O + DB 0B4H ; #L + DB 05BH ; #K + DB 060H ; #, + DB 01CH ; #M + ;S6 30 - 37 + DB 09EH ; #^ + DB 0D2H ; #- + DB 0D8H ; #[ + DB 0B2H ; #@ + DB 0B6H ; ##: + DB 042H ; #; + DB 0DBH ; #/ + DB 0B8H ; #. + ;S7 38 - 3F + DB 0C5H ; HOME + DB 0D4H ; #\ + DB 0C3H ; CURSOR RIGHT + DB 0C2H ; CURSOR UP + DB 0CDH ; CR + DB 04EH ; #J + DB 000H ; NULL + DB 0BAH ; #? + ; + ; + ; CONTROL CODE + ; +KTBLGS: ;S0 00 - 07 ; ;S0 00 - 07 + DB 036H ; DB 0F0H + DB 03FH ; DB 0F0H + DB 078H ; DB 0F0H ; ^ + DB 07CH ; DB 0F0H + DB 046H ; DB 0F0H + DB 0C8H ; DB 0F0H + DB 000H ; DB 0F0H + DB 077H ; DB 0F0H + ;S1 08 - 0F ; ;S1 08 - 0F + DB 036H ; ?2 + DB 03FH ; ?1 + DB 078H ; ?W + DB 07CH ; ?Q + DB 046H ; ?A + DB 0C8H ; INST + DB 000H ; NULL + DB 077H ; ?Z + ;S2 10 - 17 + DB 03BH ; ?4 + DB 07EH ; ?3 + DB 070H ; ?R + DB 074H ; ?E + DB 048H ; ?D + DB 041H ; ?S + DB 0DDH ; ?X + DB 0D9H ; C + ;S3 18 - 1F + DB 01EH ; ?6 + DB 07AH ; ?5 + DB 035H ; ?Y + DB 031H ; ?T + DB 04CH ; ?G + DB 043H ; ?F + DB 0A6H ; ?V + DB 06EH ; ?B + ;S4 20 - 27 + DB 0A2H ; ?8 + DB 05FH ; ?7 + DB 03DH ; ?I + DB 039H ; ?U + DB 05DH ; ?J + DB 073H ; ?H + DB 033H ; ?N + DB 000H ; SPACE + ;S5 28 - 2F + DB 09DH ; ?0 + DB 0A3H ; ?9 + DB 0B1H ; ?P + DB 0D5H ; ?O + DB 056H ; ?L + DB 06CH ; ?K + DB 0D0H ; ?, + DB 01DH ; ?M + ;S6 30 - 37 + DB 09FH ; ?^ + DB 0D1H ; ?- + DB 0B3H ; ?[ + DB 0D7H ; ?@ + DB 04DH ; ?: + DB 0B5H ; ?; + DB 01BH ; ?/ + DB 0B9H ; ?. + ;S7 38 - 3F + DB 0C6H ; CLR + DB 0D3H ; ?\ + DB 0C4H ; CURSOR RIGHT + DB 0C1H ; CURSOR UP + DB 0CDH ; CR + DB 0B7H ; ?J + DB 000H ; NULL + DB 0BBH ; ?? + ; + ; KANA + ; +KTBLC: ;S0 00 - 07 ; ;S0 00 - 07 + DB 0F0H ; DB 0BFH ; SPARE + DB 0F0H ; DB 0F0H ; GRAPH BUT NULL + DB 0E2H ; DB 0CFH ; NIKO WH. + DB 0C1H ; DB 0C9H ; ALPHA + DB 0E0H ; DB 0F0H ; NO + DB 0F0H ; DB 0B5H ; MO + DB 000H ; DB 4DH ; DAKU TEN + DB 0E5H ; DB 0CDH ; CR + ;S1 08 - 0F ; ;S1 08 - 0F + DB 0F0H ; CODE 80H=NOT KEY + DB 0F0H ; + DB 0E2H ; CTRL + W + DB 0C1H ; CTRL + Q + DB 0E0H ; CTRL + A SHIFT LOCK + DB 0F0H ; + DB 000H ; + DB 0E5H ; CTRL + Z + ;S2 10 - 17 ; ;S2 10 - 17 + DB 0F0H ; + DB 0F0H ; + DB 0C2H ; CTRL + R + DB 0CFH ; CTRL + E ROLL DOWN + DB 0CEH ; CTRL + D ROLL UP + DB 0C3H ; CTRL + S + DB 0E3H ; CTRL + X + DB 0F3H ; CTRL + C + ;S3 18 - 1F ; ;S3 18 - 1F + DB 0F0H ; + DB 0F0H ; + DB 0E4H ; CTRL + Y + DB 0C4H ; CTRL + T + DB 0F7H ; CTRL + G + DB 0F6H ; CTRL + F + DB 0C6H ; CTRL + V CLR + DB 0F2H ; CTRL + B + ;S4 20 - 27 ; ;S4 20 - 27 + DB 0F0H ; + DB 0F0H ; + DB 0F9H ; CTRL + I + DB 0C5H ; CTRL + U HOME + DB 0FAH ; CTRL + J + DB 0F8H ; CTRL + H + DB 0FEH ; CTRL + N + DB 0F0H ; + ;S5 28 - 2F ; ;S5 28 - 2F + DB 0F0H ; + DB 0F0H ; + DB 0E1H ; CTRL + P + DB 0FFH ; CTRL + O + DB 0FCH ; CTRL + L + DB 0FBH ; CTRL + K + DB 0F0H ; + DB 0FDH ; CTRL + M + ;S6 30 - 37 ; ;S6 30 - 37 + DB 0EFH ; CTRL + ^ + DB 0F4H ; CTRL + - + DB 0E6H ; CTRL + [ + DB 0CCH ; CTRL + @ REVERSE + DB 0F0H ; + DB 0F0H ; + DB 0F0H ; + DB 0F0H ; + ;S7 38 - 3F ; ;S7 38 - 3F + DB 0F0H ; + DB 0EBH ; CTRL + \ + DB 0F0H ; + DB 0F0H ; + DB 0F0H ; + DB 0EEH ; CTRL + ] + DB 0F0H ; + + ; MEMORY DUMP COMMAND "D" + +DUMP: CALL HEXIY ; START ADDRESS + CALL P4DE + PUSH HL + CALL HLHEX ; END ADDRESS + POP DE + JR C,DUM1 ; DATA ERROR THEN +L0D36: EX DE,HL +DUM3: LD B,08H ; DISPLAY 8 BYTES + LD C,23 ; CHANGE PRINT BIAS + CALL NLPHL ; NEWLINE PRINT +DUM2: CALL SPHEX ; SPACE PRINT + ACC PRINT + INC HL + PUSH AF + LD A,(DSPXY) ; DISPLAY POINT + ADD A,C + LD (DSPXY),A ; X AXIS=X+CREG + POP AF + CP 20H + JR NC,L0D51 + LD A,2EH ; "." +L0D51: CALL QADCN ; ASCII TO DISPLAY CODE + CALL PRNT3 + LD A,(DSPXY) + INC C + SUB C ; ASCII DISPLAY POSITION + LD (DSPXY),A + DEC C + DEC C + DEC C + PUSH HL + SBC HL,DE + POP HL + JR Z,L0D85 + LD A,0F8H + LD (KEYPA),A + NOP + LD A,(KEYPB) + CP 0FEH ; SHIFT KEY ? + JR NZ,L0D78 + CALL QBLNK ; 64MSEC DELAY +L0D78: DJNZ DUM2 +L0D7A: CALL QKEY ; STOP DISPLAY + OR A + JR Z,L0D7A ; SPACE KEY THEN STOP + CALL QBRK ; BREAK IN ? + JR NZ,DUM3 +L0D85: JP ST1 ; COMMAND IN ! + +DUM1: LD HL,160 ; 20*8 BYTES + ADD HL,DE + JR L0D36 + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; V-BLANK CHECK + +QBLNK: PUSH AF +L0DA7: LD A,(KEYPC) ; V-BLANK + RLCA + JR NC,L0DA7 +L0DAD: LD A,(KEYPC) ; 64 + RLCA ; + JR C,L0DAD ; MSEC + POP AF + RET + ; DISPLAY ON POINTER + ; ACC=DISPLAY CODE + ; EXCEPT F0H + +QDSP: PUSH AF + PUSH BC + PUSH DE + PUSH HL +DSP01: CALL QPONT ; DISPLAY POSITION + LD (HL),A + LD HL,(DSPXY) + LD A,L + CP COLW-1 + JR NZ,DSP04 + CALL PMANG + JR C,DSP04 + EX DE,HL + LD (HL),1 ; LOGICAL 1ST COLUMN + INC HL + LD (HL),0 ; LOGICAL 2ND COLUMN +DSP04: LD A,0C3H ; CURSL + JR L0DE0 + + ; GRAPHIC STATUS CHECK + +GRSTAS: LD A,(KANAF) + CP 01H + LD A,0CAH + RET + + ; DISPLAY CONTROL + ; ACC=CONTROL CODE + +QDPCT: PUSH AF + PUSH BC + PUSH DE + PUSH HL +L0DE0: LD B,A + AND 0F0H + CP 0C0H + JR NZ,CURS5 + XOR B + RLCA + LD C,A + LD B,0 + LD HL,CTBL ; PAGE MODE1 + ADD HL,BC + LD E,(HL) + INC HL + LD D,(HL) + LD HL,(DSPXY) + EX DE,HL + JP (HL) + +CURSD: EX DE,HL ; LD HL,(DSPXY) + LD A,H + CP 24 + JR Z,CURS4 + INC H +CURS1: +CURS3: LD (DSPXY),HL +CURS5: JP QRSTR + +CURSU: EX DE,HL ; LD HL,(DSPXY) + LD A,H + OR A + JR Z,CURS5 + DEC H +CURSU1: JR CURS3 + +CURSR: EX DE,HL ; LD HL,(DSPXY) + LD A,L + CP COLW-1 + JR NC,CURS2 + INC L + JR CURS3 + +CURS2: LD L,0 + INC H + LD A,H + CP 25 + JR C,CURS1 + LD H,24 + LD (DSPXY),HL +CURS4: JR SCROL + +CURSL: EX DE,HL ; LD HL,(DSPXY) + LD A,L + OR A + JR Z,L0E2D + DEC L + JR CURS3 + +L0E2D: LD L,COLW-1 + DEC H + JP P,CURSU1 + LD H,0 + LD (DSPXY),HL + JR CURS5 + +CLRS: LD HL,MANG + LD B,27 + CALL QCLER + LD HL,0D000H ; SCRN TOP + CALL NCLR08 + IF MODE80C = 0 + LD A,017H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode. + ELSE + LD A,017H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode. + ENDIF + ;LD A,71H ; COLOR DATA + CALL NCLR8 ; D800H-DFFFH CLEAR +HOME: LD HL,0 ; DSPXY:0 X=0,Y=0 + JR CURS3 + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; CR + +CR: CALL PMANG + RRCA + JR NC,CURS2 + LD L,0 + INC H + CP 24 + JR Z,CR1 + INC H + JR CURS1 + +CR1: LD (DSPXY),HL + + ; SCROLL + +SCROL: LD BC,SCRNSZ - COLW + LD DE,SCRN ; TOP OF $CRT ADDRESS + LD HL,SCRN+COLW ; COLUMN + PUSH BC ; 1000 STORE + LDIR + POP BC + PUSH DE + LD DE,SCRN + 800H ; COLOR RAM SCROLL + LD HL,SCRN + 800H + COLW ; SCROLL TOP + 1 LINE + LDIR + LD B,COLW ; ONE LINE + EX DE,HL + IF MODE80C = 0 + LD A,017H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode. + ELSE + LD A,017H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode. + ENDIF + ;LD A,71H ; COLOR RAM INITIAL DATA + CALL QDINT + POP HL + LD B,COLW + CALL QCLER ; LAST LINE CLEAR + LD BC,ROW + 1 ; ROW NUMBER+1 + LD DE,MANG ; LOGICAL MANAGEMENT + LD HL,MANG+1 + LDIR + LD (HL),0 + LD A,(MANG) + OR A + JR Z,QRSTR + LD HL,DSPXY+1 + DEC (HL) + JR SCROL + + ; CONTROL CODE TABLE + +CTBL: DW SCROL ; SCROLLING 10H + DW CURSD ; CURSOR DOWN 11H + DW CURSU ; CURSOR UP 12H + DW CURSR ; CURSOR RIGHT 13H + DW CURSL ; CURSOR LEFT 14H + DW HOME ; 15H + DW CLRS ; 16H + DW DEL ; 17H + DW INST ; 18H + DW ALPHA ; 19H + DW KANA ; GRAPHIC 1AH + DW QRSTR ; 1BH + DW QRSTR ; 1CH + DW CR ; 1DH + DW QRSTR ; 1EH + DW QRSTR ; 1FH + + ; INST BYPASS + +INST2: SET 3,H ; COLOR RAM + LD A,(HL) ; FROM + INC HL + LD (HL),A ; TO + DEC HL ; ADDRESS ADJUST + RES 3,H + LDD ; CHANGE TRNS. + LD A,C + OR B ; BC=0 ? + JR NZ,INST2 + EX DE,HL + LD (HL),0 + SET 3,H ; COLOR RAM + IF MODE80C = 0 + LD (HL),17H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode. + ELSE + LD (HL),17H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode. + ENDIF + ;LD (HL),71H + JR QRSTR + +ALPHA: XOR A +ALPH1: LD (KANAF),A + + ; RESTORE + +QRSTR: POP HL +QRSTR1: POP DE + POP BC + POP AF + RET + + NOP + NOP + NOP + NOP + +KANA: CALL GRSTAS + JP Z,DSP01 ; NOT GRAPH KEY THEN JUMP + LD A,01H + JR ALPH1 + +DEL: EX DE,HL ; LD HL,(DSPXY) + LD A,H ; HOME ? + OR L + JR Z,QRSTR + LD A,L + OR A + JR NZ,DEL1 ; LEFT SIDE ? + CALL PMANG + JR C,DEL1 + CALL QPONT + DEC HL + LD (HL),0 + JR L0F33 ; JUMP CURSL + +DEL1: CALL PMANG + RRCA + LD A,COLW + JR NC,L0F17 + RLCA ; ACC=80 +L0F17: SUB L + LD B,A ; TRNS. BYTE + CALL QPONT +DEL2: LD A,(HL) ; CHANGE FROM ADDRESS + DEC HL + LD (HL),A ; TO + INC HL + SET 3,H ; COLOR RAM + LD A,(HL) + DEC HL + LD (HL),A + RES 3,H ; CHANGE + INC HL + INC HL ; NEXT + DJNZ DEL2 + DEC HL ; ADDRESS ADJUST + LD (HL),0 + SET 3,H + IF MODE80C = 0 + LD HL,017H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode. + ELSE + LD HL,017H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode. + ENDIF + ;LD HL,71H ; BLUE + WHITE +L0F33: LD A,0C4H ; JP CURSL + JP L0DE0 + +INST: CALL PMANG + RRCA + LD L,COLW - 1 + LD A,L + JR NC,L0F42 + INC H +L0F42: CALL QPNT1 + PUSH HL + LD HL,(DSPXY) + JR NC,L0F4D + LD A,(COLW*2) - 1 +L0F4D: SUB L + LD B,0 + LD C,A + POP DE + JR Z,QRSTR + LD A,(DE) + OR A + JR NZ,QRSTR + LD H,D ; HL<-DE + LD L,E + DEC HL + JP INST2 ; JUMP NEXT (BYPASS) + + ; PROGRAM SAVE + ; COMMAND "S" + +SAVE: CALL HEXIY ; START ADDRESS + LD (DTADR),HL ; DATA ADDRESS BUFFER + LD B,H + LD C,L + CALL P4DE + CALL HEXIY ; END ADDRESS + SBC HL,BC ; BYTE SIZE + INC HL + LD (SIZE),HL ; BYTE SIZE BUFFER + CALL P4DE + CALL HEXIY ; EXECUTE ADDRESS + LD (EXADR),HL ; BUFFER + CALL NL + LD DE,MSGSV ; SAVED FILENAME + RST 18H ; CALL MSGX + CALL BGETL ; FILENAME INPUT + CALL P4DE + CALL P4DE + LD HL,NAME ; NAME BUFFER +SAV1: INC DE + LD A,(DE) + LD (HL),A ; FILENAME TRANS. + INC HL + CP 0DH ; END CODE + JR NZ,SAV1 + LD A,01H ; ATTRIBUTE: OBJECT CODE + LD (ATRB),A + CALL QWRI + JP C,QER ; WRITE ERROR + CALL QWRD ; DATA + JP C,QER + CALL NL + LD DE,MSGOK ; OK MESSAGE + RST 18H ; CALL MSGX + JP ST1 + + ; COMPUTE POINT ADDRESS + ; HL=SCREEN COORDINATE + ; EXIT HL=POINT ADDRESS ON SCREEN + +QPONT: LD HL,(DSPXY) +QPNT1: PUSH AF + PUSH BC + PUSH DE + PUSH HL + POP BC + LD DE,COLW ; 40 + LD HL,SCRN-COLW +QPNT2: ADD HL,DE + DEC B + JP P,QPNT2 + LD B,0 + ADD HL,BC + POP DE + POP BC + POP AF + RET + + ; VERIFYING COMMAND "V" + +VRFY: CALL QVRFY + JP C,QER + LD DE,MSGOK + RST 18H + JP ST1 + + ; CLER + ; B=SIZE + ; HL=LOW ADDRESS + +QCLER: XOR A + JR QDINT + +QCLRFF: LD A,0FFH +QDINT: LD (HL),A + INC HL + DJNZ QDINT + RET + + ; GAP CHECK + +GAPCK: PUSH BC + PUSH DE + PUSH HL + LD BC,KEYPB + LD DE,CSTR +GAPCK1: LD H,100 +GAPCK2: CALL EDGE + JR C,GAPCK3 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR NZ,GAPCK1 + DEC H + JR NZ,GAPCK2 +GAPCK3: JP RET3 + + ; MONITOR WORK AREA + ; (MZ700) + + ORG 10F0H +SPV: +IBUFE: ; TAPE BUFFER (128 BYTES) +ATRB: DS virtual 1 ; ATTRIBUTE +NAME: DS virtual 17 ; FILE NAME +SIZE: DS virtual 2 ; BYTESIZE +DTADR: DS virtual 2 ; DATA ADDRESS +EXADR: DS virtual 2 ; EXECUTION ADDRESS +COMNT: DS virtual 104 ; COMMENT +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 27 ; COLUMN MANAGEMENT +FLASH: DS virtual 1 ; FLASHING DATA +FLPST: DS virtual 2 ; FLASHING POSITION +FLSST: DS virtual 1 ; FLASHING STATUS +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER + + ; EQU TABLE I/O REPORT + +KEYPA: EQU 0E000H +KEYPB: EQU 0E001H +KEYPC: EQU 0E002H +KEYPF: EQU 0E003H +CSTR: EQU 0E002H +CSTPT: EQU 0E003H +CONT0: EQU 0E004H +CONT1: EQU 0E005H +CONT2: EQU 0E006H +CONTF: EQU 0E007H +SUNDG: EQU 0E008H +TEMP: EQU 0E008H + ; MONITOR WORK AREA + +SCRN: EQU 0D000H +KANST: EQU 0E003H ; KANA STATUS REPORT + + diff --git a/software/asm/1Z-013A.asm b/software/asm/1Z-013A.asm index d644405..a0a99ca 100644 --- a/software/asm/1Z-013A.asm +++ b/software/asm/1Z-013A.asm @@ -146,11 +146,11 @@ QER: CP 02H ; A=02H JR Z,ST1 LD DE,MSGE1 ; CHECK SUM ERROR RST 18H ; CALL MSGX -L010F: JR ST1 +L010F: JR ST1 ; LOAD COMMAND -LOAD: CALL QRDI +LOAD: CALL QRDI JR C,QER LOA0: CALL NL LD DE,MSGQ2 ; LOADING @@ -2374,382 +2374,386 @@ DACN1: OR A ; ; KEY MATRIX TO DISPLAY CODE TABL ; - -KTBL: ;S0 00 - 07 ; - DB 0F0H ; NULL - DB 0F0H ; NULL - DB 040H ; CURSOR DOWN - DB 0F0H ; NULL - DB 0F0H ; NULL - DB 04FH ; : - DB 02CH ; ; - DB 0CDH ; CR - ;S1 08 - 0F ; - DB 022H ; 2 - DB 021H ; 1 - DB 017H ; W - DB 011H ; Q - DB 001H ; A - DB 0C7H ; DEL - DB 000H ; NULL - DB 01AH ; Z - ;S2 10 - 17 ; - DB 024H ; 4 - DB 023H ; 3 - DB 012H ; R - DB 005H ; E - DB 004H ; D - DB 013H ; S - DB 018H ; X - DB 003H ; C - ;S3 18 - 1F ; - DB 026H ; 6 - DB 025H ; 5 - DB 019H ; Y - DB 014H ; T - DB 007H ; G - DB 006H ; F - DB 016H ; V - DB 002H ; B - ;S4 20 - 27 ; - DB 028H ; 8 - DB 027H ; 7 - DB 009H ; I - DB 015H ; U - DB 00AH ; J - DB 008H ; H - DB 00EH ; N - DB 000H ; SPACE - ;S5 28 - 2F ; - DB 020H ; 0 - DB 029H ; 9 - DB 010H ; P - DB 00FH ; O - DB 00CH ; L - DB 00BH ; K - DB 02FH ; , - DB 00DH ; M - ;S6 30 - 37 ; - DB 0BEH ; ^ - DB 02AH ; - - DB 052H ; [ - DB 055H ; @ - DB 04FH ; : - DB 02CH ; ; - DB 02DH ; / - DB 02EH ; . - ;S7 38 - 3F ; - DB 0C5H ; HOME - DB 059H ; \ - DB 0C3H ; CURSOR RIGHT - DB 0C2H ; CURSOR UP - DB 0CDH ; CR - DB 054H ; ] - DB 000H ; NULL - DB 049H ; ? - +KTBL: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0CAH ; GRAPH + DB 58H ; + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 2CH ; ; + DB 4FH ; : + DB 0CDH ; CR + ;S1 08 - 0F + DB 19H ; Y + DB 1AH ; Z + DB 55H ; @ + DB 52H ; [ + DB 54H ; ] + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 0F0H ; NULL + ;S2 10 - 17 + DB 11H ; Q + DB 12H ; R + DB 13H ; S + DB 14H ; T + DB 15H ; U + DB 16H ; V + DB 17H ; W + DB 18H ; X + ;S3 18 - 1F + DB 09H ; I + DB 0AH ; J + DB 0BH ; K + DB 0CH ; L + DB 0DH ; M + DB 0EH ; N + DB 0FH ; O + DB 10H ; P + ;S4 20 - 27 + DB 01H ; A + DB 02H ; B + DB 03H ; C + DB 04H ; D + DB 05H ; E + DB 06H ; F + DB 07H ; G + DB 08H ; H + ;S5 28 - 2F + DB 21H ; 1 + DB 22H ; 2 + DB 23H ; 3 + DB 24H ; 4 + DB 25H ; 5 + DB 26H ; 6 + DB 27H ; 7 + DB 28H ; 8 + ;S6 30 - 37 + DB 59H ; \ + DB 50H ; + DB 2AH ; - + DB 00H ; SPACE + DB 20H ; 0 + DB 29H ; 9 + DB 2FH ; , + DB 2EH ; . + ;S7 38 - 3F + DB 0C8H ; INST. + DB 0C7H ; DEL. + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 49H ; ? + DB 2DH ; / ; ; ; KTBL SHIFT ON ; -KTBLS: ;S0 00 - 07 - DB 0F0H ; NULL - DB 0F0H ; NULL - DB 040H ; CURSOR DOWN - DB 0F0H ; NULL - DB 0F0H ; NULL - DB 04FH ; : - DB 02CH ; ; - DB 0CDH ; CR - ;S1 08 - 0F - DB 062H ; " - DB 061H ; ! - DB 097H ; w - DB 091H ; q - DB 081H ; a - DB 0C8H ; INSERT - DB 000H ; NULL - DB 09AH ; z - ;S2 10 - 17 - DB 064H ; $ - DB 063H ; # - DB 092H ; r - DB 085H ; e - DB 084H ; d - DB 093H ; s - DB 098H ; x - DB 083H ; c - ;S3 18 - 1F ; - DB 066H ; & - DB 065H ; % - DB 099H ; y - DB 094H ; t - DB 087H ; g - DB 086H ; f - DB 096H ; v - DB 082H ; b - ;S4 20 - 27 - DB 068H ; ( - DB 067H ; ' - DB 089H ; i - DB 095H ; u - DB 08AH ; j - DB 088H ; h - DB 08EH ; n - DB 000H ; SPACE - ;S5 28 - 2F - DB 0BFH ; _ - DB 069H ; ) - DB 090H ; p - DB 08FH ; o - DB 08CH ; l - DB 08BH ; k - DB 051H ; < - DB 08DH ; m - ;S6 30 - 37 - DB 0A5H ; ~ - DB 02BH ; = - DB 0BCH ; ( - DB 0A4H ; ' - DB 06BH ; # - DB 06AH ; + - DB 045H ; <- - DB 057H ; > - ;S7 38 - 3F - DB 0C6H ; CLR - DB 080H ; | - DB 0C4H ; CURSOR LEFT - DB 0C1H ; CURSOR DOWN - DB 0CDH ; CR - DB 040H ; ) - DB 000H ; NULL - DB 050H ; UP^ +KTBLS: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0CAH ; GRAPH + DB 1BH ; POND + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 6AH ; + + DB 6BH ; * + DB 0CDH ; CR + ;S1 08 - 0F + DB 99H ; y + DB 9AH ; z + DB 0A4H ; ` + DB 0BCH ; { + DB 40H ; } + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 0F0H ; NULL + ;S2 10 - 17 + DB 91H ; q + DB 92H ; r + DB 93H ; s + DB 94H ; t + DB 95H ; u + DB 96H ; v + DB 97H ; w + DB 98H ; x + ;S3 18 - 1F + DB 89H ; i + DB 8AH ; j + DB 8BH ; k + DB 8CH ; l + DB 8DH ; m + DB 8EH ; n + DB 8FH ; o + DB 90H ; p + ;S4 20 - 27 + DB 81H ; a + DB 82H ; b + DB 83H ; c + DB 84H ; d + DB 85H ; e + DB 86H ; f + DB 87H ; g + DB 88H ; h + ;S5 28 - 2F + DB 61H ; ! + DB 62H ; " + DB 63H ; # + DB 64H ; $ + DB 65H ; % + DB 66H ; & + DB 67H ; ' + DB 68H ; ( + ;S6 30 - 37 + DB 80H ; \ + DB 0A5H ; POND MARK + DB 2BH ; YEN + DB 00H ; SPACE + DB 60H ; ¶ + DB 69H ; ) + DB 51H ; < + DB 57H ; > + ;S7 38 - 3F + DB 0C6H ; CLR + DB 0C5H ; HOME + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 5AH ; + DB 45H ; ; ; ; GRAPHIC ; -KTBLG: ;S0 00 - 07 ; ;S0 00 - 07 - DB 03EH ; DB 0BFH ; SPARE - DB 037H ; DB 0F0H ; GRAPH BUT NULL - DB 038H ; DB 0E5H ; # - DB 03CH ; DB 0C9H ; ALPHA - DB 053H ; DB 0F0H ; NO - DB 0C7H ; DB 42H ; # ; - DB 000H ; DB 0B6H ; #: - DB 076H ; DB 0CDH ; CR - ;S1 08 - 0F ; ;S1 08 - 0F - DB 03EH ; #2 - DB 037H ; #1 - DB 038H ; #W - DB 03CH ; #Q - DB 053H ; #A - DB 0C7H ; #DEL - DB 000H ; #NULL - DB 076H ; #Z - ;S2 10 - 17 - DB 07BH ; #4 - DB 07FH ; #3 - DB 030H ; #R - DB 034H ; #E - DB 047H ; #D - DB 044H ; #S - DB 06DH ; #X - DB 0DEH ; #C - ;S3 18 - 1F - DB 05EH ; #6 - DB 03AH ; #5 - DB 075H ; #Y - DB 071H ; #T - DB 04BH ; #G - DB 04AH ; #F - DB 0DAH ; #V - DB 06FH ; #B - ;S4 20 - 27 - DB 0BDH ; #8 - DB 01FH ; #7 - DB 07DH ; #I - DB 079H ; #U - DB 05CH ; #J - DB 072H ; #H - DB 032H ; #N - DB 000H ; SPACE - ;S5 28 - 2F - DB 09CH ; #0 - DB 0A1H ; #9 - DB 0D6H ; #P - DB 0B0H ; #O - DB 0B4H ; #L - DB 05BH ; #K - DB 060H ; #, - DB 01CH ; #M - ;S6 30 - 37 - DB 09EH ; #^ - DB 0D2H ; #- - DB 0D8H ; #[ - DB 0B2H ; #@ - DB 0B6H ; ##: - DB 042H ; #; - DB 0DBH ; #/ - DB 0B8H ; #. - ;S7 38 - 3F - DB 0C5H ; HOME - DB 0D4H ; #\ - DB 0C3H ; CURSOR RIGHT - DB 0C2H ; CURSOR UP - DB 0CDH ; CR - DB 04EH ; #J - DB 000H ; NULL - DB 0BAH ; #? +KTBLGS: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0F0H ; GRAPH BUT NULL + DB 0E5H ; # + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 42H ; # ; + DB 0B6H ; #: + DB 0CDH ; CR + ;S1 08 - 0F + DB 75H ; #Y + DB 76H ; #Z + DB 0B2H ; #@ + DB 0D8H ; #[ + DB 4EH ; #] + DB 0F0H ; #NULL + DB 0F0H ; #NULL + DB 0F0H ; #NULL + ;S2 10 - 17 + DB 3CH ; #Q + DB 30H ; #R + DB 44H ; #S + DB 71H ; #T + DB 79H ; #U + DB 0DAH ; #V + DB 38H ; #W + DB 6DH ; #X + ;S3 18 - 1F + DB 7DH ; #I + DB 5CH ; #J + DB 5BH ; #K + DB 0B4H ; #L + DB 1CH ; #M + DB 32H ; #N + DB 0B0H ; #O + DB 0D6H ; #P + ;S4 20 - 27 + DB 53H ; #A + DB 6FH ; #B + DB 0DEH ; #C + DB 47H ; #D + DB 34H ; #E + DB 4AH ; #F + DB 4BH ; #G + DB 72H ; #H + ;S5 28 - 2F + DB 37H ; #1 + DB 3EH ; #2 + DB 7FH ; #3 + DB 7BH ; #4 + DB 3AH ; #5 + DB 5EH ; #6 + DB 1FH ; #7 + DB 0BDH ; #8 + ;S6 30 - 37 + DB 0D4H ; #YEN + DB 9EH ; #+ + DB 0D2H ; #- + DB 00H ; SPACE + DB 9CH ; #0 + DB 0A1H ; #9 + DB 0CAH ; #, + DB 0B8H ; #. + ;S7 38 - 3F + DB 0C8H ; INST + DB 0C7H ; DEL. + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 0BAH ; #? + DB 0DBH ; #/ ; ; ; CONTROL CODE ; -KTBLGS: ;S0 00 - 07 ; ;S0 00 - 07 - DB 036H ; DB 0F0H - DB 03FH ; DB 0F0H - DB 078H ; DB 0F0H ; ^ - DB 07CH ; DB 0F0H - DB 046H ; DB 0F0H - DB 0C8H ; DB 0F0H - DB 000H ; DB 0F0H - DB 077H ; DB 0F0H - ;S1 08 - 0F ; ;S1 08 - 0F - DB 036H ; ?2 - DB 03FH ; ?1 - DB 078H ; ?W - DB 07CH ; ?Q - DB 046H ; ?A - DB 0C8H ; INST - DB 000H ; NULL - DB 077H ; ?Z - ;S2 10 - 17 - DB 03BH ; ?4 - DB 07EH ; ?3 - DB 070H ; ?R - DB 074H ; ?E - DB 048H ; ?D - DB 041H ; ?S - DB 0DDH ; ?X - DB 0D9H ; C - ;S3 18 - 1F - DB 01EH ; ?6 - DB 07AH ; ?5 - DB 035H ; ?Y - DB 031H ; ?T - DB 04CH ; ?G - DB 043H ; ?F - DB 0A6H ; ?V - DB 06EH ; ?B - ;S4 20 - 27 - DB 0A2H ; ?8 - DB 05FH ; ?7 - DB 03DH ; ?I - DB 039H ; ?U - DB 05DH ; ?J - DB 073H ; ?H - DB 033H ; ?N - DB 000H ; SPACE - ;S5 28 - 2F - DB 09DH ; ?0 - DB 0A3H ; ?9 - DB 0B1H ; ?P - DB 0D5H ; ?O - DB 056H ; ?L - DB 06CH ; ?K - DB 0D0H ; ?, - DB 01DH ; ?M - ;S6 30 - 37 - DB 09FH ; ?^ - DB 0D1H ; ?- - DB 0B3H ; ?[ - DB 0D7H ; ?@ - DB 04DH ; ?: - DB 0B5H ; ?; - DB 01BH ; ?/ - DB 0B9H ; ?. +KTBLC: + ;S0 00 - 07 + DB 0F0H + DB 0F0H + DB 0F0H ; ^ + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + ;S1 08 - 0F + DB 0F0H ; ^Y E3 + DB 5AH ; ^Z E4 (CHECKER) + DB 0F0H ; ^@ + DB 0F0H ; ^[ EB/E5 + DB 0F0H ; ^] EA/E7 + DB 0F0H ; #NULL + DB 0F0H ; #NULL + DB 0F0H ; #NULL + ;S2 10 - 17 + DB 0C1H ; ^Q + DB 0C2H ; ^R + DB 0C3H ; ^S + DB 0C4H ; ^T + DB 0C5H ; ^U + DB 0C6H ; ^V + DB 0F0H ; ^W E1 + DB 0F0H ; ^X E2 + ;S3 18 - 1F + DB 0F0H ; ^I F9 + DB 0F0H ; ^J FA + DB 0F0H ; ^K FB + DB 0F0H ; ^L FC + DB 0F0H ; ^M CD + DB 0F0H ; ^N FE + DB 0F0H ; ^O FF + DB 0F0H ; ^P E0 + ;S4 20 - 27 + DB 0F0H ; ^A F1 + DB 0F0H ; ^B F2 + DB 0F0H ; ^C F3 + DB 0F0H ; ^D F4 + DB 0F0H ; ^E F5 + DB 0F0H ; ^F F6 + DB 0F0H ; ^G F7 + DB 0F0H ; ^H F8 + ;S5 28 - 2F + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + ;S6 30 - 37 (ERROR? 7 VALUES ONLY!!) + DB 0F0H ; ^YEN E6 + DB 0F0H ; ^ EF + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H ; ^, + DB 0F0H ;S7 38 - 3F - DB 0C6H ; CLR - DB 0D3H ; ?\ - DB 0C4H ; CURSOR RIGHT - DB 0C1H ; CURSOR UP - DB 0CDH ; CR - DB 0B7H ; ?J - DB 000H ; NULL - DB 0BBH ; ?? + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H ; ^/ EE + ; ; ; KANA ; -KTBLC: ;S0 00 - 07 ; ;S0 00 - 07 - DB 0F0H ; DB 0BFH ; SPARE - DB 0F0H ; DB 0F0H ; GRAPH BUT NULL - DB 0E2H ; DB 0CFH ; NIKO WH. - DB 0C1H ; DB 0C9H ; ALPHA - DB 0E0H ; DB 0F0H ; NO - DB 0F0H ; DB 0B5H ; MO - DB 000H ; DB 4DH ; DAKU TEN - DB 0E5H ; DB 0CDH ; CR - ;S1 08 - 0F ; ;S1 08 - 0F - DB 0F0H ; CODE 80H=NOT KEY - DB 0F0H ; - DB 0E2H ; CTRL + W - DB 0C1H ; CTRL + Q - DB 0E0H ; CTRL + A SHIFT LOCK - DB 0F0H ; - DB 000H ; - DB 0E5H ; CTRL + Z - ;S2 10 - 17 ; ;S2 10 - 17 - DB 0F0H ; - DB 0F0H ; - DB 0C2H ; CTRL + R - DB 0CFH ; CTRL + E ROLL DOWN - DB 0CEH ; CTRL + D ROLL UP - DB 0C3H ; CTRL + S - DB 0E3H ; CTRL + X - DB 0F3H ; CTRL + C - ;S3 18 - 1F ; ;S3 18 - 1F - DB 0F0H ; - DB 0F0H ; - DB 0E4H ; CTRL + Y - DB 0C4H ; CTRL + T - DB 0F7H ; CTRL + G - DB 0F6H ; CTRL + F - DB 0C6H ; CTRL + V CLR - DB 0F2H ; CTRL + B - ;S4 20 - 27 ; ;S4 20 - 27 - DB 0F0H ; - DB 0F0H ; - DB 0F9H ; CTRL + I - DB 0C5H ; CTRL + U HOME - DB 0FAH ; CTRL + J - DB 0F8H ; CTRL + H - DB 0FEH ; CTRL + N - DB 0F0H ; - ;S5 28 - 2F ; ;S5 28 - 2F - DB 0F0H ; - DB 0F0H ; - DB 0E1H ; CTRL + P - DB 0FFH ; CTRL + O - DB 0FCH ; CTRL + L - DB 0FBH ; CTRL + K - DB 0F0H ; - DB 0FDH ; CTRL + M - ;S6 30 - 37 ; ;S6 30 - 37 - DB 0EFH ; CTRL + ^ - DB 0F4H ; CTRL + - - DB 0E6H ; CTRL + [ - DB 0CCH ; CTRL + @ REVERSE - DB 0F0H ; - DB 0F0H ; - DB 0F0H ; - DB 0F0H ; - ;S7 38 - 3F ; ;S7 38 - 3F - DB 0F0H ; - DB 0EBH ; CTRL + \ - DB 0F0H ; - DB 0F0H ; - DB 0F0H ; - DB 0EEH ; CTRL + ] - DB 0F0H ; +KTBLG: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0F0H ; GRAPH BUT NULL + DB 0CFH ; NIKO WH. + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 0B5H ; MO + DB 4DH ; DAKU TEN + DB 0CDH ; CR + ;S1 08 - 0F + DB 35H ; HA + DB 77H ; TA + DB 0D7H ; WA + DB 0B3H ; YO + DB 0B7H ; HANDAKU + DB 0F0H + DB 0F0H + DB 0F0H + ;S2 10 - 17 + DB 7CH ; KA + DB 70H ; KE + DB 41H ; SHI + DB 31H ; KO + DB 39H ; HI + DB 0A6H ; TE + DB 78H ; KI + DB 0DDH ; CHI + ;S3 18 - 1F + DB 3DH ; FU + DB 5DH ; MI + DB 6CH ; MU + DB 56H ; ME + DB 1DH ; RHI + DB 33H ; RA + DB 0D5H ; HE + DB 0B1H ; HO + ;S4 20 - 27 + DB 46H ; SA + DB 6EH ; TO + DB 0D9H ; THU + DB 48H ; SU + DB 74H ; KU + DB 43H ; SE + DB 4CH ; SO + DB 73H ; MA + ;S5 28 - 2F + DB 3FH ; A + DB 36H ; I + DB 7EH ; U + DB 3BH ; E + DB 7AH ; O + DB 1EH ; NA + DB 5FH ; NI + DB 0A2H ; NU + ;S6 30 - 37 + DB 0D3H ; YO + DB 9FH ; YU + DB 0D1H ; YA + DB 00H ; SPACE + DB 9DH ; NO + DB 0A3H ; NE + DB 0D0H ; RU + DB 0B9H ; RE + ;S7 38 - 3F + DB 0C6H ; ?CLR + DB 0C5H ; ?HOME + DB 0C2H ; ?CURSOR UP + DB 0C1H ; ?CURSOR DOWN + DB 0C3H ; ?CURSOR RIGHT + DB 0C4H ; ?CURSOR LEFT + DB 0BBH ; DASH + DB 0BEH ; RO ; MEMORY DUMP COMMAND "D" diff --git a/software/asm/include/TZFS_Definitions.asm b/software/asm/include/TZFS_Definitions.asm index 50f082f..2ffd222 100644 --- a/software/asm/include/TZFS_Definitions.asm +++ b/software/asm/include/TZFS_Definitions.asm @@ -194,6 +194,12 @@ CPLDCFG EQU 06EH ; Versi CPLDSTATUS EQU 06EH ; Version 2.1 CPLD status register. CPLDINFO EQU 06FH ; Version 2.1 CPLD version information register. +;----------------------------------------------- +; CPLD Configuration constants. +;----------------------------------------------- +SET_MODE_MZ80A EQU 1 ; Set to original unmodified hardware. +SET_MODE_MZ700 EQU 2 ; Map keyboard and memory mode settings to MZ700 mode. + ;----------------------------------------------- ; tranZPUter SW Memory Management modes ;----------------------------------------------- diff --git a/software/asm/monitor_1Z-013A-KM.asm b/software/asm/monitor_1Z-013A-KM.asm new file mode 100644 index 0000000..78d3fea --- /dev/null +++ b/software/asm/monitor_1Z-013A-KM.asm @@ -0,0 +1,7 @@ +; Configurable parameters. +COLW: EQU 40 ; Width of the display screen (ie. columns). +ROW: EQU 25 ; Number of rows on display screen. +SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. +MODE80C:EQU 0 + + INCLUDE "1Z-013A-KM.asm" diff --git a/software/asm/monitor_80c_1Z-013A-KM.asm b/software/asm/monitor_80c_1Z-013A-KM.asm new file mode 100644 index 0000000..aaf1380 --- /dev/null +++ b/software/asm/monitor_80c_1Z-013A-KM.asm @@ -0,0 +1,7 @@ +; Configurable parameters. +COLW: EQU 80 ; Width of the display screen (ie. columns). +ROW: EQU 25 ; Number of rows on display screen. +SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. +MODE80C:EQU 1 + + INCLUDE "1Z-013A-KM.asm" diff --git a/software/asm/tzfs.asm b/software/asm/tzfs.asm index 358e318..b1d5224 100644 --- a/software/asm/tzfs.asm +++ b/software/asm/tzfs.asm @@ -533,21 +533,27 @@ SETMODE80: LD A, 128 LD A,TZSVC_CMD_LOAD80BIOS ; Request the I/O processor loads the SA1510 80column BIOS into memory. JR SETBIOS - ; Commands to switch into MZ-700 compatible mode. This involves loading the original (but patched for keyboard use) 1Z-013A BIOS - ; and changing the frequency, also enabling of additional traps to detect and change memory mode. + ; Commands to switch into MZ-700 compatible mode. This involves loading the original (but patched for keyboard use for v1.1) 1Z-013A BIOS + ; and changing the frequency, and on the v1.1 board also enabling of additional traps to detect and change memory mode which are catered for in + ; hardware on v2+ boards.. SETMODE700: LD A, 0 LD (DSPCTL), A LD (SCRNMODE),A ; 0 = 40char mode on reset. - ; + LD A,SET_MODE_MZ700 + OUT (CPLDCFG),A ; Set the CPLD compatibility mode. LD A,TZSVC_CMD_LOAD700BIOS40 ; Request the I/O processor loads the MZ700 1Z-013A 40column BIOS into memory. JR SETBIOS + SETMODE7008:LD A, 128 LD (DSPCTL), A LD A,1 LD (SCRNMODE),A + LD A,SET_MODE_MZ700 + OUT (CPLDCFG),A ; Set the CPLD compatibility mode. LD A,TZSVC_CMD_LOAD700BIOS80 ; Request the I/O processor loads the SA1510 80column BIOS into memory. JR SETBIOS + ; Command to switch into the Sharp MZ-80B compatible mode. This involves loading the IPL, switching ; the frequency to 4MHz and enabling of additional traps to detect and change memory mode. SETMODE80B: LD A, 128 diff --git a/software/asm/tzfs_bank2.asm b/software/asm/tzfs_bank2.asm index 5f5675d..2cc3486 100644 --- a/software/asm/tzfs_bank2.asm +++ b/software/asm/tzfs_bank2.asm @@ -350,7 +350,9 @@ HELPSCR: ; "--------- 40 column width -------------" DB "700 - Select MZ-700 Mode.", 00DH DB "7008 - Select MZ-700 80 col Mode.", 00DH DB "B - toggle keyboard bell.", 00DH + DB "BASIC - Load BASIC SA-5510.", 00DH DB "C[b] - clear memory $1200-$D000.", 00DH + DB "CPM - Load CPM.", 00DH DB "DXXXX[YYYY] - dump mem XXXX to YYYY.", 00DH DB "EC[fn]- erase file, fn=No or Filename", 00DH DB "F[x] - boot fd drive x.", 00DH diff --git a/software/roms/monitor_1Z-013A-KM.rom b/software/roms/monitor_1Z-013A-KM.rom new file mode 100644 index 0000000000000000000000000000000000000000..0ebd5619a4086d0de1d515b6152132d4959292ed GIT binary patch literal 4096 zcmZ`+e_&J9^}jDaUXr%?@d#~iQ-PO;mPZ36gptMw58G18@3OYQ&(#;u zO3*4165J-?7fQja79tAaU4?K&F+OJMT0nRWai%!3B$iD-8)jmC)`tIY zdGUN0OvbnQYZhsjkCY9TN`%205(vn$h<@`BpX+?qFBIU6eW(&Z| zkSe)Msf4phWgM2OI1|}L3GX3hxe6zkpc2P;6;|*H@;rr4@x$;f11cl?soJxB{F<|p zfr9sjvyvEWNmyWtykPd*cvC?9Tl|cQkcmd3ik!ls&J>1cNInWB(DTkGd{*s_*)oGfc@jbR=S1O zT8?l!o6TnGE;KiZw%}shf@obMr}OM!CUeTsxF=^PW8J~H6!w7GQq~!h9GudJ)#lnx zqu07kv95ZqXFF5Yu-0_Dsk}ifnWmk(L{qwvo;HCldsTDTPu+Ytu}aHNzw3?_@xCS}%t0)vb+K|!RBU49@>3V~hXz4VT@!A)_wVL9hbtU7eVb)dqY;76)+lCvX`70Rl z23XL!mEmK~ZH)Eko`$Z92#Q)YA=hKBz4nzgc2|lE*=(*g_PM@;Z11X1*jsjRCReX( zk}dGVP&m-kD_$safTKlZ-Zl0cix>2+exEZmfXuE6w<+q`%7jJc=pJaVQep9il@9sF zE%A+8*lWho1c0z^WqemDZ$Eov@d9AXvfHEKl{Fwe-YXJT=OcpBC)NS2#|nfJMtDev z5&|O*jW7gJI-O46X_QjjisPE&4)MIBT}qj9`n*OmO@TKt83$iK$jEY8tN>Mi- zQ-zyaBEn{90^+#2Nfl>?p9FXS65w^zsL8!aYET29f$u*;@K>pEJ7CCDP*jLfga}2u ztH{h0ODF5kQde0K%6XZQRgjUi`!25xiM;k z4^}L5avb;tr?d_onzM!J7m~k)k}Ki8IiB zm5^=>OKC3)DBa2T;S3-Rgve3qS4 zK6ge{c?CQEp0SSc6N*?iKVOd^^1}>|)Xh}IIJL{tw zd1=89Ed^S@x@L*}d5w=nVsENdd)hXptT@*{6i~C*vsj*vTfl zA(ca*b{=8BgwsaP(Q>cdYs2U6e-NMMrq3Q7-(EStnB@{Jks$d%mnegC&v?$OuC*>_ zAX^^|)Up{8;pR(i{v0hF7&_^MBc(07)}baJ=`kS}^|&=0ab??FdR%FA6ygc61!P`- z1{qxG|JRZm3Yv3>x%9jOL_RbIfJXdRbSvu8+kFztbrXXw5Qdce6A`c_@?z4+ zM4cHY`g{IP138dN9)XcKlb?o*`L;%!1+jBJ)_Oc9e3pvjBak?>wHi0g$Kaf^AA#HGB zO)?F97Z4K>2nLPD{k&&WGW5g$V{d#p0f)abL>6h_A4-V9*SI+F;cZ?2=-avhw*G_x z`MGgK#~NK`rbETwT_`q){1joS1_dJxboW9z>{J=+@lc0)Ay%~YsB0muOV?Pf)Xm)} z4hKYFAJ@ozwIojqrGiGIDPNsybbMd8wj7^{#bP&N37~^dQ?qca<@jJPhJLm5*AM*W zx66L_;KL7%%P$zqT61h8bMr=Vqszzq+`e$ee7S5;(;BTVB{fZNFq)Vl=Ar2snK;W* zv8ZZZ>4{d+-*%FGcIwi9zKUG=rt5Uz%-M6n^B3Cx+41?sFaC9O&EePfeRSZ%?eFhD zc;xjD8bA5;&2@j@wR`iQ*Khmd-=5m^!k;#-ef8xRxBO*i!?RDn^v1jIJhNf%d(XYK z=k4eJ`j7wHy5p5YAK!hKXZfTR_e?HXFlG46JMQCuIbzA;!qrc@p72eWHG9}2_tq9o z{Mlm;_v3fYss6pw`-hs9Wp$O~=RP`pTK&}QU#u#=-@1u$U6Z}ltu#6mu0CG^^0m*o zfr)z?pvv)%^NOw#e5EB~-IP*JBb^UtFBo6oD3XtF2y+;%x{pFs*FFvc0isK6w0Bk1 zW3cGmu~_*Sl4H$es1wLC(l$h`GGk?4Zq`r@ouS}H>C#iQ2E>jw8Pih7>5t@B%r74^ zwxDH^&`he(j6wdTzj}G&+E(=H1Haz1?x`35_NU+e=9SHVe)^?9{%+Y{wmh?b1N!vA z7oPv?vp;`sm;KP+AAYEG;qf)cn#kQ~9$)C5RCxmZVX$5Oq~m90Qy=};V$b6%X3gxV zK0Km+)h}zDXxq;7dq2GQ{yVmxX@7rz@#i16oCE!H(LvXg+PZ12$UE5HJaT&2>wyn0%=sw$!11%7zY%>Bi(PIC#ZctO zw)xa&!k0H3%cS-9`}-q`JHH#<)zoh}OWYD`YRyA=^gya9Jb zl-3$D`}46a;aS0~b*^CI66;X#1^sCX#?m&zpkA+!bXA18VLwETB(X}eTW>lBLEFgn z$dU3s6!6v^C=2iTNgn*4PC|}gM~_V1JrJ65u7g7y3fFpR6q^c})=fuUl+A^B0jGiU zNEGi+PLqrBqipsb4Y-Q+9fJ-kc;Jd&iPlM&%N?1sf)OGHxu);V#n+=C&7mBFuN0t> zbyAi)oQGioo*u1l(zUMumP0O zu^%LXBIQWD1(>L#N(P;_a;ICm_BI6>)NbY4yY|vt6u7@IhG`DOQ5M9kWUP-dU3*=~ zvyy4#imWxvL@YdN=+>(ZdPA;Zj=^K-Hn@#p!&O5B{_aWAwu?TS*WR|RYtO2^?DeP% zwOw>&VpW54xqNc>CoghN??0f2D(vfM-ACM4^^H)kg6*_mOuGx=Tp2UZIVjDRGCAn% zUK>cYd)v0b6(|lf+Adl%5r0ew$!x}gQS}aLBphuKFe&VP`4$?L2e^%vM)tX-58DO5 z0h}gB#Y~+8o&&F4#kL#;)Bm1BGx8<#S=}Z1G>6Z-6>u>&Tf8>7<8{NG7m8MwszXDO z$CDK17V9p7qkt-T`t`Qla#h{?6uXp13p@WByc*Y1yV5en10k3|tB;Z&~El#zb$CG1_n~IRBoziI;bg zxm|s=Rh<0ZEAuWf%vpG92gCupZUePIKoo>JcngeUMVIGaWSG17!cK?>cJJG) I$$Om%0F+L{pa1{> delta 359 zcmZorXi(VjgG2Zgk7S+1jnf4h?1EW5lI9Yh1Xpe5=Dg2T|KWqfhY$WbXO$Gi1sRVs zNU10bv9btDFsrFbimC*Q?AO?(8qaM-lBM0%h+OLhPjJ3 zUJc8+AUpr!=Ig#&rFR~?40OPDM~2-WK0G@3-~+=`1byiIxx0U~}63#e;t+Pdw!eJzT$g9($i z*}An^n%0(PSgToW3-%#tYQhuc4c>HAlqFkdY=?~|bVi*d$j6>HKy82QgE{xz`|dgC zch5cN+;hb_NbF)nqh7>%k<*J~_2Lx0_@YkSr4tY9M0=d*(1?#|#14(vs}VP9#S@gM zQzIlg&EhZAqFXBlRpPrU@rY_t*xa*-2n?~u*-~YWOFA21!vmIw5T!*u4PtoUtY1Wk z9!{1Jr{TIyBCRqPqkzS26 zkWI5S@(5?3`^%;w-EumAw)@tX5n|Rjy|=oHW)&CB<;oY%=Zed64QX-~mzS?Lk3huVZN{4UBT9+{)+4r}*3D z37|O#+6&NHEf1?WjpZp-BDqcFyg*u2&Lr}#ssNu9)WDjEj|mk17KWo>|A@GqZlQH) zM|i!}YBl%fB{oUc_NCTEp_)cspI^sLG==wT$`C3##mtD(#gplo zo!XK-ZNY9$p;Z~DRB8>aOE66x79QXNsCKrZq_u4XEZb-RGhZ? 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