Removed unneeded files
This commit is contained in:
Philip Smart
@@ -1,397 +0,0 @@
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-- megafunction wizard: %ALTPLL%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altpll
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-- ============================================================
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-- File Name: Clock_50to100.vhd
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-- Megafunction Name(s):
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-- altpll
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY Clock_50to100 IS
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PORT
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(
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areset : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC
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);
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END Clock_50to100;
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ARCHITECTURE SYN OF clock_50to100 IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC ;
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SIGNAL sub_wire4 : STD_LOGIC ;
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SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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COMPONENT altpll
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GENERIC (
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clk0_divide_by : NATURAL;
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clk0_duty_cycle : NATURAL;
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clk0_multiply_by : NATURAL;
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clk0_phase_shift : STRING;
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clk1_divide_by : NATURAL;
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clk1_duty_cycle : NATURAL;
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clk1_multiply_by : NATURAL;
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clk1_phase_shift : STRING;
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compensate_clock : STRING;
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gate_lock_signal : STRING;
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inclk0_input_frequency : NATURAL;
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intended_device_family : STRING;
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invalid_lock_multiplier : NATURAL;
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lpm_hint : STRING;
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lpm_type : STRING;
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operation_mode : STRING;
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port_activeclock : STRING;
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port_areset : STRING;
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port_clkbad0 : STRING;
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port_clkbad1 : STRING;
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port_clkloss : STRING;
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port_clkswitch : STRING;
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port_configupdate : STRING;
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port_fbin : STRING;
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port_inclk0 : STRING;
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port_inclk1 : STRING;
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port_locked : STRING;
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port_pfdena : STRING;
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port_phasecounterselect : STRING;
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port_phasedone : STRING;
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port_phasestep : STRING;
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port_phaseupdown : STRING;
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port_pllena : STRING;
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port_scanaclr : STRING;
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port_scanclk : STRING;
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port_scanclkena : STRING;
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port_scandata : STRING;
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port_scandataout : STRING;
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port_scandone : STRING;
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port_scanread : STRING;
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port_scanwrite : STRING;
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port_clk0 : STRING;
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port_clk1 : STRING;
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port_clk2 : STRING;
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port_clk3 : STRING;
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port_clk4 : STRING;
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port_clk5 : STRING;
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port_clkena0 : STRING;
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port_clkena1 : STRING;
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port_clkena2 : STRING;
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port_clkena3 : STRING;
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port_clkena4 : STRING;
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port_clkena5 : STRING;
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port_extclk0 : STRING;
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port_extclk1 : STRING;
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port_extclk2 : STRING;
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port_extclk3 : STRING;
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valid_lock_multiplier : NATURAL
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);
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PORT (
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areset : IN STD_LOGIC ;
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clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
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inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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locked : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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sub_wire6_bv(0 DOWNTO 0) <= "0";
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sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
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sub_wire3 <= sub_wire0(0);
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sub_wire1 <= sub_wire0(1);
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c1 <= sub_wire1;
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locked <= sub_wire2;
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c0 <= sub_wire3;
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sub_wire4 <= inclk0;
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sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
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altpll_component : altpll
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GENERIC MAP (
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clk0_divide_by => 1,
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clk0_duty_cycle => 50,
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clk0_multiply_by => 2,
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clk0_phase_shift => "-2000",
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clk1_divide_by => 1,
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clk1_duty_cycle => 50,
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clk1_multiply_by => 4,
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clk1_phase_shift => "0",
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compensate_clock => "CLK0",
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gate_lock_signal => "NO",
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inclk0_input_frequency => 20000,
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intended_device_family => "Cyclone II",
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invalid_lock_multiplier => 5,
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lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100",
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lpm_type => "altpll",
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operation_mode => "NORMAL",
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port_activeclock => "PORT_UNUSED",
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port_areset => "PORT_USED",
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port_clkbad0 => "PORT_UNUSED",
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port_clkbad1 => "PORT_UNUSED",
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port_clkloss => "PORT_UNUSED",
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port_clkswitch => "PORT_UNUSED",
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port_configupdate => "PORT_UNUSED",
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port_fbin => "PORT_UNUSED",
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port_inclk0 => "PORT_USED",
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port_inclk1 => "PORT_UNUSED",
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port_locked => "PORT_USED",
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port_pfdena => "PORT_UNUSED",
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port_phasecounterselect => "PORT_UNUSED",
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port_phasedone => "PORT_UNUSED",
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port_phasestep => "PORT_UNUSED",
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port_phaseupdown => "PORT_UNUSED",
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port_pllena => "PORT_UNUSED",
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port_scanaclr => "PORT_UNUSED",
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port_scanclk => "PORT_UNUSED",
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port_scanclkena => "PORT_UNUSED",
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port_scandata => "PORT_UNUSED",
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port_scandataout => "PORT_UNUSED",
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port_scandone => "PORT_UNUSED",
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port_scanread => "PORT_UNUSED",
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port_scanwrite => "PORT_UNUSED",
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port_clk0 => "PORT_USED",
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port_clk1 => "PORT_USED",
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port_clk2 => "PORT_UNUSED",
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port_clk3 => "PORT_UNUSED",
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port_clk4 => "PORT_UNUSED",
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port_clk5 => "PORT_UNUSED",
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port_clkena0 => "PORT_UNUSED",
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port_clkena1 => "PORT_UNUSED",
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port_clkena2 => "PORT_UNUSED",
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port_clkena3 => "PORT_UNUSED",
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port_clkena4 => "PORT_UNUSED",
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port_clkena5 => "PORT_UNUSED",
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port_extclk0 => "PORT_UNUSED",
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port_extclk1 => "PORT_UNUSED",
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port_extclk2 => "PORT_UNUSED",
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port_extclk3 => "PORT_UNUSED",
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valid_lock_multiplier => 1
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)
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PORT MAP (
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areset => areset,
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inclk => sub_wire5,
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clk => sub_wire0,
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locked => sub_wire2
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
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-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
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-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
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-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
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-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
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-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
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-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
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-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
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-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
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-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
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-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
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-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
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-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
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-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
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-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
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-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
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-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
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-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
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-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
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-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
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-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
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-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
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-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
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-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
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-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
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-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
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-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
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-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
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-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
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||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
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||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
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||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
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||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
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||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
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||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,162 +0,0 @@
|
||||
## Generated SDC file "hello_led.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2011 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
|
||||
|
||||
## DATE "Fri Jul 06 23:05:47 2012"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25Q240C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
derive_pll_clocks
|
||||
create_generated_clock -name sysclk -source [get_pins {mypll|altpll_component|pll|clk[0]}]
|
||||
create_generated_clock -name sd1clk_pin -source [get_pins {mypll|altpll_component|pll|clk[1]}] [get_ports {DRAM_CLK}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
derive_clock_uncertainty;
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
#set_input_delay -clock sd1clk_pin -max 5.8 [get_ports DRAM_DQ*]
|
||||
#set_input_delay -clock sd1clk_pin -min 3.2 [get_ports DRAM_DQ*]
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
|
||||
set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
|
||||
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {SD_DAT}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {SD_DAT}]
|
||||
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {GPIO*}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {GPIO*}]
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {PS2_*}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {PS2_*}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
#set_output_delay -clock sd1clk_pin -max 1.5 [get_ports DRAM_*]
|
||||
#set_output_delay -clock sd1clk_pin -min -0.8 [get_ports DRAM_*]
|
||||
#set_output_delay -clock sd1clk_pin -max 0.5 [get_ports DRAM_CLK]
|
||||
#set_output_delay -clock sd1clk_pin -min 0.5 [get_ports DRAM_CLK]
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
set_output_delay -clock sysclk -min 0.0 [get_ports UART_TXD]
|
||||
set_output_delay -clock sysclk -max 0.5 [get_ports UART_TXD]
|
||||
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {SD_DAT3}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {SD_DAT3}]
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {SD_CLK}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {SD_CLK}]
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {SD_CMD}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {SD_CMD}]
|
||||
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {VGA_*}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {VGA_*}]
|
||||
|
||||
set_output_delay -clock sysclk -min 0.5 [get_ports {LED*}]
|
||||
set_output_delay -clock sysclk -max 0.5 [get_ports {LED*}]
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {HEX*}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {HEX*}]
|
||||
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {GPIO*}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {GPIO*}]
|
||||
#set_output_delay -clock sysclk -min 0.5 [get_ports {PS2_*}]
|
||||
#set_output_delay -clock sysclk -max 0.5 [get_ports {PS2_*}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from {KEY*} -to {*}
|
||||
set_false_path -from {SW*} -to {*}
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
#set_multicycle_path -from [get_clocks {mypll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sd2clk_pin}] -setup -end 2
|
||||
#set_multicycle_path -from [get_clocks {mypll2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sd2clk_pin}] -setup -end 2
|
||||
|
||||
set_multicycle_path -from [get_clocks {sd1clk_pin}] -to [get_clocks {mypll|altpll_component|pll|clk[0]}] -setup -end 2
|
||||
|
||||
# set_multicycle_path -from {VirtualToplevel:myVirtualToplevel|*:myrom|*} -to {VirtualToplevel:myVirtualToplevel|zpu_core:zpu|*} -setup -end 2
|
||||
# set_multicycle_path -from {VirtualToplevel:myVirtualToplevel|*:myrom|*} -to {VirtualToplevel:myVirtualToplevel|zpu_core:zpu|*} -hold -end 2
|
||||
|
||||
# The result from the hardware multiplier isn't used for two clocks, so we set a multicycle for that.
|
||||
set_multicycle_path -through [get_nets {*zpu|Mult0*}] -setup -end 2
|
||||
set_multicycle_path -through [get_nets {*zpu|Mult0*}] -hold -end 2
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
@@ -1,126 +0,0 @@
|
||||
## Generated SDC file "tranZPUter.out.sdc"
|
||||
|
||||
## Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
## Your use of Intel Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Intel Program License
|
||||
## Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
## the Intel FPGA IP License Agreement, or other applicable license
|
||||
## agreement, including, without limitation, that your use is for
|
||||
## the sole purpose of programming logic devices manufactured by
|
||||
## Intel and sold by Intel or its authorized distributors. Please
|
||||
## refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus Prime"
|
||||
## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
|
||||
|
||||
## DATE "Tue Sep 17 13:54:17 2019"
|
||||
|
||||
##
|
||||
## DEVICE "10CL025YU256C8G"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}]
|
||||
create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {USER_BTN*}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -137,90 +137,90 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
# SDRAM
|
||||
#============================================================
|
||||
# Data bus
|
||||
set_location_assignment PIN_B10 -to DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[0]
|
||||
set_location_assignment PIN_A10 -to DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[1]
|
||||
set_location_assignment PIN_B11 -to DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[2]
|
||||
set_location_assignment PIN_A11 -to DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[3]
|
||||
set_location_assignment PIN_A12 -to DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[4]
|
||||
set_location_assignment PIN_D9 -to DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[5]
|
||||
set_location_assignment PIN_B12 -to DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[6]
|
||||
set_location_assignment PIN_C9 -to DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[7]
|
||||
set_location_assignment PIN_D11 -to DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[8]
|
||||
set_location_assignment PIN_E11 -to DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[9]
|
||||
set_location_assignment PIN_A15 -to DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[10]
|
||||
set_location_assignment PIN_E9 -to DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[11]
|
||||
set_location_assignment PIN_D14 -to DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[12]
|
||||
set_location_assignment PIN_F9 -to DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[13]
|
||||
set_location_assignment PIN_C14 -to DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[14]
|
||||
set_location_assignment PIN_A14 -to DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[15]
|
||||
set_location_assignment PIN_B10 -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_A10 -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_B11 -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_A11 -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_A12 -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_D9 -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_B12 -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_C9 -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_D11 -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_E11 -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_A15 -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_E9 -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_D14 -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_F9 -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_C14 -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_A14 -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
||||
# Address Bus
|
||||
set_location_assignment PIN_A3 -to A[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[0]
|
||||
set_location_assignment PIN_B5 -to A[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[1]
|
||||
set_location_assignment PIN_B4 -to A[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[2]
|
||||
set_location_assignment PIN_B3 -to A[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[3]
|
||||
set_location_assignment PIN_C3 -to A[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[4]
|
||||
set_location_assignment PIN_D3 -to A[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[5]
|
||||
set_location_assignment PIN_E6 -to A[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[6]
|
||||
set_location_assignment PIN_E7 -to A[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[7]
|
||||
set_location_assignment PIN_D6 -to A[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[8]
|
||||
set_location_assignment PIN_D8 -to A[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[9]
|
||||
set_location_assignment PIN_A5 -to A[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[10]
|
||||
set_location_assignment PIN_E8 -to A[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[11]
|
||||
set_location_assignment PIN_A2 -to A[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[12]
|
||||
set_location_assignment PIN_C6 -to A[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[13]
|
||||
set_location_assignment PIN_A3 -to SDRAM_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
|
||||
set_location_assignment PIN_B5 -to SDRAM_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
|
||||
set_location_assignment PIN_B4 -to SDRAM_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
|
||||
set_location_assignment PIN_B3 -to SDRAM_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
|
||||
set_location_assignment PIN_C3 -to SDRAM_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
|
||||
set_location_assignment PIN_D3 -to SDRAM_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
|
||||
set_location_assignment PIN_E6 -to SDRAM_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
|
||||
set_location_assignment PIN_E7 -to SDRAM_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
|
||||
set_location_assignment PIN_D6 -to SDRAM_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
|
||||
set_location_assignment PIN_D8 -to SDRAM_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
|
||||
set_location_assignment PIN_A5 -to SDRAM_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
|
||||
set_location_assignment PIN_E8 -to SDRAM_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
|
||||
set_location_assignment PIN_A2 -to SDRAM_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
|
||||
set_location_assignment PIN_C6 -to SDRAM_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13]
|
||||
# Byte addressing
|
||||
set_location_assignment PIN_A4 -to BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BA[0]
|
||||
set_location_assignment PIN_B6 -to BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BA[1]
|
||||
set_location_assignment PIN_B13 -to DQM[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQM[0]
|
||||
set_location_assignment PIN_D12 -to DQM[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQM[1]
|
||||
set_location_assignment PIN_A4 -to SDRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_B6 -to SDRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_B13 -to SDRAM_DQM[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
|
||||
set_location_assignment PIN_D12 -to SDRAM_DQM[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
|
||||
# Chip control.
|
||||
set_location_assignment PIN_C8 -to CAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAS
|
||||
set_location_assignment PIN_B7 -to RAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAS
|
||||
set_location_assignment PIN_A7 -to WE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WE
|
||||
set_location_assignment PIN_A6 -to CS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CS
|
||||
set_location_assignment PIN_C8 -to SDRAM_CAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS
|
||||
set_location_assignment PIN_B7 -to SDRAM_RAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS
|
||||
set_location_assignment PIN_A7 -to SDRAM_WE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE
|
||||
set_location_assignment PIN_A6 -to SDRAM_CS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS
|
||||
# Clock and enabling.
|
||||
set_location_assignment PIN_F8 -to CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CKE
|
||||
set_location_assignment PIN_B14 -to SDRAMCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAMCLK
|
||||
set_location_assignment PIN_F8 -to SDRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
set_location_assignment PIN_B14 -to SDRAM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
|
||||
#============================================================
|
||||
# FT2232H
|
||||
@@ -446,25 +446,14 @@ set_global_assignment -name QIP_FILE Clock_12to100.qip
|
||||
set_global_assignment -name SDC_FILE tranZPUter_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_flex_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_small.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_small_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_evo.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_medium_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_uart_debug.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/dpram.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_brgen.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_mv_filter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_rx.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_tx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/fifo/fifo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/intr/interrupt_controller.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/SDMMC/SDCard.vhd
|
||||
@@ -480,27 +469,8 @@ set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/TCPU/tcpu.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
|
||||
set_global_assignment -name QIP_FILE ../../zpu/devices/WishBone/SDRAM/sdram.qip
|
||||
#set_global_assignment -name VERILOG_FILE ../../zpu/cpu/qdiv.v
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Peripherals/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/SysRAM/SysRAM.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/DualPortRAM.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../../zpu/devices/sysbus/RAM/TwoWayCache.v
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/sdram_cached.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/Toplevel_Config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/DMACache_config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Video/video_vga_master.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Video/video_vga_dither.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Video/vga_controller.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/DMACache.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/DMACache_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/FIFO_Counter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/DMACacheRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/SDRAM/sdram.vhd
|
||||
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
|
||||
|
||||
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
Reference in New Issue
Block a user