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Philip Smart
2019-10-26 23:34:05 +01:00
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README.md
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@@ -10,7 +10,9 @@ The Sharp MZ80A is based on the Z80 CPU running at 2MHz. It is vintage and under
Besides providing more powerful and alternative CPU's and memory, the FPGA can also act as a Floppy Drive, Hard Drive etc using the connected SD Card and provide a menu system by overlaying the video memory when invoked.
This design is still in its infancy, many features have been tested and the schematic/pcb made, it is just a matter of the VHDL and software being further developed.
This design is still a work in progress, I stopped development when I needed to advance the ZPU Evo SDRAM controller which I had been putting off for a while. The SDRAM is critical as the Cyclone 10LP on the CYC1000 has limited BRAM, only enough for the cache and IOCP Bootloader. Many features have been tested and the schematic/pcb made, it is just a matter of furthering the VHDL now that the SDRAM controller works and to develop the C/C++ code to provide the menu/SD services (already done in the ZPU code base).
I chose the CYC1000 as the FPGA solution as I am not competent soldering BGA devices, also at US$30 it is quite a cost effective choice. For software minded people, it is not that difficult to use a Pi Zero W or similar in place of the CYC1000 just a reworking of the PCB and interface logic, but that is a project for another time.
As the design replaces a Z80 in-situ it is not limited to the MZ80A but can be used in any Z80 based computer with the right software.
@@ -18,6 +20,11 @@ As the design replaces a Z80 in-situ it is not limited to the MZ80A but can be u
## tranZPUter v1.0
The tranZPUter gets its name from: A TRANsformable ZPU compuTER as the base CPU in the FPGA will be the ZPU Evo. The ZPU Evo will provide the Menu, SD, Video Overlay services to the Sharp MZ80A by tri-stating the original Z80 and accessing the MZ80A memory and peripherals as though they were ZPU devices.
To provide different CPU's it is just a matter of mapping in VHDL the softcore CPU signals to the MZ80A bus via this designs interface. The program memory could either be that on the MZ80A or the faster SDRAM. ie. There is no real need to use the MZ80A memory when using a softcore CPU. In my SharpMZ Emulator I run a Z80 at 112MHz using FPGA BRAM but tests show at least 128MHz is sustainable, thus a softcore Z80 CPU running at 128MHz with 48K BRAM slowing down only for MZ80A peripheral access would see a 64x boost in program run, which for say CP/M or database use is very desirable.
Below are pictures of the current design and files uploaded onto github are relatively stable, WIP files wont be uploaded.
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