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2018-09-28 17:04:36 +01:00
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3281
asm/1Z-013A.asm Normal file
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3274
asm/1Z-013A_80c.asm Normal file
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5170
asm/MZ700.LST Normal file
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asm/hi-ramcheck.asm Normal file
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KEYPC: EQU 0E002h
KEYPF: EQU 0E003h
CSTR: EQU 0E002h
CSTPT: EQU 0E003h
CONT0: EQU 0E004h
CONT1: EQU 0E005h
CONT2: EQU 0E006h
CONTF: EQU 0E007h
SUNDG: EQU 0E008h
TEMP: EQU 0E008h
LETNL: EQU 0006h
NL: EQU 0009h
PRNTS: EQU 000Ch
PRNT: EQU 0012h
MSG: EQU 0015h
MSGX: EQU 0018h
MONIT: EQU 0086h
ST1: EQU 0095h
PRTHL: EQU 03BAh
PRTHX: EQU 03C3h
DPCT: EQU 0DDCh
?BRK: EQU 0D11h
?RSTR1: EQU 0EE6h
GRAMSTART: EQU 0C000h
GRAMEND: EQU 0FFFFh
TPSTART: EQU 10F0h
MEMSTART: EQU 1200h
MSTART: EQU 0BE00h
ORG TPSTART
SPV:
IBUFE: ; TAPE BUFFER (128 BYTES)
;ATRB: DS virtual 1 ; ATTRIBUTE
ATRB: DB 01h ; Code Type, 01 = Machine Code.
;NAME: DS virtual 17 ; FILE NAME
NAME: DB "TAPE CHECK V1.0", 0Dh, 00h ; Title/Name (17 bytes).
;SIZE: DS virtual 2 ; BYTESIZE
SIZE: DW MEND - MSTART ; Size of program.
;DTADR: DS virtual 2 ; DATA ADDRESS
DTADR: DW MSTART ; Load address of program.
;EXADR: DS virtual 2 ; EXECUTION ADDRESS
EXADR: DW MSTART ; Exec address of program.
COMNT: DS 104 ; COMMENT
KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE)
DSPXY: DS virtual 2 ; DISPLAY COORDINATES
MANG: DS virtual 27 ; COLUMN MANAGEMENT
FLASH: DS virtual 1 ; FLASHING DATA
FLPST: DS virtual 2 ; FLASHING POSITION
FLSST: DS virtual 1 ; FLASHING STATUS
FLSDT: DS virtual 1 ; CURSOR DATA
STRGF: DS virtual 1 ; STRING FLAG
DPRNT: DS virtual 1 ; TAB COUNTER
TMCNT: DS virtual 2 ; TAPE MARK COUNTER
SUMDT: DS virtual 2 ; CHECK SUM DATA
CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA
AMPM: DS virtual 1 ; AMPM DATA
TIMFG: DS virtual 1 ; TIME FLAG
SWRK: DS virtual 1 ; KEY SOUND FLAG
TEMPW: DS virtual 1 ; TEMPO WORK
ONTYO: DS virtual 1 ; ONTYO WORK
OCTV: DS virtual 1 ; OCTAVE WORK
RATIO: DS virtual 2 ; ONPU RATIO
BUFER: DS virtual 81 ; GET LINE BUFFER
ORG MSTART
START: LD A,0FFh ; Set Red filter.
OUT (0EBh),A
LD A,000h ; Set Green filter.
OUT (0ECh),A
LD A,000h ; Set Blue filter.
OUT (0EDh),A
LD A,000h
CALL GRAMINIT
LD A,005h
CALL GRAMINIT
LD A,00Ah
CALL GRAMINIT
LD A, 0CCh ; Set graphics mode to Indirect Page write.
OUT (0EAh),A
LD HL,0DE00h
LD (GRPHPOS),HL
JR SIGNON
GRAMINIT: LD HL,GRAMSTART
LD BC,GRAMEND - GRAMSTART
GRAM0: OUT (0EAh),A
OUT (0E8h),A
GRAM1: LD A,000h
LD (HL),A
INC HL
DEC BC
LD A,B
OR C
JR NZ,GRAM1
OUT (0E9h),A
RET
SIGNON: CALL LETNL
LD DE,TITLE
CALL MSG
CALL LETNL
LD B,240 ; Number of loops
LOOP: LD HL,MEMSTART ; Start of checked memory,
LD D,0BEh ; End memory check BE00
LOOP1: LD A,000h
CP L
JR NZ,LOOP1b
CALL PRTHL ; Print HL as 4digit hex.
LD A,0C4h ; Move cursor left.
LD E,004h ; 4 times.
LOOP1a: CALL DPCT
DEC E
JR NZ,LOOP1a
LOOP1b: INC HL
LD A,H
CP D ; Have we reached end of memory.
JR Z,LOOP3 ; Yes, exit.
LD A,(HL) ; Read memory location under test, ie. 0.
CPL ; Subtract, ie. FF - A, ie FF - 0 = FF.
LD (HL),A ; Write it back, ie. FF.
SUB (HL) ; Subtract written memory value from A, ie. should be 0.
JR NZ,LOOP2 ; Not zero, we have an error.
LD A,(HL) ; Reread memory location, ie. FF
CPL ; Subtract FF - FF
LD (HL),A ; Write 0
SUB (HL) ; Subtract 0
JR Z,LOOP1 ; Loop if the same, ie. 0
LOOP2: LD A,16h
CALL PRNT ; Print A
CALL PRTHX ; Print HL as 4 digit hex.
CALL PRNTS ; Print space.
XOR A
LD (HL),A
LD A,(HL) ; Get into A the failing bits.
CALL PRTHX ; Print A as 2 digit hex.
CALL PRNTS ; Print space.
LD A,0FFh ; Repeat but first load FF into memory
LD (HL),A
LD A,(HL)
CALL PRTHX ; Print A as 2 digit hex.
NOP
JR LOOP4
LOOP3: CALL PRTHL
LD DE,OKCHECK
CALL MSG ; Print check message in DE
LD A,B ; Print loop count.
CALL PRTHX
LD DE,OKMSG
CALL MSG ; Print ok message in DE
CALL NL
LD HL,(GRPHPOS) ; Get position of graphics progress line.
OUT (0E8h),A ; Enable graphics memory.
LD A,0FFh
LD (HL),A
OUT (0E9h),A ; Disable graphics memory.
INC HL
LD (GRPHPOS),HL
DEC B
JR NZ,LOOP
LD DE,DONEMSG
CALL MSG ; Print check message in DE
JP MONIT
LOOP4: LD B,09h
CALL PRNTS ; Print space.
XOR A ; Zero A
SCF ; Set Carry
LOOP5: PUSH AF ; Store A and Flags
LD (HL),A ; Store 0 to bad location.
LD A,(HL) ; Read back
CALL PRTHX ; Print A as 2 digit hex.
CALL PRNTS ; Print space
POP AF ; Get back A (ie. 0 + C)
RLA ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB
DJNZ LOOP5 ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit.
XOR A ; Zero A, clears flags.
LD A,80h
LD B,08h
LOOP6: PUSH AF ; Repeat above but AND memory location with original A (ie. 80)
LD C,A ; Basically walk through all the bits to find which one is stuck.
LD (HL),A
LD A,(HL)
AND C
NOP
JR Z,LOOP8 ; If zero then print out the bit number
NOP
NOP
LD A,C
CPL
LD (HL),A
LD A,(HL)
AND C
JR NZ,LOOP8 ; As above, if the compliment doesnt yield zero, print out the bit number.
LOOP7: POP AF
RRCA
NOP
DJNZ LOOP6
JP MONIT
LOOP8: CALL LETNL ; New line.
LD DE,BITMSG ; BIT message
CALL MSG ; Print message in DE
LD A,B
DEC A
CALL PRTHX ; Print A as 2 digit hex, ie. BIT number.
CALL LETNL ; New line
LD DE,BANKMSG ; BANK message
CALL MSG ; Print message in DE
LD A,H
CP 50h ; 'P'
JR NC,LOOP9 ; Work out bank number, 1, 2 or 3.
LD A,01h
JR LOOP11
LOOP9: CP 90h
JR NC,LOOP10
LD A,02h
JR LOOP11
LOOP10: LD A,03h
LOOP11: CALL PRTHX ; Print A as 2 digit hex, ie. BANK number.
JR LOOP7
OKCHECK: DB ", CHECK: ", 0Dh
OKMSG: DB " OK.", 0Dh
DONEMSG: DB 11h
DB "RAM TEST COMPLETE.", 0Dh
BITMSG: DB " BIT: ", 0Dh
BANKMSG: DB " BANK: ", 0Dh
TITLE: DB "SHARPMZ RAM TEST (C) P. SMART 2018", 0Dh, 00h
GRPHPOS: DB 00h, 00h
MEND:

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asm/monitor_1Z-013A.asm Normal file
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; Configurable parameters.
COLW: EQU 40 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 0
INCLUDE "1Z-013A.asm"

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asm/monitor_80c_1Z-013A.asm Normal file
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; Configurable parameters.
COLW: EQU 80 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 1
INCLUDE "1Z-013A.asm"

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asm/monitor_80c_SA1510.asm Normal file
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; Configurable parameters.
COLW: EQU 80 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 1
INCLUDE "sa1510.asm"

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asm/monitor_SA1510.asm Normal file
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; Configurable parameters.
COLW: EQU 40 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 0
INCLUDE "sa1510.asm"

401
asm/monitor_mz-1r12.asm Normal file
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; V1.00
;
; To compile use:
;
; GLASS Z80 Assembler
;
; java -jar ../tools/glass.jar mz-1r12.asm mz-1r12.obj mz-1r12.sym
LETNL EQU 00006h
PRNT EQU 00012h
MSG EQU 00015h
GETKY EQU 0001Bh
RDINF EQU 00027h
RDDAT EQU 0002Ah
ST1 EQU 000ADh
QNL EQU 00918h
NAME EQU 010F1h
SIZE EQU 01102h
DTADR EQU 01104h
COMNT EQU 01108h
; Macro to align boundaries.
ALIGN: MACRO ?boundary, ?fill
DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, ?fill
ENDM
ORG 0E800h
MZ1R12:
NOP
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
ST1X:
CALL LETNL
CALL LETNL
LD DE,LE83B ; 'PRESS R, W OR M'
CALL MSG
CALL LETNL
CALL LETNL
LD DE,LE85B ; 'R: READ S-RAM'
CALL MSG
CALL LETNL
LD DE,LE877 ; 'W: WRITE S-RAM'
CALL MSG
CALL LETNL
LD DE,LE893 ; 'M: MONITOR'
CALL MSG
CALL LETNL
JR LE8AB
LE83B: DB " P",005h,"RESS",005h," R , W ",005h,"OR",005h," M",00Dh
LE85B: DB " R:",005h,"READ",005h," S-RAM",00Dh
LE877: DB " W:",005h,"WRITE",005h," S-RAM",00Dh
LE893: DB " M:",005h,"MONITOR",005h,00Dh
LE8AB:
NOP
CALL GETKY
CP 'M'
JP Z,MON
CP 'W'
JP Z,LE96A
CP 'R'
JP Z,LE8C1
JP NZ,LE8AB
LE8C1:
NOP
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
CALL LETNL
LD DE,LEB1B ; 'LOADING PROGRAM FROM S-RAM'
CALL MSG
CALL LETNL
CALL LETNL
CALL CHECK
IN A,(0F8h) ; Counter reset
IN A,(0F9h)
LD C,A
IN A,(0F9h)
LD B,A
IN A,(0F9h)
LD L,A
IN A,(0F9h)
LD H,A
IN A,(0F9h)
LD E,A
IN A,(0F9h)
LD D,A
PUSH DE
LD D,B
LD E,C
IN A,(0F9h)
LD C,A
IN A,(0F9h)
LD B,A
IN A,(0F9h)
PUSH BC
PUSH DE
PUSH HL
LD C,0F9h
LD A,E
OR A
JR Z,LE90A
LD B,A
LE908:
INIR
LE90A:
LD B,000h
DEC D
JP P,LE908
POP DE ; Data adr
POP BC ; Size
CALL SUM
POP DE
OR A
SBC HL,DE
JR NZ,LE956
POP HL
JP (HL)
;
; sum check
;
; IN BC=Size
; DE=Data adr
; EXIT HL=Check sum
;
SUM:
PUSH BC
PUSH DE
EXX
LD HL,00000h ; HL'= Check sum clr
LD C,008h ; C' = Loop count
EXX
SUMCK1:
LD A,B ; BC = Size
OR C
JR Z,SUMCK2
LD A,(DE) ; DE = Data adrs
EXX
LD B,C ; BC'
SUMCK3:
RLCA
JR NC,LE931
INC HL ; HL' = Check sum data
LE931:
DJNZ SUMCK3
EXX
INC DE ; DE
DEC BC ; BC
JP SUMCK1
SUMCK2:
EXX
POP DE
POP BC
RET
;
; Information's sum check
;
CHECK:
IN A,(0F8h) ; Counter reset
LD BC,00800h ; B=Byte Counter C=Sum Counter
CK1:
IN A,(0F9h) ; Counter=Counter+1
PUSH BC
LD B,008h ; Bit Counter
CK2:
RLCA
JR NC,LE94B
INC C
LE94B:
DJNZ CK2
LD A,C
POP BC
LD C,A
DJNZ CK1
IN A,(0F9h)
CP C
RET
LE956:
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
LD DE,LEA8F ; 'CHECK SUM ERROR'
CALL LEA3D
JP ST1X
LE96A:
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
CALL LETNL
LD DE,LEAAC ; 'S-RAM PROGRAMMING'
CALL LEA36
LD DE,LEACB ; 'SET MASTER TAPE PLAY'
LD A,011h
LD HL,0D8F0h
CALL LEA4A
CALL LETNL
CALL LEA39
CALL RDINF
PUSH AF
PUSH BC
LD BC,(SIZE)
LD A,07Fh
CP B
JR C,LE9A8
JR NZ,LE9A4
LD A,0F6h
CP C
JR C,LE9A8
LE9A4:
POP BC
POP AF
JR LE9AD
LE9A8:
POP BC
POP AF
JP LEA74
LE9AD:
LD A,000h
LD HL,0D0F0h
CALL LEA4A
LD A,071h
LD HL,0D8F0h
CALL LEA4A
LD A,002h
JP C,LEA42
CALL LETNL
LD DE,LEAF1 ; 'FOUND : '
CALL LEA3D
LD DE,NAME
PUSH DE
RST 018h
CALL LETNL
LD DE,LEB06 ; 'LOADING : '
CALL LEA3D
POP DE
RST 018h
;
; Read data block
;
CALL RDDAT
JR C,LEA42
;
; Counter reset
;
IN A,(0F8h)
;
; Sum check for data
;
LD DE,(DTADR)
LD BC,(SIZE)
PUSH DE
PUSH BC
CALL SUM
LD (COMNT),HL
;
; Write information (8Byte)
;
LD HL,SIZE
LD BC,008FAh ; B=Byte Counter
PUSH HL
PUSH BC
OTIR
POP BC
POP HL
;
; Sum check for information block
; AccCheck sum data
;
PUSH DE ; DE Size
LD D,000h ; Sum Counter
WCK1:
PUSH BC
LD B,008h
LD A,(HL)
WCK2:
RLCA
JR NC,WCK3
INC D
WCK3:
DJNZ WCK2
INC HL
POP BC
DJNZ WCK1
LD A,D
POP DE
OUT (0FAh),A
;
; Write data block
;
POP DE ; DE Size
POP HL ; HL Data adrs
LD A,E
OR A
JR Z,LEA1C
LD B,E
LEA1A:
OTIR
LEA1C:
LD B,000h
DEC D
JP P,LEA1A
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
LD DE,LEB8C ; 'WRITING S-RAM O.K.!'
CALL MSG
JP ST1X
LEA36:
CALL QNL
LEA39:
RST 018h
JP QNL
LEA3D:
CALL QNL
RST 018h
RET
LEA42:
CP 002h
JP Z,LEA60
JP LE956
LEA4A:
LD B,006h
LEA4C:
LD (HL),A
INC HL
DEC B
JR NZ,LEA4C
RET
MON:
LD A,016h
CALL PRNT
LD DE,LEB3E ; '** MONITOR 1Z-009A **'
CALL MSG
JP ST1
LEA60:
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
LD DE,LEB77 ; 'BREAK !'
CALL MSG
JP ST1X
LEA74:
LD DE,00000h
LD (SIZE),DE
LD A,016h
CALL PRNT
CALL LETNL
CALL LETNL
LD DE,LEBAD ; 'FILE IS TOO LONG'
CALL MSG
JP ST1X
LEA8F: DB " C",005h,"HECK SUM ERROR",005h,00Dh
LEAAC: DB " S-RAM ",005h,"PROGRAMMING",005h,00Dh
LEACB: DB " S",005h,"ET MASTER TAPE",005h," ",07Fh,"P",005h,"LAY",005h," ",00Dh
LEAF1: DB " F",005h,"OUND",005h," : ",00Dh
LEB06: DB " L",005h,"OADING",005h,": ",00Dh
LEB1B: DB " L",005h,"OADING PROGRAM FROM ",005h,"S-RAM",00Dh
LEB3E: DB "** MONITOR 1Z-009A **",00Dh
LEB56: DB " R",005h,"EADING",005h," S-RAM O.K.!",00Dh
LEB77: DB " B",005h,"REAK",005h," !",00Dh
LEB8C: DB " W",005h,"RITING",005h," S-RAM O.K.!",00Dh
LEBAD: DB " F",005h,"ILE IS TOO LONG",005h,00Dh
; the following is only to get the original length of 4096 bytes
ALIGN 0F7FFh, 0FFh
DB 0FFh

1483
asm/mz-1e14.asm Normal file
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661
asm/mz80kfdif.asm Normal file
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;
; MZ-80K FDC ROM
;
ORG F000H
F000 00 NOP
F001 F3 DI
F002 AF XOR A
F003 329C11 LD (#119C),A ;clock off
F006 3EC3 LD A,#C3 ;JP code for error trap
F008 320B10 LD (#100B),A
F00B 215AF0 LD HL,#F05A ;error can't boot
F00E 220C10 LD (#100C),HL ;error trap
F011 11F09F LD DE,#9FF0 ;transfer 9 bytes from
F014 2187F0 LD HL,#F087 ;ROM to RAM for use
;
;IBT1
;
F017 010900 IBT1: LD BC,#0009 ;by (IX+D) in reader
F01A EDB0 LDIR
F01C CD0900 CALL CRLF ;NL
F01F 117AF0 LD DE,MESS1
F022 CD1500 CALL MESSAGE ;msg "BOOT DRIVE ?"
F025 11009F LD DE,BUFF2
F028 CD0300 CALL USER ;get line
F02B 210C00 LD HL,#000C
F02E 19 ADD HL,DE ;skip around msg
F02F 7E LD A,(HL) ;pickup answer to prompt
F030 FE0D CP #0D ;CR ?
F032 2002 JR NZ,#F036 ;Z=CR assume drive 1
F034 3E31 LD A,#31 ;ASCII for 1
;
;IBT2
;
F036 47 IBT2: LD B,A ;save driveno
F037 E6F0 AND #F0 ;take ASCII and convert
F039 FE30 CP #30 ;to numeric having
F03B 20DF JR NZ,IBT1 ;checked >1 & <=4
F03D 78 LD A,B ;get driveno
F03E E60F AND #0F ;mask
F040 3D DEC A ;-1 00-03
F041 FE04 CP #04
F043 30D7 JR NC,IBT1 ;dud key, >=4, try again
F045 32F09F LD (#9FF0),A ;save drive no
F048 321110 LD (#1011),A ;save drive no
F04B DD21F09F LD IX,#9FF0 ;IX pointer to fdc parameters at 9FF0
;ready for disk read
F04F CD3BF1 CALL READER ;get boot records
F052 3A0098 LD A,(#9800) ;1st byte of input buffer of boot records
F055 FEC3 CP #C3 ;jump cmd?
F057 CA0098 JP Z,#9800 ;yes, execute to 9800
;
;IBT3
;
F05A 31F010 IBT3: LD SP,#10F0 ;no, reset stack
F05D CD0900 CALL CRLF ;NL
F060 116CF0 LD DE,MESS2 ;msg can't boot
F063 CD1500 CALL MESSAGE
F066 CDA7F0 CALL MOTOFF ;motor off
F069 C38200 JP MAINLP ;warm start, ret to monitor
;
;MESS2
;
F06C 45523A43 MESS2: DB "ER:CAN'T BOOT"
F070 414E2754
F074 20424F4F
F078 54
F079 0D DB 0DH
;
;MESS1
;
F07A 424F4F54 DB "BOOT DRIVE ?"
F07E 20445249
F082 5645203F
F086 0D DB 0DH
;
;DDATA
;fdc parameters
;
F087 00 DB 00H ;drive no-1
F088 00 DB 00H ;trk*2 remainder = head
F089 01 DB 01H ;sector no (range: 01 - 10)
F08A 00 DB 00H ;$80 = add 1 record to read to (F08B)
F08B 0700 DB 07H ;07H = 07*2 = 14 sectors to read, add 1 if (F08A = $80)
F08D 0098 DB 00H,98H ;9800H = load addr.
F08F 00 DB 00H ;no meaning
;
;MOTON
;
F090 C5 MOTON: PUSH BC ;starts motors
F091 01F808 LD BC,#08F8
F094 ED78 IN A,(C) ;start motor
F096 010000 LD BC,#0000
;
;WAIT1
;
F099 0B WAIT1: DEC BC ;wait for motor to
F09A 00 NOP ;get up to speed
F09B 00 NOP
F09C 78 LD A,B
F09D B1 OR C
F09E 20F9 JR NZ,WAIT1
F0A0 3E01 LD A,#01
F0A2 320210 LD (MOTFLG),A ;01=on 00=off
F0A5 C1 POP BC
F0A6 C9 RET
;
;MOTOFF
;
F0A7 C5 MOTOFF: PUSH BC ;stop motors
F0A8 CDAEF1 CALL LNGDEL ;timed wait
F0AB 01F800 LD BC,#00F8
F0AE ED78 IN A,(C)
F0B0 C1 POP BC
F0B1 C9 RET
;
;SKZERO
;
F0B2 CDBDF0 SKZERO: CALL DREADY ;seek track 0
F0B5 AF XOR A
F0B6 D3F9 OUT (#F9),A ;clear track reg
F0B8 320010 LD (#1000),A
F0BB D3FA OUT (#FA),A ;send seek zero code
;
;DREADY
;
F0BD C5 DREADY: PUSH BC
F0BE 010000 LD BC,#0000
;
;DRY1
;
F0C1 DBF9 DRY1: IN A,(#F9) ;get DRDY, CRDY, RQM
F0C3 E603 AND #03 ;leave DRDY, CRDY
;
;DRY2
;
F0C5 FE02 DRY2: CP #02 ;wait for DRDY & CRDY
F0C7 2002 JR NZ,WAIT2 ;no, =03
F0C9 C1 POP BC ;yes, =02
F0CA C9 RET
;
;WAIT2
;
F0CB 0B WAIT2: DEC BC
F0CC 78 LD A,B
F0CD B1 OR C
F0CE 20F1 JR NZ,DRY1
F0D0 C1 POP BC
F0D1 3E32 LD A,#32
F0D3 320810 LD (#1008),A ;error 40 (not found)
F0D6 C30B10 JP #100B ;error can't boot
;
;STATUS
;
F0D9 DBFA STATUS: IN A,(#FA) ;read status
F0DB E6F0 AND #F0
F0DD 07 RLCA
F0DE 30F9 JR NC,STATUS ;wait for CRDY
F0E0 E6F0 AND #F0 ;mask leave CRDY, S1, S2, S3
F0E2 0F RRCA ;move right until S§
F0E3 0F RRCA ;is in B0
F0E4 0F RRCA
F0E5 0F RRCA
F0E6 B7 OR A ;clear flags
F0E7 C8 RET Z ;Z=ok
F0E8 FE0C CP #0C ;0C=drive not ready etc.
F0EA 2004 JR NZ,STS1
F0EC 3E32 LD A,#32 ;error code 40 (not found)
F0EE 180A JR STS3
;
STS1
;
F0F0 FE04 STS1: CP #04 ;04=ID not found
F0F2 2004 JR NZ,STS2
F0F4 3E36 LD A,#36 ;error code 54 (unformat error)
F0F6 1802 JR STS3
;
;STS2
;
F0F8 3E29 STS2: LD A,#29
F0FA 320810 LD (#1008),A ;error code 41 disk hw error
F0FD 37 SCF
F0FE C9 RET
;
;PRMDRV
;
F0FF C5 PRMDRV: PUSH BC ;prime drive
F100 E5 PUSH HL
F101 CD90F0 CALL MOTON
F104 DD7E00 LD A,(IX+#00) ;get drive no-1
F107 E603 AND #03 ;form drive code
F109 F61C OR #1C ;set TND, MOTOR, SELECT BIT
F10B 320110 LD (#1001),A ;keep drive code
F10E E60F AND #0F ;mask out TND
F110 47 LD B,A
F111 0EF8 LD C,#F8
F113 ED60 IN H,(C) ;select drive
F115 3E32 LD A,#32
;
;PRM1
;
F117 CDAEF1 PRM1: CALL LNGDEL ;wait for head
F11A 3D DEC A :to load
F11B 20FA JR NZ,PRM1
F11D 010000 LD BC,#0000
;
;PRM2
;
F120 DBF9 PRM2: IN A,(#F9) ;get DRDY, CRDY, RQM
F122 E607 AND #07 ;mask out RUBBISH
F124 FE06 CP #06 ;DRDY & CRDY ?
F126 2006 JR NZ,PRM3 ;NZ=no, keep trying
F128 CDB2F0 CALL SKZERO
F12B E1 POP HL
F12C C1 POP BC
F12D C9 RET ;correct exit
;
;PRM3
;
F12E 0B PRM3: DEC BC
F12F 78 LD A,B
F130 B1 OR C
F131 20ED JR NZ,PRM2
F133 3E32 LD A,#32
F135 320810 LD (#1008),A ;error 40 (not found)
F138 C30B10 JP #100B ;abort; error can't boot
;
;READER
;
F13B 3E0A READER: LD A,#0A ;no. of tries
F13D 320710 LD (#1007),A
;
;RDR1
;
F140 CDFFF0 RDR1: CALL PRMDRV
F143 3A0110 LD A,(#1001) ;keep drive in use
F146 47 LD B,A
F147 0EF8 LD C,#F8
F149 D9 EXX ;save all regs
F14A 0EFB LD C,#FB ;port fb??
F14C DD5E03 LD E,(IX+#03) ;no meaning
F14F DD5604 LD D,(IX+#04) ;get half of numbers to read (7)
F152 CB13 RL E ;B7 to carry
F154 CB12 RL D ;double number of sectors (14), add carry
F156 1E03 LD E,#03 ;no meaning
F158 DD6E05 LD L,(IX+#05) ;get loading address lo
F15B DD6606 LD H,(IX+#06) ;hi into HL
F15E CDBDF0 CALL DREADY
F161 AF XOR A ;no meaning
F162 DD7E01 LD A,(IX+#01) ;get track to read
F165 1F RRA ;divide by 2, remainder to carry = head no.
F166 D3F9 OUT (#F9),A ;send track to FDC
F168 DD7E02 LD A,(IX+#02) ;sector number
F16B 3002 JR NC,RDR2
F16D F680 OR #80 ;odds/evens for side code
;
;RDR2
;
F16F D3F8 RDR2: OUT (#F8),A ;send sect+side
F171 CDA6F1 CALL SHTDEL ;short delay
F174 3E70 LD A,#70 ;seek & read code
F176 320010 LD (#1000),A ;keep it
F179 F3 DI
F17A D3FA OUT (#FA),A ;send seek & read code to FDC
;
;RDR3
;
F17C 0680 RDR3: LD B,#80 ;128 bytes/sector
;
;RDR4
;
F17E DBF9 RDR4: IN A,(#F9) ;get DRDY, CRDY, RQM
F180 A3 AND E ;mask with 03
F181 28FB JR Z,RDR4 ;wait for either CRDY/RQM
F183 0F RRCA ;RQM into carry
F184 300C JR NC,RDR5 ;NC=no RQM
F186 EDA2 INI ;get data. port FB to (HL), B=B-1
F188 C27EF1 JP NZ,RDR4 ;do whole sector
F18B 15 DEC D ;dec sector counter
F18C C27CF1 JP NZ,RDR3 ;NZ=more to do
F18F D9 EXX ;restore all regs
F190 ED78 IN A,(C) ;send TND high
;
;RDR5
;
F192 CDD9F0 RDR5: CALL STATUS
F195 D0 RET NC ;NC=good read
F196 3A0710 LD A,(#1007)
F199 3D DEC A ;A try gone
F19A 320710 LD (#1007),A ;counter 10times
F19D CA0B10 JP Z,#100B ;can't read at all abort
F1A0 CDB2F0 CALL SKZERO
F1A3 C340F1 JP RDR1
;
;SHTDEL
;
F1A6 F5 SHTDEL: PUSH AF
F1A7 3E0A LD A,#0A
;
;SDY1
;
F1A9 3D SDY1: DEC A
F1AA 20FD JR NZ,SDY1
F1AC F1 POP AF
F1AD C9 RET
;
;LNGDEL
;
F1AE F5 LNGDEL: PUSH AF ;long delay
F1AF 3E0A LD A,#0A
;
;LDY1
;
F1B1 CDA6F1 LDY1: CALL SHTDEL
F1B4 3D DEC A
F1B5 20FA JR NZ,LDY1
F1B7 F1 POP AF
F1B8 C9 RET
CRLF: EQU 00009H
MESSAGE: EQU 00015H
BUFF2: EQU 9F00H
USER: EQU 00003H
MAINLP: EQU 00082H
MOTFLG: EQU 1002H
END
;
;no meaning !!
;
F1B9 13 INC DE
F1BA 1B DEC DE
F1BB 72 LD (HL),D
F1BC DE42 SBC A,#42
F1BE FB EI
F1BF 2F CPL
F1C0 58 LD E,B
F1C1 43 LD B,E
F1C2 7C LD A,H
F1C3 52 LD D,D
F1C4 3023 JR NC,#F1E9 ; (35)
F1C6 71 LD (HL),C
F1C7 42 LD B,D
F1C8 1020 DJNZ #F1EA ; (32)
F1CA 74 LD (HL),H
F1CB 40 LD B,B
F1CC 43 LD B,E
F1CD 03 INC BC
F1CE 51 LD D,C
F1CF 00 NOP
F1D0 3C INC A
F1D1 42 LD B,D
F1D2 D8 RET C
F1D3 60 LD H,B
F1D4 FB EI
F1D5 09 ADD HL,BC
F1D6 FC402C CALL M,#2C40
F1D9 80 ADD A,B
F1DA 79 LD A,C
F1DB 2A4940 LD HL,(#4049)
F1DE 4D LD C,L
F1DF EE3E XOR #3E
F1E1 B2 OR D
F1E2 1EA2 LD E,#A2
F1E4 58 LD E,B
F1E5 02 LD (BC),A
F1E6 58 LD E,B
F1E7 12 LD (DE),A
F1E8 02 LD (BC),A
F1E9 43 LD B,E
F1EA 02 LD (BC),A
F1EB 220002 LD (#0200),HL
F1EE 2D DEC L
F1EF 4B LD C,E
F1F0 5A LD E,D
F1F1 0A LD A,(BC)
F1F2 40 LD B,B
F1F3 4A LD C,D
F1F4 13 INC DE
F1F5 42 LD B,D
F1F6 45 LD B,L
F1F7 0A LD A,(BC)
F1F8 5B LD E,E
F1F9 6E LD L,(HL)
F1FA 6A LD L,D
F1FB 4E LD C,(HL)
F1FC 4E LD C,(HL)
F1FD 4E LD C,(HL)
F1FE 5D LD E,L
F1FF 7E LD A,(HL)
F200 3011 JR NC,#F213 ; (17)
F202 DD300E JR NC,#F213 ; (14)
F205 067E LD B,#7E
F207 FE3A CP #3A
F209 CAC221 JP Z,#21C2
F20C 12 LD (DE),A
F20D 23 INC HL
F20E 13 INC DE
F20F 0D DEC C
F210 C20622 JP NZ,#2206
F213 C3C221 JP #21C2
F216 3AB830 LD A,(#30B8)
F219 FEB1 CP #B1
F21B CA4522 JP Z,#2245
F21E 2A5030 LD HL,(#3050)
F221 CD1E20 CALL #201E
F224 7E LD A,(HL)
F225 FE27 CP #27
F227 CA5722 JP Z,#2257
F22A 3E84 LD A,#84
F22C 327630 LD (#3076),A
F22F 3E02 LD A,#02
F231 327730 LD (#3077),A
F234 CDCA13 CALL #13CA
F237 D24A22 JP NC,#224A
F23A 2E00 LD L,#00
F23C 3EB2 LD A,#B2
F23E 32C830 LD (#30C8),A
F241 7D LD A,L
F242 326F30 LD (#306F),A
F245 3E01 LD A,#01
F247 C3C321 JP #21C3
F24A 3ABE30 LD A,(#30BE)
F24D FEC5 CP #C5
F24F C23C22 JP NZ,#223C
F252 3EB0 LD A,#B0
F254 C33E22 JP #223E
F257 23 INC HL
F258 7E LD A,(HL)
F259 E67F AND #7F
F25B 6F LD L,A
F25C C33C22 JP #223C
F25F 3AB830 LD A,(#30B8)
F262 FEB1 CP #B1
F264 CA9022 JP Z,#2290
F267 2A5030 LD HL,(#3050)
F26A CD1E20 CALL #201E
F26D 3E80 LD A,#80
F26F 327630 LD (#3076),A
F272 3E01 LD A,#01
F274 327730 LD (#3077),A
F277 CDCA13 CALL #13CA
F27A D29522 JP NC,#2295
F27D 210000 LD HL,#0000
F280 3E82 LD A,#82
F282 32C830 LD (#30C8),A
F285 226330 LD (#3063),HL
F288 116F30 LD DE,#306F
F28B 7C LD A,H
F28C 12 LD (DE),A
F28D 13 INC DE
F28E 7D LD A,L
F28F 12 LD (DE),A
F290 3E02 LD A,#02
F292 C3C321 JP #21C3
F295 3ABE30 LD A,(#30BE)
F298 FEC5 CP #C5
F29A C2A222 JP NZ,#22A2
F29D 3EB1 LD A,#B1
F29F C38222 JP #2282
F2A2 CDEA1A CALL #1AEA
F2A5 C38222 JP #2282
F2A8 2A5030 LD HL,(#3050)
F2AB CD1E20 CALL #201E
F2AE 116F30 LD DE,#306F
F2B1 0600 LD B,#00
F2B3 0E04 LD C,#04
F2B5 7E LD A,(HL)
F2B6 23 INC HL
F2B7 FE27 CP #27
F2B9 C2F822 JP NZ,#22F8
F2BC 7E LD A,(HL)
F2BD FE27 CP #27
F2BF C2DE22 JP NZ,#22DE
F2C2 3AB830 LD A,(#30B8)
F2C5 FEB1 CP #B1
F2C7 CAD522 JP Z,#22D5
F2CA AF XOR A
F2CB 21C830 LD HL,#30C8
F2CE B8 CP B
F2CF CAD922 JP Z,#22D9
F2D2 3EB3 LD A,#B3
F2D4 77 LD (HL),A
F2D5 78 LD A,B
F2D6 C3C321 JP #21C3
F2D9 3EB4 LD A,#B4
F2DB C3D422 JP #22D4
F2DE FE8D CP #8D
F2E0 CAF822 JP Z,#22F8
F2E3 FE0A CP #0A
F2E5 CAF822 JP Z,#22F8
F2E8 E67F AND #7F
F2EA 12 LD (DE),A
F2EB 23 INC HL
F2EC 13 INC DE
F2ED 04 INC B
F2EE 0D DEC C
F2EF C2BC22 JP NZ,#22BC
F2F2 117A30 LD DE,#307A
F2F5 C3BC22 JP #22BC
F2F8 3E53 LD A,#53
F2FA CD111C CALL #1C11
F2FD C3C222 JP #22C2
F300 CDE511 CALL #11E5
F303 CD0C20 CALL #200C
F306 FE3A CP #3A
F308 C26423 JP NZ,#2364
F30B 2A5030 LD HL,(#3050)
F30E CD1E20 CALL #201E
F311 3E80 LD A,#80
F313 327630 LD (#3076),A
F316 3E02 LD A,#02
F318 327730 LD (#3077),A
F31B CDCA13 CALL #13CA
F31E DA2E23 JP C,#232E
F321 3ACC30 LD A,(#30CC)
F324 FE01 CP #01
F326 C23123 JP NZ,#2331
F329 3ECC LD A,#CC
F32B CD111C CALL #1C11
F32E 210000 LD HL,#0000
F331 3AB830 LD A,(#30B8)
F334 FEB1 CP #B1
F336 CA6E23 JP Z,#236E
F339 FEB2 CP #B2
F33B CAC221 JP Z,#21C2
F33E 226330 LD (#3063),HL
F341 3EA2 LD A,#A2
F343 32C830 LD (#30C8),A
F346 CDB51D CALL #1DB5
F349 06DD LD B,#DD
F34B 30CD JR NC,#F31A ; (-51)
F34D E5 PUSH HL
F34E 1111DD LD DE,#DD11
F351 300E JR NC,#F361 ; (14)
F353 067E LD B,#7E
F355 FE3A CP #3A
F357 CAC221 JP Z,#21C2
F35A 12 LD (DE),A
F35B 23 INC HL
F35C 13 INC DE
F35D 0D DEC C
F35E C25423 JP NZ,#2354
F361 C3C221 JP #21C2
F364 3E4E LD A,#4E
F366 CD111C CALL #1C11
F369 3EB4 LD A,#B4
F36B C3BF21 JP #21BF
F36E EB EX DE,HL
F36F 2A4D31 LD HL,(#314D)
F372 2B DEC HL
F373 2B DEC HL
F374 2B DEC HL
F375 72 LD (HL),D
F376 23 INC HL
F377 73 LD (HL),E
F378 23 INC HL
F379 3680 LD (HL),#80
F37B C3C221 JP #21C2
F37E CC44A0 CALL Z,#A044
F381 41 LD B,C
F382 AC XOR H
F383 2842 JR Z,#F3C7 ; (66)
F385 C3A9F1 JP #F1A9
F388 0A LD A,(BC)
F389 CC44A0 CALL Z,#A044
F38C 41 LD B,C
F38D AC XOR H
F38E 2844 JR Z,#F3D4 ; (68)
F390 C5 PUSH BC
F391 A9 XOR C
F392 F1 POP AF
F393 1A LD A,(DE)
F394 CC44A0 CALL Z,#A044
F397 2842 JR Z,#F3DB ; (66)
F399 C3A9AC JP #ACA9
F39C 41 LD B,C
F39D F1 POP AF
F39E 02 LD (BC),A
F39F CC44A0 CALL Z,#A044
F3A2 2844 JR Z,#F3E8 ; (68)
F3A4 C5 PUSH BC
F3A5 A9 XOR C
F3A6 AC XOR H
F3A7 41 LD B,C
F3A8 F1 POP AF
F3A9 12 LD (DE),A
F3AA CC44A0 CALL Z,#A044
F3AD 41 LD B,C
F3AE AC XOR H
F3AF C9 RET
F3B0 F2ED57 JP P,#57ED
F3B3 CC44A0 CALL Z,#A044
F3B6 41 LD B,C
F3B7 AC XOR H
F3B8 D2F2ED JP NC,#EDF2
F3BB 5F LD E,A
F3BC CC44A0 CALL Z,#A044
F3BF C9 RET
F3C0 AC XOR H
F3C1 41 LD B,C
F3C2 F2ED47 JP P,#47ED
F3C5 CC44A0 CALL Z,#A044
F3C8 D2AC41 JP NC,#41AC
F3CB F2ED4F JP P,#4FED
F3CE CC44A0 CALL Z,#A044
F3D1 53 LD D,E
F3D2 50 LD D,B
F3D3 AC XOR H
F3D4 48 LD C,B
F3D5 CCF1F9 CALL Z,#F9F1
F3D8 CC44A0 CALL Z,#A044
F3DB 53 LD D,E
F3DC 50 LD D,B
F3DD AC XOR H
F3DE C9 RET
F3DF D8 RET C
F3E0 F2DDF9 JP P,#F9DD
F3E3 CC44A0 CALL Z,#A044
F3E6 53 LD D,E
F3E7 50 LD D,B
F3E8 AC XOR H
F3E9 C9 RET
F3EA 59 LD E,C
F3EB F2FDF9 JP P,#F9FD
F3EE 50 LD D,B
F3EF 55 LD D,L
F3F0 53 LD D,E
F3F1 48 LD C,B
F3F2 A0 AND B
F3F3 42 LD B,D
F3F4 C3F1C5 JP #C5F1
F3F7 50 LD D,B
F3F8 55 LD D,L
F3F9 53 LD D,E
F3FA 48 LD C,B
F3FB A0 AND B
F3FC 44 LD B,H
F3FD C5 PUSH BC
F3FE F1 POP AF
F3FF D5 PUSH DE

620
asm/quickdisk_mz-1e05.asm Normal file
View File

@@ -0,0 +1,620 @@
; V1.10
;
; To compile use:
;
; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor.
;
; Available from:
; - http://www.falstaff.demon.co.uk/cross.html
; - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip
; - and many Simtel mirrors.
;
; as80 -i -l -n -x2 -v -z mz-1e05.asm
;
;----< MFM Minifloppy control >----
;
;
; Call condition
;
; Case of disk initialize
; Drive N = IX+0 (0 - 3)
;
;
; Case of sequential read & write
; Drive N = IX+0 (0 - 3)
;
; Sector addrs = IX+1,2 (0 - $045F) H C S
; (0 - 1119) -> 70 x 16 sectors -> 2 x 35 x 16
; Byte size = IX+3,4
; Address = IX+5,6
; Next track = IX+7
; Next sector = IX+8
; Start track = IX+9
; Start sector = IX+10
;
;
; I/O Port address
;
CR EQU 0D8h ; CommandRegister
TR EQU 0D9h ; TrackRegister
SCR EQU 0DAh ; SeCtorRegister
DR EQU 0DBh ; DataRegister
DM EQU 0DCh ; DriveMotor
HS EQU 0DDh ; HeadSelect
TIMST EQU 00033h
;
; Subroutine work
;
BPRO EQU 0CF00h
BUF EQU 011A3h
BPARA EQU BPRO - 23 ; BootPARAmeter
CMD EQU BPARA + 11 ; CoMmanD
MTFG EQU CMD + 1 ; MoTorFlaG
CLBF0 EQU MTFG + 1
CLBF1 EQU CLBF0 + 1
CLBF2 EQU CLBF1 + 1
CLBF3 EQU CLBF2 + 1
VRFCNT EQU CLBF3 + 1 ; VeRiFyCouNT
STAFG EQU VRFCNT + 1 ; STAtusFlaG
; Macro to align boundaries.
ALIGN: MACRO ?boundary, ?fill
DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, ?fill
ENDM
;
;
;--------< Ercode map >--------
;
; 50 : Not ready
; 41 : Data error
; Track 80 err
; Write protect err
; Seek err
; CRC err
; Lost data
; 54 : Unformat
; Recode not found
; 56 : Invalid data
;
;
ORG 0F000h
MZ_1E05:
NOP
LD HL,000ADh
JR L_F007
FDX:
EX (SP),HL
L_F007:
LD (BPARA + 21),HL
XOR A
LD DE,0
CALL TIMST
CALL FDCC ; FD i/o check
JP NZ,NOTIO
LD DE,BPARA ; destination address
LD HL,BOOT ; source address
LD BC,11 ; 11 bytes
LDIR ; copy
SJP:
LD IX,BPARA
CALL BREAD ; read from drive 0, sector 0,
;
LD HL,BPRO ; compare this address
LD DE,IPLMC ; with the IPL MasterCode
LD B,7 ; this are 7 bytes : 3,'IPLPRO'
MCHECK:
LD C,(HL)
LD A,(DE)
CP C
JP NZ,MASTE ; not equal than MasterError
INC HL
INC DE
DJNZ MCHECK
; else Master was found
LD DE,IPLM0 ; 'IPL IS LOADING'
RST 018h
LD DE,BPRO + 7 ; NAME
RST 018h
LD HL,(BPRO + 016h) ; TARGETADDRESS from BootBlock
LD A,H
OR L
JR NZ,L_F051 ; if it is != 0 than normal file
LD HL,(BPRO + 018h) ; TARGETADDRESS from BootBlock
LD A,H
OR L
JR Z,L_F057 ; if it is also 0 than ROM replace file
L_F051:
XOR A ; else normal file,
LD HL,(BPRO + 018h) ; TARGETADDRESS from BootBlock
JR L_F05C
L_F057:
LD A,0FFh ; target is at $0000, bankswitching is needed
LD HL,01200h ; for now use temporary buffer at $1200
L_F05C:
LD (0CEFDh),A
LD (IX + 5),L ; set the TargetAddress
LD (IX + 6),H
LD HL,(BPRO + 014h) ; BYTE SIZE from BootBlock
LD (IX + 3),L
LD (IX + 4),H
LD HL,(BPRO + 01Eh) ; START SECTOR from BootBlock
LD (IX + 1),L
LD (IX + 2),H
;
CALL BREAD
CALL MOFF
LD A,(0CEFDh)
CP 0FFh
JR NZ,L_F093
OUT (0E0h),A
LD HL,01200h ; SourceAddress
LD DE,(BPRO + 016h) ; TargetAddress
LD BC,(BPRO + 014h) ; ByteCounter
LDIR ; copy
L_F093:
LD BC,00200h ; Default code
LD HL,(BPRO + 018h) ; TARGET/EXECUTION ADDRESS from BootBlock
JP (HL)
MASTE:
CALL MOFF
LD DE,ERRM1 ; 'NOT MASTER'
JR ERRTR1
ERRTRT:
CP 50
NOTIO:
LD DE,IPLM3 ; 'MAKE READY FD'
JR Z,ERRTR1
LD DE,ERRM0 ; 'FD:LOADING ERROR'
ERRTR1:
CALL 00009h
RST 018h
LD SP,010EEh
LD HL,(BPARA + 21)
EX (SP),HL
RET
;
;
; PARAMETER SETTING
;
IPLMC:
DB 003h ; IPL MASTER FLAG
DB "IPLPRO"
BOOT:
DB 000h ; DRIVE NO.
DW 00000h ; SECTOR ADDR.
DW 00100h ; IFM BYTE SIZE
DW BPRO ; IFM LOADING ADDR.
DW 00000h ; IX+7,8 (track 0, sector 0)
ERRM1:
DB "FD:NOT MASTER",00Dh
IPLM0:
DB "IPL IS LOADING ",00Dh
IPLM3:
DB "MAKE READY FD",00Dh
ERRM0:
DB "FD:LOADING ERROR",00Dh
FDCC:
LD A,0A5h
LD B,A
OUT (TR),A
CALL DLY80U
IN A,(TR)
CP B
RET
L_F111:
DB 000h, 000h
;
;
; READY CHECK
;
READY:
LD A,(MTFG)
RRCA
CALL NC,MTON
LD A,(IX + 0) ; DRIVE NO SET
OR 084h
OUT (DM),A ; DRIVE SELECT MOTON
XOR A
LD (CMD),A
CALL DLY60M
LD HL,0
REDY0:
DEC HL
LD A,H
OR L
JR Z,REDY1
IN A,(CR) ; STATUS GET
CPL
RLCA
JR C,REDY0
LD C,(IX + 0)
LD HL,CLBF0
LD B,000h
ADD HL,BC
BIT 0,(HL)
JR NZ,REDY2
CALL RCLB
SET 0,(HL)
REDY2:
RET
REDY1:
LD A,032h
JP ERJMP
;
;
; MOTOR ON
;
MTON:
LD A,080h
OUT (DM),A
LD B,16
MTD1:
CALL DLY60M
DJNZ MTD1
LD A,1
LD (MTFG),A
RET
;
;
; SEEK TREATMENT
;
SEEK:
LD A,01Bh ; 1x = SEEK,
CALL CMDOT1 ; load head, no verify, max stepping rate
AND 099h
RET
;
;
; MOTOR OFF
;
MOFF:
PUSH AF
CALL DLY1M ; 1000 US DELAY
XOR A
OUT (DM),A
LD (CLBF0),A
LD (CLBF1),A
LD (CLBF2),A
LD (CLBF3),A
LD (MTFG),A
POP AF
RET
;
;
; RECALIBRATION
;
RCLB:
LD A,00Bh ; 0x = RESTORE (seek track 0)
CALL CMDOT1 ; load head, no verify, max stepping rate
AND 085h
XOR 004h
RET Z
L_F189:
JP STERROR
;
;
; COMMAND OUT ROUTINE
;
CMDOT1:
LD (CMD),A
CPL
OUT (CR),A
CALL BSYON
CALL DLY60M
IN A,(CR)
CPL
LD (STAFG),A
RET
;
;
; BUSY AND WAIT
;
BSYON:
PUSH DE
PUSH HL
CALL BSY0
BSYON2:
LD HL,00000h
BSYON0:
DEC HL
LD A,H
OR L
JR Z,BSYON1
IN A,(CR)
RRCA
JR NC,BSYON0
POP HL
POP DE
RET
;
BSYON1:
DEC E
JR NZ,BSYON2
BSYONE:
LD A,029h
POP HL
POP DE
JP ERJMP
;
BSYOFF:
PUSH DE
PUSH HL
CALL BSY0
BSYOF2:
LD HL,00000h
BSYOF0:
DEC HL
LD A,H
OR L
JR Z,BSYOF1
IN A,(CR) ; Status Register
RRCA
JR C,BSYOF0
POP HL
POP DE
RET
;
BSYOF1:
DEC E
JR NZ,BSYOF2
JR BSYONE
;
BSY0:
CALL DLY80U
LD E,007h
RET
;
;
; SEQUENTIAL READ
;
BREAD:
CALL CNVRT
CALL PARST1 ; HL = IX + 5,6 (TargetAddress)
RE8:
CALL SIDST
CALL SEEK
JP NZ,ERJMP
CALL PARST2 ; C = DataRegister
DI ; disable interrupts
LD A,094h ; 9x = READ SECTOR, multiple records
CALL CMDOT2 ; compare for side 0, 15ms delay,
RE6: ; disable side select compare
LD B,0 ; ByteCounter = 0, to load 256 bytes of the sector
RE4:
IN A,(CR)
RRCA
JR C,RE3
RRCA
JR C,RE4
INI ; (HL) = in(C), B = B - 1 , HL = HL + 1
JR NZ,RE4
INC (IX + 8) ; NextSector = NextSector + 1
LD A,(IX + 8)
CP 011h ; if NextSector = 17
JR Z,L_F213 ; than end
DEC D ; else SectorCounter = SectorCounter - 1
JR NZ,RE6 ; if SectorCounter = 0
JR L_F214 ; than end
L_F213:
DEC D
L_F214:
CALL INTER
RE3:
EI ; enable interrupts
IN A,(CR)
CPL
LD (STAFG),A
AND 0FFh
JR NZ,STERROR
CALL ADJ ; adjust sector and track
JP Z,REND
LD A,(IX + 7) ; track
JR RE8
REND:
LD A,080h
OUT (DM),A ; motor on
RET
;
;
; PARAMETER SET
;
;
PARST1:
CALL READY
LD D,(IX + 4) ; D = bytes to read (highbyte) (256 bytes)
LD A,(IX + 3) ; A = bytes to read (lowbyte)
OR A ; if A = 0
JR Z,L_F23F ; than it's ok
INC D ; else read 256 bytes more (1 sector)
L_F23F:
LD A,(IX + 10) ; NextSector = StartSector
LD (IX + 8),A
LD A,(IX + 9) ; NextTrack = StartTrack
LD (IX + 7),A
LD L,(IX + 5) ; HL = TargetAddress
LD H,(IX + 6)
RET
;
;
; SIZE SEEK SET
;
SIDST:
SRL A
CPL
OUT (DR),A
JR NC,L_F25D ; NC than Head 0
LD A,1 ; else Head 1
JR L_F25E
L_F25D:
XOR A
L_F25E:
CPL
OUT (HS),A ; set HeadSelect
RET
;
;
; TRACK & SECTOR SET
;
PARST2:
LD C,DR
LD A,(IX + 7) ; A = NextTrack
SRL A
CPL
OUT (TR),A
LD A,(IX + 8) ; A = NextSector
CPL
OUT (SCR),A
RET
;
;
; ADJUST SECT & TRACK
;
ADJ:
LD A,(IX + 8) ; A = NextSector
CP 17 ; if NextSector = 17
JR NZ,L_F282 ; than the border is not reached
LD A,001h ; else
LD (IX + 8),A ; NextSector = 1
INC (IX + 7) ; NextTrack = NextTrack + 1
L_F282:
LD A,D
OR A
RET
;
;
; COMMAND OUT & WAIT
;
CMDOT2:
LD (CMD),A
CPL
OUT (CR),A
CALL BSYOFF
RET
;
;
; FORCE INTERRUPT
;
INTER:
LD A,0D8h
CPL
OUT (CR),A
CALL BSYON
RET
;
;
; STATUS CHECK
;
STERROR:
LD A,(CMD)
CP 00Bh ; Restore (seek track 0)
JR Z,ERCK1
CP 01Bh ; Seek
JR Z,ERCK1
CP 0F4h ; Write track
JR Z,ERCK1
LD A,(STAFG)
BIT 7,A
JR NZ,ERRET
BIT 6,A
JR NZ,ERRET1
BIT 4,A
LD A,54
JR NZ,ERJMP
JR ERRET1
ERCK1:
LD A,(STAFG)
BIT 7,A
JR NZ,ERRET
ERRET1:
LD A,41
JR ERJMP
ERRET:
LD A,50
ERJMP:
CALL MOFF
JP ERRTRT
;
;
; SECTOR TO TRACK & SECTOR CONVERT
;
CNVRT:
LD B,0 ; TrackCounter = 0
LD DE,16 ; 16 sectors per track
LD L,(IX + 1) ; HL = SectorAddress
LD H,(IX + 2)
XOR A
TRANS0:
SBC HL,DE ; SectorAddress - SectorPerTrack
JR C,TRANS1 ; if < 0 than ready
INC B ; else TrackCounter = TrackCounter + 1
JR TRANS0 ; next try
TRANS1:
ADD HL,DE ; undo the last substraction
LD H,B
INC L ; adjust sector (sector is 1..16 and not 0..15)
LD (IX + 9),H ; set StartTrack
LD (IX + 10),L ; set StartSector
RET
;
;
; TIME DELAY ( 1m & 60m & 80u )
;
DLY80U:
PUSH DE
LD DE,15
JP DLYT
DLY1M:
PUSH DE
LD DE,160
JP DLYT
DLY60M:
PUSH DE
LD DE,8230
DLYT:
DEC DE
LD A,E
OR D
JR NZ,DLYT
POP DE
RET
ALIGN 0FFF0h, 000h
DB " 84.03.14 V1.0A"

1484
asm/quickdisk_mz-1e14.asm Normal file
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155
asm/ramcheck.asm Normal file
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LETNL: EQU 0006h
PRNTS: EQU 000Ch
PRNT: EQU 0012h
MSG: EQU 0015h
MONIT: EQU 0086h
PRTHL: EQU 03BAh
PRTHX: EQU 03C3h
DPCT: EQU 0DDCh
MSTART: EQU 1200h
ORG 10F0h
DB 01h ; Code Type, 01 = Machine Code.
DB "RAM TEST V1.0", 0Dh, 00h, 00h ; Title/Name (17 bytes).
DW MSTART - START ; Size of program.
DW START ; Load address of program.
DW START ; Exec address of program.
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h ; Comment (104 bytes).
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
ORG 01200h
START: LD DE,TITLE
CALL MSG
CALL LETNL
LD B, 20 ; Number of loops
LOOP: LD HL,MSTART ; Start of checked memory,
LD D,0CEh ; End memory check CE00
LOOP1: LD A,000h
CP L
JR NZ,LOOP1b
CALL PRTHL ; Print HL as 4digit hex.
LD A,0C4h ; Move cursor left.
LD E,004h ; 4 times.
LOOP1a: CALL DPCT
DEC E
JR NZ,LOOP1a
LOOP1b: INC HL
LD A,H
CP D ; Have we reached end of memory.
JR Z,LOOP3 ; Yes, exit.
LD A,(HL) ; Read memory location under test, ie. 0.
CPL ; Subtract, ie. FF - A, ie FF - 0 = FF.
LD (HL),A ; Write it back, ie. FF.
SUB (HL) ; Subtract written memory value from A, ie. should be 0.
JR NZ,LOOP2 ; Not zero, we have an error.
LD A,(HL) ; Reread memory location, ie. FF
CPL ; Subtract FF - FF
LD (HL),A ; Write 0
SUB (HL) ; Subtract 0
JR Z,LOOP1 ; Loop if the same, ie. 0
LOOP2: LD A,16h
CALL PRNT ; Print A
CALL PRTHX ; Print HL as 4 digit hex.
CALL PRNTS ; Print space.
XOR A
LD (HL),A
LD A,(HL) ; Get into A the failing bits.
CALL PRTHX ; Print A as 2 digit hex.
CALL PRNTS ; Print space.
LD A,0FFh ; Repeat but first load FF into memory
LD (HL),A
LD A,(HL)
CALL PRTHX ; Print A as 2 digit hex.
NOP
JR LOOP4
LOOP3: LD DE,OKCHECK
CALL MSG ; Print check message in DE
LD A,B ; Print loop count.
CALL PRTHX
LD DE,OKMSG
CALL MSG ; Print ok message in DE
DEC B
JR NZ,LOOP
LD DE,DONEMSG
CALL MSG ; Print check message in DE
JP MONIT
OKCHECK: DB 11h
DB "CHECK: ", 0Dh
OKMSG: DB "OK.", 0Dh
DONEMSG: DB 11h
DB "RAM TEST COMPLETE.", 0Dh
LOOP4: LD B,09h
CALL PRNTS ; Print space.
XOR A ; Zero A
SCF ; Set Carry
LOOP5: PUSH AF ; Store A and Flags
LD (HL),A ; Store 0 to bad location.
LD A,(HL) ; Read back
CALL PRTHX ; Print A as 2 digit hex.
CALL PRNTS ; Print space
POP AF ; Get back A (ie. 0 + C)
RLA ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB
DJNZ LOOP5 ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit.
XOR A ; Zero A, clears flags.
LD A,80h
LD B,08h
LOOP6: PUSH AF ; Repeat above but AND memory location with original A (ie. 80)
LD C,A ; Basically walk through all the bits to find which one is stuck.
LD (HL),A
LD A,(HL)
AND C
NOP
JR Z,LOOP8 ; If zero then print out the bit number
NOP
NOP
LD A,C
CPL
LD (HL),A
LD A,(HL)
AND C
JR NZ,LOOP8 ; As above, if the compliment doesnt yield zero, print out the bit number.
LOOP7: POP AF
RRCA
NOP
DJNZ LOOP6
JP MONIT
LOOP8: CALL LETNL ; New line.
LD DE,BITMSG ; BIT message
CALL MSG ; Print message in DE
LD A,B
DEC A
CALL PRTHX ; Print A as 2 digit hex, ie. BIT number.
CALL LETNL ; New line
LD DE,BANKMSG ; BANK message
CALL MSG ; Print message in DE
LD A,H
CP 50h ; 'P'
JR NC,LOOP9 ; Work out bank number, 1, 2 or 3.
LD A,01h
JR LOOP11
LOOP9: CP 90h
JR NC,LOOP10
LD A,02h
JR LOOP11
LOOP10: LD A,03h
LOOP11: CALL PRTHX ; Print A as 2 digit hex, ie. BANK number.
JR LOOP7
BITMSG: DB " BIT: ", 0Dh
BANKMSG: DB " BANK: ", 0Dh
TITLE: DB "SHARPMZ RAM TEST (C) P. SMART 2018", 0Dh, 00h

2788
asm/sa1510.asm Normal file
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1114
asm/tapecheck.asm Normal file
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2
build_id.v Normal file
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`define BUILD_DATE "180928"
`define BUILD_TIME "165433"

38
clean.bat Normal file
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@@ -0,0 +1,38 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

37
clean.sh Executable file
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@@ -0,0 +1,37 @@
#!/bin/bash -x
rm -f *.bak
rm -f *.orig
rm -f *.rej
rm -f *~
rm -fr db
rm -fr incremental_db
rm -fr output_files
rm -fr simulation
rm -fr greybox_tmp
rm -fr hc_output
rm -fr .qsys_edit
rm -fr hps_isw_handoff
rm -fr sys\.qsys_edit
rm -fr sys\vip
#rm build_id.v
rm -f c5_pin_model_dump.txt
rm -f PLLJ_PLLSPE_INFO.txt
rm -f *.qws
rm -f *.ppf
rm -f *.ddb
rm -f *.csv
rm -f *.cmp
rm -f *.sip
rm -f *.spd
rm -f *.bsf
rm -f *.f
rm -f *.sopcinfo
rm -f *.xml
rm -f *.cdf
rm -f *.rpt
rm -f new_rtl_netlist
rm -f old_rtl_netlist
rm -f asm/*.obj
rm -f asm/*.sym
(cd ../Main_MiSTer; make clean)

1094
common/T80/T80.vhd Normal file
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194
common/T80/T8080se.vhd Normal file
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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

371
common/T80/T80_ALU.vhd Normal file
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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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---------------------------------------------------------------------------------------------------------
--
-- Name: clk_div.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: A basic frequency divider module.
-- This module takes an input frequency and divides it based on a provided divider.
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_div is
GENERIC (
divider : natural
);
PORT (
clk_in : in std_logic;
reset : in std_logic;
clk_out : out std_logic
);
end clk_div;
architecture Behavioral of clk_div is
signal temporal: std_logic;
signal counter : integer range 0 to divider-1 := 0;
begin
process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = divider-1) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;

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---------------------------------------------------------------------------------------------------------
--
-- Name: clkgen.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: A programmable Clock Generate module.
-- This module is the heart of the emulator, providing all required frequencies
-- from a given input clock (ie. DE10 Nano 50MHz).
--
-- Based on input control signals from the MCTRL block, it changes the core frequencies
-- according to requirements and adjusts delays (such as memory) accordingly.
--
-- The module also has debugging logic to create debug frequencies (in the FPGA, static
-- is quite possible). The debug frequencies can range from CPU down to 1/10 Hz.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
package clkgen_pkg is
-- Clock bus, various clocks on a single bus construct.
--
subtype CLKBUS_WIDTH is integer range 9 downto 0;
-- Indexes to the various clocks on the bus.
--
constant CKSYS : integer := 0; -- Master Clock (Out)
constant CKHPS : integer := 1; -- HPS clock.
constant CKMEM : integer := 2; -- Memory Clock, running 2x the CPU clock.
constant CKVIDEO : integer := 3; -- Video base frequency.
constant CKSOUND : integer := 4; -- Sound base frequency.
constant CKRTC : integer := 5; -- RTC base frequency.
constant CKLEDS : integer := 6; -- Debug leds time base.
constant CKCPU : integer := 7; -- Variable CPU clock
constant CKPERIPH : integer := 8; -- Peripheral clock
constant CKRESET : integer := 9;
end clkgen_pkg;
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity clkgen is
Port (
RST : in std_logic; -- Reset
-- Clocks
CKBASE : in std_logic; -- Base system main clock.
CLKBUS : out std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module.
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- Debug modes.
DEBUG : in std_logic_vector(DEBUG_WIDTH)
);
end clkgen;
architecture RTL of clkgen is
--
-- Selectable output Clocks
--
signal PLLLOCKED : std_logic;
signal SYSFREQLOCKED : std_logic; -- System clock is locked and running.
signal CK448Mi : std_logic; -- 448MHz
signal CK224Mi : std_logic; -- 224MHz
signal CK112Mi : std_logic; -- 112MHz
signal CK64Mi : std_logic; -- 64MHz
signal CK56Mi : std_logic; -- 56MHz
signal CK32Mi : std_logic; -- 32MHz
signal CK28Mi : std_logic; -- 28MHz
signal CK17M7i : std_logic; -- 17.7MHz
signal CK16Mi : std_logic; -- 16MHz
signal CK14Mi : std_logic; -- 14MHz
signal CK8M8i : std_logic; -- 8.8MHz
signal CK8Mi : std_logic; -- 8MHz
signal CK7Mi : std_logic; -- 7MHz
signal CK4Mi : std_logic; -- 4MHz
signal CK3M5i : std_logic; -- 3.5MHz
signal CK2Mi : std_logic; -- 2MHz
signal CK1Mi : std_logic; -- 1MHz
signal CK895Ki : std_logic; -- 895KHz Sound frequency.
signal CK100Ki : std_logic; -- Debug frequency.
signal CK31500i : std_logic; -- Clock base frequency,
signal CK31250i : std_logic; -- Clock base frequency.
signal CK15611i : std_logic; -- Clock base frequency.
signal CK10Ki : std_logic; -- 10KHz debug CPU frequency.
signal CK5Ki : std_logic; -- 5KHz debug CPU frequency.
signal CK1Ki : std_logic; -- 1KHz debug CPU frequency.
signal CK500i : std_logic; -- 500Hz debug CPU frequency.
signal CK100i : std_logic; -- 100Hz debug CPU frequency.
signal CK50i : std_logic; -- 50Hz debug CPU frequency.
signal CK10i : std_logic; -- 10Hz debug CPU frequency.
signal CK5i : std_logic; -- 5Hz debug CPU frequency.
signal CK2i : std_logic; -- 2Hz debug CPU frequency.
signal CK1i : std_logic; -- 1Hz debug CPU frequency.
signal CK0_5i : std_logic; -- 0.5Hz debug CPU frequency.
signal CK0_2i : std_logic; -- 0.2Hz debug CPU frequency.
signal CK0_1i : std_logic; -- 0.1Hz debug CPU frequency.
--
-- Functional clocks.
--
signal CKLEDSi : std_logic; -- Debug Leds base clock.
signal CKCPUi : std_logic;
signal CKMEMd : std_logic_vector(64 downto 0); -- Delay line for the CPU clock to create the memory clock.
signal CKSOUNDi : std_logic;
signal CKVIDEOi : std_logic;
signal CKRTCi : std_logic;
signal CKPERIPHi : std_logic;
--
--
-- Components
--
component pll
Port (
refclk : in std_logic; -- Reference clock
rst : in std_logic; -- Reset
outclk_0 : out std_logic; -- 895MHz
locked : out std_logic -- PLL locked.
);
end component;
begin
PLLMAIN : pll
port map (
refclk => CKBASE, -- Reference clock
rst => RST, -- Reset
outclk_0 => CK448Mi, -- 448MHz
locked => PLLLOCKED -- PLL locked.
);
--
-- Clock Generator - Basic divide circuit for higher end frequencies.
--
process (RST, PLLLOCKED, CK448Mi)
--
variable counter224M : unsigned(1 downto 0); -- Binary divider to create 224MHz clock.
variable counter112M : unsigned(2 downto 0); -- Binary divider to create 112MHz clock.
variable counter64M : unsigned(2 downto 0); -- Binary divider to create 64MHz clock.
variable counter56M : unsigned(3 downto 0); -- Binary divider to create 56MHz clock.
variable counter32M : unsigned(3 downto 0); -- Binary divider to create 32MHz clock.
variable counter28M : unsigned(4 downto 0); -- Binary divider to create 28MHz clock.
variable counter17M7 : unsigned(5 downto 0); -- Binary divider to create 17.734475MHz clock.
variable counter16M : unsigned(4 downto 0); -- Binary divider to create 16MHz clock.
variable counter14M : unsigned(5 downto 0); -- Binary divider to create 16MHz clock.
variable counter8M8 : unsigned(5 downto 0); -- Binary divider to create 8.8672375MHz clock.
variable counter8M : unsigned(5 downto 0); -- Binary divider to create 8MHz clock.
variable counter7M : unsigned(6 downto 0); -- Binary divider to create 7MHz clock.
variable counter4M : unsigned(6 downto 0); -- Binary divider to create 4MHz clock.
variable counter3M5 : unsigned(6 downto 0); -- Binary divider to create 3.5MHz clock.
variable counter2M : unsigned(7 downto 0); -- Binary divider to create 2MHz clock.
variable counter1M : unsigned(8 downto 0); -- Binary divider to create 1MHz clock.
variable counter895K : unsigned(8 downto 0); -- Binary divider to create 895K clock.
variable waittosync : integer range 0 to 5; -- Counter which waits until the main clock stabilizes.
begin
if RST = '1' or PLLLOCKED = '0' then
counter224M := (others => '0');
counter112M := (others => '0');
counter64M := (others => '0');
counter56M := (others => '0');
counter32M := (others => '0');
counter28M := (others => '0');
counter17M7 := (others => '0');
counter16M := (others => '0');
counter14M := (others => '0');
counter8M8 := (others => '0');
counter8M := (others => '0');
counter7M := (others => '0');
counter4M := (others => '0');
counter3M5 := (others => '0');
counter2M := (others => '0');
counter1M := (others => '0');
counter895K := (others => '0');
CK224Mi <= '0';
CK112Mi <= '0';
CK64Mi <= '0';
CK56Mi <= '0';
CK32Mi <= '0';
CK28Mi <= '0';
CK17M7i <= '0';
CK16Mi <= '0';
CK14Mi <= '0';
CK8M8i <= '0';
CK8Mi <= '0';
CK7Mi <= '0';
CK4Mi <= '0';
CK3M5i <= '0';
CK2Mi <= '0';
CK1Mi <= '0';
CK895Ki <= '0';
SYSFREQLOCKED <= '0';
waittosync := 5;
elsif rising_edge(CK448Mi) then
-- If the main system frequency has stabilized and locked, commence oscillation of sub-frequencies.
if SYSFREQLOCKED = '1' then
-- 224MHz
if counter224M = 2 then
counter224M := (others => '0');
CK224Mi <= not CK224Mi;
else
counter224M := counter224M + 1;
end if;
-- 112MHz
if counter112M = 2 then
counter112M := (others => '0');
CK112Mi <= not CK112Mi;
else
counter112M := counter112M + 1;
end if;
-- 64MHz
if counter64M = 3 or counter64M = 7 then
CK64Mi <= not CK64Mi;
if counter64M = 7 then
counter64M := (others => '0');
else
counter64M := counter64M + 1;
end if;
else
counter64M := counter64M + 1;
end if;
-- 56MHz
if counter56M = 4 then
CK56Mi <= not CK56Mi;
counter56M := (others => '0');
else
counter56M := counter56M + 1;
end if;
-- 32MHz
if counter32M = 7 then
counter32M := (others => '0');
CK32Mi <= not CK32Mi;
else
counter32M := counter32M + 1;
end if;
-- 28MHz
if counter28M = 8 then
counter28M := (others => '0');
CK28Mi <= not CK28Mi;
else
counter28M := counter28M + 1;
end if;
-- 17.734475MHz
if counter17M7 = 13 or counter17M7 = 25 then
CK17M7i <= not CK17M7i;
if counter17M7 = 25 then
counter17M7 := (others => '0');
else
counter17M7 := counter17M7 + 1;
end if;
else
counter17M7 := counter17M7 + 1;
end if;
-- 16MHz
if counter16M = 14 then
counter16M := (others => '0');
CK16Mi <= not CK16Mi;
else
counter16M := counter16M + 1;
end if;
-- 14MHz
if counter14M = 16 then
counter14M := (others => '0');
CK14Mi <= not CK14Mi;
else
counter14M := counter14M + 1;
end if;
-- 8.8672375MHz
if counter8M8 = 25 then
counter8M8 := (others => '0');
CK8M8i <= not CK8M8i;
else
counter8M8 := counter8M8 + 1;
end if;
-- 8MHz
if counter8M = 28 then
counter8M := (others => '0');
CK8Mi <= not CK8Mi;
else
counter8M := counter8M + 1;
end if;
-- 7MHz
if counter7M = 32 then
counter7M := (others => '0');
CK7Mi <= not CK7Mi;
else
counter7M := counter7M + 1;
end if;
-- 4MHz
if counter4M = 56 then
counter4M := (others => '0');
CK4Mi <= not CK4Mi;
else
counter4M := counter4M + 1;
end if;
-- 3.546875MHz
if counter3M5 = 63 then
counter3M5 := (others => '0');
CK3M5i <= not CK3M5i;
else
counter3M5 := counter3M5 + 1;
end if;
-- 2MHz
if counter2M = 112 then
counter2M := (others => '0');
CK2Mi <= not CK2Mi;
else
counter2M := counter2M + 1;
end if;
-- 1MHz
if counter1M = 224 then
counter1M := (others => '0');
CK1Mi <= not CK1Mi;
else
counter1M := counter1M + 1;
end if;
-- 895K
if counter895K = 250 then
counter895K := (others => '0');
CK895Ki <= not CK895Ki;
else
counter895K := counter895K + 1;
end if;
else
waittosync := waittosync -1;
if waittosync = 0 then
SYSFREQLOCKED <= '1';
end if;
end if;
end if;
end process;
--
-- Clock Generator - Basic divide circuit for middle end frequencies.
--
process (RST, PLLLOCKED, CK1Mi)
--
variable counter100K : unsigned(5 downto 0); -- Binary divider to create 100K clock.
variable counter31250: unsigned(6 downto 0); -- Binary divider to create 31.250KHz clock.
variable counter15611: unsigned(7 downto 0); -- Binary divider to create 15.611KHz clock.
begin
if RST = '1' or PLLLOCKED = '0' then
counter100K := (others => '0');
counter31250 := (others => '0');
counter15611 := (others => '0');
CK100Ki <= '0';
CK31250i <= '0';
CK15611i <= '0';
elsif rising_edge(CK1Mi) then
-- 100K
if counter100K = 5 then
counter100K := (others => '0');
CK100Ki <= not CK100Ki;
else
counter100K := counter100K + 1;
end if;
-- 31,250KHz
if counter31250 = 16 then
counter31250 := (others => '0');
CK31250i <= not CK31250i;
else
counter31250 := counter31250 + 1;
end if;
-- 15.611KHz
if counter15611 = 32 then
counter15611 := (others => '0');
CK15611i <= not CK15611i;
else
counter15611 := counter15611 + 1;
end if;
end if;
end process;
--
-- Clock Generator - Basic divide circuit for middle end frequencies.
--
process (RST, PLLLOCKED, CK17M7i)
--
variable counter31500: unsigned(9 downto 0); -- Binary divider to create 31.500KHz clock.
begin
if RST = '1' or PLLLOCKED = '0' then
counter31500 := (others => '0');
CK31500i <= '0';
elsif rising_edge(CK17M7i) then
-- 31.5KHz
if counter31500 = 281 or counter31500=563 then
CK31500i <= not CK31500i;
counter31500 := (others => '0');
if counter31500 = 563 then
counter31500 := (others => '0');
else
counter31500 := counter31500 + 1;
end if;
else
counter31500 := counter31500 + 1;
end if;
end if;
end process;
--
-- Clock Generator - Basic divide circuit for middle end frequencies.
--
process (RST, PLLLOCKED, CK100Ki)
--
variable counter10K : unsigned(3 downto 0); -- Binary divider to create 10KHz clock.
variable counter5K : unsigned(4 downto 0); -- Binary divider to create 5KHz clock.
variable counter1K : unsigned(6 downto 0); -- Binary divider to create 1KHz clock.
variable counter500 : unsigned(7 downto 0); -- Binary divider to create 500Hz clock.
begin
if RST = '1' or PLLLOCKED = '0' then
counter10K := (others => '0');
counter5K := (others => '0');
counter1K := (others => '0');
counter500 := (others => '0');
CK10Ki <= '0';
CK5Ki <= '0';
CK1Ki <= '0';
CK500i <= '0';
elsif rising_edge(CK100Ki) then
-- 10KHz
if counter10K = 5 then
counter10K := (others => '0');
CK10Ki <= not CK10Ki;
else
counter10K := counter10K + 1;
end if;
-- 5KHz
if counter5K = 10 then
counter5K := (others => '0');
CK5Ki <= not CK5Ki;
else
counter5K := counter5K + 1;
end if;
-- 1KHz
if counter1K = 50 then
counter1K := (others => '0');
CK1Ki <= not CK1Ki;
else
counter1K := counter1K + 1;
end if;
-- 500Hz
if counter500 = 100 then
counter500 := (others => '0');
CK500i <= not CK500i;
else
counter500 := counter500 + 1;
end if;
end if;
end process;
--
-- Clock Generator - Basic divide circuit for middle end frequencies.
--
process (RST, PLLLOCKED, CK1Ki)
--
variable counter100 : unsigned(3 downto 0); -- Binary divider to create 100Hz clock.
variable counter50 : unsigned(4 downto 0); -- Binary divider to create 50Hz clock.
variable counter10 : unsigned(6 downto 0); -- Binary divider to create 10Hz clock.
variable counter5 : unsigned(7 downto 0); -- Binary divider to create 5Hz clock.
begin
if RST = '1' or PLLLOCKED = '0' then
counter100 := (others => '0');
counter50 := (others => '0');
counter10 := (others => '0');
counter5 := (others => '0');
CK100i <= '0';
CK50i <= '0';
CK10i <= '0';
CK5i <= '0';
elsif rising_edge(CK1Ki) then
-- 100Hz
if counter100 = 5 then
counter100 := (others => '0');
CK100i <= not CK100i;
else
counter100 := counter100 + 1;
end if;
-- 50Hz
if counter50 = 10 then
counter50 := (others => '0');
CK50i <= not CK50i;
else
counter50 := counter50 + 1;
end if;
-- 10Hz
if counter10 = 50 then
counter10 := (others => '0');
CK10i <= not CK10i;
else
counter10 := counter10 + 1;
end if;
-- 5Hz
if counter5 = 100 then
counter5 := (others => '0');
CK5i <= not CK5i;
else
counter5 := counter5 + 1;
end if;
end if;
end process;
--
-- Clock Generator - Basic divide circuit for low end frequencies.
--
process (RST, PLLLOCKED, CK100i)
--
variable counter2 : unsigned(5 downto 0); -- Binary divider to create 2Hz clock.
variable counter1 : unsigned(6 downto 0); -- Binary divider to create 1Hz clock.
variable counter0_5 : unsigned(7 downto 0); -- Binary divider to create 0.5Hz clock.
variable counter0_2 : unsigned(8 downto 0); -- Binary divider to create 0.2Hz clock.
variable counter0_1 : unsigned(9 downto 0); -- Binary divider to create 0.1Hz clock.
begin
if RST = '1' or PLLLOCKED = '0' then
counter2 := (others => '0');
counter1 := (others => '0');
counter0_5 := (others => '0');
counter0_2 := (others => '0');
counter0_1 := (others => '0');
CK2i <= '0';
CK1i <= '0';
CK0_5i <= '0';
CK0_2i <= '0';
CK0_1i <= '0';
elsif rising_edge(CK100i) then
-- 2Hz
if counter2 = 25 then
counter2 := (others => '0');
CK2i <= not CK2i;
else
counter2 := counter2 + 1;
end if;
-- 1Hz
if counter1 = 50 then
counter1 := (others => '0');
CK1i <= not CK1i;
else
counter1 := counter1 + 1;
end if;
-- 0.5Hz
if counter0_5 = 100 then
counter0_5 := (others => '0');
CK0_5i <= not CK0_5i;
else
counter0_5 := counter0_5 + 1;
end if;
-- 0.2Hz
if counter0_2 = 250 then
counter0_2 := (others => '0');
CK0_2i <= not CK0_5i;
else
counter0_2 := counter0_2 + 1;
end if;
-- 0.1Hz
if counter0_1 = 500 then
counter0_1 := (others => '0');
CK0_1i <= not CK0_5i;
else
counter0_1 := counter0_1 + 1;
end if;
end if;
end process;
--
-- Clock Generator - Basic divide circuit based on a 18 bit counter.
--
process (RST, PLLLOCKED, CK448Mi, CK224Mi, CK112Mi, CK64Mi, CK56Mi, CK32Mi, CK28Mi, CK17M7i, CK16Mi, CK14Mi, CK8M8i, CK8Mi, CK7Mi, CK4Mi, CK3M5i, CK2Mi,
CK1Mi, CK895Ki, CK100Ki, CK31500i, CK31250i, CK15611i, CK10Ki, CK5Ki, CK1Ki, CK500i, CK100i, CK50i, CK10i, CK5i, CK2i, CK1i, CK0_5i, CK0_2i, CK0_1i,
SYSFREQLOCKED, CKCPUi, CKMEMd, CKSOUNDi, CKVIDEOi, CKRTCi, CKPERIPHi, CKLEDSi)
--
variable mdelay : integer range 0 to 64; -- Memory clock delay line index.
begin
if RST = '1' or PLLLOCKED = '0' then
mdelay := 32;
CKCPUi <= '0';
CKMEMd <= (others => '0');
CKSOUNDi <= '0';
CKVIDEOi <= '0';
CKRTCi <= '0';
CKPERIPHi <= '0';
CKLEDSi <= '0';
elsif rising_edge(CK448Mi) then
-- Only start meaningful assignment once the main clock frequency is locked.
--
if SYSFREQLOCKED = '1' then
-- Delay line, different CPU frequencies require different memory delays.
CKMEMd(64 downto 1) <= CKMEMd(63 downto 0);
CKMEMd(0) <= CKCPUi;
-- If debugging has been enabled and the debug cpu frequency set to a valid value, change cpu clock accordingly.
if DEBUG(ENABLED) = '0' or DEBUG(CPUFREQ) = "0000" then
-- The CPU speed is configured by the CMT register and CMT state or the CPU register. Select the right
-- frequency and form the clock by flipping on the right flip flag.
--
case CONFIG(CPUSPEED) is
when "0001" => -- 3.5MHz
mdelay := 20;
CKCPUi <= CK3M5i;
when "0010" => -- 4MHz
mdelay := 16;
CKCPUi <= CK4Mi;
when "0011" => -- 7MHz
mdelay := 10;
CKCPUi <= CK7Mi;
when "0100" => -- 8MHz
mdelay := 8;
CKCPUi <= CK8Mi;
when "0101" => -- 14MHz
mdelay := 4;
CKCPUi <= CK14Mi;
when "0110" => -- 16MHz
mdelay := 4;
CKCPUi <= CK16Mi;
when "0111" => -- 28MHz
mdelay := 2;
CKCPUi <= CK28Mi;
when "1000" => -- 32MHz
mdelay := 4; -- was 2
CKCPUi <= CK32Mi;
when "1001" => -- 56MHz
mdelay := 4; -- was 3;
CKCPUi <= CK56Mi;
when "1010" => -- 64MHz
mdelay := 2; -- was 2;
CKCPUi <= CK64Mi;
when "1011" => -- 112MHz
mdelay := 1; -- was2;
CKCPUi <= CK112Mi;
-- Unallocated frequencies, use default.
when "0000"| "1100" | "1101" | "1110" | "1111" => -- 2MHz
mdelay := 32;
CKCPUi <= CK2Mi;
end case;
else
case DEBUG(CPUFREQ) is
when "0000" => -- Use normal cpu frequency, so this choice shouldnt be selected.
mdelay := 32;
CKCPUi <= CK2Mi;
when "0001" => -- 1MHz
mdelay := 64;
CKCPUi <= CK1Mi;
when "0010" => -- 100KHz
mdelay := 12;
CKCPUi <= CK100Ki;
when "0011" => -- 10KHz
mdelay := 24;
CKCPUi <= CK10Ki;
when "0100" => -- 5KHz
mdelay := 32;
CKCPUi <= CK5Ki;
when "0101" => -- 1KHz
mdelay := 36;
CKCPUi <= CK1Ki;
when "0110" => -- 500Hz
mdelay := 40;
CKCPUi <= CK500i;
when "0111" => -- 100Hz
mdelay := 44;
CKCPUi <= CK100i;
when "1000" => -- 50Hz
mdelay := 48;
CKCPUi <= CK50i;
when "1001" => -- 10Hz
mdelay := 52;
CKCPUi <= CK10i;
when "1010" => -- 5Hz
mdelay := 56;
CKCPUi <= CK5i;
when "1011" => -- 2Hz
mdelay := 58;
CKCPUi <= CK2i;
when "1100" => -- 1Hz
mdelay := 60;
CKCPUi <= CK1i;
when "1101" => -- 0.5Hz
mdelay := 60;
CKCPUi <= CK0_5i;
when "1110" => -- 0.2Hz
mdelay := 60;
CKCPUi <= CK0_2i;
when "1111" => -- 0.1Hz
mdelay := 60;
CKCPUi <= CK0_1i;
end case;
end if;
-- Form the video frequency according to the user selection.
--
case CONFIG(VIDSPEED) is
when "000" => -- 8MHz
CKVIDEOi <= CK8Mi;
when "001" => -- 16MHz
CKVIDEOi <= CK16Mi;
when "010" => -- 8.8672375MHz
CKVIDEOi <= CK8M8i;
when "011" => -- 17.734475MHz
CKVIDEOi <= CK17M7i;
when "100" | "101" | "110" | "111" => -- Unassigned default to 8MHz
CKVIDEOi <= CK8Mi;
end case;
-- Form the RTC frequency according to the user selection.
--
case CONFIG(RTCSPEED) is
when "01" => -- 31,250KHz
CKRTCi <= CK31250i;
when "10" => -- 15.611KHz
CKRTCi <= CK15611i;
when "00" | "11" => -- 31.5KHz
CKRTCi <= CK31500i;
end case;
-- Form the peripheral frequency according to the user selection.
--
case CONFIG(PERSPEED) is
when "00" | "01" | "10" | "11" =>
CKPERIPHi <= CK2Mi;
end case;
-- Form the sound frequency according to the user selection.
--
case CONFIG(SNDSPEED) is
when "01" => -- 895K
CKSOUNDi <= CK895Ki;
when "00" | "10" | "11" =>
CKSOUNDi <= CK2Mi;
end case;
-- Sampling frequency of signals, typically used to drive LED outputs but could easily be read by an oscilloscope.
--
case DEBUG(SMPFREQ) is
when "0000" => -- Use normal cpu frequency.
CKLEDSi <= CKCPUi;
when "0001" => -- 1MHz
CKLEDSi <= CK1Mi;
when "0010" => -- 100KHz
CKLEDSi <= CK100Ki;
when "0011" => -- 10KHz
CKLEDSi <= CK10Ki;
when "0100" => -- 5KHz
CKLEDSi <= CK5Ki;
when "0101" => -- 1KHz
CKLEDSi <= CK1Ki;
when "0110" => -- 500Hz
CKLEDSi <= CK500i;
when "0111" => -- 100Hz
CKLEDSi <= CK100i;
when "1000" => -- 50Hz
CKLEDSi <= CK50i;
when "1001" => -- 10Hz
CKLEDSi <= CK10i;
when "1010" => -- 5Hz
CKLEDSi <= CK5i;
when "1011" => -- 2Hz
CKLEDSi <= CK2i;
when "1100" => -- 1Hz
CKLEDSi <= CK1i;
when "1101" => -- 0.5Hz
CKLEDSi <= CK0_5i;
when "1110" => -- 0.2Hz
CKLEDSi <= CK0_2i;
when "1111" => -- 0.1Hz
CKLEDSi <= CK0_1i;
end case;
end if;
end if;
-- Until the clock generator is programmed and locked to the initial
-- frequency as determined by mctrl, default to a fixed speed set.
--
if SYSFREQLOCKED = '0' then
CLKBUS(CKCPU) <= CK2Mi;
CLKBUS(CKMEM) <= CKMEMd(32);
CLKBUS(pkgs.clkgen_pkg.CKSYS) <= CK224Mi;
CLKBUS(CKHPS) <= CK32Mi;
CLKBUS(CKSOUND) <= CK2Mi;
CLKBUS(CKRTC) <= CK31500i;
CLKBUS(CKVIDEO) <= CK8Mi;
CLKBUS(CKPERIPH) <= CK2Mi;
CLKBUS(CKLEDS) <= CK100Ki;
CLKBUS(CKRESET) <= CK224Mi;
else
CLKBUS(CKCPU) <= CKCPUi; -- CPU clock.
CLKBUS(CKMEM) <= CKMEMd(mdelay); -- Synchronous Memory clock.
CLKBUS(pkgs.clkgen_pkg.CKSYS) <= CK224Mi; -- System clock.
CLKBUS(CKHPS) <= CK32Mi; -- HPS Sysyem clock.
CLKBUS(CKSOUND) <= CKSOUNDi; -- Clock for the sound generator,
CLKBUS(CKRTC) <= CKRTCi; -- Clock for the RTC generator,
CLKBUS(CKVIDEO) <= CKVIDEOi; -- Video base clock.
CLKBUS(CKPERIPH) <= CKPERIPHi; -- Peripheral base clock.
CLKBUS(CKLEDS) <= CKLEDSi; -- Output sampling base frequency.
CLKBUS(CKRESET) <= CK224Mi;
--
end if;
end process;
end RTL;

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---------------------------------------------------------------------------------------------------------
--
-- Name: dpram.vhd
-- Created: July 2018
-- Author(s): Altera/Intel - refactored by Philip Smart
-- Description: Dual Port RAM as provided by Altera in the Megafunctions suite.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
widthad_b : natural;
width_b : natural := 8;
-- clock_en_a : string := "NORMAL";
-- clock_en_b : string := "NORMAL";
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
clock_a : IN STD_LOGIC;
clocken_a : IN STD_LOGIC := '1';
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
clock_b : IN STD_LOGIC;
clocken_b : IN STD_LOGIC := '1';
address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
wren_b : IN STD_LOGIC := '1';
q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
clocken0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
clock1 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
wren_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_b-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_b,
operation_mode => "BIDIR_DUAL_PORT",
--operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_b,
width_a => width_a,
width_b => width_b,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clock0 => clock_a,
clocken0 => clocken_a,
address_a => address_a,
data_a => data_a,
wren_a => wren_a,
q_a => sub_wire0,
clock1 => clock_b,
clocken1 => clocken_b,
address_b => address_b,
wren_b => wren_b,
data_b => data_b,
q_b => sub_wire1
);
END SYN;

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---------------------------------------------------------------------------------------------------------
--
-- Name: dprom.vhd
-- Created: July 2018
-- Author(s): Altera/Intel - refactored by Philip Smart
-- Description: Dual Port ROM as provided by Altera in the Megafunctions suite.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_b : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_b : IN STD_LOGIC;
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dprom;
ARCHITECTURE SYN OF dprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock1 : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
--operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
clock0 => clock_a,
data_a => data_a,
wren_a => wren_a,
q_a => sub_wire0,
address_b => address_b,
clock1 => clock_b,
data_b => data_b,
wren_b => wren_b,
q_b => sub_wire1
);
END SYN;

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---------------------------------------------------------------------------------------------------------
--
-- Name: counter0.vhd
-- Created: July 2018
-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart
-- Description: Sharp MZ series i8253 PIT - Counter 0
-- This module emulates Counter 0 of the Intel i8253 Programmable Interval Timer.
--
-- Credits:
-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module refactored and updated for this emulation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter0 is
Port (
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WRM : in std_logic;
WRD : in std_logic;
KCLK : in std_logic;
CLK : in std_logic;
GATE : in std_logic;
POUT : out std_logic
);
end counter0;
architecture Behavioral of counter0 is
--
-- counter
--
signal CREG : std_logic_vector(15 downto 0);
--
-- initialize
--
signal INIV : std_logic_vector(15 downto 0);
signal RL : std_logic_vector(1 downto 0);
signal PO : std_logic;
signal UL : std_logic;
signal NEWM : std_logic;
--
-- count control
--
signal CEN : std_logic;
signal GT : std_logic;
begin
-- Default for unused bus.
DO <= "00000000";
--
-- Counter access mode
--
process( KCLK, WRM ) begin
if( KCLK'event and KCLK='1' and WRM='0' ) then
RL<=DI(5 downto 4);
end if;
end process;
--
-- Counter initialize
--
process( KCLK, WRD, WRM ) begin
if( KCLK'event and KCLK='1' ) then
if( WRM='0' ) then
NEWM<='1';
UL<='0';
elsif( WRD='0' ) then
if( RL="01" ) then
INIV(7 downto 0)<=DI;
NEWM<='0';
elsif( RL="10" ) then
INIV(15 downto 8)<=DI;
NEWM<='0';
elsif( RL="11" ) then
if( UL='0' ) then
INIV(7 downto 0)<=DI;
UL<='1';
else
INIV(15 downto 8)<=DI;
UL<='0';
NEWM<='0';
end if;
end if;
end if;
end if;
end process;
--
-- Count enable
--
CEN<='1' when NEWM='0' and GATE='1' else '0';
--
-- Count (mode 3)
--
process( CLK, WRM, DI(3 downto 1) ) begin
if( CLK'event and CLK='1' ) then
GT<=GATE;
if( WRM='0' ) then
case DI(3 downto 1) is
when "000" => PO<='0';
when others => PO<='1';
end case;
elsif( (GT='0' and GATE='1') or CREG=2 ) then
CREG<=INIV;
PO<=not PO;
elsif( CEN='1' ) then
if( CREG(0)='1' ) then
if( PO='1' ) then
CREG<=CREG-3;
else
CREG<=CREG-1;
end if;
else
CREG<=CREG-2;
end if;
end if;
end if;
end process;
POUT<=PO;
end Behavioral;

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---------------------------------------------------------------------------------------------------------
--
-- Name: counter1.vhd
-- Created: July 2018
-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart
-- Description: Sharp MZ series i8253 PIT - Counter 1
-- This module emulates Counter 1 of the Intel i8253 Programmable Interval Timer.
--
-- Credits:
-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module refactored and updated for this emulation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter1 is
Port (
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WRM : in std_logic;
WRD : in std_logic;
KCLK : in std_logic;
CLK : in std_logic;
GATE : in std_logic;
POUT : out std_logic
);
end counter1;
architecture Behavioral of counter1 is
-- counter
--
signal CREG : std_logic_vector(15 downto 0);
--
-- initialize
--
signal INIV : std_logic_vector(15 downto 0);
signal RL : std_logic_vector(1 downto 0);
signal PO : std_logic;
signal UL : std_logic;
signal NEWM : std_logic;
--
-- count control
--
signal CEN : std_logic;
signal GT : std_logic;
begin
-- Default for unused bus.
DO <= "00000000";
--
-- Counter access mode
--
process( KCLK, WRM ) begin
if( KCLK'event and KCLK='1' and WRM='0' ) then
RL<=DI(5 downto 4);
end if;
end process;
--
-- Counter initialize
--
process( KCLK ) begin
if( KCLK'event and KCLK='1' ) then
if( WRM='0' ) then
NEWM<='1';
UL<='0';
elsif( WRD='0' ) then
if( RL="01" ) then
INIV(7 downto 0)<=DI;
NEWM<='0';
elsif( RL="10" ) then
INIV(15 downto 8)<=DI;
NEWM<='0';
elsif( RL="11" ) then
if( UL='0' ) then
INIV(7 downto 0)<=DI;
UL<='1';
else
INIV(15 downto 8)<=DI;
UL<='0';
NEWM<='0';
end if;
end if;
end if;
end if;
end process;
--
-- Count enable
--
CEN<='1' when NEWM='0' and GATE='1' else '0';
--
-- Count (mode 2)
--
process( CLK ) begin
if( CLK'event and CLK='0' ) then
GT<=GATE;
if( WRM='0' ) then
PO<='1';
elsif( (GT='0' and GATE='1') or CREG=1 ) then
CREG<=INIV;
PO<='1';
elsif( CREG=2 ) then
PO<='0';
CREG<=CREG-1;
elsif( CEN='1' ) then
CREG<=CREG-1;
end if;
end if;
end process;
POUT<=PO when GATE='1' else '1';
end Behavioral;

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--
-- counter2.vhd
---------------------------------------------------------------------------------------------------------
--
-- Name: counter2.vhd
-- Created: July 2018
-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart
-- Description: Sharp MZ series i8253 PIT - Counter 2
-- This module emulates Counter 2 of the Intel i8253 Programmable Interval Timer.
--
-- Credits:
-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module refactored and updated for this emulation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter2 is
Port (
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WRD : in std_logic;
WRM : in std_logic;
KCLK : in std_logic;
RD : in std_logic;
CLK : in std_logic;
GATE : in std_logic;
POUT : out std_logic
);
end counter2;
architecture Behavioral of counter2 is
--
-- counter
--
signal CREG : std_logic_vector(15 downto 0);
--
-- initialize and read out
--
signal INIV : std_logic_vector(15 downto 0);
signal RL : std_logic_vector(1 downto 0);
signal WUL : std_logic;
signal RUL : std_logic;
--
-- count control
--
signal PO : std_logic;
signal CD : std_logic_vector(15 downto 0);
signal DTEN : std_logic;
signal CEN : std_logic;
signal LEN : std_logic;
signal LEN_S : std_logic;
begin
--
-- Counter latch
--
process( KCLK, WRM ) begin
if( KCLK'event and KCLK='1' and WRM='0' ) then
if( DI(5 downto 4)="00" ) then
CD<=CREG;
else
RL<=DI(5 downto 4);
end if;
end if;
end process;
--
-- Initialize
--
process( KCLK, WRD, WRM, DI(5 downto 4) ) begin
if( KCLK'event and KCLK='1' ) then
if( WRM='0' ) then
if( DI(5 downto 4)/="00" ) then
WUL<='0';
end if;
elsif( WRD='0' ) then
if( RL="01" ) then
INIV(7 downto 0)<=DI;
LEN<='1';
CEN<='1';
elsif( RL="10" ) then
INIV(15 downto 8)<=DI;
LEN<='1';
CEN<='1';
elsif( RL="11" ) then
if( WUL='0' ) then
INIV(7 downto 0)<=DI;
WUL<='1';
LEN<='0';
CEN<='0';
else
INIV(15 downto 8)<=DI;
WUL<='0';
LEN<='1';
CEN<='1';
end if;
end if;
else
LEN<='0';
end if;
end if;
end process;
--
-- Read control
--
process( RD, WRM, DI(5 downto 4) ) begin
if( WRM='0' ) then
if( DI(5 downto 4)="00" ) then
DTEN<='1';
else
RUL<='0';
end if;
elsif( RD'event and RD='1' ) then
RUL<=not RUL;
if( DTEN='1' and RUL='1' ) then
DTEN<='0';
end if;
end if;
end process;
DO<=CD(7 downto 0) when RUL='0' and DTEN='1' else
CD(15 downto 8) when RUL='1' and DTEN='1' else
CREG(7 downto 0) when RUL='0' and DTEN='0' else
CREG(15 downto 8) when RUL='1' and DTEN='0' else (others=>'1');
--
-- Count (mode 0)
--
process( CLK, WRM, WRD, DI(5 downto 4), RL, LEN, WUL ) begin
if LEN='1' then
LEN_S<='1';
PO<='0';
elsif CLK'event and CLK='0' then
if WRM='0' then
if DI(5 downto 4)/="00" then
PO<='0';
end if;
elsif GATE='1' and CEN='1' then
if CREG=1 then
PO<='1';
end if;
if LEN_S='1' then
CREG<=INIV;
LEN_S<='0';
else
CREG<=CREG-1;
end if;
end if;
end if;
end process;
POUT<=PO;
end Behavioral;

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---------------------------------------------------------------------------------------------------------
--
-- Name: i8253.vhd
-- Created: July 2018
-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart
-- Description: Sharp MZ series i8253 PIT
-- This module emulates the Intel i8253 Programmable Interval Timer.
--
-- Credits:
-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module refactored and updated for this emulation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i8253 is
Port (
RST : in std_logic;
CLK : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end i8253;
architecture Behavioral of i8253 is
signal WRD0 : std_logic;
signal WRD1 : std_logic;
signal WRD2 : std_logic;
signal WRM0 : std_logic;
signal WRM1 : std_logic;
signal WRM2 : std_logic;
--signal RD0 : std_logic;
signal RD1 : std_logic;
signal RD2 : std_logic;
signal DO0 : std_logic_vector(7 downto 0);
signal DO1 : std_logic_vector(7 downto 0);
signal DO2 : std_logic_vector(7 downto 0);
component counter0
Port (
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WRD : in std_logic;
WRM : in std_logic;
KCLK : in std_logic;
CLK : in std_logic;
GATE : in std_logic;
POUT : out std_logic
);
end component;
component counter1
Port (
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WRD : in std_logic;
WRM : in std_logic;
KCLK : in std_logic;
CLK : in std_logic;
GATE : in std_logic;
POUT : out std_logic
);
end component;
component counter2
Port (
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WRD : in std_logic;
WRM : in std_logic;
KCLK : in std_logic;
RD : in std_logic;
CLK : in std_logic;
GATE : in std_logic;
POUT : out std_logic
);
end component;
begin
WRD0 <= WR_n when CS_n='0' and A="00" else '1';
WRD1 <= WR_n when CS_n='0' and A="01" else '1';
WRD2 <= WR_n when CS_n='0' and A="10" else '1';
WRM0 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="00" else '1';
WRM1 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="01" else '1';
WRM2 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="10" else '1';
-- RD0 <= RD_n when CS_n='0' and A="00" else '1';
RD1 <= RD_n when CS_n='0' and A="01" else '1';
RD2 <= RD_n when CS_n='0' and A="10" else '1';
DO <= DO0 when CS_n='0' and A="00" else
DO1 when CS_n='0' and A="01" else
DO2 when CS_n='0' and A="10" else (others=>'1');
CTR0 : counter0 port map (
DI => DI,
DO => DO0,
WRD => WRD0,
WRM => WRM0,
KCLK => CLK,
CLK => CLK0,
GATE => GATE0,
POUT => OUT0
);
CTR1 : counter1 port map (
DI => DI,
DO => DO1,
WRD => WRD1,
WRM => WRM1,
KCLK => CLK,
CLK => CLK1,
GATE => GATE1,
POUT => OUT1
);
CTR2 : counter2 port map (
DI => DI,
DO => DO2,
WRD => WRD2,
WRM => WRM2,
KCLK => CLK,
RD => RD2,
CLK => CLK2,
GATE => GATE2,
POUT => OUT2
);
end Behavioral;

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---------------------------------------------------------------------------------------------------------
--
-- Name: i8255.vhd
-- Created: Feb 2007
-- Author(s): MikeJ, Refactored and ported for this emulation by Philip Smart
-- Description: Sharp MZ series i8255 PPI
-- This module emulates the Intel i8255 Programmable Peripheral Interface chip.
--
-- Credits:
-- Copyright: (c) MikeJ - Feb 2007
--
-- History: July 2018 - Initial module refactored and updated for this emulation.
--
---------------------------------------------------------------------------------------------------------
--
-- Original copyright notice below:-
--
-- A simulation model of i8255 PIA
-- Copyright (c) MikeJ - Feb 2007
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
---------------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity i8255 is
port (
RESET : in std_logic;
CLK : in std_logic;
ENA : in std_logic; -- (CPU) clk enable
ADDR : in std_logic_vector(1 downto 0); -- A1-A0
DI : in std_logic_vector(7 downto 0); -- D7-D0
DO : out std_logic_vector(7 downto 0);
-- DO_OE_n : out std_logic;
CS_n : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
PA_I : in std_logic_vector(7 downto 0);
PA_O : out std_logic_vector(7 downto 0);
PA_O_OE_n : out std_logic_vector(7 downto 0);
PB_I : in std_logic_vector(7 downto 0);
PB_O : out std_logic_vector(7 downto 0);
PB_O_OE_n : out std_logic_vector(7 downto 0);
PC_I : in std_logic_vector(7 downto 0);
PC_O : out std_logic_vector(7 downto 0);
PC_O_OE_n : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of i8255 is
-- registers
signal bit_mask : std_logic_vector(7 downto 0);
signal r_porta : std_logic_vector(7 downto 0);
signal r_portb : std_logic_vector(7 downto 0);
signal r_portc : std_logic_vector(7 downto 0);
signal r_control : std_logic_vector(7 downto 0);
--
signal porta_we : std_logic;
signal portb_we : std_logic;
signal porta_re : std_logic;
signal portb_re : std_logic;
--
signal porta_we_t1 : std_logic;
signal portb_we_t1 : std_logic;
signal porta_re_t1 : std_logic;
signal portb_re_t1 : std_logic;
--
signal porta_we_rising : boolean;
signal portb_we_rising : boolean;
signal porta_re_rising : boolean;
signal portb_re_rising : boolean;
--
signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper
signal groupb_mode : std_logic; -- port b/c lower
--
signal porta_read : std_logic_vector(7 downto 0);
signal portb_read : std_logic_vector(7 downto 0);
signal portc_read : std_logic_vector(7 downto 0);
signal control_read : std_logic_vector(7 downto 0);
signal mode_clear : std_logic;
--
signal a_inte1 : std_logic;
signal a_inte2 : std_logic;
signal b_inte : std_logic;
--
signal a_intr : std_logic;
signal a_obf_l : std_logic;
signal a_ibf : std_logic;
signal a_ack_l : std_logic;
signal a_stb_l : std_logic;
signal a_ack_l_t1 : std_logic;
signal a_stb_l_t1 : std_logic;
--
signal b_intr : std_logic;
signal b_obf_l : std_logic;
signal b_ibf : std_logic;
signal b_ack_l : std_logic;
signal b_stb_l : std_logic;
signal b_ack_l_t1 : std_logic;
signal b_stb_l_t1 : std_logic;
--
signal a_ack_l_rising : boolean;
signal a_stb_l_rising : boolean;
signal b_ack_l_rising : boolean;
signal b_stb_l_rising : boolean;
--
signal porta_ipreg : std_logic_vector(7 downto 0);
signal portb_ipreg : std_logic_vector(7 downto 0);
begin
--
-- mode 0 - basic input/output
-- mode 1 - strobed input/output
-- mode 2/3 - bi-directional bus
--
-- control word (write)
--
-- D7 mode set flag 1 = active
-- D6..5 GROUPA mode selection (mode 0,1,2)
-- D4 GROUPA porta 1 = input, 0 = output
-- D3 GROUPA portc upper 1 = input, 0 = output
-- D2 GROUPB mode selection (mode 0 ,1)
-- D1 GROUPB portb 1 = input, 0 = output
-- D0 GROUPB portc lower 1 = input, 0 = output
--
-- D7 bit set/reset 0 = active
-- D6..4 x
-- D3..1 bit select
-- d0 1 = set, 0 - reset
--
-- all output registers including status are reset when mode is changed
--1. Port A:
--All Modes: Output data is cleared, input data is not cleared.
--2. Port B:
--Mode 0: Output data is cleared, input data is not cleared.
--Mode 1 and 2: Both output and input data are cleared.
--3. Port C:
--Mode 0:Output data is cleared, input data is not cleared.
--Mode 1 and 2: IBF and INTR are cleared and OBF# is set.
--Outputs in Port C which are not used for handshaking or interrupt signals are cleared.
--Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled.
p_bit_mask : process(DI)
begin
bit_mask <= x"01";
case DI(3 downto 1) is
when "000" => bit_mask <= x"01";
when "001" => bit_mask <= x"02";
when "010" => bit_mask <= x"04";
when "011" => bit_mask <= x"08";
when "100" => bit_mask <= x"10";
when "101" => bit_mask <= x"20";
when "110" => bit_mask <= x"40";
when "111" => bit_mask <= x"80";
when others => null;
end case;
end process;
p_write_reg_reset : process(RESET, CLK)
variable r_portc_masked : std_logic_vector(7 downto 0);
variable r_portc_setclr : std_logic_vector(7 downto 0);
begin
if (RESET = '1') then
r_porta <= x"00";
r_portb <= x"00";
r_portc <= x"00";
r_control <= x"9B"; -- 10011011
mode_clear <= '1';
elsif rising_edge(CLK) then
r_portc_masked := (not bit_mask) and r_portc;
for i in 0 to 7 loop
r_portc_setclr(i) := bit_mask(i) and DI(0);
end loop;
if (ENA = '1') then
mode_clear <= '0';
if (CS_n = '0') and (WR_n = '0') then
case ADDR is
when "00" => r_porta <= DI;
when "01" => r_portb <= DI;
when "10" => r_portc <= DI;
when "11" => if (DI(7) = '0') then -- set/clr
r_portc <= r_portc_masked or r_portc_setclr;
else
--mode_clear <= '1';
--r_porta <= x"00";
--r_portb <= x"00"; -- clear port b input reg
--r_portc <= x"00"; -- clear control sigs
r_control <= DI; -- load new mode
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_decode_control : process(r_control)
begin
groupa_mode <= r_control(6 downto 5);
groupb_mode <= r_control(2);
end process;
--p_oe : process(CS_n, RD_n)
--begin
-- DO_OE_n <= '1';
-- if (CS_n = '0') and (RD_n = '0') then
-- DO_OE_n <= '0';
-- end if;
--end process;
p_read : process(ADDR , porta_read, portb_read, portc_read, control_read)
begin
DO <= x"00"; -- default
--if (CS_n = '0') and (RD_n = '0') then -- not required
case ADDR is
when "00" => DO <= porta_read;
when "01" => DO <= portb_read;
when "10" => DO <= portc_read;
when "11" => DO <= control_read;
when others => null;
end case;
--end if;
end process;
control_read(7) <= '1'; -- always 1
control_read(6 downto 0) <= r_control(6 downto 0);
p_rw_control : process(CS_n, RD_n, WR_n, ADDR )
begin
porta_we <= '0';
portb_we <= '0';
porta_re <= '0';
portb_re <= '0';
if (CS_n = '0') and (ADDR = "00") then
porta_we <= not WR_n;
porta_re <= not RD_n;
end if;
if (CS_n = '0') and (ADDR = "01") then
portb_we <= not WR_n;
portb_re <= not RD_n;
end if;
end process;
p_rw_control_reg : process
begin
wait until rising_edge(CLK);
if (ENA = '1') then
porta_we_t1 <= porta_we;
portb_we_t1 <= portb_we;
porta_re_t1 <= porta_re;
portb_re_t1 <= portb_re;
a_stb_l_t1 <= a_stb_l;
a_ack_l_t1 <= a_ack_l;
b_stb_l_t1 <= b_stb_l;
b_ack_l_t1 <= b_ack_l;
end if;
end process;
porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted
portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- "
porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted
portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- "
--
a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0');
a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0');
b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0');
b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0');
--
-- GROUP A
-- in mode 1
--
-- d4=1 (porta = input)
-- pc7,6 io (d3=1 input, d3=0 output)
-- pc5 output a_ibf
-- pc4 input a_stb_l
-- pc3 output a_intr
--
-- d4=0 (porta = output)
-- pc7 output a_obf_l
-- pc6 input a_ack_l
-- pc5,4 io (d3=1 input, d3=0 output)
-- pc3 output a_intr
--
-- GROUP B
-- in mode 1
-- d1=1 (portb = input)
-- pc2 input b_stb_l
-- pc1 output b_ibf
-- pc0 output b_intr
--
-- d1=0 (portb = output)
-- pc2 input b_ack_l
-- pc1 output b_obf_l
-- pc0 output b_intr
-- WHEN AN INPUT
--
-- stb_l a low on this input latches input data
-- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L
-- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L
-- inte A controlled by bit/set PC4
-- inte B controlled by bit/set PC2
-- WHEN AN OUTPUT
--
-- obf_l output will go low when cpu has written data
-- ack_l input - a low on this clears obf_l
-- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L
-- inte A controlled by bit/set PC6
-- inte B controlled by bit/set PC2
-- GROUP A
-- in mode 2
--
-- porta = IO
--
-- control bits 2..0 still control groupb/c lower 2..0
--
--
-- PC7 output a_obf
-- PC6 input a_ack_l
-- PC5 output a_ibf
-- PC4 input a_stb_l
-- PC3 is still interrupt out
p_control_flags : process(RESET, CLK)
variable we : boolean;
variable set1 : boolean;
variable set2 : boolean;
begin
if (RESET = '1') then
a_obf_l <= '1';
a_inte1 <= '0';
a_ibf <= '0';
a_inte2 <= '0';
a_intr <= '0';
--
b_inte <= '0';
b_obf_l <= '1';
b_ibf <= '0';
b_intr <= '0';
elsif rising_edge(CLK) then
we := (CS_n = '0') and (WR_n = '0') and (ADDR = "11") and (DI(7) = '0');
if (ENA = '1') then
if (mode_clear = '1') then
a_obf_l <= '1';
a_inte1 <= '0';
a_ibf <= '0';
a_inte2 <= '0';
a_intr <= '0';
--
b_inte <= '0';
b_obf_l <= '1';
b_ibf <= '0';
b_intr <= '0';
else
if (bit_mask(7) = '1') and we then
a_obf_l <= DI(0);
else
if porta_we_rising then
a_obf_l <= '0';
elsif (a_ack_l = '0') then
a_obf_l <= '1';
end if;
end if;
--
if (bit_mask(6) = '1') and we then a_inte1 <= DI(0); end if; -- bus set when mode1 & input?
--
if (bit_mask(5) = '1') and we then
a_ibf <= DI(0);
else
if porta_re_rising then
a_ibf <= '0';
elsif (a_stb_l = '0') then
a_ibf <= '1';
end if;
end if;
--
if (bit_mask(4) = '1') and we then a_inte2 <= DI(0); end if; -- bus set when mode1 & output?
--
set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1');
set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1');
--
if (bit_mask(3) = '1') and we then
a_intr <= DI(0);
else
if (groupa_mode(1) = '1') then
if (porta_we = '1') or (porta_re = '1') then
a_intr <= '0';
elsif set1 or set2 then
a_intr <= '1';
end if;
else
if (r_control(4) = '0') then -- output
if (porta_we = '1') then -- falling ?
a_intr <= '0';
elsif set1 then
a_intr <= '1';
end if;
elsif (r_control(4) = '1') then -- input
if (porta_re = '1') then -- falling ?
a_intr <= '0';
elsif set2 then
a_intr <= '1';
end if;
end if;
end if;
end if;
--
if (bit_mask(2) = '1') and we then b_inte <= DI(0); end if; -- bus set?
if (bit_mask(1) = '1') and we then
b_obf_l <= DI(0);
else
if (r_control(1) = '0') then -- output
if portb_we_rising then
b_obf_l <= '0';
elsif (b_ack_l = '0') then
b_obf_l <= '1';
end if;
else
if portb_re_rising then
b_ibf <= '0';
elsif (b_stb_l = '0') then
b_ibf <= '1';
end if;
end if;
end if;
if (bit_mask(0) = '1') and we then
b_intr <= DI(0);
else
if (r_control(1) = '0') then -- output
if (portb_we = '1') then -- falling ?
b_intr <= '0';
elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then
b_intr <= '1';
end if;
else
if (portb_re = '1') then -- falling ?
b_intr <= '0';
elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then
b_intr <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_porta : process(r_porta, r_control, groupa_mode, PA_I, porta_ipreg, a_ack_l)
begin
-- D4 GROUPA porta 1 = input, 0 = output
PA_O <= x"FF"; -- if not driven, float high
PA_O_OE_n <= x"FF";
porta_read <= x"00";
if (groupa_mode = "00") then -- simple io
if (r_control(4) = '0') then -- output
PA_O <= r_porta;
PA_O_OE_n <= x"00";
end if;
porta_read <= PA_I;
elsif (groupa_mode = "01") then -- strobed
if (r_control(4) = '0') then -- output
PA_O <= r_porta;
PA_O_OE_n <= x"00";
end if;
porta_read <= porta_ipreg;
else -- if (groupa_mode(1) = '1') then -- bi dir
if (a_ack_l = '0') then -- output enable
PA_O <= r_porta;
PA_O_OE_n <= x"00";
end if;
porta_read <= porta_ipreg; -- latched data
end if;
end process;
p_portb : process(r_portb, r_control, groupb_mode, PB_I, portb_ipreg)
begin
PB_O <= x"FF"; -- if not driven, float high
PB_O_OE_n <= x"FF";
portb_read <= x"00";
if (groupb_mode = '0') then -- simple io
if (r_control(1) = '0') then -- output
PB_O <= r_portb;
PB_O_OE_n <= x"00";
end if;
portb_read <= PB_I;
else -- strobed mode
if (r_control(1) = '0') then -- output
PB_O <= r_portb;
PB_O_OE_n <= x"00";
end if;
portb_read <= portb_ipreg;
end if;
end process;
p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode,
a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr)
begin
PC_O <= x"FF"; -- if not driven, float high
PC_O_OE_n <= x"FF";
-- bits 7..4
if (groupa_mode = "00") then -- simple io
if (r_control(3) = '0') then -- output
PC_O (7 downto 4) <= r_portc(7 downto 4);
PC_O_OE_n(7 downto 4) <= x"0";
end if;
elsif (groupa_mode = "01") then -- mode1
if (r_control(4) = '0') then -- port a output
PC_O (7) <= a_obf_l;
PC_O_OE_n(7) <= '0';
-- 6 is ack_l input
if (r_control(3) = '0') then -- port c output
PC_O (5 downto 4) <= r_portc(5 downto 4);
PC_O_OE_n(5 downto 4) <= "00";
end if;
else -- port a input
if (r_control(3) = '0') then -- port c output
PC_O (7 downto 6) <= r_portc(7 downto 6);
PC_O_OE_n(7 downto 6) <= "00";
end if;
PC_O (5) <= a_ibf;
PC_O_OE_n(5) <= '0';
-- 4 is stb_l input
end if;
else -- if (groupa_mode(1) = '1') then -- mode2
PC_O (7) <= a_obf_l;
PC_O_OE_n(7) <= '0';
-- 6 is ack_l input
PC_O (5) <= a_ibf;
PC_O_OE_n(5) <= '0';
-- 4 is stb_l input
end if;
-- bit 3 (controlled by group a)
if (groupa_mode = "00") then -- group a steals this bit
--if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this
if (r_control(0) = '0') then -- ouput (note, groupb control bit)
PC_O (3) <= r_portc(3);
PC_O_OE_n(3) <= '0';
end if;
--
else -- stolen
PC_O (3) <= a_intr;
PC_O_OE_n(3) <= '0';
end if;
-- bits 2..0
if (groupb_mode = '0') then -- simple io
if (r_control(0) = '0') then -- output
PC_O (2 downto 0) <= r_portc(2 downto 0);
PC_O_OE_n(2 downto 0) <= "000";
end if;
else
-- mode 1
-- 2 is input
if (r_control(1) = '0') then -- output
PC_O (1) <= b_obf_l;
PC_O_OE_n(1) <= '0';
else -- input
PC_O (1) <= b_ibf;
PC_O_OE_n(1) <= '0';
end if;
PC_O (0) <= b_intr;
PC_O_OE_n(0) <= '0';
end if;
end process;
p_portc_in : process(r_portc, PC_I, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l,
a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr)
begin
portc_read <= x"00";
a_stb_l <= '1';
a_ack_l <= '1';
b_stb_l <= '1';
b_ack_l <= '1';
if (groupa_mode = "01") then -- mode1 or 2
if (r_control(4) = '0') then -- port a output
a_ack_l <= PC_I(6);
else -- port a input
a_stb_l <= PC_I(4);
end if;
elsif (groupa_mode(1) = '1') then -- mode 2
a_ack_l <= PC_I(6);
a_stb_l <= PC_I(4);
end if;
if (groupb_mode = '1') then
if (r_control(1) = '0') then -- output
b_ack_l <= PC_I(2);
else -- input
b_stb_l <= PC_I(2);
end if;
end if;
if (groupa_mode = "00") then -- simple io
portc_read(7 downto 3) <= PC_I(7 downto 3);
elsif (groupa_mode = "01") then
if (r_control(4) = '0') then -- port a output
portc_read(7 downto 3) <= a_obf_l & a_inte1 & PC_I(5 downto 4) & a_intr;
else -- input
portc_read(7 downto 3) <= PC_I(7 downto 6) & a_ibf & a_inte2 & a_intr;
end if;
else -- mode 2
portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr;
end if;
if (groupb_mode = '0') then -- simple io
portc_read(2 downto 0) <= PC_I(2 downto 0);
else
if (r_control(1) = '0') then -- output
portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr;
else -- input
portc_read(2 downto 0) <= b_inte & b_ibf & b_intr;
end if;
end if;
end process;
p_ipreg : process
begin
wait until rising_edge(CLK);
-- pc4 input a_stb_l
-- pc2 input b_stb_l
if (ENA = '1') then
if (a_stb_l = '0') then
porta_ipreg <= PA_I;
end if;
if (mode_clear = '1') then
portb_ipreg <= (others => '0');
elsif (b_stb_l = '0') then
portb_ipreg <= PB_I;
end if;
end if;
end process;
end architecture RTL;

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---------------------------------------------------------------------------------------------------------
--
-- Name: keymatrix.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: Keyboard module to convert PS2 key codes into Sharp scan matrix key connections.
-- For each scan output (10 lines) sent by the Sharp, an 8bit response is read in
-- and the bits set indicate keys pressed. This allows for multiple keys to be pressed
-- at the same time. The PS2 scan code is mapped via a rom and the output is used to drive
-- the data in lines of the 8255.
--
-- Credits: Nibbles Lab (c) 2005-2012
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written, originally based on the Nibbles Lab code but
-- rewritten to match the overall design of this emulation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity keymatrix is
Port (
RST_n : in std_logic;
-- i8255
PA : in std_logic_vector(3 downto 0);
PB : out std_logic_vector(7 downto 0);
STALL : in std_logic;
-- PS/2 Keyboard Data
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- Clock signals used by this module.
CLKBUS : in std_logic_vector(CLKBUS_WIDTH);
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
);
end keymatrix;
architecture Behavioral of keymatrix is
--
-- prefix flag
--
signal FLGF0 : std_logic;
signal FLGE0 : std_logic;
--
-- MZ-series matrix registers
--
signal SCAN00 : std_logic_vector(7 downto 0);
signal SCAN01 : std_logic_vector(7 downto 0);
signal SCAN02 : std_logic_vector(7 downto 0);
signal SCAN03 : std_logic_vector(7 downto 0);
signal SCAN04 : std_logic_vector(7 downto 0);
signal SCAN05 : std_logic_vector(7 downto 0);
signal SCAN06 : std_logic_vector(7 downto 0);
signal SCAN07 : std_logic_vector(7 downto 0);
signal SCAN08 : std_logic_vector(7 downto 0);
signal SCAN09 : std_logic_vector(7 downto 0);
signal SCAN10 : std_logic_vector(7 downto 0);
signal SCAN11 : std_logic_vector(7 downto 0);
signal SCAN12 : std_logic_vector(7 downto 0);
signal SCAN13 : std_logic_vector(7 downto 0);
signal SCAN14 : std_logic_vector(7 downto 0);
signal SCANLL : std_logic_vector(7 downto 0);
--
-- Key code exchange table
--
signal MTEN : std_logic_vector(3 downto 0);
signal F_KBDT : std_logic_vector(7 downto 0);
signal MAP_DATA : std_logic_vector(7 downto 0);
signal MAP_ADDR : std_logic_vector(7 downto 0);
signal KEY_BANK : std_logic_vector(2 downto 0);
--
-- HPS access
--
signal IOCTL_KEYMAP_WEN : std_logic;
signal IOCTL_DIN_KEYMAP : std_logic_vector(7 downto 0); -- HPS Data to be read into HPS.
signal KEY_EXTENDED : std_logic;
signal KEY_FLAG : std_logic;
signal KEY_PRESS : std_logic;
signal KEY_VALID : std_logic;
--
-- Components
--
component dprom
GENERIC (
init_file : string;
widthad_a : natural;
width_a : natural
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
-- data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-- wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
-- 0 = MZ80K KEYMAP = 256Bytes -> 0000:00ff 0000 bytes padding
-- 1 = MZ80C KEYMAP = 256Bytes -> 0100:01ff 0000 bytes padding
-- 2 = MZ1200 KEYMAP = 256Bytes -> 0200:02ff 0000 bytes padding
-- 3 = MZ80A KEYMAP = 256Bytes -> 0300:03ff 0000 bytes padding
-- 4 = MZ700 KEYMAP = 256Bytes -> 0400:04ff 0000 bytes padding
-- 5 = MZ80B KEYMAP = 256Bytes -> 0500:05ff 0000 bytes padding
MAP0 : dprom
GENERIC MAP (
--init_file => "./mif/key_80k_80b.mif",
init_file => "./mif/combined_keymap.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
clock_a => CLKBUS(CKCPU),
address_a => KEY_BANK & F_KBDT,
-- data_a => IOCTL_DOUT(7 DOWNTO 0),
-- wren_a =>
q_a => MAP_DATA,
clock_b => IOCTL_CLK,
address_b => IOCTL_ADDR(10 DOWNTO 0),
data_b => IOCTL_DOUT(7 DOWNTO 0),
wren_b => IOCTL_KEYMAP_WEN,
q_b => IOCTL_DIN_KEYMAP
);
-- Store changes to the key valid flag in a flip flop.
process( CLKBUS(CKCPU) ) begin
if rising_edge(CLKBUS(CKCPU)) then
KEY_FLAG <= PS2_KEY(10);
end if;
end process;
KEY_PRESS <= PS2_KEY(9);
KEY_EXTENDED <= PS2_KEY(8);
KEY_VALID <= '1' when KEY_FLAG /= PS2_KEY(10) else '0';
KEY_BANK <= "000" when CONFIG(MZ80K) = '1' else -- Key map for MZ80K
"001" when CONFIG(MZ80C) = '1' else -- Key map for MZ80C
"010" when CONFIG(MZ1200) = '1' else -- Key map for MZ1200
"011" when CONFIG(MZ80A) = '1' else -- Key map for MZ80A
"100" when CONFIG(MZ700) = '1' else -- Key map for MZ700
"101" when CONFIG(MZ800) = '1' else -- Key map for MZ800
"110" when CONFIG(MZ80B) = '1' else -- Key map for MZ80B
"111" when CONFIG(MZ2000) = '1'; -- Key map for MZ2000
--
-- Convert
--
process( RST_n, CLKBUS(CKCPU) ) begin
if RST_n = '0' then
SCAN00 <= (others=>'0');
SCAN01 <= (others=>'0');
SCAN02 <= (others=>'0');
SCAN03 <= (others=>'0');
SCAN04 <= (others=>'0');
SCAN05 <= (others=>'0');
SCAN06 <= (others=>'0');
SCAN07 <= (others=>'0');
SCAN08 <= (others=>'0');
SCAN09 <= (others=>'0');
SCAN10 <= (others=>'0');
SCAN11 <= (others=>'0');
SCAN12 <= (others=>'0');
SCAN13 <= (others=>'0');
SCAN14 <= (others=>'0');
FLGF0 <= '0';
FLGE0 <= '0';
MTEN <= (others=>'0');
MAP_ADDR <= (others=>'1');
elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then
MTEN <= MTEN(2 downto 0) & KEY_VALID;
if KEY_VALID='1' then
if(KEY_EXTENDED='1') then
FLGE0 <= '1';
end if;
if(KEY_PRESS='0') then
FLGF0 <= '1';
end if;
if(PS2_KEY(7 downto 0) = X"AA" ) then
F_KBDT <= X"EF";
else
F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0';
end if;
end if;
if MTEN(3)='1' then
case MAP_DATA(7 downto 4) is
when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0;
when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
end case;
end if;
end if;
end process;
PA_L : for I in 0 to 7 generate
SCANLL(I) <= SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I) or
SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I) or
SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
end generate PA_L;
--
-- response from key access
--
PB <= (not SCANLL) when STALL='0' and CONFIG(MZ_B)='1' else
(not SCAN00) when PA="0000" else
(not SCAN01) when PA="0001" else
(not SCAN02) when PA="0010" else
(not SCAN03) when PA="0011" else
(not SCAN04) when PA="0100" else
(not SCAN05) when PA="0101" else
(not SCAN06) when PA="0110" else
(not SCAN07) when PA="0111" else
(not SCAN08) when PA="1000" else
(not SCAN09) when PA="1001" else
(not SCAN10) when PA="1010" else
(not SCAN11) when PA="1011" else
(not SCAN12) when PA="1100" else
(not SCAN13) when PA="1101" else (others=>'1');
--
-- HPS access to reload keymap.
--
IOCTL_KEYMAP_WEN <= '1' when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_WR = '1'
else '0';
IOCTL_DIN <= X"00" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_RD = '1'
else
(others=>'0');
end Behavioral;

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---------------------------------------------------------------------------------------------------------
--
-- Name: mctrl.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Programmable Machine Control logic.
-- This module forms the Programmable control of the emulation along with sync reset
-- management.
-- A set of 16 addressable registers is presented on the external IOCTL interface.
-- Each register controls an aspect of the emulation, such as video mode or cpu speed.
--
-- Reset to all components is managed by this module, taking cold, warm and internally
-- generated reset signals and creating a unified system reset output.
--
-- Please see the docs/SharpMZ_Notes.xlsx spreadsheet for details on these registers
-- and the values they take.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: July 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
package mctrl_pkg is
-- Config Bus
--
subtype CONFIG_WIDTH is integer range 58 downto 0;
-- Mode signals indicating type of machine we are emulating.
--
constant MZ80K : integer := 0; -- Machine is an MZ80K
constant MZ80C : integer := 1; -- Machine is an MZ80C
constant MZ1200 : integer := 2; -- Machine is an MZ1200
constant MZ80A : integer := 3; -- Machine is an MZ80A
constant MZ700 : integer := 4; -- Machine is an MZ700
constant MZ800 : integer := 5; -- Machine is an MZ800
constant MZ80B : integer := 6; -- Machine is an MZ80B
constant MZ2000 : integer := 7; -- Machine is an MZ2000
subtype CURRENTMACHINE is integer range 7 downto 0; -- Range of bits to indicate current machine, only 1 bit is set at a time.
constant MZ_KC : integer := 8; -- Machine is an MZ80K/MZ80C
constant MZ_A : integer := 9; -- Machine is an MZ1200/MZ80A
constant MZ_B : integer := 10; -- Machine is an MZ2000/MZ80B
constant MZ_80B : integer := 11; -- Machine is an MZ2000/MZ80B
constant MZ_80C : integer := 12; -- Machine is an MZ80K/MZ80C/MZ1200/MZ80A
-- Type of display to emulate.
--
constant NORMAL : integer := 13; -- Normal 40 x 25 character monochrome display.
constant NORMAL80 : integer := 14; -- Normal 80 x 25 character monochrome display.
constant COLOUR : integer := 15; -- Colour 40 x 25 character display.
constant COLOUR80 : integer := 16; -- Colour 80 x 25 character display.
-- Option Roms Enable (some machines by design dont have them, but this emulation allows them to be enabled if needed).
--
subtype USERROM is integer range 24 downto 17; -- User ROM E800 - EFFF enable per machine.
subtype FDCROM is integer range 32 downto 25; -- FDC ROM F000 - FFFF enable per machine.
-- Various configurable settings.
--
constant AUDIOSRC : integer := 33; -- Audio source, 0 = sound generator, 1 = tape audio.
subtype TURBO is integer range 36 downto 34; -- 2MHz/4MHz/8MHz/16MHz/32MHz switch (various).
subtype FASTTAPE is integer range 39 downto 37; -- Speed of tape read/write.
subtype BUTTONS is integer range 41 downto 40; -- Various external buttons, such as CMT play/record.
constant PCGRAM : integer := 42; -- PCG ROM(0) or RAM(1) based.
constant VRAMWAIT : integer := 43; -- Insert video wait states on CPU access as per original design.
constant VRAMDISABLE : integer := 44; -- Disable the Video RAM from display output.
constant GRAMDISABLE : integer := 45; -- Disable the graphics RAM from display output.
-- Derivative settings to program the clock generator.
--
subtype CPUSPEED is integer range 49 downto 46; -- Active CPU Speed.
subtype VIDSPEED is integer range 52 downto 50; -- Active Video Speed.
subtype PERSPEED is integer range 54 downto 53; -- Active Peripheral Speed.
subtype RTCSPEED is integer range 56 downto 55; -- Active RTC Speed.
subtype SNDSPEED is integer range 58 downto 57; -- Active Sound Speed.
-- CMT Bus
--
subtype CMTBUS_WIDTH is integer range 8 downto 0;
-- CMT Signals.
--
constant PLAY_READY : integer := 0; -- Tape play back buffer, 0 = empty, 1 = full.
constant PLAYING : integer := 1; -- Tape playback, 0 = stopped, 1 = in progress.
constant RECORD_READY : integer := 2; -- Tape record buffer full.
constant RECORDING : integer := 3; -- Tape recording, 0 = stopped, 1 = in progress.
constant ACTIVE : integer := 4; -- Tape transfer in progress, 0 = no activity, 1 = activity.
constant SENSE : integer := 5; -- Tape state Sense out.
constant WRITEBIT : integer := 6; -- Write bit to MZ.
constant READBIT : integer := 7; -- Receive bit from MZ.
constant MOTOR : integer := 8; -- Motor on/off.
-- Debug Bus
--
subtype DEBUG_WIDTH is integer range 15 downto 0;
-- Debugging signals.
--
subtype LEDS_BANK is integer range 2 downto 0;
subtype LEDS_SUBBANK is integer range 5 downto 3;
constant LEDS_ON : integer := 6;
constant ENABLED : integer := 7;
subtype SMPFREQ is integer range 11 downto 8;
subtype CPUFREQ is integer range 15 downto 12;
end mctrl_pkg;
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use pkgs.mctrl_pkg.all;
use pkgs.clkgen_pkg.all;
entity mctrl is
Port (
-- Clock signals used by this module.
CLKBUS : in std_logic_vector(CLKBUS_WIDTH);
-- Reset's
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
SYSTEM_RESET : out std_logic;
-- HPS Interface
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
-- Different operations modes.
CONFIG : out std_logic_vector(CONFIG_WIDTH);
-- Cassette magnetic tape signals.
CMTBUS : in std_logic_vector(CMTBUS_WIDTH);
-- Debug modes.
DEBUG : out std_logic_vector(DEBUG_WIDTH)
);
end mctrl;
architecture rtl of mctrl is
signal REGISTER_MODEL : std_logic_vector(7 downto 0) := "00000011";
signal REGISTER_DISPLAY : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CPU : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_AUDIO : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CMT : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CMT2 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_USERROM : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_FDCROM : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_8 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_9 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_10 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_11 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_12 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_13 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_DEBUG : std_logic_vector(7 downto 0) := "00001000";
signal REGISTER_DEBUG2 : std_logic_vector(7 downto 0) := "00000000";
signal delay : integer range 0 to 31;
signal REGISTER_RESET : std_logic;
begin
-- Synchronise the register update with the configuration signals according to the CPU clock.
--
process (COLD_RESET, CLKBUS(CKCPU))
begin
if COLD_RESET = '1' then
CONFIG(CONFIG_WIDTH) <= "00000000000000000000000000000000000000000000011001000001000";
elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='0' then
if REGISTER_MODEL(2 downto 0) = "000" then
CONFIG(MZ80K) <= '1';
else
CONFIG(MZ80K) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ80C) <= '1';
else
CONFIG(MZ80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" then
CONFIG(MZ1200) <= '1';
else
CONFIG(MZ1200) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ80A) <= '1';
else
CONFIG(MZ80A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(MZ700) <= '1';
else
CONFIG(MZ700) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "101" then
CONFIG(MZ800) <= '1';
else
CONFIG(MZ800) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(MZ80B) <= '1';
else
CONFIG(MZ80B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ2000) <= '1';
else
CONFIG(MZ2000) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "000" or REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ_KC) <= '1';
else
CONFIG(MZ_KC) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" or REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ_A) <= '1';
else
CONFIG(MZ_A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_B) <= '1';
else
CONFIG(MZ_B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(MZ_80C) <= '1';
else
CONFIG(MZ_80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_80B) <= '1';
else
CONFIG(MZ_80B) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "000" then
CONFIG(NORMAL) <= '1';
else
CONFIG(NORMAL) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "001" then
CONFIG(NORMAL80) <= '1';
else
CONFIG(NORMAL80) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "010" then
CONFIG(COLOUR) <= '1';
else
CONFIG(COLOUR) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "011" then
CONFIG(COLOUR80) <= '1';
else
CONFIG(COLOUR80) <= '0';
end if;
-- Convert CPU/CMT and Debug speed selections to actual CPU speed.
-- If debugging enabled and Debug freq not 0, select otherwise CMT if CMT is active, otherwise CPU speed as required.
--
-- Mapping could be made in software or 1-1 with the register, but setting restrictions and mapping in hw preferred, it
-- limits frequencies belonging to a given machine and makes it easier to change the frequency by NIOS or other controller if
-- MiSTer not used.
if CMTBUS(ACTIVE) = '1' then
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "1011"; -- 112MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
end if;
else
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "1011"; -- 112MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
end if;
end if;
-- Setup the video speed dependent upon model and graphics option.
--
-- MZ700/MZ800 Models.
if REGISTER_MODEL(2 downto 0) = "100" or REGISTER_MODEL(2 downto 0) = "101" then
-- Currently all modes default to one speed!
case REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8.8MHz clock, Mono and Colour.
when "000" | "010" | "100" | "101" | "110" | "111" =>
CONFIG(VIDSPEED) <= "010";
-- 80x25 mode requires 17.7MHz clock, Mono and Colour.
when "001" | "011" =>
CONFIG(VIDSPEED) <= "011";
end case;
-- MZ80K/C/1200/A
elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8MHz clock, Mono and Colour.
when "000" | "010" | "100" | "101" | "110" | "111" =>
CONFIG(VIDSPEED) <= "000";
-- 80x25 mode requires 16MHz clock, Mono and Colour.
when "001" | "011" =>
CONFIG(VIDSPEED) <= "001";
end case;
-- MZ80B or MZ2200
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
case REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 16MHz clock
when "000" | "001" | "010" | "011" | "100" | "101" | "110" | "111" =>
CONFIG(VIDSPEED) <= "001";
end case;
else
CONFIG(VIDSPEED) <= "000";
end if;
-- Setup RTC clock frequency dependent upon model.
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(RTCSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(RTCSPEED) <= "01";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(RTCSPEED) <= "10";
else
CONFIG(RTCSPEED) <= "00";
end if;
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(SNDSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(SNDSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(SNDSPEED) <= "01";
else
CONFIG(SNDSPEED) <= "00";
end if;
-- Setup the peripheral speed.
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(PERSPEED) <= "00";
else
CONFIG(PERSPEED) <= "00";
end if;
CONFIG(VRAMDISABLE)<= REGISTER_DISPLAY(4);
CONFIG(GRAMDISABLE)<= REGISTER_DISPLAY(5);
CONFIG(VRAMWAIT) <= REGISTER_DISPLAY(6);
CONFIG(PCGRAM) <= REGISTER_DISPLAY(7);
CONFIG(TURBO) <= REGISTER_CPU(2 downto 0);
CONFIG(FASTTAPE) <= REGISTER_CMT(2 downto 0);
CONFIG(BUTTONS) <= REGISTER_CMT(4 downto 3);
CONFIG(AUDIOSRC) <= REGISTER_AUDIO(0);
DEBUG(LEDS_BANK) <= REGISTER_DEBUG(2 downto 0);
DEBUG(LEDS_SUBBANK)<= REGISTER_DEBUG(5 downto 3);
DEBUG(LEDS_ON) <= REGISTER_DEBUG(6);
DEBUG(ENABLED) <= REGISTER_DEBUG(7);
DEBUG(SMPFREQ) <= REGISTER_DEBUG2(3 downto 0);
DEBUG(CPUFREQ) <= REGISTER_DEBUG2(7 downto 4);
end if;
end process;
-- Machine control is just a set of registers holding latched signals to configure machine components.
-- A write is made on address 100000000000000000000AAAA to read/write the registers, direction is via the
-- RD/WR signals.
-- AAAA specifies which register to read/write.
--
process (COLD_RESET, IOCTL_CLK)
begin
if COLD_RESET = '1' then
REGISTER_MODEL <= "00000011";
REGISTER_DISPLAY <= "00000000";
REGISTER_CPU <= "00000000";
REGISTER_AUDIO <= "00000000";
REGISTER_CMT <= "00000000";
REGISTER_CMT2 <= "00000000";
REGISTER_USERROM <= "00000000";
REGISTER_FDCROM <= "00000000";
REGISTER_8 <= "00000000";
REGISTER_9 <= "00000000";
REGISTER_10 <= "00000000";
REGISTER_11 <= "00000000";
REGISTER_12 <= "00000000";
REGISTER_13 <= "00000000";
REGISTER_DEBUG <= "00000000";
REGISTER_DEBUG2 <= "00000000";
REGISTER_RESET <= '1';
elsif IOCTL_CLK'event and IOCTL_CLK='1' then
-- For reading of registers, if no specific signal is required, just read back the output latch.
--
if IOCTL_ADDR(24) = '1' and IOCTL_RD = '1' then
case IOCTL_ADDR(3 downto 0) is
when "0000" => IOCTL_DIN <= X"00" & REGISTER_MODEL;
when "0001" => IOCTL_DIN <= X"00" & REGISTER_DISPLAY;
when "0010" => IOCTL_DIN <= X"00" & REGISTER_CPU;
when "0011" => IOCTL_DIN <= X"00" & REGISTER_AUDIO;
when "0100" => IOCTL_DIN <= X"00" & CMTBUS(7 downto 0);
when "0101" => IOCTL_DIN <= X"00" & REGISTER_CMT2(7 downto 1) & CMTBUS(8 downto 8);
when "0110" => IOCTL_DIN <= X"00" & REGISTER_USERROM;
when "0111" => IOCTL_DIN <= X"00" & REGISTER_FDCROM;
when "1000" => IOCTL_DIN <= X"00" & REGISTER_8;
when "1001" => IOCTL_DIN <= X"00" & REGISTER_9;
when "1010" => IOCTL_DIN <= X"00" & REGISTER_10;
when "1011" => IOCTL_DIN <= X"00" & REGISTER_11;
when "1100" => IOCTL_DIN <= X"00" & REGISTER_12;
when "1101" => IOCTL_DIN <= X"00" & REGISTER_13;
when "1110" => IOCTL_DIN <= X"00" & REGISTER_DEBUG;
when "1111" => IOCTL_DIN <= X"00" & REGISTER_DEBUG2;
end case;
end if;
-- For writing of registers, just assign the input bus to the register.
if IOCTL_ADDR(24) = '1' and IOCTL_WR = '1' then
case IOCTL_ADDR(3 downto 0) is
when "0000" =>
-- Assign the model data to the register and preset the default display hardware.
REGISTER_MODEL <= IOCTL_DOUT(7 downto 0);
case IOCTL_DOUT(2 downto 0) is
when "000" | "001" | "010" | "011" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "000";
when "100" | "101" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "010";
when "110" | "111" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "000";
end case;
REGISTER_RESET <= '1';
when "0001" =>
REGISTER_DISPLAY <= IOCTL_DOUT(7 downto 0);
-- Reset display if the mode changes.
if REGISTER_DISPLAY(2 downto 0) /= IOCTL_DOUT(2 downto 0) then
REGISTER_RESET <= '1';
end if;
when "0010" => REGISTER_CPU <= IOCTL_DOUT(7 downto 0);
when "0011" => REGISTER_AUDIO <= IOCTL_DOUT(7 downto 0);
when "0100" => REGISTER_CMT <= IOCTL_DOUT(7 downto 0);
when "0101" => REGISTER_CMT2 <= IOCTL_DOUT(7 downto 0);
when "0110" => REGISTER_USERROM <= IOCTL_DOUT(7 downto 0);
when "0111" => REGISTER_FDCROM <= IOCTL_DOUT(7 downto 0);
when "1000" => REGISTER_8 <= IOCTL_DOUT(7 downto 0);
when "1001" => REGISTER_9 <= IOCTL_DOUT(7 downto 0);
when "1010" => REGISTER_10 <= IOCTL_DOUT(7 downto 0);
when "1011" => REGISTER_11 <= IOCTL_DOUT(7 downto 0);
when "1100" => REGISTER_12 <= IOCTL_DOUT(7 downto 0);
when "1101" => REGISTER_13 <= IOCTL_DOUT(7 downto 0);
when "1110" => REGISTER_DEBUG <= IOCTL_DOUT(7 downto 0);
when "1111" => REGISTER_DEBUG2 <= IOCTL_DOUT(7 downto 0);
end case;
end if;
-- Only allow reset signal to be active for 1 clock cycle, just enough to trigger a system reset.
--
if REGISTER_RESET = '1' then
REGISTER_RESET <= '0';
end if;
end if;
end process;
-- System reset oneshot, triggered on COLD/WARM reset or a status change.
process (CLKBUS(CKRESET), COLD_RESET, WARM_RESET, REGISTER_RESET)
begin
if COLD_RESET = '1' or WARM_RESET = '1' or REGISTER_RESET = '1' then
if COLD_RESET = '1' then
delay <= 1;
elsif WARM_RESET = '1' then
delay <= 16;
else
delay <= 16;
end if;
elsif CLKBUS(CKRESET)'event and CLKBUS(CKRESET) = '1' then
if delay /= 0 then
delay <= delay + 1;
elsif delay >= 31 then
delay <= 0;
end if;
end if;
end process;
SYSTEM_RESET <= '1' when delay > 0
else '0';
end rtl;

337
common/pll.qip Normal file
View File

@@ -0,0 +1,337 @@
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTEy::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTEy::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQzNTA=::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::NTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTIgcHM=::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"

265
common/pll.v Normal file
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// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll.v
// Generated using ACDS version 17.0 598
//
// Customized by Philip Smart, July 2018 as it is not auto-generated.
// Set the module to have 1 output on which all frequencies used in the
// emulation are derived.
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
//output wire outclk_1, // outclk1.clk
//output wire outclk_2, // outclk2.clk
//output wire outclk_3, // outclk3.clk
//output wire outclk_4, // outclk4.clk
output wire locked // locked.export
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
//.outclk_1 (outclk_1), // outclk1.clk
//.outclk_2 (outclk_2), // outclk2.clk
//.outclk_3 (outclk_3), // outclk3.clk
//.outclk_4 (outclk_4), // outclk4.clk
.locked (locked) // locked.export
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="112.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="112.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="-4350" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="14.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="56.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="112.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v

4
common/pll/pll_0002.qip Normal file
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set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

107
common/pll/pll_0002.v Normal file
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// Customised by Philip Smart, July 2018.
// Set the input frequency to that of the Terasic DE10 Nano = 50MHz.
// Set the output frequency to 448MHz, all clocks used within the emulation are derived from this clock.
//
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
//output wire outclk_1,
// interface 'outclk2'
//output wire outclk_2,
// interface 'outclk3'
//output wire outclk_3,
// interface 'outclk4'
//output wire outclk_4,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
//.number_of_clocks(5),
.output_clock_frequency0("448 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
//.phase_shift1("0 ps"),
.phase_shift1("0 ps"),
//.phase_shift1("-0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
//.outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

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emu.sv Normal file
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//=======================================================================================================
//
// Name: emu.sv
// Created: June 2018
// Author(s): Philip Smart
// Description: Sharp MZ series compatible logic.
//
// This module is the main bridge between the emulator (sharpmz.vhd) and the MiSTer
// framework (hps_io.v/sys_top.v).
//
// Copyright: (C) 2018 Sorgelig
// (C) 2018 Philip Smart <philip.smart@net2net.org>
//
// History: June 2018 - Initial creation.
//
//=======================================================================================================
// This source file is free software: you can redistribute it and-or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//=======================================================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [44:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [7:0] VIDEO_ARX,
output [7:0] VIDEO_ARY,
// These video signals are defined in sys_top.v, via the video_mixer we output the video from the emulator onto these
// signals, which then get passed as follows:
// emu -> video_mixer -> vga_osd -> vga_out
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [7:0] LED_MB,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
// input TAPE_IN,
// SD-SPI
// output SD_SCK,
// output SD_MOSI,
// input SD_MISO,
// output SD_CS,
// input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE
//SDRAM interface with lower latency
// ,output SDRAM_CLK,
// output SDRAM_CKE,
// output [12:0] SDRAM_A,
// output [1:0] SDRAM_BA,
// inout [15:0] SDRAM_DQ,
// output SDRAM_DQML,
// output SDRAM_DQMH,
// output SDRAM_nCS,
// output SDRAM_nCAS,
// output SDRAM_nRAS,
// output SDRAM_nWE
);
//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign LED_USER = ioctl_download;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
wire [2:0] scale = status[4:2];
// Menu is handled in the MiSTer c++ program.
//
`include "build_id.v"
localparam CONF_STR =
{
"SHARP MZ SERIES;;",
"J,Fire;",
"V,v1.01.",`BUILD_DATE
};
///////////////// CLOCKS ////////////////////////
wire clk_sys;
///////////////// HPS ///////////////////////////
wire [31:0] status;
wire [1:0] buttons;
wire [10:0] ps2_key;
wire [24:0] ps2_mouse;
wire ioctl_download;
wire ioctl_upload;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire ioctl_rd;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] ioctl_din;
wire forced_scandoubler;
hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str(CONF_STR),
.buttons(buttons),
.status(status),
.forced_scandoubler(forced_scandoubler),
.ioctl_download(ioctl_download),
.ioctl_upload(ioctl_upload),
.ioctl_index(ioctl_index),
.ioctl_wr(ioctl_wr),
.ioctl_rd(ioctl_rd),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_din(ioctl_din),
.ioctl_wait(0),
.sd_conf(0),
.sd_ack_conf(),
//.ps2_kbd_led_use(0),
//.ps2_kbd_led_status(0),
.ps2_key(ps2_key),
.ps2_mouse(ps2_mouse)
// unused
//.joystick_0(),
//.joystick_1(),
//.new_vmode(),
//.img_mounted(),
//.img_readonly(),
//.img_size(),
//.sd_lba(),
//.sd_rd(),
//.sd_wr(),
//.sd_ack(),
//.sd_buff_addr(),
//.sd_buff_dout(),
//.sd_buff_din(),
//.sd_buff_wr(),
//.ps2_kbd_clk_out(),
//.ps2_kbd_data_out(),
//.ps2_kbd_clk_in(),
//.ps2_kbd_data_in(),
//.ps2_mouse_clk_out(),
//.ps2_mouse_data_out(),
//.ps2_mouse_data_in(),
//.ps2_mouse_clk_in(),
//.joystick_analog_0(),
//.joystick_analog_1(),
//.RTC(),
//.TIMESTAMP()
);
///////////////// RESET /////////////////////////
//wire reset = RESET | status[0] | buttons[1] | status[6] | ioctl_download;
wire reset = RESET;
wire warm_reset = status[0] | buttons[1]; //| ioctl_download;
//////////////// Machine ////////////////////////
wire [7:0] audio_l_emu;
wire [7:0] audio_r_emu;
assign AUDIO_L = {audio_l_emu,8'd0};
assign AUDIO_R = {audio_r_emu,8'd0};
assign AUDIO_S = 1;
assign AUDIO_MIX = 0;
wire clk_video_in;
wire [7:0] R_emu;
wire [7:0] G_emu;
wire [7:0] B_emu;
wire hblank_emu;
wire vblank_emu;
wire hsync_emu;
wire vsync_emu;
sharpmz sharp_mz
(
// Clocks Input to Emulator.
.clkmaster(CLK_50M),
// System clock.
.clksys(clk_sys),
// Clocks output by the emulator.
.clkvid(clk_video_in),
// Reset
.cold_reset(reset),
.warm_reset(warm_reset),
// LED on MB
.main_leds(LED_MB),
// PS2 via USB.
.ps2_key(ps2_key),
// VGA on IO daughter card.
.vga_hb_o(hblank_emu),
.vga_vb_o(vblank_emu),
.vga_hs_o(hsync_emu),
.vga_vs_o(vsync_emu),
.vga_r_o(R_emu),
.vga_g_o(G_emu),
.vga_b_o(B_emu),
// AUDIO on IO daughter card.
.audio_l_o(audio_l_emu),
.audio_r_o(audio_r_emu),
// HPS Interface
.ioctl_download(ioctl_download), // HPS Downloading to FPGA.
.ioctl_upload(ioctl_upload), // HPS Uploading from FPGA.
.ioctl_clk(clk_sys), // HPS I/O Clock.
.ioctl_wr(ioctl_wr), // HPS Write Enable to FPGA.
.ioctl_rd(ioctl_rd), // HPS Read Enable from FPGA.
.ioctl_addr(ioctl_addr), // HPS Address in FPGA to write into.
.ioctl_dout(ioctl_dout), // HPS Data to be written into FPGA.
.ioctl_din(ioctl_din) // HPS Data to be read into HPS.
);
// If ce_pix is same as pixel clock, uncomment below and remove CE_PIXEL from .ce_pix_out below.
//
//assign CE_PIXEL=1;
//assign CLK_VIDEO = clk_sys;
assign CLK_VIDEO = clk_video_in;
assign CE_PIXEL = clk_video_in;
//video_mixer #(.HALF_DEPTH(0)) video_mixer
video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_sys),
.ce_pix(clk_video_in), // Video pixel clock from core.
//.ce_pix_out(CE_PIXEL),
.scanlines({scale == 4, scale == 3, scale == 2}),
.scandoubler(scale || forced_scandoubler),
.hq2x(scale==1),
.mono(0),
// Input signals into the mixer, originating from the emulator.
.R(R_emu),
.G(G_emu),
.B(B_emu),
// Positive pulses.
.HSync(hsync_emu),
.VSync(vsync_emu),
.HBlank(hblank_emu),
.VBlank(vblank_emu),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.VGA_DE(VGA_DE)
// Outputs of the mixer are bound to the VGA_x signals defined in the sys_top module and passed into this module as parameters.
// These signals then feed the vga_osd -> vga_out modules in systop.v
);
// Uncomment below and comment out video_mixer to pass original signal to sys_top.v.
// To output original signal, edit sys_top.v and comment out vga_osd and vga_out, uncomment the assign statements.
//
//assign VGA_R = R_emu;
//assign VGA_G = G_emu;
//assign VGA_B = B_emu;
//assign VGA_HS = hsync_emu;
//assign VGA_VS = vsync_emu;
//assign VGA_DE = ~(vblank_emu | hblank_emu);
endmodule

13
jtag.cdf Normal file
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JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz-lite.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1392
jtag_uart_0.vhd Normal file
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File diff suppressed because it is too large Load Diff

47
memory_hw.tcl Normal file
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@@ -0,0 +1,47 @@
# TCL File Generated by Component Editor 17.0
# Mon Jun 11 22:55:14 BST 2018
# DO NOT MODIFY
#
# memory "memory" v1.0
# 2018.06.11.22:55:14
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module memory
#
set_module_property DESCRIPTION ""
set_module_property NAME memory
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME memory
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
#
# parameters
#
#
# display items
#

774
mif/combined_cgrom.mif Normal file
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@@ -0,0 +1,774 @@
DEPTH = 12288;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
0010: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
0020: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
0030: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
0040: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
0050: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0060: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
0070: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
0080: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
0090: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
00a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
00b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
00c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
00d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
00e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
00f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
0100: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
0110: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
0120: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
0130: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
0140: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
0150: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
0160: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
0170: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0180: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
0190: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
01a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
01b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
01c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
01d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
01e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
01f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
0200: 00 00 00 00 00 00 00 00 08 1c 3e 7f 7f 1c 3e 00;
0210: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
0220: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
0230: 08 1c 2a 7f 2a 08 08 00 00 3c 7e 7e 7e 7e 3c 00;
0240: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
0250: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
0260: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
0270: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
0280: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
0290: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
02a0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
02b0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
02c0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
02d0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
02e0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
02f0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
0300: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
0310: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
0320: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
0330: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
0340: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
0350: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
0360: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
0370: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
0380: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0390: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
03a0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
03b0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
03c0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
03d0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
03e0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
03f0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
0400: 00 00 00 00 00 00 00 00 00 00 38 04 3c 44 3a 00;
0410: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
0420: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
0430: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
0440: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
0450: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
0460: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
0470: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
0480: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
0490: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
04a0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 42 3c 00;
04b0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
04c0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
04d0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
04e0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
04f0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
0500: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
0510: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
0520: 22 44 88 11 22 44 88 11 88 44 22 11 88 44 22 11;
0530: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
0540: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
0550: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 22 1c 00;
0560: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
0570: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
0580: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
0590: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
05a0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
05b0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
05c0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
05d0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
05e0: 22 14 3e 08 3e 08 08 00 08 08 08 08 ff 08 08 08;
05f0: 24 24 24 24 c3 81 42 3c 00 3c 7a a9 a9 7a 3c 00;
0600: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
0610: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
0620: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
0630: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
0640: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
0650: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
0660: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
0670: 3c 7e ff db ff 67 7e 3c 3c 42 81 a5 81 99 42 3c;
0680: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
0690: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
06a0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
06b0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
06c0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
06d0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
06e0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
06f0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
0700: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
0710: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
0720: 00 0e 11 22 c4 04 02 01 00 ff 00 81 42 42 81 00;
0730: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
0740: 00 23 25 49 f1 49 25 23 88 90 a0 c0 c0 a8 98 b8;
0750: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
0760: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
0770: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
0780: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
07a0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
07b0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
07c0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
07d0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
07e0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
07f0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
0800: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
0810: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
0820: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
0830: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
0840: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
0850: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0860: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
0870: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
0880: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
0890: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
08a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
08b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
08c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
08d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
08e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
08f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
0900: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
0910: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
0920: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
0930: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
0940: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
0950: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
0960: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
0970: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0980: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
0990: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
09a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
09b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
09c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
09d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
09e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
09f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
0a00: 00 00 00 00 00 00 00 00 08 1c 3e 7f 7f 1c 3e 00;
0a10: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
0a20: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
0a30: 08 1c 2a 7f 2a 08 08 00 00 3c 7e 7e 7e 7e 3c 00;
0a40: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
0a50: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
0a60: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
0a70: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
0a80: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
0a90: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
0aa0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
0ab0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
0ac0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
0ad0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
0ae0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
0af0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
0b00: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
0b10: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
0b20: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
0b30: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
0b40: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
0b50: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
0b60: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
0b70: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
0b80: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0b90: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
0ba0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
0bb0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
0bc0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
0bd0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
0be0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
0bf0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
0c00: 00 00 00 00 00 00 00 00 00 00 38 04 3c 44 3a 00;
0c10: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
0c20: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
0c30: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
0c40: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
0c50: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
0c60: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
0c70: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
0c80: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
0c90: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
0ca0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 42 3c 00;
0cb0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
0cc0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
0cd0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
0ce0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
0cf0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
0d00: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
0d10: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
0d20: 22 44 88 11 22 44 88 11 88 44 22 11 88 44 22 11;
0d30: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
0d40: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
0d50: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 22 1c 00;
0d60: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
0d70: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
0d80: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
0d90: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
0da0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
0db0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
0dc0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
0dd0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
0de0: 22 14 3e 08 3e 08 08 00 08 08 08 08 ff 08 08 08;
0df0: 24 24 24 24 c3 81 42 3c 00 3c 7a a9 a9 7a 3c 00;
0e00: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
0e10: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
0e20: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
0e30: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
0e40: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
0e50: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
0e60: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
0e70: 3c 7e ff db ff 67 7e 3c 3c 42 81 a5 81 99 42 3c;
0e80: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
0e90: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
0ea0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
0eb0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
0ec0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
0ed0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
0ee0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
0ef0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
0f00: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
0f10: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
0f20: 00 0e 11 22 c4 04 02 01 00 ff 00 81 42 42 81 00;
0f30: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
0f40: 00 23 25 49 f1 49 25 23 88 90 a0 c0 c0 a8 98 b8;
0f50: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
0f60: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
0f70: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
0f80: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
0f90: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
0fa0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
0fb0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
0fc0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
0fd0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
0fe0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
0ff0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
1000: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
1010: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
1020: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
1030: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
1040: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
1050: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
1060: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
1070: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
1080: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
1090: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
10a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
10b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
10c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
10d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
10e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
10f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
1100: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
1110: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
1120: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
1130: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
1140: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
1150: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
1160: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
1170: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
1180: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
1190: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
11a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
11b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
11c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
11d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
11e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
11f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
1200: 10 08 08 04 08 08 10 00 08 1c 3e 7f 7f 1c 3e 00;
1210: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
1220: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
1230: 1c 1c 6b 7f 6b 08 1c 00 00 3c 7e 7e 7e 7e 3c 00;
1240: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
1250: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
1260: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
1270: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
1280: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
1290: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
12a0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
12b0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
12c0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
12d0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
12e0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
12f0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
1300: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
1310: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
1320: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
1330: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
1340: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
1350: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
1360: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
1370: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
1380: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
1390: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
13a0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
13b0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
13c0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
13d0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
13e0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
13f0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
1400: 18 18 18 18 18 18 18 00 00 00 38 04 3c 44 3a 00;
1410: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
1420: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
1430: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
1440: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
1450: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
1460: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
1470: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
1480: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
1490: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
14a0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
14b0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
14c0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
14d0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
14e0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
14f0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
1500: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
1510: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
1520: 20 10 08 00 00 00 00 00 00 00 00 32 4c 00 00 00;
1530: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
1540: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
1550: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 26 1a 00;
1560: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
1570: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
1580: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
1590: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
15a0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
15b0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
15c0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
15d0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
15e0: 08 10 10 20 10 10 08 00 08 08 08 08 ff 08 08 08;
15f0: 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7e 00;
1600: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
1610: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
1620: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
1630: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
1640: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
1650: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
1660: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
1670: 3c 7e ff db ff e7 7e 3c 3c 42 81 a5 81 99 42 3c;
1680: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
1690: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
16a0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
16b0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
16c0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
16d0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
16e0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
16f0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
1700: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
1710: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
1720: 00 0e 11 22 c4 04 02 01 88 44 22 11 88 44 22 11;
1730: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
1740: 00 43 45 49 f1 49 45 43 88 90 a0 c0 c0 a8 98 b8;
1750: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
1760: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
1770: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
1780: 22 44 88 11 22 44 88 11 00 70 70 70 00 00 00 00;
1790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
17a0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
17b0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
17c0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
17d0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
17e0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
17f0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
1800: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
1810: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
1820: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
1830: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
1840: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
1850: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
1860: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
1870: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
1880: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
1890: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
18a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
18b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
18c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
18d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
18e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
18f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
1900: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
1910: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
1920: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
1930: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
1940: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
1950: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
1960: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
1970: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
1980: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
1990: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
19a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
19b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
19c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
19d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
19e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
19f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
1a00: 10 08 08 04 08 08 10 00 08 1c 3e 7f 7f 1c 3e 00;
1a10: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
1a20: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
1a30: 1c 1c 6b 7f 6b 08 1c 00 00 3c 7e 7e 7e 7e 3c 00;
1a40: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
1a50: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
1a60: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
1a70: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
1a80: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
1a90: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
1aa0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
1ab0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
1ac0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
1ad0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
1ae0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
1af0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
1b00: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
1b10: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
1b20: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
1b30: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
1b40: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
1b50: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
1b60: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
1b70: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
1b80: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
1b90: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
1ba0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
1bb0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
1bc0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
1bd0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
1be0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
1bf0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
1c00: 18 18 18 18 18 18 18 00 00 00 38 04 3c 44 3a 00;
1c10: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
1c20: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
1c30: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
1c40: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
1c50: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
1c60: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
1c70: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
1c80: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
1c90: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
1ca0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
1cb0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
1cc0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
1cd0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
1ce0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
1cf0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
1d00: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
1d10: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
1d20: 20 10 08 00 00 00 00 00 00 00 00 32 4c 00 00 00;
1d30: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
1d40: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
1d50: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 26 1a 00;
1d60: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
1d70: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
1d80: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
1d90: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
1da0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
1db0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
1dc0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
1dd0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
1de0: 08 10 10 20 10 10 08 00 08 08 08 08 ff 08 08 08;
1df0: 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7e 00;
1e00: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
1e10: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
1e20: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
1e30: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
1e40: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
1e50: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
1e60: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
1e70: 3c 7e ff db ff e7 7e 3c 3c 42 81 a5 81 99 42 3c;
1e80: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
1e90: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
1ea0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
1eb0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
1ec0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
1ed0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
1ee0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
1ef0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
1f00: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
1f10: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
1f20: 00 0e 11 22 c4 04 02 01 88 44 22 11 88 44 22 11;
1f30: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
1f40: 00 43 45 49 f1 49 45 43 88 90 a0 c0 c0 a8 98 b8;
1f50: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
1f60: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
1f70: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
1f80: 22 44 88 11 22 44 88 11 00 70 70 70 00 00 00 00;
1f90: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
1fa0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
1fb0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
1fc0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
1fd0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
1fe0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
1ff0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
2000: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
2010: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
2020: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
2030: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
2040: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
2050: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
2060: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
2070: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
2080: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
2090: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
20a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
20b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
20c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
20d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
20e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
20f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
2100: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
2110: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
2120: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
2130: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
2140: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
2150: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
2160: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
2170: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
2180: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
2190: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
21a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
21b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
21c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
21d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
21e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
21f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
2200: 10 08 08 04 08 08 10 00 08 1c 3e 7f 7f 1c 3e 00;
2210: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
2220: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
2230: 1c 1c 6b 7f 6b 08 1c 00 00 3c 7e 7e 7e 7e 3c 00;
2240: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
2250: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
2260: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
2270: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
2280: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
2290: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
22a0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
22b0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
22c0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
22d0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
22e0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
22f0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
2300: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
2310: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
2320: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
2330: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
2340: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
2350: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
2360: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
2370: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
2380: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
2390: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
23a0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
23b0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
23c0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
23d0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
23e0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
23f0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
2400: 18 18 18 18 18 18 18 00 00 00 38 04 3c 44 3a 00;
2410: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
2420: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
2430: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
2440: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
2450: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
2460: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
2470: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
2480: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
2490: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
24a0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
24b0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
24c0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
24d0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
24e0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
24f0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
2500: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
2510: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
2520: 20 10 08 00 00 00 00 00 00 00 00 32 4c 00 00 00;
2530: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
2540: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
2550: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 26 1a 00;
2560: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
2570: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
2580: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
2590: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
25a0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
25b0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
25c0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
25d0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
25e0: 08 10 10 20 10 10 08 00 08 08 08 08 ff 08 08 08;
25f0: 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7e 00;
2600: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
2610: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
2620: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
2630: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
2640: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
2650: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
2660: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
2670: 3c 7e ff db ff e7 7e 3c 3c 42 81 a5 81 99 42 3c;
2680: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
2690: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
26a0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
26b0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
26c0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
26d0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
26e0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
26f0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
2700: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
2710: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
2720: 00 0e 11 22 c4 04 02 01 11 22 44 88 11 22 44 88;
2730: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
2740: 00 23 25 29 f1 29 25 23 88 90 a0 c0 c0 a8 98 b8;
2750: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
2760: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
2770: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
2780: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
2790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
27a0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
27b0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
27c0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
27d0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
27e0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
27f0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
2800: 00 00 00 00 00 00 00 00 7c c6 ba ba 82 ba aa ee;
2810: fc 86 ba 84 ba ba 86 fc 7e c2 be a0 a0 be c2 7e;
2820: f8 8c b6 aa aa b6 8c f8 fe 82 be 88 88 be 82 fe;
2830: fe 82 be 88 b8 a0 a0 e0 7e 82 be a0 ae ba 82 7e;
2840: ee aa ba 82 ba aa aa ee fe 82 ee 28 28 ee 82 fe;
2850: 1f 11 1b 0a ea ba c6 7c e6 aa b4 88 88 b4 aa e6;
2860: e0 a0 a0 a0 a0 be 82 fe fe 82 aa aa ba aa aa ee;
2870: ee 9a 8a a2 b2 aa aa ee 7c c6 ba aa aa ba c6 7c;
2880: fc 86 ba ba 86 bc a0 e0 7c c6 ba ba aa b2 c2 7c;
2890: fc 86 ba ba 84 b4 aa e6 7e c2 be c4 7a fa 86 fc;
28a0: fe 82 ee 28 28 28 28 38 ee aa aa aa aa ba c6 7c;
28b0: ee aa aa aa aa 54 28 10 ee aa aa ba aa aa 82 fe;
28c0: c6 aa 54 28 28 54 aa c6 ee aa 92 44 28 28 28 38;
28d0: fe 82 fa 14 28 5e 82 fe 00 40 a0 90 ff 7e 00 00;
28e0: 00 02 05 09 ff 7e 00 00 00 7c d6 7c 38 54 92 00;
28f0: 92 54 38 fe 38 54 92 00 00 00 38 54 fe 00 00 00;
2900: 7c 82 b2 aa aa 9a 82 7c 38 48 68 28 28 6c 44 7c;
2910: 7c 82 ba ca 14 2e 42 fe fc 82 fa 22 22 fa 82 fc;
2920: 0c 14 24 54 b6 82 f6 1c fe 82 be 84 7a fa 86 fc;
2930: 7e 82 be bc 82 ba 82 7c fe 82 fa 14 28 50 50 70;
2940: 7c 82 ba 7c 82 ba 82 7c 7c 82 ba 82 7a fa 82 fc;
2950: f8 88 be aa fa 22 3e 00 1f 11 7d 55 5f 44 7c 00;
2960: 3c 5a ff e7 7e 24 42 81 3c 5a ff e7 7e 24 24 66;
2970: 08 1c 2a 7f 77 3e 36 63 08 1c 2a 7f 77 3e 36 14;
2980: 41 a2 3c 5a 7e ff 42 63 82 45 3c 5a 7e ff 42 c6;
2990: 00 5a bd 99 24 42 24 00 81 a5 5a 18 18 24 c3 00;
29a0: 00 24 7e bd 7e 24 24 e7 24 7e bd 7e 24 42 42 c3;
29b0: 3c 5a ff ab d5 ff dd 89 3c 5a ff ab d5 ff 77 22;
29c0: 3c 42 a5 81 99 81 d5 aa 3c 42 a5 81 99 81 ab 55;
29d0: 42 42 66 e7 ff ff 7e 3c 1c fe 3f 0f 0f 3f fe 1c;
29e0: 3c 7e ff ff e7 66 42 42 38 7f fc f0 f0 fc 7f 38;
29f0: 3c 7e ff ff ff ff 7e 3c 10 38 28 28 28 7c fe d6;
2a00: 00 03 07 7e c7 7e 07 03 6b 7f 3e 14 14 14 1c 08;
2a10: 00 c0 e0 7e e3 7e e0 c0 3c 0c 3c 18 3c 76 76 46;
2a20: 3c 24 3c 18 3c 5a 5a 7e 3c 30 3c 18 3c 6e 6e 62;
2a30: 7e 7e 24 24 24 24 24 6c 7e 7e 24 24 24 24 24 66;
2a40: 7e 7e 24 24 24 24 24 36 22 63 f7 b7 ff 7e 3c 3c;
2a50: 38 6c ff 3f 0f 3f fc 38 3c 3c 7e ff ed ef c6 44;
2a60: 1c 36 ff fc f0 fc 3f 1e 3c 7e ff bf ff 7e 3c 3c;
2a70: 3c 3c 7e ff fd ff 7e 3c 1c 36 ff ff ff ff 3e 1c;
2a80: 38 6c ff ff ff ff 7c 38 18 3c 3c 3c 3c 18 3c 3c;
2a90: 00 00 7b ff ff 7b 00 00 3c 3c 18 3c 3c 3c 3c 18;
2aa0: 00 00 de ff ff de 00 00 20 60 20 20 30 28 3c 3c;
2ab0: 00 40 ff 0b 07 03 00 00 3c 3c 14 0c 04 04 06 04;
2ac0: 00 02 ff d0 e0 c0 00 00 10 10 38 7c 92 10 10 38;
2ad0: 00 08 10 31 ff 31 10 08 38 10 10 92 7c 38 10 10;
2ae0: 00 10 08 8c ff 8c 08 10 00 78 60 50 48 04 02 00;
2af0: 00 02 04 48 50 60 78 00 00 40 20 12 0a 06 1e 00;
2b00: 00 1e 06 0a 12 20 40 00 18 7e 7e ff c3 81 81 81;
2b10: 1f 78 70 f0 f0 70 78 1f 81 81 81 c3 ff 7e 7e 18;
2b20: f8 1e 0e 0f 0f 0e 1e f8 bf a1 ad a5 a5 bd 81 ff;
2b30: ff 81 bd a5 85 fd 01 ff ff 81 bd a5 a5 b5 85 fd;
2b40: ff 80 bf a1 a5 bd 81 ff 00 18 00 3c 00 7e 00 ff;
2b50: 01 05 15 55 55 15 05 01 ff 00 7e 00 3c 00 18 00;
2b60: 80 a0 a8 aa aa a8 a0 80 00 08 1c 3e 00 08 1c 3e;
2b70: 00 00 11 33 77 33 11 00 00 3e 1c 08 00 3e 1c 08;
2b80: 00 00 44 66 77 66 44 00 00 00 e7 a5 e7 00 00 00;
2b90: 10 38 54 10 10 54 38 10 00 00 24 42 ff 42 24 00;
2ba0: 7f 41 22 1c 08 08 08 7f 55 55 55 55 55 55 55 55;
2bb0: ff 00 ff 00 ff 00 ff 00 a5 42 a5 00 00 a5 42 a5;
2bc0: 24 42 81 00 00 81 42 24 ff 80 9f a0 a0 a0 a0 a0;
2bd0: ff 01 e5 11 15 11 15 11 00 00 00 ff a0 af a0 ff;
2be0: 00 00 00 ff 41 41 55 ff a0 9f 80 ff 30 30 30 78;
2bf0: 11 e1 01 ff 0c 0c 0c 1e 80 aa 80 95 80 8f 80 ff;
2c00: 01 a9 01 51 01 e1 01 ff 3c 42 ab d5 10 10 14 08;
2c10: 00 00 18 24 24 18 00 00 00 18 24 42 42 24 18 00;
2c20: 3c 42 81 81 81 81 42 3c 00 00 00 18 18 00 00 00;
2c30: 00 00 3c 3c 3c 3c 00 00 00 7e 7e 7e 7e 7e 7e 00;
2c40: 3c 42 9d a1 a1 9d 42 3c ff ff ff e7 e7 ff ff ff;
2c50: ff ff c3 c3 c3 c3 ff ff ff 81 81 81 81 81 81 ff;
2c60: 20 30 20 20 ff 7e 3c 00 3c 42 81 ff ff 81 42 3c;
2c70: 3c 5a 99 99 99 99 5a 3c 3c 5a 99 ff ff 99 5a 3c;
2c80: 00 28 fe aa fe 54 38 10 0f 30 40 4e 8a 8e 80 81;
2c90: f0 0c 02 72 51 71 01 81 0f 30 40 40 8e 80 80 81;
2ca0: f0 0c 02 02 71 01 01 81 81 80 88 84 43 40 30 0f;
2cb0: 81 01 11 21 c2 02 0c f0 81 80 80 87 40 40 30 0f;
2cc0: 81 01 01 e1 02 02 0c f0 81 80 83 84 43 40 30 0f;
2cd0: 81 01 c1 21 c2 02 0c f0 81 80 87 88 48 40 30 0f;
2ce0: 81 01 e1 11 12 02 0c f0 08 10 54 fe fe fe fe 7c;
2cf0: 00 06 08 10 30 78 78 30 00 52 34 06 60 2c 4a 00;
2d00: 91 52 00 03 c0 00 4a 89 80 c0 e0 f0 ff ff ff ff;
2d10: 00 00 01 02 ff c3 c3 ff 00 00 80 40 ff c3 c3 ff;
2d20: 00 c0 20 10 fc fe ff fc 01 03 07 0f ff ff ff ff;
2d30: 02 14 28 08 14 14 08 00 00 fe 42 20 10 20 42 fe;
2d40: 00 03 04 08 3f 7f ff 3f 00 20 10 10 10 28 48 86;
2d50: 00 3c 42 42 42 24 a5 e7 00 44 82 82 92 6c 00 00;
2d60: 00 00 6c 92 92 6c 00 00 00 02 6c 90 90 6e 00 00;
2d70: 00 1e 10 50 50 b0 10 00 00 00 10 00 7c 00 10 00;
2d80: 00 f1 5b 55 55 51 51 00 ff 89 91 c5 a3 89 91 ff;
2d90: ff c3 a5 99 99 a5 c3 ff 00 92 54 38 ee 38 54 92;
2da0: ff 99 99 ff ff 99 99 ff 92 54 38 10 10 10 10 10;
2db0: 38 10 38 10 38 10 38 10 00 00 00 aa ff aa 00 00;
2dc0: 00 10 10 7c 10 10 00 7c 7e 42 7e 42 7e 42 7e 42;
2dd0: 00 ff 55 55 55 55 ff 00 00 00 00 c0 b0 8c 83 ff;
2de0: 00 00 00 03 0d 31 c1 ff 00 00 00 00 3c 7e ff ff;
2df0: ff ff 7e 3c 00 00 00 00 c0 e0 f0 f0 f0 f0 e0 c0;
2e00: 03 07 0f 0f 0f 0f 07 03 03 0c 3f 3f ff 7f 37 1f;
2e10: c0 30 b8 dc ee f6 fb fb 0e 0e 0a 04 01 01 03 0f;
2e20: 7a 74 f4 f4 f4 fa fd fd 04 4e e4 46 6f 7f 60 3f;
2e30: 20 72 27 62 f6 fe 06 fc 3b 31 1b 1f 10 1f 0f 07;
2e40: dc 8c d8 f8 08 f8 f0 e0 01 03 07 06 0e 3e 70 30;
2e50: 80 c0 e0 60 70 7c 0e 0c 1e 0e 06 07 03 37 7f 8b;
2e60: 78 70 60 e0 c0 ec fe d1 01 33 7b 59 8c df 7f 3f;
2e70: 80 cc de 9a 31 fb fe fc 3f 1f 1f 0f 0f 7f 00 ff;
2e80: fc f8 f8 f0 f0 fe 00 ff 00 01 02 04 02 01 1f 1f;
2e90: 00 80 40 20 40 80 f8 f8 02 02 02 02 1f 20 7f 00;
2ea0: 40 40 40 40 f8 04 fe 00 73 73 73 7f 3f 1f 0f 0f;
2eb0: ce ce ce fe fc f8 f0 f0 0f 0f 0f 18 7f 40 7f ff;
2ec0: f0 f0 f0 18 fe 02 fe ff f8 44 42 21 21 42 44 f8;
2ed0: ff 05 07 00 00 07 05 ff fc 86 82 81 81 82 86 fc;
2ee0: 00 00 80 40 7f 80 00 00 00 00 00 00 ff 01 01 01;
2ef0: 01 01 01 01 ff 00 00 00 ff 80 80 80 80 00 00 00;
2f00: 00 00 00 00 80 80 80 ff 00 08 0c 0a f9 0a 0c 08;
2f10: 00 08 0c 3a e9 3a 0c 08 1f 28 48 fe 88 88 8f 00;
2f20: 40 c0 40 e6 09 02 04 0f 40 c0 40 e2 06 0a 1f 02;
2f30: 40 c0 40 ef 01 07 01 0f 40 a0 20 4f e1 07 01 0f;
2f40: c0 60 18 06 18 60 80 fe 01 06 18 60 18 06 01 7f;
2f50: 00 01 06 1d 2a 2a 2a 1f 1b 8f 65 11 c9 a9 b1 f3;
2f60: 4c f7 f0 18 07 02 3e fe 7f 9f 31 41 81 81 f9 fd;
2f70: 88 02 40 00 88 41 00 91 40 01 88 00 40 04 80 11;
2f80: 00 30 58 fd ff 79 30 00 00 0c 1a bf ff 9e 0c 00;
2f90: 00 30 58 fd 3f f9 30 00 00 0c 1a bf fc 9f 0c 00;
2fa0: 10 28 68 bc fc 78 10 38 ba ee aa 38 38 ba fe ba;
2fb0: ba fe ba 38 38 aa ee ba 00 e7 42 ff 9f ff 42 e7;
2fc0: 00 e7 42 ff f9 ff 42 e7 00 00 fc 1c 7f 63 3e 00;
2fd0: 00 00 3f 38 fe c6 7c 00 ff 81 a5 81 81 a5 81 ff;
2fe0: e7 81 81 00 00 81 81 e7 00 04 08 fe 10 fe 20 40;
2ff0: 18 24 24 20 10 10 10 10 08 08 08 08 04 24 24 18;
END;

102
mif/combined_keymap.mif Normal file
View File

@@ -0,0 +1,102 @@
DEPTH = 1536;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: ff ff ff ff ff ff ff 86 ff 37 ff ff ff 90 93 ff;
0010: ff ff 80 ff ff 20 00 ff ff ff 60 50 40 30 10 ff;
0020: ff 61 70 41 21 11 01 ff ff 91 71 51 22 31 02 ff;
0030: ff 72 62 52 42 32 12 ff ff ff 63 43 23 03 13 ff;
0040: ff 73 53 33 24 14 04 ff ff 64 74 44 54 34 05 ff;
0050: ff 95 45 ff 25 15 ff ff 81 85 84 55 ff 75 ff ff;
0060: ff ff ff ff ff ff 65 ff ff 66 35 46 26 ff ff ff;
0070: 96 87 76 56 47 36 ff 06 77 57 67 17 07 27 ff ff;
0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
00c0: ff ff ff ff ff ff ff ff ff ff 16 ff ff ff ff ff;
00d0: ff ff ff ff ff ff ff ff ff ff 97 ff ff ff ff ff;
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ef;
00f0: ff 81 92 ff 83 ff ff ff ff ff ff ff ff ff ff ff;
0100: ff ff ff ff ff ff ff 86 ff 37 ff ff ff 90 93 ff;
0110: ff ff 80 ff ff 20 00 ff ff ff 60 50 40 30 10 ff;
0120: ff 61 70 41 21 11 01 ff ff 91 71 51 22 31 02 ff;
0130: ff 72 62 52 42 32 12 ff ff ff 63 43 23 03 13 ff;
0140: ff 73 53 33 24 14 04 ff ff 64 74 44 54 34 05 ff;
0150: ff 95 45 ff 25 15 ff ff 81 85 84 55 ff 75 ff ff;
0160: ff ff ff ff ff ff 65 ff ff 66 35 46 26 ff ff ff;
0170: 96 87 76 56 47 36 ff 06 77 57 67 17 07 27 ff ff;
0180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
01a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
01b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
01c0: ff ff ff ff ff ff ff ff ff ff 16 ff ff ff ff ff;
01d0: ff ff ff ff ff ff ff ff ff ff 97 ff ff ff ff ff;
01e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ef;
01f0: ff 81 92 ff 83 ff ff ff ff ff ff ff ff ff ff ff;
0200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0210: ff ff 00 ff 27 14 16 ff ff ff 10 22 13 15 17 ff;
0220: ff 20 21 23 24 27 26 ff ff 40 31 32 34 25 36 ff;
0230: ff 41 30 42 33 35 37 ff ff ff 50 43 44 46 47 ff;
0240: ff 51 52 45 54 57 56 ff ff 60 70 53 63 55 67 ff;
0250: ff ff 62 ff 65 66 ff ff 11 07 73 72 64 76 ff ff;
0260: ff ff ff ff ff ff 61 ff ff 8a ff 84 77 ff ff ff;
0270: 12 ff 74 85 75 a7 ff ff ff 97 92 95 90 96 ff ff;
0280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
02a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
02b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
02c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
02d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
02e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
02f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0310: ff ff 00 ff 27 14 16 ff ff ff 10 22 13 15 17 ff;
0320: ff 20 21 23 24 27 26 ff ff 40 31 32 34 25 36 ff;
0330: ff 41 30 42 33 35 37 ff ff ff 50 43 44 46 47 ff;
0340: ff 51 52 45 54 57 56 ff ff 60 70 53 63 55 67 ff;
0350: ff ff 62 ff 65 66 ff ff 11 07 73 72 64 76 ff ff;
0360: ff ff ff ff ff ff 61 ff ff 8a ff 84 77 ff ff ff;
0370: 12 ff 74 85 75 a7 ff ff ff 97 92 95 90 96 ff ff;
0380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
03a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
03b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
03c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
03d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
03e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
03f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0400: ff ff ff 93 95 97 96 ff ff ff ff ff 94 ff ff ff;
0410: ff 06 80 ff a6 27 57 ff ff ff 16 25 47 21 56 ff;
0420: ff 45 20 44 43 45 55 ff ff 64 22 42 24 26 53 ff;
0430: ff 32 46 40 41 17 52 ff ff ff 33 36 23 51 50 ff;
0440: ff 61 35 37 31 63 62 ff ff 60 70 34 0a 30 75 ff;
0450: ff ff ff ff 14 65 ff ff 04 ff 00 13 ff 67 ff ff;
0460: ff ff ff ff ff ff ff ff ff ff ff 72 ff ff ff ff;
0470: 77 76 74 ff 73 75 87 ff ff ff ff ff ff ff ff ff;
0480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0500: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff;
0510: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff;
0520: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff;
0530: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff;
0540: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff;
0550: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff;
0560: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff;
0570: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff;
0580: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff;
0590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff;
05d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff;
05e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef;
05f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff;
END;

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---------------------------------------------------------------------------------------------------------
--
-- Name: mz80b.vhd
-- Created: August 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Business Computer:
-- Models MZ-80B, MZ-2000
--
-- This module is the main (top level) container for the Business MZ Computer
-- Emulation.
--
-- The design tries to work from top-down, where components which are common
-- to the Business and Personal MZ series are at the top (ie. main memory,
-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
-- to the machine specific modules and components. Some components are common
-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
-- tree branch as their design use is less generic.
--
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- | -> mz80c_video.vhd
-- | -> pcg.vhd
-- | -> cmt.vhd (this may move to common and be shared with mz80b)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- | -> i8253 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
--
--
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: August 2018 - Initial module created.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity mz80b is
PORT (
-- Clocks
CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module.
-- Resets.
SYSTEM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_CLK : in std_logic;
T80_CLKEN : out std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
T80_BUSRQ_n : out std_logic;
T80_M1_n : in std_logic;
T80_MREQ_n : in std_logic;
T80_IORQ_n : in std_logic;
T80_RD_n : in std_logic;
T80_WR_n : in std_logic;
T80_RFSH_n : in std_logic;
T80_HALT_n : in std_logic;
T80_BUSAK_n : in std_logic;
T80_A16 : in std_logic_vector(15 downto 0);
T80_DI : out std_logic_vector(7 downto 0);
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CS_ROM_n : out std_logic;
CS_RAM_n : out std_logic;
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Video signals.
R : out std_logic;
G : out std_logic;
B : out std_logic;
HSYNC_n : out std_logic;
VSYNC_n : out std_logic;
HBLANK : out std_logic;
VBLANK : out std_logic;
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- I/O -- I/O down to the core.
PS2_KEY : in std_logic_vector(10 downto 0);
-- Cassette magnetic tape signals.
CMTBUS : out std_logic_vector(CMTBUS_WIDTH);
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status.
);
end mz80b;
architecture rtl of mz80b is
begin
T80_CLKEN <= '1';
T80_WAIT_n <= '1';
T80_INT_n <= '1';
T80_NMI_n <= '1';
T80_BUSRQ_n <= '1';
T80_DI <= (others => '0');
CS_ROM_n <= '1';
CS_RAM_n <= '1';
AUDIO_L <= '1';
AUDIO_R <= '1';
R <= '0';
G <= '0';
B <= '0';
HSYNC_n <= '0';
VSYNC_n <= '0';
HBLANK <= '0';
VBLANK <= '0';
CMTBUS <= (others => '0');
IOCTL_DIN <= (others => '0');
DEBUG_STATUS_LEDS <= (others => '0');
end rtl;

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
# Date created = 01:53:32 April 20, 2017
#
# -------------------------------------------------------------------------- #
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
#set_global_assignment -name TOP_LEVEL_ENTITY emu
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
#set_location_assignment PIN_U9 -to ADC_CONVST
#set_location_assignment PIN_V10 -to ADC_SCK
#set_location_assignment PIN_AC4 -to ADC_SDI
#set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
#set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
#set_location_assignment PIN_U14 -to ARDUINO_IO[4]
#set_location_assignment PIN_U13 -to ARDUINO_IO[5]
#set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
#set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
#set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
#set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
#set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
#set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
#set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
#set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
#set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
#set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
#set_location_assignment PIN_AF25 -to SDIO_DAT[0]
#set_location_assignment PIN_AF23 -to SDIO_DAT[1]
#set_location_assignment PIN_AD26 -to SDIO_DAT[2]
#set_location_assignment PIN_AF28 -to SDIO_DAT[3]
#set_location_assignment PIN_AF27 -to SDIO_CMD
#set_location_assignment PIN_AH26 -to SDIO_CLK
#set_location_assignment PIN_AH7 -to SDIO_CD
#
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
#
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
#set_location_assignment PIN_Y11 -to SDRAM_A[0]
#set_location_assignment PIN_AA26 -to SDRAM_A[1]
#set_location_assignment PIN_AA13 -to SDRAM_A[2]
#set_location_assignment PIN_AA11 -to SDRAM_A[3]
#set_location_assignment PIN_W11 -to SDRAM_A[4]
#set_location_assignment PIN_Y19 -to SDRAM_A[5]
#set_location_assignment PIN_AB23 -to SDRAM_A[6]
#set_location_assignment PIN_AC23 -to SDRAM_A[7]
#set_location_assignment PIN_AC22 -to SDRAM_A[8]
#set_location_assignment PIN_C12 -to SDRAM_A[9]
#set_location_assignment PIN_AB26 -to SDRAM_A[10]
#set_location_assignment PIN_AD17 -to SDRAM_A[11]
#set_location_assignment PIN_D12 -to SDRAM_A[12]
#set_location_assignment PIN_Y17 -to SDRAM_BA[0]
#set_location_assignment PIN_AB25 -to SDRAM_BA[1]
#set_location_assignment PIN_E8 -to SDRAM_DQ[0]
#set_location_assignment PIN_V12 -to SDRAM_DQ[1]
#set_location_assignment PIN_D11 -to SDRAM_DQ[2]
#set_location_assignment PIN_W12 -to SDRAM_DQ[3]
#set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
#set_location_assignment PIN_D8 -to SDRAM_DQ[5]
#set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
#set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
#set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
#set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
#set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
#set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
#set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
#set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
#set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
#set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
#set_location_assignment PIN_AG13 -to SDRAM_DQML
#set_location_assignment PIN_AF13 -to SDRAM_DQMH
#set_location_assignment PIN_AD20 -to SDRAM_CLK
#set_location_assignment PIN_AG10 -to SDRAM_CKE
#set_location_assignment PIN_AA19 -to SDRAM_nWE
#set_location_assignment PIN_AA18 -to SDRAM_nCAS
#set_location_assignment PIN_Y18 -to SDRAM_nCS
#set_location_assignment PIN_W14 -to SDRAM_nRAS
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
#set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
#set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
#set_location_assignment PIN_U10 -to HDMI_I2C_SCL
#set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
#set_location_assignment PIN_T13 -to HDMI_I2S
#set_location_assignment PIN_T11 -to HDMI_LRCLK
#set_location_assignment PIN_U11 -to HDMI_MCLK
#set_location_assignment PIN_T12 -to HDMI_SCLK
#set_location_assignment PIN_AG5 -to HDMI_TX_CLK
#set_location_assignment PIN_AD19 -to HDMI_TX_DE
#set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
#set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
#set_location_assignment PIN_W8 -to HDMI_TX_D[2]
#set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
#set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
#set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
#set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
#set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
#set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
#set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
#set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
#set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
#set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
#set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
#set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
#set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
#set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
#set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
#set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
#set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
#set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
#set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
#set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
#set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
#set_location_assignment PIN_T8 -to HDMI_TX_HS
#set_location_assignment PIN_AF11 -to HDMI_TX_INT
#set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
#set_location_assignment PIN_Y24 -to SW[0]
#set_location_assignment PIN_W24 -to SW[1]
#set_location_assignment PIN_W21 -to SW[2]
#set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VHDL_FILE jtag_uart_0.vhd
set_global_assignment -name SYSTEMVERILOG_FILE emu.sv
set_global_assignment -name VHDL_FILE sharpmz.vhd
#============================================================
# Original MZ80C T80 CPU
#============================================================
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_Reg.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_Pack.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_MCode.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_ALU.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80s.vhd
#============================================================
# Latest T80 CPU
#============================================================
set_global_assignment -name VHDL_FILE common/T80/T80.vhd
set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE common/T80/T80a.vhd
set_global_assignment -name VHDL_FILE common/T80/T80se.vhd
set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd
#============================================================
# i8253 Programmable Interval Timer
#============================================================
set_global_assignment -name VHDL_FILE common/i8253/i8253.vhd
set_global_assignment -name VHDL_FILE common/i8253/counter0.vhd
set_global_assignment -name VHDL_FILE common/i8253/counter1.vhd
set_global_assignment -name VHDL_FILE common/i8253/counter2.vhd
#============================================================
# i8255 Programmable Peripheral Interface
#============================================================
set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd
#============================================================
# MZ80C specific modules.
#============================================================
set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd
set_global_assignment -name VHDL_FILE mz80c/cmt.vhd
set_global_assignment -name VHDL_FILE mz80c/mz80c_video.vhd
#============================================================
# MZ80B specific modules.
#============================================================
set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd
#============================================================
# PLL
#============================================================
set_global_assignment -name QIP_FILE common/pll.qip
set_global_assignment -name VHDL_FILE common/clkgen.vhd
#============================================================
# Common modules
#============================================================
set_global_assignment -name VHDL_FILE common/dprom.vhd
set_global_assignment -name VHDL_FILE common/clk_div.vhd
set_global_assignment -name VHDL_FILE common/mctrl.vhd
set_global_assignment -name VHDL_FILE common/dpram.vhd
set_global_assignment -name VHDL_FILE common/keymatrix.vhd
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
set_global_assignment -name ALLOW_REGISTER_RETIMING ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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sharpmz-lite.qws Normal file
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sharpmz-lite.rbf Normal file
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sharpmz-lite.srf Normal file
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{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(15): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(14): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(32): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

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sharpmz-lite_assignment_defaults.qdf Normal file
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@@ -0,0 +1,808 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
# Date created = 18:06:35 June 18, 2018
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL -value ENABLE
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

13
sharpmz.qpf Normal file
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@@ -0,0 +1,13 @@
#
# please keep this file read-only!
# Quartus changes this file everytime revision is switched,
# and it will be marked as changed with every commit.
#
QUARTUS_VERSION = "16.1"
DATE = "23:13:02 April 27, 2017"
# Revisions
PROJECT_REVISION = "sharpmz-lite"
PROJECT_REVISION = "sharpmz"

357
sharpmz.qsf Normal file
View File

@@ -0,0 +1,357 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
# Date created = 01:53:32 April 20, 2017
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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## Generated SDC file "sharpmz.sdc"
## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition"
## DATE "Mon Jul 16 23:49:03 2012"
##
## DEVICE "EP3C16F484C6"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
#create_clock -name {MCLK} -period 10.000 -waveform { 0.000 5.000 } [get_ports {SDRAM_CLK}]
#create_clock -name {SDCLK} -period 100.000 -waveform { 0.000 50.000 } [get_ports {SDIO_CLK}]
#create_clock -name {VMCLK} -period 10.000 -waveform { 0.000 5.000 }
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[0]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[0]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[1]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[1]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[2]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[2]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[3]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[3]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[4]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[4]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[5]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[5]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[6]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[6]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[7]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[7]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[8]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[8]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[9]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[9]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[10]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[10]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[11]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[11]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[12]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[12]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[13]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[13]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[14]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[14]}]
#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[15]}]
#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[15]}]
#**************************************************************
# Set Output Delay
#**************************************************************
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[0]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[1]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[2]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[3]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[4]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[5]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[6]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[7]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[8]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[9]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[10]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nCAS}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nCS}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[0]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[1]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[2]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[3]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[4]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[5]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[6]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[7]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[8]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[9]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[10]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[11]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[12]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[13]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[14]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[15]}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQML}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nRAS}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQMH}]
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nWE}]
#set_output_delay -add_delay -clock [get_clocks {SDCLK}] 0.000 [get_ports {SDIO_CMD}]
#set_output_delay -add_delay -clock [get_clocks {SDCLK}] 0.000 [get_ports {SDIO_DAT[3]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 0.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|*resetlatch}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[33]}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[0]}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[34]}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|*MonDReg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|*jdo*}]
set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|ir*}]
set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go}]
set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_writedata_d1*|*}] -to [get_registers *]
set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_nativeaddress_d1*|*}] -to [get_registers *]
set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
set_false_path -from [get_keepers -nocase {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

371
sharpmz.tl Normal file
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@@ -0,0 +1,371 @@
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
# Quartus Prime: Generate Tcl File for Project
# File: sharpmz.tcl
# Generated on: Wed Jun 20 13:50:16 2018
# Load Quartus Prime Tcl Project package
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "sharpmz"]} {
puts "Project sharpmz is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists sharpmz]} {
project_open -revision sharpmz-lite sharpmz
} else {
project_new -revision sharpmz-lite sharpmz
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VHDL_FILE jtag_uart_0.vhd
set_global_assignment -name SYSTEMVERILOG_FILE sharpmz.sv
set_global_assignment -name VHDL_FILE mz80c/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE mz80c/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE mz80c/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE mz80c/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE mz80c/T80/T80.vhd
set_global_assignment -name VHDL_FILE mz80c/T80/T80s.vhd
set_global_assignment -name VHDL_FILE mz80c/cmt.vhd
set_global_assignment -name VHDL_FILE mz80c/counter0.vhd
set_global_assignment -name VHDL_FILE mz80c/counter1.vhd
set_global_assignment -name VHDL_FILE mz80c/counter2.vhd
set_global_assignment -name VHDL_FILE mz80c/dpram64k.vhd
set_global_assignment -name VHDL_FILE mz80c/dpram.vhd
set_global_assignment -name VHDL_FILE mz80c/i8253.vhd
set_global_assignment -name VHDL_FILE mz80c/i8255.vhd
set_global_assignment -name VHDL_FILE mz80c/keymatrix.vhd
set_global_assignment -name VHDL_FILE mz80c/ls367.vhd
set_global_assignment -name VHDL_FILE mz80c/mctrl.vhd
set_global_assignment -name VHDL_FILE mz80c/sharpmz.vhd
set_global_assignment -name VHDL_FILE mz80c/pcg.vhd
set_global_assignment -name VERILOG_FILE mz80c/pll_mz80c.v
set_global_assignment -name VERILOG_FILE mz80c/pll_mz80c_1.v
set_global_assignment -name VHDL_FILE mz80c/ps2kb.vhd
set_global_assignment -name VHDL_FILE mz80c/ScanConv.vhd
set_global_assignment -name VHDL_FILE mz80c/dprom.vhd
set_global_assignment -name VHDL_FILE mz80c/videoout.vhd
set_global_assignment -name VHDL_FILE mz80c/clk_div.vhd
set_global_assignment -name VHDL_FILE mz80c/clkgen.vhd
set_global_assignment -name VHDL_FILE mz80c/mrom.vhd
set_global_assignment -name VHDL_FILE mz80c/ram1k.vhd
set_global_assignment -name QIP_FILE mz80c/linebuf.qip
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# Including default assignments
set_global_assignment -name REVISION_TYPE BASE -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS OFF -family "Cyclone V"
set_global_assignment -name TIMEQUEST_CCPP_TRADEOFF_TOLERANCE 0 -family "Cyclone V"
set_global_assignment -name TDC_CCPP_TRADEOFF_TOLERANCE 30 -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -family "Cyclone V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -family "Cyclone V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ON -family "Cyclone V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS ON -family "Cyclone V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ -family "Cyclone V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION ON -family "Cyclone V"
set_global_assignment -name ENABLE_OCT_DONE OFF -family "Cyclone V"
# Commit assignments
export_assignments
# Close project
if {$need_to_close_project} {
project_close
}
}

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sharpmz_assignment_defaults.qdf Normal file
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@@ -0,0 +1,807 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 18:26:55 June 18, 2018
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

69
sys/build_id.tcl Normal file
View File

@@ -0,0 +1,69 @@
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Build CDF file
# Sorgelig - 17/2/2018
proc generateCDF {revision device outpath} {
set outputFileName "jtag.cdf"
set outputFile [open $outputFileName "w"]
puts $outputFile "JedecChain;"
puts $outputFile " FileRevision(JESD32A);"
puts $outputFile " DefaultMfr(6E);"
puts $outputFile ""
puts $outputFile " P ActionCode(Ign)"
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
puts $outputFile " P ActionCode(Cfg)"
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
puts $outputFile "ChainEnd;"
puts $outputFile ""
puts $outputFile "AlteraBegin;"
puts $outputFile " ChainType(JTAG);"
puts $outputFile "AlteraEnd;"
}
set project_name [lindex $quartus(args) 1]
set revision [lindex $quartus(args) 2]
if {[project_exists $project_name]} {
if {[string equal "" $revision]} {
project_open $project_name -revision [get_current_revision $project_name]
} else {
project_open $project_name -revision $revision
}
} else {
post_message -type error "Project $project_name does not exist"
exit
}
set device [get_global_assignment -name DEVICE]
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
if [is_project_open] {
project_close
}
generateBuildID_Verilog
generateCDF $revision $device $outpath

202
sys/hdmi_config.sv Normal file
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@@ -0,0 +1,202 @@
module hdmi_config
(
// Host Side
input iCLK,
input iRST_N,
input dvi_mode,
input audio_96k,
// I2C Side
output I2C_SCL,
inout I2C_SDA
);
// Internal Registers/Wires
reg mI2C_GO = 0;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [7:0] LUT_INDEX = 0;
i2c #(50_000_000, 20_000) i2c_av
(
.CLK(iCLK),
.I2C_SCL(I2C_SCL), // I2C CLOCK
.I2C_SDA(I2C_SDA), // I2C DATA
.I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
.START(mI2C_GO), // START transfer
.END(mI2C_END), // END transfer
.ACK(mI2C_ACK) // ACK
);
////////////////////// Config Control ////////////////////////////
always@(posedge iCLK or negedge iRST_N) begin
reg [1:0] mSetup_ST = 0;
if(!iRST_N) begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end else begin
if(init_data[LUT_INDEX] != 16'hFFFF) begin
case(mSetup_ST)
0: begin
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: if(~mI2C_END) mSetup_ST <= 2;
2: begin
mI2C_GO <= 0;
if(mI2C_END) begin
mSetup_ST <= 0;
if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
end
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
wire [15:0] init_data[58] =
'{
16'h9803, // ADI required Write.
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
// 00 = HPD is from both HPD pin or CDC HPD
// 01 = HPD is from CDC HPD
// 10 = HPD is from HPD pin
// 11 = HPD is always high
16'h4110, // Power Down control
16'h9A70, // ADI required Write.
16'h9C30, // ADI required Write.
{8'h9D, 8'b0110_0001}, // [7:4] must be b0110!.
// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
// [1:0] must be b01!
16'hA2A4, // ADI required Write.
16'hA3A4, // ADI required Write.
16'hE0D0, // ADI required Write.
16'h35_40,
16'h36_D9,
16'h37_0A,
16'h38_00,
16'h39_2D,
16'h3A_00,
{8'h16, 8'b0011_1000}, // Output Format 444 [7]=0.
// [6] must be 0!
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
// DDR Input Edge falling [1]=0 (not using DDR atm).
// Output Colour Space RGB [0]=0.
{8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
{8'h18, 8'b0100_0110}, // CSC disabled [7]=0.
// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
// CSC Equation 3 [4:0] b00110.
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
16'h4000, // General Control Packet Enable
{8'h48, 8'b0000_1000}, // [6]=0 Normal bus order!
// [5] DDR Alignment.
// [4:3] b01 Data right justified (for YCbCr 422 input modes).
16'h49A8, // ADI required Write.
16'h4C00, // ADI required Write.
{8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
// AVI InfoFrame Valid [4].
// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
16'h7301,
{8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
16'h9902, // ADI required Write.
16'h9B18, // ADI required Write.
16'h9F00, // ADI required Write.
{8'hA1, 8'b0000_0000}, // [6]=1 Monitor Sense Power Down DISabled.
16'hA408, // ADI required Write.
16'hA504, // ADI required Write.
16'hA600, // ADI required Write.
16'hA700, // ADI required Write.
16'hA800, // ADI required Write.
16'hA900, // ADI required Write.
16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write.
{8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
// [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [3:2] must be b01!
// [1]=1 HDMI Mode.
// [0] must be b0!
16'hB900, // ADI required Write.
{8'hBA, 8'b0110_0000}, // [7:5] Input Clock delay...
// b000 = -1.2ns.
// b001 = -0.8ns.
// b010 = -0.4ns.
// b011 = No delay.
// b100 = 0.4ns.
// b101 = 0.8ns.
// b110 = 1.2ns.
// b111 = 1.6ns.
16'hBB00, // ADI required Write.
16'hDE9C, // ADI required Write.
16'hE460, // ADI required Write.
16'hFA7D, // Nbr of times to search for good phase
// (Audio stuff on Programming Guide, Page 66)...
{8'h0A, 8'b0000_0000}, // [6:4] Audio Select. b000 = I2S.
// [3:2] Audio Mode. (HBR stuff, leave at 00!).
{8'h0B, 8'b0000_1110}, //
{8'h0C, 8'b0000_0100}, // [7] 0 = Use sampling rate from I2S stream. 1 = Use samp rate from I2C Register.
// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
// [2] 1 = I2S0 Enable.
// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
{8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified.
{8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits.
{8'h15, audio_96k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
// Audio Clock Config
16'h0100, //
audio_96k ? 16'h0230 : 16'h0218, // Set N Value 12288/6144
16'h0300, //
16'h0701, //
16'h0822, // Set CTS Value 74250
16'h090A, //
16'hFFFF // END
};
////////////////////////////////////////////////////////////////////
endmodule

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//============================================================================
//
// HDMI Lite output module
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
//============================================================================
module hdmi_lite
(
input reset,
input clk_video,
input ce_pixel,
input video_vs,
input video_de,
input [23:0] video_d,
input clk_hdmi,
input hdmi_hde,
input hdmi_vde,
output reg hdmi_de,
output [23:0] hdmi_d,
input [11:0] screen_w,
input [11:0] screen_h,
input quadbuf,
// 0-3 => scale 1-4
input [1:0] scale_x,
input [1:0] scale_y,
input scale_auto,
input clk_vbuf,
output [27:0] vbuf_address,
input [127:0] vbuf_readdata,
output [127:0] vbuf_writedata,
output [7:0] vbuf_burstcount,
output [15:0] vbuf_byteenable,
input vbuf_waitrequest,
input vbuf_readdatavalid,
output reg vbuf_read,
output reg vbuf_write
);
localparam [7:0] burstsz = 64;
reg [1:0] nbuf = 0;
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
wire [95:0] hf_out;
wire [7:0] hf_usedw;
reg hf_reset = 0;
vbuf_fifo out_fifo
(
.aclr(hf_reset),
.wrclk(clk_vbuf),
.wrreq(vbuf_readdatavalid),
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
.wrusedw(hf_usedw),
.rdclk(~clk_hdmi),
.rdreq(hf_rdreq),
.q(hf_out)
);
reg [11:0] rd_stride;
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
reg [27:0] vbuf_raddress;
reg [7:0] vbuf_rburstcount;
always @(posedge clk_vbuf) begin
reg [18:0] rdcnt;
reg [7:0] bcnt;
reg vde1, vde2;
reg [1:0] mcnt;
reg [1:0] my;
reg [18:0] fsz;
reg [11:0] strd;
vde1 <= hdmi_vde;
vde2 <= vde1;
if(vbuf_readdatavalid) begin
rdcnt <= rdcnt + 1'd1;
if(bcnt) bcnt <= bcnt - 1'd1;
vbuf_raddress <= vbuf_raddress + 1'd1;
end
if(!bcnt && reading) reading <= 0;
vbuf_read <= 0;
if(~vbuf_waitrequest) begin
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
vbuf_read <= 1;
reading <= 1;
bcnt <= rd_burst;
vbuf_rburstcount <= rd_burst;
rd_stride <= rd_stride - rd_burst;
if(!(rd_stride - rd_burst)) rd_stride <= strd;
if(!rdcnt) begin
vbuf_raddress <= read_buf;
mcnt <= my;
end
else if (rd_stride == strd) begin
mcnt <= mcnt - 1'd1;
if(!mcnt) mcnt <= my;
else vbuf_raddress <= vbuf_raddress - strd;
end
end
end
hf_reset <= 0;
if(vde2 & ~vde1) begin
hf_reset <= 1;
rdcnt <= 0;
bcnt <= 0;
rd_stride <= stride;
strd <= stride;
fsz <= framesz;
my <= mult_y;
end
end
reg [11:0] off_x, off_y;
reg [11:0] x, y;
reg [11:0] vh_height;
reg [11:0] vh_width;
reg [1:0] pcnt;
reg [1:0] hload;
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
wire de_in = hdmi_hde & hdmi_vde;
always @(posedge clk_hdmi) begin
reg [71:0] px_out;
reg [1:0] mx;
reg vde;
vde <= hdmi_vde;
if(vde & ~hdmi_vde) begin
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
vh_height <= v_height;
vh_width <= v_width;
mx <= mult_x;
end
pcnt <= pcnt + 1'd1;
if(pcnt == mx) begin
pcnt <= 0;
hload <= hload + 1'd1;
end
if(~de_in || x<off_x || y<off_y) begin
hload <= 0;
pcnt <= 0;
end
hdmi_de <= de_in;
x <= x + 1'd1;
if(~hdmi_de & de_in) x <= 0;
if(hdmi_de & ~de_in) y <= y + 1'd1;
if(~hdmi_vde) y <= 0;
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
end
//////////////////////////////////////////////////////////////////////////////
reg reading = 0;
reg writing = 0;
reg op_split = 0;
always @(posedge clk_vbuf) op_split <= ~op_split;
wire allow_rd = ~reading & ~writing & op_split & ~reset;
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
//////////////////////////////////////////////////////////////////////////////
reg vf_rdreq = 0;
wire [95:0] vf_out;
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
vbuf_fifo in_fifo
(
.aclr(video_vs),
.rdclk(clk_vbuf),
.rdreq(vf_rdreq & ~vbuf_waitrequest),
.q(vf_out),
.wrclk(clk_video),
.wrreq(infifo_wr),
.data({video_de ? video_d : 24'd0, pix_acc})
);
assign vbuf_byteenable = '1;
reg [35:0] addrque[3:0] = '{0,0,0,0};
reg [7:0] flush_size;
reg [27:0] flush_addr;
reg flush_req = 0;
reg flush_ack = 0;
reg [27:0] vbuf_waddress;
reg [7:0] vbuf_wburstcount;
always @(posedge clk_vbuf) begin
reg [7:0] ibcnt = 0;
reg reqd = 0;
reqd <= flush_req;
if(~vbuf_waitrequest) begin
vbuf_write <= vf_rdreq;
if(~vf_rdreq && writing) writing <= 0;
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
ibcnt <= addrque[0][7:0];
addrque[0] <= addrque[1];
addrque[1] <= addrque[2];
addrque[2] <= addrque[3];
addrque[3] <= 0;
vf_rdreq <= 1;
writing <= 1;
end
else if(flush_ack != reqd) begin
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
flush_ack <= reqd;
end
if(vf_rdreq) begin
if(ibcnt == 1) vf_rdreq <= 0;
ibcnt <= ibcnt - 1'd1;
end
end
end
reg [11:0] stride;
reg [18:0] framesz;
reg [11:0] v_height;
reg [11:0] v_width;
reg [1:0] mult_x;
reg [1:0] mult_y;
reg [71:0] pix_acc;
wire pix_wr = ce_pixel && video_de;
reg [27:0] cur_addr;
reg [11:0] video_x;
reg [11:0] video_y;
wire infifo_tail = ~video_de && video_x[1:0];
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
wire [23:0] t_fsz = l1_stride * t_height;
reg [11:0] l1_width;
reg [11:0] l1_stride;
always @(posedge clk_video) begin
reg [7:0] loaded = 0;
reg [11:0] strd = 0;
reg old_de = 0;
reg old_vs = 0;
old_vs <= video_vs;
if(~old_vs & video_vs) begin
cur_addr<= write_buf;
video_x <= 0;
video_y <= 0;
loaded <= 0;
strd <= 0;
nbuf <= nbuf + 1'd1;
stride <= l1_stride;
framesz <= t_fsz[18:0];
v_height<= t_height;
v_width <= t_width;
mult_x <= tmf_x;
mult_y <= tmf_y;
end
if(pix_wr) begin
case(video_x[1:0])
0: pix_acc <= video_d; // zeroes upper bits too
1: pix_acc[47:24] <= video_d;
2: pix_acc[71:48] <= video_d;
3: loaded <= loaded + 1'd1;
endcase
if(video_x<screen_w) video_x <= video_x + 1'd1;
end
old_de <= video_de;
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
if(loaded + infifo_tail) begin
flush_size <= loaded + infifo_tail;
flush_addr <= cur_addr;
flush_req <= ~flush_req;
loaded <= 0;
strd <= strd + loaded;
end
cur_addr <= cur_addr + loaded + infifo_tail;
if(~video_de) begin
if(video_y<screen_h) video_y <= video_y + 1'd1;
video_x <= 0;
strd <= 0;
// measure width by first line (same as VIP)
if(!video_y) begin
l1_width <= video_x;
l1_stride <= strd + loaded + infifo_tail;
end
end
end
end
endmodule
module vbuf_fifo
(
input aclr,
input rdclk,
input rdreq,
output [95:0] q,
input wrclk,
input wrreq,
input [95:0] data,
output [7:0] wrusedw
);
dcfifo dcfifo_component
(
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.wrusedw (wrusedw),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 96,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

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