290 lines
13 KiB
VHDL
290 lines
13 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: keymatrix.vhd
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-- Created: July 2018
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-- Author(s): Philip Smart
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-- Description: Keyboard module to convert PS2 key codes into Sharp scan matrix key connections.
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-- For each scan output (10 lines) sent by the Sharp, an 8bit response is read in
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-- and the bits set indicate keys pressed. This allows for multiple keys to be pressed
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-- at the same time. The PS2 scan code is mapped via a rom and the output is used to drive
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-- the data in lines of the 8255.
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--
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-- Credits: Nibbles Lab (c) 2005-2012
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-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2018 - Initial module written, originally based on the Nibbles Lab code but
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-- rewritten to match the overall design of this emulation.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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library pkgs;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use pkgs.clkgen_pkg.all;
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use pkgs.mctrl_pkg.all;
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entity keymatrix is
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Port (
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RST_n : in std_logic;
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-- i8255
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PA : in std_logic_vector(3 downto 0);
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PB : out std_logic_vector(7 downto 0);
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STALL : in std_logic;
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-- PS/2 Keyboard Data
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PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
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-- Different operations modes.
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CONFIG : in std_logic_vector(CONFIG_WIDTH);
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-- Clock signals used by this module.
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CLKBUS : in std_logic_vector(CLKBUS_WIDTH);
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-- HPS Interface
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IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
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IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
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IOCTL_CLK : in std_logic; -- HPS I/O Clock.
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IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
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IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
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IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
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IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
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IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
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);
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end keymatrix;
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architecture Behavioral of keymatrix is
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--
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-- prefix flag
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--
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signal FLGF0 : std_logic;
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signal FLGE0 : std_logic;
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--
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-- MZ-series matrix registers
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--
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signal SCAN00 : std_logic_vector(7 downto 0);
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signal SCAN01 : std_logic_vector(7 downto 0);
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signal SCAN02 : std_logic_vector(7 downto 0);
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signal SCAN03 : std_logic_vector(7 downto 0);
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signal SCAN04 : std_logic_vector(7 downto 0);
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signal SCAN05 : std_logic_vector(7 downto 0);
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signal SCAN06 : std_logic_vector(7 downto 0);
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signal SCAN07 : std_logic_vector(7 downto 0);
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signal SCAN08 : std_logic_vector(7 downto 0);
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signal SCAN09 : std_logic_vector(7 downto 0);
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signal SCAN10 : std_logic_vector(7 downto 0);
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signal SCAN11 : std_logic_vector(7 downto 0);
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signal SCAN12 : std_logic_vector(7 downto 0);
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signal SCAN13 : std_logic_vector(7 downto 0);
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signal SCAN14 : std_logic_vector(7 downto 0);
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signal SCANLL : std_logic_vector(7 downto 0);
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--
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-- Key code exchange table
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--
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signal MTEN : std_logic_vector(3 downto 0);
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signal F_KBDT : std_logic_vector(7 downto 0);
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signal MAP_DATA : std_logic_vector(7 downto 0);
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signal MAP_ADDR : std_logic_vector(7 downto 0);
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signal KEY_BANK : std_logic_vector(2 downto 0);
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--
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-- HPS access
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--
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signal IOCTL_KEYMAP_WEN : std_logic;
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signal IOCTL_DIN_KEYMAP : std_logic_vector(7 downto 0); -- HPS Data to be read into HPS.
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signal KEY_EXTENDED : std_logic;
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signal KEY_FLAG : std_logic;
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signal KEY_PRESS : std_logic;
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signal KEY_VALID : std_logic;
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--
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-- Components
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--
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component dprom
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GENERIC (
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init_file : string;
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widthad_a : natural;
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width_a : natural
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);
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PORT
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(
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address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock_a : IN STD_LOGIC ;
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clock_b : IN STD_LOGIC ;
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-- data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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-- wren_a : IN STD_LOGIC;
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wren_b : IN STD_LOGIC;
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q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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end component;
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begin
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--
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-- Instantiation
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--
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-- 0 = MZ80K KEYMAP = 256Bytes -> 0000:00ff 0000 bytes padding
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-- 1 = MZ80C KEYMAP = 256Bytes -> 0100:01ff 0000 bytes padding
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-- 2 = MZ1200 KEYMAP = 256Bytes -> 0200:02ff 0000 bytes padding
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-- 3 = MZ80A KEYMAP = 256Bytes -> 0300:03ff 0000 bytes padding
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-- 4 = MZ700 KEYMAP = 256Bytes -> 0400:04ff 0000 bytes padding
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-- 5 = MZ80B KEYMAP = 256Bytes -> 0500:05ff 0000 bytes padding
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MAP0 : dprom
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GENERIC MAP (
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--init_file => "./mif/key_80k_80b.mif",
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init_file => "./mif/combined_keymap.mif",
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widthad_a => 11,
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width_a => 8
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)
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PORT MAP (
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clock_a => CLKBUS(CKCPU),
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address_a => KEY_BANK & F_KBDT,
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-- data_a => IOCTL_DOUT(7 DOWNTO 0),
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-- wren_a =>
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q_a => MAP_DATA,
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clock_b => IOCTL_CLK,
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address_b => IOCTL_ADDR(10 DOWNTO 0),
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data_b => IOCTL_DOUT(7 DOWNTO 0),
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wren_b => IOCTL_KEYMAP_WEN,
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q_b => IOCTL_DIN_KEYMAP
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);
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-- Store changes to the key valid flag in a flip flop.
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process( CLKBUS(CKCPU) ) begin
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if rising_edge(CLKBUS(CKCPU)) then
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KEY_FLAG <= PS2_KEY(10);
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end if;
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end process;
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KEY_PRESS <= PS2_KEY(9);
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KEY_EXTENDED <= PS2_KEY(8);
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KEY_VALID <= '1' when KEY_FLAG /= PS2_KEY(10) else '0';
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KEY_BANK <= "000" when CONFIG(MZ80K) = '1' else -- Key map for MZ80K
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"001" when CONFIG(MZ80C) = '1' else -- Key map for MZ80C
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"010" when CONFIG(MZ1200) = '1' else -- Key map for MZ1200
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"011" when CONFIG(MZ80A) = '1' else -- Key map for MZ80A
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"100" when CONFIG(MZ700) = '1' else -- Key map for MZ700
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"101" when CONFIG(MZ800) = '1' else -- Key map for MZ800
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"110" when CONFIG(MZ80B) = '1' else -- Key map for MZ80B
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"111" when CONFIG(MZ2000) = '1'; -- Key map for MZ2000
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--
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-- Convert
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--
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process( RST_n, CLKBUS(CKCPU) ) begin
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if RST_n = '0' then
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SCAN00 <= (others=>'0');
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SCAN01 <= (others=>'0');
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SCAN02 <= (others=>'0');
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SCAN03 <= (others=>'0');
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SCAN04 <= (others=>'0');
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SCAN05 <= (others=>'0');
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SCAN06 <= (others=>'0');
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SCAN07 <= (others=>'0');
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SCAN08 <= (others=>'0');
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SCAN09 <= (others=>'0');
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SCAN10 <= (others=>'0');
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SCAN11 <= (others=>'0');
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SCAN12 <= (others=>'0');
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SCAN13 <= (others=>'0');
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SCAN14 <= (others=>'0');
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FLGF0 <= '0';
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FLGE0 <= '0';
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MTEN <= (others=>'0');
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MAP_ADDR <= (others=>'1');
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elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then
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MTEN <= MTEN(2 downto 0) & KEY_VALID;
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if KEY_VALID='1' then
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if(KEY_EXTENDED='1') then
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FLGE0 <= '1';
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end if;
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if(KEY_PRESS='0') then
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FLGF0 <= '1';
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end if;
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if(PS2_KEY(7 downto 0) = X"AA" ) then
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F_KBDT <= X"EF";
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else
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F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0';
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end if;
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end if;
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if MTEN(3)='1' then
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case MAP_DATA(7 downto 4) is
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when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0;
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when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
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end case;
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end if;
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end if;
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end process;
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PA_L : for I in 0 to 7 generate
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SCANLL(I) <= SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I) or
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SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I) or
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SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
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end generate PA_L;
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--
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-- response from key access
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--
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PB <= (not SCANLL) when STALL='0' and CONFIG(MZ_B)='1' else
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(not SCAN00) when PA="0000" else
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(not SCAN01) when PA="0001" else
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(not SCAN02) when PA="0010" else
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(not SCAN03) when PA="0011" else
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(not SCAN04) when PA="0100" else
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(not SCAN05) when PA="0101" else
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(not SCAN06) when PA="0110" else
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(not SCAN07) when PA="0111" else
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(not SCAN08) when PA="1000" else
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(not SCAN09) when PA="1001" else
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(not SCAN10) when PA="1010" else
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(not SCAN11) when PA="1011" else
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(not SCAN12) when PA="1100" else
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(not SCAN13) when PA="1101" else (others=>'1');
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--
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-- HPS access to reload keymap.
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--
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IOCTL_KEYMAP_WEN <= '1' when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_WR = '1'
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else '0';
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IOCTL_DIN <= X"00" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_RD = '1'
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else
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(others=>'0');
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end Behavioral;
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