162 lines
5.7 KiB
VHDL
162 lines
5.7 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: i8253.vhd
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-- Created: July 2018
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-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart
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-- Description: Sharp MZ series i8253 PIT
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-- This module emulates the Intel i8253 Programmable Interval Timer.
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--
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-- Credits:
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-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart <philip.smart@net2net.org>
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--
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-- History: July 2018 - Initial module refactored and updated for this emulation.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity i8253 is
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Port (
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RST : in std_logic;
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CLK : in std_logic;
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A : in std_logic_vector(1 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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CS_n : in std_logic;
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WR_n : in std_logic;
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RD_n : in std_logic;
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CLK0 : in std_logic;
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GATE0 : in std_logic;
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OUT0 : out std_logic;
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CLK1 : in std_logic;
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GATE1 : in std_logic;
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OUT1 : out std_logic;
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CLK2 : in std_logic;
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GATE2 : in std_logic;
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OUT2 : out std_logic
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);
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end i8253;
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architecture Behavioral of i8253 is
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signal WRD0 : std_logic;
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signal WRD1 : std_logic;
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signal WRD2 : std_logic;
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signal WRM0 : std_logic;
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signal WRM1 : std_logic;
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signal WRM2 : std_logic;
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--signal RD0 : std_logic;
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signal RD1 : std_logic;
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signal RD2 : std_logic;
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signal DO0 : std_logic_vector(7 downto 0);
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signal DO1 : std_logic_vector(7 downto 0);
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signal DO2 : std_logic_vector(7 downto 0);
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component counter0
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Port (
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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WRD : in std_logic;
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WRM : in std_logic;
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KCLK : in std_logic;
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CLK : in std_logic;
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GATE : in std_logic;
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POUT : out std_logic
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);
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end component;
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component counter1
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Port (
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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WRD : in std_logic;
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WRM : in std_logic;
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KCLK : in std_logic;
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CLK : in std_logic;
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GATE : in std_logic;
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POUT : out std_logic
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);
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end component;
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component counter2
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Port (
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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WRD : in std_logic;
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WRM : in std_logic;
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KCLK : in std_logic;
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RD : in std_logic;
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CLK : in std_logic;
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GATE : in std_logic;
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POUT : out std_logic
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);
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end component;
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begin
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WRD0 <= WR_n when CS_n='0' and A="00" else '1';
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WRD1 <= WR_n when CS_n='0' and A="01" else '1';
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WRD2 <= WR_n when CS_n='0' and A="10" else '1';
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WRM0 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="00" else '1';
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WRM1 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="01" else '1';
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WRM2 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="10" else '1';
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-- RD0 <= RD_n when CS_n='0' and A="00" else '1';
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RD1 <= RD_n when CS_n='0' and A="01" else '1';
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RD2 <= RD_n when CS_n='0' and A="10" else '1';
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DO <= DO0 when CS_n='0' and A="00" else
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DO1 when CS_n='0' and A="01" else
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DO2 when CS_n='0' and A="10" else (others=>'1');
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CTR0 : counter0 port map (
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DI => DI,
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DO => DO0,
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WRD => WRD0,
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WRM => WRM0,
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KCLK => CLK,
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CLK => CLK0,
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GATE => GATE0,
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POUT => OUT0
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);
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CTR1 : counter1 port map (
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DI => DI,
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DO => DO1,
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WRD => WRD1,
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WRM => WRM1,
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KCLK => CLK,
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CLK => CLK1,
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GATE => GATE1,
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POUT => OUT1
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);
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CTR2 : counter2 port map (
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DI => DI,
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DO => DO2,
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WRD => WRD2,
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WRM => WRM2,
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KCLK => CLK,
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RD => RD2,
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CLK => CLK2,
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GATE => GATE2,
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POUT => OUT2
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);
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end Behavioral;
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