commit 0acc4dfbf05679c4342b6f6bc2a477071d8e5cff Author: root Date: Fri Sep 28 17:04:36 2018 +0100 Initial commit diff --git a/asm/1Z-013A.asm b/asm/1Z-013A.asm new file mode 100644 index 0000000..235e5a3 --- /dev/null +++ b/asm/1Z-013A.asm @@ -0,0 +1,3281 @@ + ; MONITOR PROGRAM 1Z-013A + ; (MZ700) FOR PAL + ; REV. 83.4.7 + ; Tuesday, 02 of June 1998 at 10:02 PM + ; Tuesday, 09 of June 1998 at 07:17 AM +; Configurable parameters. These are set in the wrapper file, ie monitor_SA1510.asm +; +;COLW: EQU 40 ; Width of the display screen (ie. columns). +;ROW: EQU 25 ; Number of rows on display screen. +;SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. + + ORG 0000h ; 0000h Entrypoint +MONIT: JP START ; MONITOR ON +GETL: JP QGETL ; GET LINE (END "CR") +LETNL: JP QLTNL ; NEW LINE +NL: JP QNL ; +PRNTS: JP QPRTS ; PRINT SPACE +PRNTT: JP QPRTT ; PRINT TAB +PRNT: JP QPRNT ; 1 CHARACTER PRINT +MSG: JP QMSG ; 1 LINE PRINT (END "0DH") +MSGX: JP QMSGX ; RST 18H +GETKY: JP QGET ; GET KEY +BRKEY: JP QBRK ; GET BREAK +WRINF: JP QWRI ; WRITE INFORMATION +WRDAT: JP QWRD ; WRITE DATA +RDINF: JP QRDI ; READ INFORMATION +RDDAT: JP QRDD ; READ DATA +VERFY: JP QVRFY ; VERIFYING CMT +MELDY: JP QMLDY ; RST 30H +TIMST: JP QTMST ; TIME SET + NOP + NOP + JP 1038H ; INTERRUPT ROUTINE (8253) +TIMRD: JP QTMRD ; TIME READ +BELL: JP QBEL ; BELL ON +XTEMP: JP QTEMP ; TEMPO SET (1 - 7) +MSTA: JP MLDST ; MELODY START +MSTP: JP MLDSP ; MELODY STOP + +START: LD SP,SPV ; STACK SET (10F0H) + IM 1 ; IM 1 SET + CALL QMODE ; 8255 MODE SET + CALL QBRK ; CTRL ? + JR NC,ST0 + CP 20H ; KEY IS CTRL KEY + JR NZ,ST0 +CMY0: OUT (0E1H),A ; D000-FFFFH IS DRAM + LD DE,0FFF0H ; TRANS. ADR. + LD HL,DMCP ; MEMORY CHANG PROGRAM + LD BC,05H ; BYTE SIZE + LDIR + JP 0FFF0H ; JUMP $FFF0 + +DMCP: OUT (0E0H),A ; 0000H-0FFFH IS DRAM + JP 0000H + +ST0: LD B,0FFH ; BUFFER CLEAR + LD HL,NAME ; 10F1H-11F0H CLEAR + CALL QCLER + LD A,16H ; LASTER CLR. + CALL PRNT + LD A,71H ; BACK:BLUE CHA.:WRITE + LD HL,0D800H ; COLOR ADDRESS + CALL NCLR8 + LD HL,TIMIN ; INTERRUPT JUMP ROUTINE + LD A,0C3H + LD (1038H),A + LD (1039H),HL + LD A,04H ; NORMAL TEMPO + LD (TEMPW),A + CALL MLDSP ; MELODY STOP + CALL NL + LD DE,MSGQ3 ; ** MONITOR 1Z-013A ** + RST 18H ; CALL MGX + CALL QBEL +SS: LD A,01H + LD (SWRK),A ; KEY IN SILENT + LD HL,0E800H ; USR ROM? + LD (HL),A ; ROM CHECK + JR FD2 + +ST1: CALL NL + LD A,2AH ; "*" PRINT + CALL PRNT + LD DE,BUFER ; GET LINE WORK (11A3H) + CALL GETL +ST2: LD A,(DE) + INC DE + CP 0DH + JR Z,ST1 + CP 'J' ; JUMP + JR Z,GOTO + CP 'L' ; LOAD PROGRAM + JR Z,LOAD + CP 'F' ; FLOPPY ACCESS + JR Z,FD + CP 'B' ; KEY IN BELL + JR Z,SG + CP '#' ; CHANG MEMORY + JR Z,CMY0 + CP 'P' ; PRINTER TEST + JR Z,PTEST + CP 'M' ; MEMORY CORRECTION + JP Z,MCOR + CP 'S' ; SAVE DATA + JP Z,SAVE + CP 'V' ; VERIFYING DATA + JP Z,VRFY + CP 'D' ; DUMP DATA + JP Z,DUMP + NOP + NOP + NOP + NOP + JR ST2 ; NO COMMAND + + ; JUMP COMMAND + +GOTO: CALL HEXIY + JP (HL) + + ; KEY SOUND ON/OFF + +SG: LD A,(SWRK) ; D0=SOUND WORK + RRA + CCF ; CHANGE MODE + RLA + JR SS+2 + + ; FLOPPY + +FD: LD HL,0F000H ; FLOPPY I/O CHECK +FD2: LD A,(HL) + OR A + JR NZ,ST1 +FD1: JP (HL) + + ; ERROR (LOADING) + +QER: CP 02H ; A=02H : BREAK IN + JR Z,ST1 + LD DE,MSGE1 ; CHECK SUM ERROR + RST 18H ; CALL MSGX +L010F: JR ST1 + + ; LOAD COMMAND + +LOAD: CALL QRDI + JR C,QER +LOA0: CALL NL + LD DE,MSGQ2 ; LOADING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + CALL QRDD + JR C,QER + LD HL,(EXADR) ; EXECUTE ADDRESS + LD A,H + CP 12H ; EXECUTE CHECK + JR C,L010F + JP (HL) + + ; GETLINE AND BREAK IN CHECK + ; + ; EXIT BREAK IN THEN JUMP (ST1) + ; ACC=TOP OF LINE DATA + +BGETL: EX (SP),HL + POP BC ; STACK LOAD + LD DE,BUFER ; MONITOR GETLINE BUFF + CALL GETL + LD A,(DE) + CP 1BH ; BREAK CODE + JR Z,L010F ; JP Z,ST1 + JP (HL) + + ; ASCII TO HEX CONVERT + ; INPUT (DE)=ASCII + ; CY=1 THEN JUMP (ST1) + +HEXIY: EX (SP),IY + POP AF + CALL HLHEX + JR C,L010F ; JP C,ST1 + JP (IY) + +MSGE1: DB "CHECK SUM ER.\r" + + ; PLOTTER PRINTER TEST COMMAND + ; (DPG23) + ; &=CONTROL COMMANDS GROUP + ; C=PEN CHANGE + ; G=GRAPH MODE + ; S=80 CHA. IN 1 LINE + ; L=40 CHA. IN 1 LINE + ; T=PLOTTER TEST + ; IN (DE)=PRINT DATA + +PTEST: LD A,(DE) + CP '&' + JR NZ,PTST1 +PTST0: INC DE + LD A,(DE) + CP 'L' ; 40 IN 1 LINE + JR Z,PLPT + CP 'S' ; 80 IN 1 LINE + JR Z,PPLPT + CP 'C' ; PEN CHANGE + JR Z,PEN + CP 'G' ; GRAPH MODE + JR Z,PLOT + CP 'T' ; TEST + JR Z,PTRN +PTST1: CALL PMSG ; PLOT MESSAGE + JP ST1 + +PLPT: LD DE,LLPT ; 01-09-09-0B-0D + JR PTST1 + +PPLPT: LD DE,SLPT ; 01-09-09-09-0D + JR PTST1 + +PTRN: LD A,04H ; TEST PATTERN + JR PLOT+2 + +PLOT: LD A,02H ; GRAPH CODE + CALL LPRNT + JR PTST0 + +PEN: LD A,1DH ; 1 CHANGE CODE (TEXT MODE) + JR PLOT+2 + + ; 1CHA. PRINT TO $LPT + ; IN: ACC PRINT DATA + +LPRNT: LD C,0 ; RDA TEST (READY? RDA=0) + LD B,A ; PRINT DATA STORE + CALL RDA + LD A,B + OUT (0FFH),A ; DATA OUT + LD A,80H ; RDP HIGH + OUT (0FEH),A + LD C,01H ; RDA TEST + CALL RDA + XOR A ; RDP LOW + OUT (0FEH),A + RET + + ; $LPT MSG + ; IN: DE DATA LOW ADDRESS + ; 0DH MSG END + +PMSG: PUSH DE + PUSH BC + PUSH AF +PMSG1: LD A,(DE) ; ACC=DATA + CALL LPRNT + LD A,(DE) + INC DE + CP 0DH ; END? + JR NZ,PMSG1 + POP AF + POP BC + POP DE + RET + + ; RDA CHECK + ; BRKEY IN TO MONITOR RETURN + ; IN: C RDA CODE + +RDA: IN A,(0FEH) + AND 0DH ; RDA ONLY + CP C + RET Z + CALL BRKEY + JR NZ,RDA + LD SP,SPV + JP ST1 + + ; MELODY + ; DE=DATA LOW ADDRESS + ; EXIT CF=1 BREAK + ; CF=0 OK + +QMLDY: PUSH BC + PUSH DE + PUSH HL + LD A,02H + LD (OCTV),A + LD B,01H +MLD1: LD A,(DE) + CP 0DH ; CR + JR Z,MLD4 + CP 0C8H ; END MARK + JR Z,MLD4 + CP 0CFH ; UNDER OCTAVE + JR Z,MLD2 + CP 2DH ; "-" + JR Z,MLD2 + CP 2BH ; "+" + JR Z,MLD3 + CP 0D7H ; UPPER OCTAVE + JR Z,MLD3 + CP 23H ; "#" HANON + LD HL,MTBL + JR NZ,L01F5 + LD HL,MNTBL + INC DE +L01F5: CALL ONPU ; ONTYO SET + JR C,MLD1 + CALL RYTHM + JR C,MLD5 + CALL MLDST ; MELODY START + LD B,C + JR MLD1 + +MLD2: LD A,3 +L0207: LD (OCTV),A + INC DE + JR MLD1 + +MLD3: LD A,01H + JR L0207 + +MLD4: CALL RYTHM +MLD5: PUSH AF + CALL MLDSP + POP AF + JP RET3 + + ; ONPU TO RATIO CONV + ; EXIT (RATIO)=RATIO VALUE + ; C=ONTYO*TEMPO + +ONPU: PUSH BC + LD B,8 +ONP1: LD A,(DE) +L0220: CP (HL) + JR Z,ONP2 + INC HL + INC HL + INC HL + DJNZ L0220 + SCF + INC DE + POP BC + RET + +ONP2: INC HL + PUSH DE + LD E,(HL) + INC HL + LD D,(HL) + EX DE,HL + LD A,H + OR A + JR Z,L023F + LD A,(OCTV) ; 11A0H OCTAVE WORK +L0239: DEC A + JR Z,L023F + ADD HL,HL + JR L0239 + +L023F: LD (RATIO),HL ; 11A1H ONPU RATIO + LD HL,OCTV + LD (HL),02H + DEC HL + POP DE + INC DE + LD A,(DE) + LD B,A + AND 0F0H ; ONTYO ? + CP 30H + JR Z,L0255 + LD A,(HL) ; HL=ONTYO + JR L025A + +L0255: INC DE + LD A,B + AND 0FH + LD (HL),A ; HL=ONTYO +L025A: LD HL,OPTBL + ADD A,L + LD L,A + LD C,(HL) + LD A,(TEMPW) + LD B,A + XOR A +ONP3: ADD A,C + DJNZ ONP3 + POP BC + LD C,A + XOR A + RET + +MTBL: DB "C" + DW 0846H + DB "D" + DW 075FH + DB "E" + DW 0691H + DB "F" + DW 0633H + DB "G" + DW 0586H + DB "A" + DW 04ECH + DB "B" + DW 0464H + DB "R" + DW 0000H +MNTBL: DB "C" ; #C + DW 07CFH + DB "D" ; #D + DW 06F5H + DB "E" ; #E + DW 0633H + DB "F" ; #F + DW 05DAH + DB "G" ; #G + DW 0537H + DB "A" ; #A + DW 04A5H + DB "B" ; #B + DW 0423H + DB "R" ; #R + DW 0000H +OPTBL: DB 01H + DB 02H + DB 03H + DB 04H + DB 06H + DB 08H + DB 0CH + DB 10H + DB 18H + DB 20H + + ; INCREMENT DE REG. + +P4DE: INC DE + INC DE + INC DE + INC DE + RET + + ; MELODY START & STOP + +MLDST: LD HL,(RATIO) + LD A,H + OR A + JR Z,MLDSP + PUSH DE + EX DE,HL + LD HL,CONT0 + LD (HL),E + LD (HL),D + LD A,01H + POP DE + JR MLDS1 + +MLDSP: LD A,36H ; MODE SET (8253 C0) + LD (CONTF),A ; E007H + XOR A +MLDS1: LD (SUNDG),A ; E008H + RET ; TEHRO SET + + ; RHYTHM + ; B=COUNT DATA + ; IN + ; EXIT CF=1 BREAK + ; CF=0 OK + +RYTHM: LD HL,KEYPA ; E000H + LD (HL),0F8H + INC HL + LD A,(HL) + AND 81H ; BREAK IN CHECK + JR NZ,L02D5 + SCF + RET + +L02D5: LD A,(TEMP) ; E008H + RRCA ; TEMPO OUT + JR C,L02D5 +L02DB: LD A,(TEMP) + RRCA + JR NC,L02DB + DJNZ L02D5 + XOR A + RET + + ; TEMPO SET + ; ACC=VALUE (1-7) + +QTEMP: PUSH AF + PUSH BC + AND 0FH + LD B,A + LD A,8 + SUB B + LD (TEMPW),A + POP BC + POP AF + RET + + ; CRT MANAGEMENT + ; EXIT HL:DSPXY H=Y,L=X + ; DE:MANG ADR. (ON DSPXY) + ; A :MANG DATA + ; CY:MANG=1 + +PMANG: LD HL,MANG ; CRT MANG POINTER + LD A,(1172H) ; DSPXY+1 + ADD A,L + LD L,A + LD A,(HL) + INC HL + RL (HL) + OR (HL) + RR (HL) + RRCA + EX DE,HL + LD HL,(DSPXY) + RET + + ; TIME SET + ; ACC=0 : AM + ; =1 : PM + ; DE=SEC: BINARY + +QTMST: DI + PUSH BC + PUSH DE + PUSH HL + LD (AMPM),A ; AMPM DATA + LD A,0F0H + LD (TIMFG),A ; TIME FLAG + LD HL,0A8C0H ; 12 HOURS (43200 SECONDS) + XOR A + SBC HL,DE ; COUNT DATA = 12H-IN DATA + PUSH HL + NOP + EX DE,HL + LD HL,CONTF ; E007H + LD (HL),74H ; C1 + LD (HL),0B0H ; C2 + DEC HL ; CONT2 + LD (HL),E ; E006H + LD (HL),D + DEC HL ; CONT1 + LD (HL),0AH ; E005H STROBE 640,6µSECONDS COUNT2 + LD (HL),0 + INC HL + INC HL ; CONTF + LD (HL),80H ; E007H + DEC HL ; CONT2 +QTMS1: LD C,(HL) ; E006H + LD A,(HL) + CP D + JR NZ,QTMS1 + LD A,C + CP E + JR NZ,QTMS1 + DEC HL ; E005H + NOP + NOP + NOP + LD (HL),0FBH ; 1 SECOND (15611HZ) E005H + LD (HL),3CH + INC HL + POP DE +QTMS2: LD C,(HL) ; E006H + LD A,(HL) + CP D + JR NZ,QTMS2 + LD A,C + CP E + JR NZ,QTMS2 + POP HL + POP DE + POP BC + EI + RET + + ; BELL DATA + ; +QBELD: DB 0D7H + DB "A0" + DB 0DH + NOP + NOP + + ; TIME READ + ; EXIT ACC=0 :AM + ; =1 :PM + ; DE=SEC. BINARY + +QTMRD: PUSH HL + LD HL,CONTF + LD (HL),80H ; E007H C2 + DEC HL ; CONT2 + DI + LD E,(HL) + LD D,(HL) ; e006H C2 MODE0 + EI +L0363: LD A,E + OR D + JR Z,QTMR1 + XOR A + LD HL,0A8C0H ; 12 HOURS + SBC HL,DE + JR C,QTMR2 + EX DE,HL + LD A,(AMPM) + POP HL + RET + +QTMR1: LD DE,0A8C0H +L0378: LD A,(AMPM) + XOR 01H + POP HL + RET + +QTMR2: DI + LD HL,CONT2 + LD A,(HL) + CPL + LD E,A + LD A,(HL) + CPL + LD D,A + EI + INC DE + JR L0378 + + ; TIME INTERRUPT + +TIMIN: PUSH AF + PUSH BC + PUSH DE + PUSH HL + LD HL,AMPM + LD A,(HL) + XOR 01H + LD (HL),A + LD HL,CONTF + LD (HL),80H ; CONT2 + DEC HL + PUSH HL + LD E,(HL) + LD D,(HL) + LD HL,0A8C0H + ADD HL,DE + DEC HL + DEC HL + EX DE,HL + POP HL + LD (HL),E + LD (HL),D + POP HL + POP DE + POP BC + POP AF + EI + RET + + ; SPACE PRINT AND DISP ACC + ; INPUT:HL=DISP. ADR. + +SPHEX: CALL QPRTS ; SPACE PRINT + LD A,(HL) + CALL PRTHX ; DSP OF ACC (ASCII) + LD A,(HL) + RET + + ; (ASCII PRINT) FOR HL + +PRTHL: LD A,H + CALL PRTHX + LD A,L + JR PRTHX + + NOP + NOP + + ; (ASCII PRINT) FOR ACC + +PRTHX: PUSH AF + RRCA + RRCA + RRCA + RRCA + CALL ASC + CALL PRNT + POP AF + CALL ASC + JP PRNT + + ; 80 CHA. 1 LINE CODE (DATA) + +SLPT: DB 01H ; TEXT MODE + DB 09H + DB 09H + DB 09H + DB 0DH + + ; HEXADECIMAL TO ASCII + ; IN : ACC (D3-D0)=HEXADECIMAL + ; EXIT: ACC = ASCII +ASC: AND 0FH + CP 0AH + JR C,NOADD + ADD A,07H +NOADD: ADD A,30H + RET + + ; ASCII TO HEXADECIMAL + ; IN : ACC = ASCII + ; EXIT: ACC = HEXADECIMAL + ; CY = 1 ERROR + +HEXJ: SUB 30H + RET C ; <0 + CP 0AH + CCF + RET NC ; 0-9 + SUB 07H + CP 10H + CCF + RET C + CP 0AH + RET + + NOP + NOP + NOP + NOP + +HEX: JR HEXJ + + ; PRESS PLAY MESSAGE + +MSGN1: DW 207FH +MSGN2: DB "PLAY\r" +MSGN3: DW 207FH + DB "RECORD.\r" ; PRESS RECORD + + NOP + NOP + NOP + NOP + + ; 4 ASCII TO (HL) + ; IN DE=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : OUT + +HLHEX: PUSH DE + CALL L2HEX + JR C,L041D + LD H,A + CALL L2HEX + JR C,L041D + LD L,A +L041D: POP DE + RET + + ; 2 ASCII TO (ACC) + ; IN DE=DATA LOW ADRRESS + ; EXIT CF=0 : OK + ; =1 : OUT + +L2HEX: PUSH BC + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + RRCA + RRCA + RRCA + RRCA + LD C,A + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + OR C +L0434: POP BC + RET + + ; WRITE INFORMATION + +QWRI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,0CCH ; "L" + LD HL,IBUFE ; 10F0H + LD BC,80H ; WRITE BYTE SIZE +WRI1: CALL CKSUM ; CHECK SUM + CALL MOTOR ; MOTOR ON + JR C,WRI3 + LD A,E + CP 0CCH ; "L" + JR NZ,WRI2 + CALL NL + PUSH DE + LD DE,MSGN7 ; WRITING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + POP DE +WRI2: CALL GAP + CALL WTAPE +WRI3: JP RET2 + +MSGN7: DB "WRITING \r" + + ; 40 CHA. IN 1 LINE CODE (DATA) + +LLPT: DB 01H ; TEXT MODE + DB 09H + DB 09H + DB 0BH + DB 0DH + + ; WRITE DATA + ; EXIT CF=0 : OK + ; =1 : BREAK + +QWRD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,53H ; "S" +L047D: LD BC,(SIZE) ; WRITE DATA BYTE SIZE + LD HL,(DTADR) ; WRITE DATA ADDRESS + LD A,B + OR C + JR Z,RET1 + JR WRI1 + + ; TAPE WRITE + ; BC=BYTE SIZE + ; HL=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : BREAK + +WTAPE: PUSH DE + PUSH BC + PUSH HL + LD D,02H + LD A,0F8H ; 88H WOULD BE BETTER!! + LD (KEYPA),A ; E000H +WTAP1: LD A,(HL) + CALL WBYTE ; 1 BYTE WRITE + LD A,(KEYPB) ; E001H + AND 81H ; SHIFT & BREAK + JP NZ,WTAP2 + LD A,02H ; BREAK IN CODE + SCF + JR WTAP3 + +WTAP2: INC HL + DEC BC + LD A,B + OR C + JP NZ,WTAP1 + LD HL,(SUMDT) ; SUM DATA SET + LD A,H + CALL WBYTE + LD A,L + CALL WBYTE + CALL LONG + DEC D + JP NZ,L04C2 + OR A + JP WTAP3 + +L04C2: LD B,0 +L04C4: CALL SHORT + DEC B + JP NZ,L04C4 + POP HL + POP BC + PUSH BC + PUSH HL + JP WTAP1 + +WTAP3: +RET1: POP HL + POP BC + POP DE + RET + + DB 2FH + DB 4EH + + ; READ INFORMATION (FROM $CMT) + ; EXIT ACC=0: OK CF=0 + ; =1: ER CF=1 + ; =2: BREAK CF=1 + +QRDI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H ; "R" + LD E,0CCH ; "L" + LD BC,80H + LD HL,IBUFE +RD1: CALL MOTOR + JP C,RTP6 + CALL TMARK + JP C,RTP6 + CALL RTAPE + JP RTP4 + + ; READ DATA (FROM $CMT) + ; EXIT SAME UP + +QRDD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H ; "R" + LD E,53H ; "S" + LD BC,(SIZE) + LD HL,(DTADR) + LD A,B + OR C + JP Z,RTP4 + JR RD1 + + ; READ TAPE + ; IN BC=SIZE + ; DE=LOAD ADDRESS + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK=1 + +RTAPE: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; TWICE WRITE +RTP1: LD BC,KEYPB + LD DE,CSTR +RTP2: CALL EDGE ; 1-->0 EDGE DETECT + JR C,RTP6 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) ; DATA (1 BIT) READ + AND 20H + JP Z,RTP2 + LD D,H + LD HL,0 + LD (SUMDT),HL + POP HL + POP BC + PUSH BC + PUSH HL +RTP3: CALL RBYTE ; 1 BYTE READ + JR C,RTP6 + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JR NZ,RTP3 + LD HL,(SUMDT) ; CHECK SUM + CALL RBYTE ; CHECK SUM DATA + JR C,RTP6 + LD E,A + CALL RBYTE ; CHECK SUM DATA + JR C,RTP6 + CP L + JR NZ,RTP5 + LD A,E + CP H + JR NZ,RTP5 +RTP8: XOR A +RTP4: +RET2: POP HL + POP BC + POP DE + CALL MSTOP + PUSH AF + LD A,(TIMFG) ; INT. CHECK + CP 0F0H + JR NZ,L0563 + EI +L0563: POP AF + RET + +RTP5: DEC D + JR Z,RTP7 + LD H,D + CALL GAPCK + JR RTP1 + +RTP7: LD A,01H + JR RTP9 + +RTP6: LD A,02H +RTP9: SCF + JR RTP4 + + ; BELL + +QBEL: PUSH DE + LD DE,QBELD + RST 30H ; CALL MELODY + POP DE + RET + + ; FLASHING AND KEYIN + ; EXIT: ACC INPUT KEY DATA (DSP.CODE) + ; H=F0H THEN NO KEYIN (Z FLAG) + +FLKEY: CALL QFLAS + CALL QKEY + CP 0F0H + RET + + NOP + + ; VERIFY (FROM $CMT) + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER CF=1 + ; =2 : BREAK CF=1 + +QVRFY: DI + PUSH DE + PUSH BC + PUSH HL + LD BC,(SIZE) + LD HL,(DTADR) + LD D,0D2H ; "R" + LD E,53H ; "S" + LD A,B + OR C + JR Z,RTP4 ; END + CALL CKSUM + CALL MOTOR + JR C,RTP6 ; BRK + CALL TMARK ; TAPE MARK DETECT + JR C,RTP6 ; BRK + CALL TVRFY + JR RTP4 + + ; DATA VERIFY + ; BC=SIZE + ; HL=DATA LOW ADDRESS + ; CSMDT=CHECK SUM + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK =1 + +TVRFY: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; COMPARE TWICE +TVF1: LD BC,KEYPB + LD DE,CSTR +TVF2: CALL EDGE + JP C,RTP6 ; BRK + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JP Z,TVF2 + LD D,H + POP HL + POP BC + PUSH BC + PUSH HL + ; COMPARE TAPE DATA AND STORAGE +TVF3: CALL RBYTE + JR C,RTP6 ; BRK + CP (HL) + JR NZ,RTP7 ; ERROR, NOT EQUAL + INC HL ; STORAGE ADDRESS + 1 + DEC BC ; SIZE - 1 + LD A,B + OR C + JR NZ,TVF3 + ; COMPARE CHECK SUM (1199H/CSMDT) AND TAPE + LD HL,(CSMDT) + CALL RBYTE + CP H + JR NZ,RTP7 ; ERROR, NOT EQUAL + CALL RBYTE + CP L + JR NZ,RTP7 ; ERROR, NOT EQUAL + DEC D ; NUMBER OF COMPARES (2) - 1 + JP Z,RTP8 ; OK, 2 COMPARES + LD H,D ; (-->05C7H), SAVE NUMBER OF COMPARES + JR TVF1 ; NEXT COMPARE + + ; FLASHING DATA LOAD + +QLOAD: PUSH AF + LD A,(FLASH) + CALL QPONT + LD (HL),A + POP AF + RET + + ; NEW LINE AND PRINT HL REG (ASCII) + +NLPHL: CALL NL + CALL PRTHL + RET + + ; EDGE (TAPE DATA EDGE DETECT) + ; BC=KEYPB (E001H) + ; DE=CSTR (E002H) + ; EXIT CF=0 OK CF=1 BREAK + +EDGE: LD A,0F8H ; BREAK KEY IN (88H WOULD BE BETTER!!) + LD (KEYPA),A + NOP +EDG1: LD A,(BC) + AND 81H ; SHIFT & BREAK + JR NZ,L060E + SCF + RET + +L060E: LD A,(DE) + AND 20H + JR NZ,EDG1 ; CSTR D5 = 0 +EDG2: LD A,(BC) ; 8 + AND 81H ; 9 + JR NZ,L061A ; 10/14 + SCF + RET + +L061A: LD A,(DE) ; 8 + AND 20H ; 9 + JR Z,EDG2 ; CSTR D5 = 1 10/14 + RET ; 11 + + NOP + NOP + NOP + NOP + ; 1 BYTE READ + ; EXIT SUMDT=STORE + ; CF=1 : BREAK + ; CF=0 : DATA=ACC + +RBYTE: PUSH BC + PUSH DE + PUSH HL + LD HL,0800H ; 8 BITS + LD BC,KEYPB ; KEY DATA E001H + LD DE,CSTR ; $TAPE DATA E002H +RBY1: CALL EDGE ; 41 OR 101 + JP C,RBY3 ; 13 (SHIFT & BREAK) + CALL DLY3 ; 20+18*63+33 + LD A,(DE) ; DATA READ :8 + AND 20H + JP Z,RBY2 ; 0 + PUSH HL + LD HL,(SUMDT) + INC HL ; CHECK SUM ; COUNT HIGH BITS ON TAPE + LD (SUMDT),HL + POP HL + SCF +RBY2: LD A,L ; BUILD CHAR + RLA + LD L,A + DEC H ; BITCOUNT-1 + JP NZ,RBY1 + CALL EDGE + LD A,L ; CHAR READ +RBY3: POP HL + POP DE + POP BC + RET + + NOP + NOP + NOP + + ; TAPE MARK DETECT + ; E=@L@ : INFORMATION + ; =@S@ : DATA + ; EXIT CF=0 OK + ; =1 BREAK + +TMARK: CALL GAPCK + PUSH BC + PUSH DE + PUSH HL + LD HL,2828H + LD A,E + CP 0CCH ; "L" + JR Z,L066C + LD HL,1414H +L066C: LD (TMCNT),HL + LD BC,KEYPB + LD DE,CSTR +TM1: LD HL,(TMCNT) +TM2: CALL EDGE + JR C,TM4 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR Z,TM1 + DEC H + JR NZ,TM2 +TM3: CALL EDGE + JR C,TM4 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR NZ,TM1 + DEC L + JR NZ,TM3 + CALL EDGE +TM4: +RET3: POP HL + POP DE + POP BC + RET + + ; MOTOR ON + ; IN D=@W@ :WRITE + ; =@R@ :READ + ; EXIT CF=0 OK + ; =1 BREAK + ; + ; If the button is pressed, + +MOTOR: PUSH BC + PUSH DE + PUSH HL + LD B,0AH ; Pulse motor upto 10 times if sense is low. Each pulse flips on->off or off->on +MOT1: LD A,(CSTR) ; Check sense, if low then pulse motor to switch it on. + AND 10H + JR Z,MOT4 ; If NZ (bit PC4 is high), then wait a bit and return, motor running. + ; If Z then pulse the motor on circuit. +MOT2: LD B,0FFH ; 2 SEC DELAY +L06AD: CALL DLY12 ; 7 MSEC DELAY + JR L06B4 ; MOTOR ENTRY ADJUST + + JR MOTOR ; ORG 06B2H + +L06B4: DJNZ L06AD + XOR A +MOT7: JR RET3 + +MOT4: LD A,06H ; + LD HL,CSTPT ; 8255 Control register + LD (HL),A ; Set PC3 low + INC A + LD (HL),A ; Set PC3 high + DJNZ MOT1 ; Check to see if sense now active. + CALL NL ; Sense not active so play button hasnt been pressed. + LD A,D ; Determine if we are Loading or Saving, display correct message. + CP 0D7H ; "W" + JR Z,MOT8 + LD DE,MSGN1 ; PLAY MARK + JR MOT9 + +MOT8: LD DE,MSGN3 ; "RECORD." + RST 18H ; CALL MSGX + LD DE,MSGN2 ; "PLAY" +MOT9: RST 18H ; CALL MSGX +MOT5: LD A,(CSTR) ; Check sense input and wait until it is high. + AND 10H + JR NZ,MOT2 + CALL QBRK ; If sense is low, check for User Key Break entry. + JR NZ,MOT5 + SCF + JR MOT7 + + ; INITIAL MESSAGE + +MSGQ3: DB "** MONITOR 1Z-013A **\r" + NOP + + ; MOTOR STOP + +MSTOP: PUSH AF + PUSH BC + PUSH DE + LD B,0AH +MST1: LD A,(CSTR) + AND 10H + JR Z,MST3 + LD A,06H + LD (CSTPT),A + INC A + LD (CSTPT),A + DJNZ MST1 +MST3: JP QRSTR1 + + ; CHECK SUM + ; IN BC=SIZE + ; HL=DATA ADDRESS + ; EXIT SUMDT=STORE + ; CSMDT=STORE + +CKSUM: PUSH BC + PUSH DE +L071C: PUSH HL + LD DE,0 +CKS1: LD A,B + OR C + JR NZ,CKS2 + EX DE,HL +L0725: LD (SUMDT),HL ; NUMBER OF HIGHBITS IN DATA + LD (CSMDT),HL + POP HL + POP DE + POP BC + RET + +CKS2: LD A,(HL) + PUSH BC + LD B,8 +CKS3: RLCA + JR NC,L0737 + INC DE +L0737: DJNZ CKS3 +L0739: POP BC + INC HL + DEC BC + JR CKS1 + + ; MODE SET OF KEYPORT + +QMODE: LD HL,KEYPF + LD (HL),8AH ; 10001010 CTRL WORD MODE0 + LD (HL),07H ; PC3=1 M-ON + LD (HL),05H ; PC2=1 INTMSK + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; 107 MICRO SEC DELAY + +DLY1: LD A,15H ; 18*21+20 +L075B: DEC A + JP NZ,L075B + RET + +DLY2: LD A,13H ; 18*19+20 +L0762: DEC A + JP NZ,L0762 + RET + + ; 1 BYTE WRITE + +WBYTE: PUSH BC + LD B,8 + CALL LONG +WBY1: RLCA + CALL C,LONG + CALL NC,SHORT + DEC B + JP NZ,WBY1 + POP BC + RET + + ; GAP + TAPEMARK + ; E=@L@ LONG GAP + ; =@s@ SHORT GAP + +GAP: PUSH BC + PUSH DE + LD A,E + LD BC,55F0H + LD DE,2828H + CP 0CCH ; "L" + JP Z,GAP1 + LD BC,2AF8H + LD DE,1414H +GAP1: CALL SHORT + DEC BC + LD A,B + OR C + JR NZ,GAP1 +GAP2: CALL LONG + DEC D + JR NZ,GAP2 +GAP3: CALL SHORT + DEC E + JR NZ,GAP3 + CALL LONG + POP DE + POP BC + RET + + ; MEMORY CORRECTION + ; COMMAND "M" + +MCOR: CALL HEXIY ; CORRECTION ADDRESS +MCR1: CALL NLPHL ; CORRECTION ADDRESS PRINT + CALL SPHEX ; ACC-->ASCII DISP. + CALL QPRTS ; SPACE PRINT + CALL BGETL ; GET DATA & CHECK DATA + CALL HLHEX ; HL<--ASCII(DE) + JR C,MCR3 + CALL P4DE ; (INC DE)*4 + INC DE + CALL L2HEX ; DATA CHECK + JR C,MCR1 + CP (HL) + JR NZ,MCR1 + INC DE + LD A,(DE) + CP 0DH ; NOT CORRECTION ? + JR Z,MCR2 + CALL L2HEX ; ACC<--HL(ASCII) + JR C,MCR1 + LD (HL),A ; DATA CORRECT +MCR2: INC HL + JR MCR1 + +MCR3: LD H,B ; MEMORY ADDRESS + LD L,C + JR MCR1 + + DB "(HL)" + DB 0F1H + DB 9EH + DB "SUB (" + + ; GET 1 LINE STATEMENT * + ; DE=DATA STORE LOW ADDRESS + ; (END=CR) + +QGETL: PUSH AF + PUSH BC + PUSH HL + PUSH DE +GETL1: CALL QQKEY ; ENTRY KEY +AUTO3: PUSH AF ; IN KEY DATA SAVE + LD B,A + LD A,(SWRK) ; BELL WORK + RRCA + CALL NC,QBEL ; ENTRY BELL + LD A,B + LD HL,KANAF ; KANA & GRAPH FLAGS + AND 0F0H + CP 0C0H + POP DE ; EREG=FLAGREG + LD A,B + JR NZ,GETL2 ; NOT C0H + CP 0CDH ; CR + JR Z,GETL3 + CP 0CBH ; BREAK + JP Z,GETLC + CP 0CFH ; NIKO MARK WH. + JR Z,GETL2 + CP 0C7H ; CRT EDITION + JR NC,GETL5 ; <=C7H + RR E ; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL. + LD A,B + JR NC,GETL5 +GETL2: CALL QDSP ; DISPL. + JR GETL1 + +GETL5: CALL QDPCT ; CRT CONTROL + JR GETL1 + + ; BREAK IN + +GETLC: POP HL + PUSH HL + LD (HL),1BH ; BREAK CODE + INC HL + LD (HL),0DH + JR GETLR + + ; GETLA + +GETLA: RRCA ; CY<--D7 + JR NC,GETL6 + JR GETLB + + ; DELAY 7 MSEC AND SWEP + +DSWEP: CALL DLY12 + CALL QSWEP + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +GETL3: CALL PMANG ; CR + LD B,COLW ; 1 LINE + JR NC,GETLA + DEC H ; BEFORE LINE +GETLB: LD B,COLW*2 ; 2 LINE +GETL6: LD L,0 + CALL QPNT1 + POP DE ; STORE TOP ADDRESS + PUSH DE +GETLZ: LD A,(HL) + CALL QDACN + LD (DE),A + INC HL + INC DE + DJNZ GETLZ + EX DE,HL +GETLU: LD (HL),0DH + DEC HL + LD A,(HL) + CP 20H ; SPACE THEN CR + + ; CR AND NEW LINE + + JR Z,GETLU + + ; NEW LINE RETURN + +GETLR: CALL QLTNL + POP DE + POP HL + POP BC + POP AF + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; MESSAGE PRINT + ; DE PRINT DATA LOW ADDRESS + ; END=CR + +QMSG: PUSH AF + PUSH BC + PUSH DE +MSG1: LD A,(DE) + CP 0DH ; CR + JR Z,MSGX2 + CALL QPRNT + INC DE + JR MSG1 + + ; ALL PRINT MESSAGE + +QMSGX: PUSH AF + PUSH BC + PUSH DE +MSGX1: LD A,(DE) + CP 0DH +MSGX2: JP Z,QRSTR1 + CALL QADCN + CALL PRNT3 + INC DE + JR MSGX1 + + ; TOP OF KEYTBLS + +QKYSM: LD DE,KTBLS ; SHIFT ALSO + JR QKY5 + + ; BREAK CODE IN + +NBRK: LD A,0CBH ; BREAK CODE + OR A + JR QKY1 + + ; GETKEY + ; NO ECHO BACK + ; EXIT ACC=ASCII CODE + +QGET: CALL QKEY ; KEY IN (DISPLAY CODE) + SUB 0F0H ; NOT KEYIN CODE + RET Z + ADD A,0F0H + JP QDACN ; DISPLAY TO ASCII CODE + + NOP + NOP + + ; 1 KEY INPUT + ; IN B=KEY MODE (SHIFT, CTRL, BREAK) + ; C=KEY DATA (COLUMN & ROW) + ; EXIT ACC=DISPLAY CODE + ; IF NO KEY ACC=F0H + ; IF CY=1 THEN ATTRIBUTE ON + ; (SMALL, HIRAKANA) + +QKEY: PUSH BC + PUSH DE + PUSH HL + CALL DSWEP ; DELAY AND KEY SWEP + LD A,B + RLCA + JR C,QKY2 + LD A,0F0H ; SHIFT OR CTRL HERE +QKY1: POP HL + POP DE + POP BC + RET + +QKY2: LD DE,KTBL ; NORMAL KEY TABLE + LD A,B + CP 88H ; BREAK IN (SHIFT & BRK) + JR Z,NBRK + LD H,0 ; HL=ROW & COLUMN + LD L,C + BIT 5,A ; CTRL CHECK + JR NZ,L08F7 ; YES, CTRL + LD A,(KANAF) ; 0=NR., 1=GRAPH + RRCA + JP C,QKYGRP ; GRAPH MODE + LD A,B ; CTRL KEY CHECK + RLA + RLA + JR C,QKYSM + JR QKY5 + +L08F7: LD DE,KTBLC ; CONTROL KEY TABLE +QKY5: ADD HL,DE ; TABLE +QKY55: LD A,(HL) + JR QKY1 + +QKYGRP: BIT 6,B + JR Z,QKYGRS + LD DE,KTBLG + ADD HL,DE + SCF + JR QKY55 + +QKYGRS: LD DE,KTBLGS + JR QKY5 + + ; NEWLINE + +QLTNL: XOR A + LD (DPRNT),A ; ROW POINTER + LD A,0CDH ; CR + JR PRNT5 + + NOP + NOP + +QNL: LD A,(DPRNT) + OR A + RET Z + JR QLTNL + + NOP + + ; PRINT SPACE + +QPRTS: LD A,20H + JR QPRNT + + ; PRINT TAB + +QPRTT: CALL PRNTS + LD A,(DPRNT) + OR A + RET Z +L092C: SUB 10 + JR C,QPRTT + JR NZ,L092C + NOP + NOP + NOP + + ; PRINT + ; IN ACC=PRINT DATA (ASCII) + +QPRNT: CP 0DH ; CR + JR Z,QLTNL + PUSH BC + LD C,A + LD B,A + CALL QPRT + LD A,B + POP BC + RET + +MSGOK: DB "OK!\r" + + ; PRINT ROUTINE + ; 1 CHARACTER + ; INPUT:C=ASCII DATA (QDSP+QDPCT) + +QPRT: LD A,C + CALL QADCN ; ASCII TO DSPLAY + LD C,A + CP 0F0H + RET Z ; ZERO=ILLEGAL DATA + AND 0F0H ; MSD CHECK + CP 0C0H + LD A,C + JR NZ,PRNT3 + CP 0C7H + JR NC,PRNT3 ; CRT EDITOR +PRNT5: CALL QDPCT + CP 0C3H ; "->" + JR Z,PRNT4 + CP 0C5H ; HOME + JR Z,PRNT2 + CP 0C6H ; CLR + RET NZ +PRNT2: XOR A +L0968: LD (DPRNT),A + RET + +PRNT3: CALL QDSP +PRNT4: LD A,(DPRNT) ; TAB POINT+1 + INC A + CP COLW*2 + JR C,L0968 + SUB COLW*2 + JR L0968 + + ; FLASHING BYPASS 1 + +FLAS1: LD A,(FLASH) + JR FLAS2 + + ; BREAK SUBROUTINE BYPASS 1 + ; CTRL OR NOT KEY + +QBRK2: BIT 5,A ; NOT OR CTRL + JR Z,QBRK3 ; CTRL + OR A ; NOTKEY A=7FH + RET + +QBRK3: LD A,20H ; CTRL D5=1 + OR A ; ZERO FLG CLR + SCF + RET + +MSGSV: DB "FILENAME? " + DB 0DH + + ; DLY 7 MSEC +DLY12: PUSH BC + LD B,15H +L0999: CALL DLY3 + DJNZ L0999 + POP BC + RET + + ; LOADING MESSAGE + +MSGQ2: DB "LOADING \r" + + ; DELAY FOR LONG PULSE + +DLY4: LD A,59H ; 18*89+20 +L09AB: DEC A + JP NZ,L09AB + RET + + NOP + NOP + NOP + + ; KEY BOARD SEARCH + ; & DISPLAY CODE CONVERSION + ; EXIT A=DISPLAY CODE + ; CY=GRAPH MODE + ; WITH CURSOR DISPLAY + +QQKEY: PUSH HL + CALL QSAVE +KSL1: CALL FLKEY ; KEY + JR NZ,KSL1 ; KEY IN THEN JUMP +KSL2: CALL FLKEY + JR Z,KSL2 ; NOT KEY IN THEN JUMP + LD H,A + CALL DLY12 ; DELAY CHATTER + CALL QKEY + PUSH AF + CP H ; CHATTER CHECK + POP HL + JR NZ,KSL2 + PUSH HL + POP AF ; IN KEY DATA + CALL QLOAD ; FLASHING DATA LOAD + POP HL + RET + + ; CLEAR 2 + +NCLR08: XOR A ; CY FLAG +NCLR8: LD BC,0800H +CLEAR: PUSH DE ; BC=CLR BYTE SIZE, A=CLR DATA + LD D,A +CLEAR1: LD (HL),D + INC HL + DEC BC + LD A,B + OR C + JR NZ,CLEAR1 + POP DE + RET + + ; FLASHING 2 + +QFLS: PUSH AF + PUSH HL + LD A,(KEYPC) + RLCA + RLCA + JR C,FLAS1 + LD A,(FLSDT) +FLAS2: CALL QPONT ; DISPLAY POSITION + LD (HL),A + POP HL + POP AF + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +QFLAS: JR QFLS + + ; SHORT AND LONG PULSE FOR 1 BIT WRITE + +SHORT: PUSH AF ; 12 + LD A,03H ; 9 + LD (CSTPT),A ; E003H PC3=1:16 + CALL DLY1 ; 20+18*21+20 + CALL DLY1 ; 20+18*21+20 + LD A,02H ; 9 + LD (CSTPT),A ; E003H PC3=0:16 + CALL DLY1 ; 20+18*21+20 + CALL DLY1 ; 20+18*21+20 + POP AF ; 11 + RET ; 11 + +LONG: PUSH AF ; 11 + LD A,03H ; 9 + LD (CSTPT),A ; 16 + CALL DLY4 ; 20+18*89+20 + LD A,02H ; 9 + LD (CSTPT),A ; 16 + CALL DLY4 ; 20+18*89+20 + POP AF ; 11 + RET ; 11 + + NOP + NOP + NOP + NOP + NOP + + ; BREAK KEY CHECK + ; AND SHIFT, CTRL KEY CHECK + ; EXIT BREAK ON : ZERO=1 + ; OFF: ZERO=0 + ; NO KEY : CY =0 + ; KEY IN : CY =1 + ; A D6=1 : SHIFT ON + ; =0 : OFF + ; D5=1 : CTRL ON + ; =0 : OFF + ; D4=1 : SHIFT+CNT ON + ; =0 : OFF + +QBRK: LD A,0F8H ; LINE 8SWEEP + LD (KEYPA),A + NOP + LD A,(KEYPB) + OR A + RRA + JP C,QBRK2 ; SHIFT ? + RLA + RLA + JR NC,QBRK1 ; BREAK ? + LD A,40H ; SHIFT D6=1 + SCF + RET + +QBRK1: XOR A ; SHIFT ? + RET + + ; 320 U SEC DELAY + +DLY3: LD A,3FH ; 18*63+33 + JP L0762 ; JP DLY2+2 + + NOP + + ; KEY BOARD SWEEP + ; EXIT B,D7=0 NO DATA + ; =1 DATA + ; D6=0 SHIFT OFF + ; =1 SHIFT ON + ; D5=0 CTRL OFF + ; =1 CTRL ON + ; D4=0 SHIFT+CTRL OFF + ; =1 SHIFT+CTRL ON + ; C = ROW & COLUMN + ; 7 6 5 4 3 2 1 0 + ; * * ^ ^ ^ < < < + +QSWEP: PUSH DE + PUSH HL + XOR A + LD B,0F8H + LD D,A + CALL QBRK + JR NZ,SWEP6 + LD D,88H ; BREAK ON + JR SWEP9 + +SWEP6: JR NC,SWEP0 + LD D,A + JR SWEP0 + +SWEP01: SET 7,D +SWEP0: DEC B + LD A,B + LD (KEYPA),A + CP 0EFH ; MAP SWEEP END ? + JR NZ,SWEP3 + CP 0F8H ; BREAK KEY ROW + JR Z,SWEP0 +SWEP9: LD B,D + POP HL + POP DE + RET + +SWEP3: LD A,(KEYPB) + CPL + OR A + JR Z,SWEP0 + LD E,A +SWEP2: LD H,8 + LD A,B + AND 0FH + RLCA + RLCA + RLCA + LD C,A + LD A,E +L0A89: DEC H + RRCA + JR NC,L0A89 + LD A,H + ADD A,C + LD C,A + JR SWEP01 + ; + ; + ; ASCII TO DISPLAY CODE TABL + ; +ATBL: + ; 00 - 0F + DB 0F0H ; ^ @ + DB 0F0H ; ^ A + DB 0F0H ; ^ B + DB 0F3H ; ^ C + DB 0F0H ; ^ D + DB 0F5H ; ^ E + DB 0F0H ; ^ F + DB 0F0H ; ^ G + DB 0F0H ; ^ H + DB 0F0H ; ^ I + DB 0F0H ; ^ J + DB 0F0H ; ^ K + DB 0F0H ; ^ L + DB 0F0H ; ^ M + DB 0F0H ; ^ N + DB 0F0H ; ^ O + ; 10 - 1F + DB 0F0H ; ^ P + DB 0C1H ; ^ Q CUR. DOWN + DB 0C2H ; ^ R CUR. UP + DB 0C3H ; ^ S CUR. RIGHT + DB 0C4H ; ^ T CUR. LEFT + DB 0C5H ; ^ U HOME + DB 0C6H ; ^ V CLEAR + DB 0F0H ; ^ W + DB 0F0H ; ^ X + DB 0F0H ; ^ Y + DB 0F0H ; ^ Z SEP. + DB 0F0H ; ^ [ + DB 0F0H ; ^ \ + DB 0F0H ; ^ ] + DB 0F0H ; ^ ^ + DB 0F0H ; ^ - + ; 20 - 2F + DB 00H ; SPACE + DB 61H ; ! + DB 62H ; " + DB 63H ; # + DB 64H ; $ + DB 65H ; % + DB 66H ; & + DB 67H ; ' + DB 68H ; ( + DB 69H ; ) + DB 6BH ; * + DB 6AH ; + + DB 2FH ; , + DB 2AH ; - + DB 2EH ; . + DB 2DH ; / + ; 30 - 3F + DB 20H ; 0 + DB 21H ; 1 + DB 22H ; 2 + DB 23H ; 3 + DB 24H ; 4 + DB 25H ; 5 + DB 26H ; 6 + DB 27H ; 7 + DB 28H ; 8 + DB 29H ; 9 + DB 4FH ; : + DB 2CH ; ; + DB 51H ; < + DB 2BH ; = + DB 57H ; > + DB 49H ; ? + ; 40 - 4F + DB 55H ; @ + DB 01H ; A + DB 02H ; B + DB 03H ; C + DB 04H ; D + DB 05H ; E + DB 06H ; F + DB 07H ; G + DB 08H ; H + DB 09H ; I + DB 0AH ; J + DB 0BH ; K + DB 0CH ; L + DB 0DH ; M + DB 0EH ; N + DB 0FH ; O + ; 50 - 5F + DB 10H ; P + DB 11H ; Q + DB 12H ; R + DB 13H ; S + DB 14H ; T + DB 15H ; U + DB 16H ; V + DB 17H ; W + DB 18H ; X + DB 19H ; Y + DB 1AH ; Z + DB 52H ; [ + DB 59H ; \ + DB 54H ; ] + DB 50H ; + DB 45H ; + ; 60 - 6F + DB 0C7H ; UFO + DB 0C8H + DB 0C9H + DB 0CAH + DB 0CBH + DB 0CCH + DB 0CDH + DB 0CEH + DB 0CFH + DB 0DFH + DB 0E7H + DB 0E8H + DB 0E5H + DB 0E9H + DB 0ECH + DB 0EDH + ; 70 - 7F + DB 0D0H + DB 0D1H + DB 0D2H + DB 0D3H + DB 0D4H + DB 0D5H + DB 0D6H + DB 0D7H + DB 0D8H + DB 0D9H + DB 0DAH + DB 0DBH + DB 0DCH + DB 0DDH + DB 0DEH + DB 0C0H + ; 80 - 8F + DB 80H ; } + DB 0BDH + DB 9DH + DB 0B1H + DB 0B5H + DB 0B9H + DB 0B4H + DB 9EH + DB 0B2H + DB 0B6H + DB 0BAH + DB 0BEH + DB 9FH + DB 0B3H + DB 0B7H + DB 0BBH + ; 90 - 9F + DB 0BFH ; _ + DB 0A3H + DB 85H + DB 0A4H ; ` + DB 0A5H ; ~ + DB 0A6H + DB 94H + DB 87H + DB 88H + DB 9CH + DB 82H + DB 98H + DB 84H + DB 92H + DB 90H + DB 83H + ; A0 - AF + DB 91H + DB 81H + DB 9AH + DB 97H + DB 93H + DB 95H + DB 89H + DB 0A1H + DB 0AFH + DB 8BH + DB 86H + DB 96H + DB 0A2H + DB 0ABH + DB 0AAH + DB 8AH + ; B0 - BF + DB 8EH + DB 0B0H + DB 0ADH + DB 8DH + DB 0A7H + DB 0A8H + DB 0A9H + DB 8FH + DB 8CH + DB 0AEH + DB 0ACH + DB 9BH + DB 0A0H + DB 99H + DB 0BCH ; { + DB 0B8H + ; C0 - CF + DB 40H + DB 3BH + DB 3AH + DB 70H + DB 3CH + DB 71H + DB 5AH + DB 3DH + DB 43H + DB 56H + DB 3FH + DB 1EH + DB 4AH + DB 1CH + DB 5DH + DB 3EH + ; D0 - DF + DB 5CH + DB 1FH + DB 5FH + DB 5EH + DB 37H + DB 7BH + DB 7FH + DB 36H + DB 7AH + DB 7EH + DB 33H + DB 4BH + DB 4CH + DB 1DH + DB 6CH + DB 5BH + ; E0 - EF + DB 78H + DB 41H + DB 35H + DB 34H + DB 74H + DB 30H + DB 38H + DB 75H + DB 39H + DB 4DH + DB 6FH + DB 6EH + DB 32H + DB 77H + DB 76H + DB 72H + ; F0 - FF + DB 73H + DB 47H + DB 7CH + DB 53H + DB 31H + DB 4EH + DB 6DH + DB 48H + DB 46H + DB 7DH + DB 44H + DB 1BH + DB 58H + DB 79H + DB 42H + DB 60H + + ; FLASHING DATA SAVE + +QSAVE: LD HL,FLSDT + LD (HL),0EFH ; NORMAL CURSOR + LD A,(KANAF) + RRCA + JR C,L0BA0 ; GRAPH MODE + RRCA + JR NC,SV0 ; NORMAL MODE +L0BA0: LD (HL),0FFH ; GRAPH CURSOR +SV0: LD A,(HL) + PUSH AF + CALL QPONT ; FLASHING POSITION + LD A,(HL) + LD (FLASH),A + POP AF + LD (HL),A + XOR A + LD HL,KEYPA +L0BB1: LD (HL),A + CPL ; OH NO! UNUSED BITS WERE TOUCHED TOO!!! + LD (HL),A + RET + +SV1: LD (HL),43H ; KANA CURSOR + JR SV0 + + ; ASCII TO DISPLAY CODE CONVERT + ; IN ACC:ASCII + ; EXIT ACC:DISPLAY CODE + +QADCN: PUSH BC + PUSH HL + LD HL,ATBL + LD C,A + LD B,0 + ADD HL,BC + LD A,(HL) + JR DACN3 + +VRNS: DB "V1.0A\r" ; VERSION MANAGEMENT + NOP + NOP + NOP + + ; DISPLAY CODE TO ASCII CONVERSION + ; IN ACC=DISPLAY CODE + ; EXIT ACC=ASCII + +QDACN: PUSH BC + PUSH HL + PUSH DE + LD HL,ATBL + LD D,H + LD E,L + LD BC,0100H + CPIR + JR Z,DACN1 + LD A,0F0H +DACN2: POP DE +DACN3: POP HL + POP BC + RET + +DACN1: OR A + DEC HL + SBC HL,DE + LD A,L + JR DACN2 + + ; + ; + ; KEY MATRIX TO DISPLAY CODE TABL + ; +KTBL: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0CAH ; GRAPH + DB 58H ; + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 2CH ; ; + DB 4FH ; : + DB 0CDH ; CR + ;S1 08 - 0F + DB 19H ; Y + DB 1AH ; Z + DB 55H ; @ + DB 52H ; [ + DB 54H ; ] + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 0F0H ; NULL + ;S2 10 - 17 + DB 11H ; Q + DB 12H ; R + DB 13H ; S + DB 14H ; T + DB 15H ; U + DB 16H ; V + DB 17H ; W + DB 18H ; X + ;S3 18 - 1F + DB 09H ; I + DB 0AH ; J + DB 0BH ; K + DB 0CH ; L + DB 0DH ; M + DB 0EH ; N + DB 0FH ; O + DB 10H ; P + ;S4 20 - 27 + DB 01H ; A + DB 02H ; B + DB 03H ; C + DB 04H ; D + DB 05H ; E + DB 06H ; F + DB 07H ; G + DB 08H ; H + ;S5 28 - 2F + DB 21H ; 1 + DB 22H ; 2 + DB 23H ; 3 + DB 24H ; 4 + DB 25H ; 5 + DB 26H ; 6 + DB 27H ; 7 + DB 28H ; 8 + ;S6 30 - 37 + DB 59H ; \ + DB 50H ; + DB 2AH ; - + DB 00H ; SPACE + DB 20H ; 0 + DB 29H ; 9 + DB 2FH ; , + DB 2EH ; . + ;S7 38 - 3F + DB 0C8H ; INST. + DB 0C7H ; DEL. + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 49H ; ? + DB 2DH ; / + ; + ; + ; KTBL SHIFT ON + ; +KTBLS: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0CAH ; GRAPH + DB 1BH ; POND + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 6AH ; + + DB 6BH ; * + DB 0CDH ; CR + ;S1 08 - 0F + DB 99H ; y + DB 9AH ; z + DB 0A4H ; ` + DB 0BCH ; { + DB 40H ; } + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 0F0H ; NULL + ;S2 10 - 17 + DB 91H ; q + DB 92H ; r + DB 93H ; s + DB 94H ; t + DB 95H ; u + DB 96H ; v + DB 97H ; w + DB 98H ; x + ;S3 18 - 1F + DB 89H ; i + DB 8AH ; j + DB 8BH ; k + DB 8CH ; l + DB 8DH ; m + DB 8EH ; n + DB 8FH ; o + DB 90H ; p + ;S4 20 - 27 + DB 81H ; a + DB 82H ; b + DB 83H ; c + DB 84H ; d + DB 85H ; e + DB 86H ; f + DB 87H ; g + DB 88H ; h + ;S5 28 - 2F + DB 61H ; ! + DB 62H ; " + DB 63H ; # + DB 64H ; $ + DB 65H ; % + DB 66H ; & + DB 67H ; ' + DB 68H ; ( + ;S6 30 - 37 + DB 80H ; \ + DB 0A5H ; POND MARK + DB 2BH ; YEN + DB 00H ; SPACE + DB 60H ; ¶ + DB 69H ; ) + DB 51H ; < + DB 57H ; > + ;S7 38 - 3F + DB 0C6H ; CLR + DB 0C5H ; HOME + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 5AH ; + DB 45H ; + ; + ; + ; GRAPHIC + ; +KTBLGS: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0F0H ; GRAPH BUT NULL + DB 0E5H ; # + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 42H ; # ; + DB 0B6H ; #: + DB 0CDH ; CR + ;S1 08 - 0F + DB 75H ; #Y + DB 76H ; #Z + DB 0B2H ; #@ + DB 0D8H ; #[ + DB 4EH ; #] + DB 0F0H ; #NULL + DB 0F0H ; #NULL + DB 0F0H ; #NULL + ;S2 10 - 17 + DB 3CH ; #Q + DB 30H ; #R + DB 44H ; #S + DB 71H ; #T + DB 79H ; #U + DB 0DAH ; #V + DB 38H ; #W + DB 6DH ; #X + ;S3 18 - 1F + DB 7DH ; #I + DB 5CH ; #J + DB 5BH ; #K + DB 0B4H ; #L + DB 1CH ; #M + DB 32H ; #N + DB 0B0H ; #O + DB 0D6H ; #P + ;S4 20 - 27 + DB 53H ; #A + DB 6FH ; #B + DB 0DEH ; #C + DB 47H ; #D + DB 34H ; #E + DB 4AH ; #F + DB 4BH ; #G + DB 72H ; #H + ;S5 28 - 2F + DB 37H ; #1 + DB 3EH ; #2 + DB 7FH ; #3 + DB 7BH ; #4 + DB 3AH ; #5 + DB 5EH ; #6 + DB 1FH ; #7 + DB 0BDH ; #8 + ;S6 30 - 37 + DB 0D4H ; #YEN + DB 9EH ; #+ + DB 0D2H ; #- + DB 00H ; SPACE + DB 9CH ; #0 + DB 0A1H ; #9 + DB 0CAH ; #, + DB 0B8H ; #. + ;S7 38 - 3F + DB 0C8H ; INST + DB 0C7H ; DEL. + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 0BAH ; #? + DB 0DBH ; #/ + ; + ; + ; CONTROL CODE + ; +KTBLC: + ;S0 00 - 07 + DB 0F0H + DB 0F0H + DB 0F0H ; ^ + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + ;S1 08 - 0F + DB 0F0H ; ^Y E3 + DB 5AH ; ^Z E4 (CHECKER) + DB 0F0H ; ^@ + DB 0F0H ; ^[ EB/E5 + DB 0F0H ; ^] EA/E7 + DB 0F0H ; #NULL + DB 0F0H ; #NULL + DB 0F0H ; #NULL + ;S2 10 - 17 + DB 0C1H ; ^Q + DB 0C2H ; ^R + DB 0C3H ; ^S + DB 0C4H ; ^T + DB 0C5H ; ^U + DB 0C6H ; ^V + DB 0F0H ; ^W E1 + DB 0F0H ; ^X E2 + ;S3 18 - 1F + DB 0F0H ; ^I F9 + DB 0F0H ; ^J FA + DB 0F0H ; ^K FB + DB 0F0H ; ^L FC + DB 0F0H ; ^M CD + DB 0F0H ; ^N FE + DB 0F0H ; ^O FF + DB 0F0H ; ^P E0 + ;S4 20 - 27 + DB 0F0H ; ^A F1 + DB 0F0H ; ^B F2 + DB 0F0H ; ^C F3 + DB 0F0H ; ^D F4 + DB 0F0H ; ^E F5 + DB 0F0H ; ^F F6 + DB 0F0H ; ^G F7 + DB 0F0H ; ^H F8 + ;S5 28 - 2F + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + ;S6 30 - 37 (ERROR? 7 VALUES ONLY!!) + DB 0F0H ; ^YEN E6 + DB 0F0H ; ^ EF + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H ; ^, + DB 0F0H + ;S7 38 - 3F + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H ; ^/ EE + ; + ; + ; KANA + ; +KTBLG: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0F0H ; GRAPH BUT NULL + DB 0CFH ; NIKO WH. + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 0B5H ; MO + DB 4DH ; DAKU TEN + DB 0CDH ; CR + ;S1 08 - 0F + DB 35H ; HA + DB 77H ; TA + DB 0D7H ; WA + DB 0B3H ; YO + DB 0B7H ; HANDAKU + DB 0F0H + DB 0F0H + DB 0F0H + ;S2 10 - 17 + DB 7CH ; KA + DB 70H ; KE + DB 41H ; SHI + DB 31H ; KO + DB 39H ; HI + DB 0A6H ; TE + DB 78H ; KI + DB 0DDH ; CHI + ;S3 18 - 1F + DB 3DH ; FU + DB 5DH ; MI + DB 6CH ; MU + DB 56H ; ME + DB 1DH ; RHI + DB 33H ; RA + DB 0D5H ; HE + DB 0B1H ; HO + ;S4 20 - 27 + DB 46H ; SA + DB 6EH ; TO + DB 0D9H ; THU + DB 48H ; SU + DB 74H ; KU + DB 43H ; SE + DB 4CH ; SO + DB 73H ; MA + ;S5 28 - 2F + DB 3FH ; A + DB 36H ; I + DB 7EH ; U + DB 3BH ; E + DB 7AH ; O + DB 1EH ; NA + DB 5FH ; NI + DB 0A2H ; NU + ;S6 30 - 37 + DB 0D3H ; YO + DB 9FH ; YU + DB 0D1H ; YA + DB 00H ; SPACE + DB 9DH ; NO + DB 0A3H ; NE + DB 0D0H ; RU + DB 0B9H ; RE + ;S7 38 - 3F + DB 0C6H ; ?CLR + DB 0C5H ; ?HOME + DB 0C2H ; ?CURSOR UP + DB 0C1H ; ?CURSOR DOWN + DB 0C3H ; ?CURSOR RIGHT + DB 0C4H ; ?CURSOR LEFT + DB 0BBH ; DASH + DB 0BEH ; RO + + ; MEMORY DUMP COMMAND "D" + +DUMP: CALL HEXIY ; START ADDRESS + CALL P4DE + PUSH HL + CALL HLHEX ; END ADDRESS + POP DE + JR C,DUM1 ; DATA ERROR THEN +L0D36: EX DE,HL +DUM3: LD B,08H ; DISPLAY 8 BYTES + LD C,23 ; CHANGE PRINT BIAS + CALL NLPHL ; NEWLINE PRINT +DUM2: CALL SPHEX ; SPACE PRINT + ACC PRINT + INC HL + PUSH AF + LD A,(DSPXY) ; DISPLAY POINT + ADD A,C + LD (DSPXY),A ; X AXIS=X+CREG + POP AF + CP 20H + JR NC,L0D51 + LD A,2EH ; "." +L0D51: CALL QADCN ; ASCII TO DISPLAY CODE + CALL PRNT3 + LD A,(DSPXY) + INC C + SUB C ; ASCII DISPLAY POSITION + LD (DSPXY),A + DEC C + DEC C + DEC C + PUSH HL + SBC HL,DE + POP HL + JR Z,L0D85 + LD A,0F8H + LD (KEYPA),A + NOP + LD A,(KEYPB) + CP 0FEH ; SHIFT KEY ? + JR NZ,L0D78 + CALL QBLNK ; 64MSEC DELAY +L0D78: DJNZ DUM2 +L0D7A: CALL QKEY ; STOP DISPLAY + OR A + JR Z,L0D7A ; SPACE KEY THEN STOP + CALL QBRK ; BREAK IN ? + JR NZ,DUM3 +L0D85: JP ST1 ; COMMAND IN ! + +DUM1: LD HL,160 ; 20*8 BYTES + ADD HL,DE + JR L0D36 + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; V-BLANK CHECK + +QBLNK: PUSH AF +L0DA7: LD A,(KEYPC) ; V-BLANK + RLCA + JR NC,L0DA7 +L0DAD: LD A,(KEYPC) ; 64 + RLCA ; + JR C,L0DAD ; MSEC + POP AF + RET + ; DISPLAY ON POINTER + ; ACC=DISPLAY CODE + ; EXCEPT F0H + +QDSP: PUSH AF + PUSH BC + PUSH DE + PUSH HL +DSP01: CALL QPONT ; DISPLAY POSITION + LD (HL),A + LD HL,(DSPXY) + LD A,L + CP COLW-1 + JR NZ,DSP04 + CALL PMANG + JR C,DSP04 + EX DE,HL + LD (HL),1 ; LOGICAL 1ST COLUMN + INC HL + LD (HL),0 ; LOGICAL 2ND COLUMN +DSP04: LD A,0C3H ; CURSL + JR L0DE0 + + ; GRAPHIC STATUS CHECK + +GRSTAS: LD A,(KANAF) + CP 01H + LD A,0CAH + RET + + ; DISPLAY CONTROL + ; ACC=CONTROL CODE + +QDPCT: PUSH AF + PUSH BC + PUSH DE + PUSH HL +L0DE0: LD B,A + AND 0F0H + CP 0C0H + JR NZ,CURS5 + XOR B + RLCA + LD C,A + LD B,0 + LD HL,CTBL ; PAGE MODE1 + ADD HL,BC + LD E,(HL) + INC HL + LD D,(HL) + LD HL,(DSPXY) + EX DE,HL + JP (HL) + +CURSD: EX DE,HL ; LD HL,(DSPXY) + LD A,H + CP 24 + JR Z,CURS4 + INC H +CURS1: +CURS3: LD (DSPXY),HL +CURS5: JP QRSTR + +CURSU: EX DE,HL ; LD HL,(DSPXY) + LD A,H + OR A + JR Z,CURS5 + DEC H +CURSU1: JR CURS3 + +CURSR: EX DE,HL ; LD HL,(DSPXY) + LD A,L + CP COLW-1 + JR NC,CURS2 + INC L + JR CURS3 + +CURS2: LD L,0 + INC H + LD A,H + CP 25 + JR C,CURS1 + LD H,24 + LD (DSPXY),HL +CURS4: JR SCROL + +CURSL: EX DE,HL ; LD HL,(DSPXY) + LD A,L + OR A + JR Z,L0E2D + DEC L + JR CURS3 + +L0E2D: LD L,COLW-1 + DEC H + JP P,CURSU1 + LD H,0 + LD (DSPXY),HL + JR CURS5 + +CLRS: LD HL,MANG + LD B,27 + CALL QCLER + LD HL,0D000H ; SCRN TOP + CALL NCLR08 + LD A,71H ; COLOR DATA + CALL NCLR8 ; D800H-DFFFH CLEAR +HOME: LD HL,0 ; DSPXY:0 X=0,Y=0 + JR CURS3 + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; CR + +CR: CALL PMANG + RRCA + JR NC,CURS2 + LD L,0 + INC H + CP 24 + JR Z,CR1 + INC H + JR CURS1 + +CR1: LD (DSPXY),HL + + ; SCROLL + +SCROL: LD BC,SCRNSZ - COLW + LD DE,SCRN ; TOP OF $CRT ADDRESS + LD HL,SCRN+COLW ; COLUMN + PUSH BC ; 1000 STORE + LDIR + POP BC + PUSH DE + LD DE,SCRN + 800H ; COLOR RAM SCROLL + LD HL,SCRN + 800H + COLW ; SCROLL TOP + 1 LINE + LDIR + LD B,COLW ; ONE LINE + EX DE,HL + LD A,71H ; COLOR RAM INITIAL DATA + CALL QDINT + POP HL + LD B,COLW + CALL QCLER ; LAST LINE CLEAR + LD BC,ROW + 1 ; ROW NUMBER+1 + LD DE,MANG ; LOGICAL MANAGEMENT + LD HL,MANG+1 + LDIR + LD (HL),0 + LD A,(MANG) + OR A + JR Z,QRSTR + LD HL,DSPXY+1 + DEC (HL) + JR SCROL + + ; CONTROL CODE TABLE + +CTBL: DW SCROL ; SCROLLING 10H + DW CURSD ; CURSOR DOWN 11H + DW CURSU ; CURSOR UP 12H + DW CURSR ; CURSOR RIGHT 13H + DW CURSL ; CURSOR LEFT 14H + DW HOME ; 15H + DW CLRS ; 16H + DW DEL ; 17H + DW INST ; 18H + DW ALPHA ; 19H + DW KANA ; GRAPHIC 1AH + DW QRSTR ; 1BH + DW QRSTR ; 1CH + DW CR ; 1DH + DW QRSTR ; 1EH + DW QRSTR ; 1FH + + ; INST BYPASS + +INST2: SET 3,H ; COLOR RAM + LD A,(HL) ; FROM + INC HL + LD (HL),A ; TO + DEC HL ; ADDRESS ADJUST + RES 3,H + LDD ; CHANGE TRNS. + LD A,C + OR B ; BC=0 ? + JR NZ,INST2 + EX DE,HL + LD (HL),0 + SET 3,H ; COLOR RAM + LD (HL),71H + JR QRSTR + +ALPHA: XOR A +ALPH1: LD (KANAF),A + + ; RESTORE + +QRSTR: POP HL +QRSTR1: POP DE + POP BC + POP AF + RET + + NOP + NOP + NOP + NOP + +KANA: CALL GRSTAS + JP Z,DSP01 ; NOT GRAPH KEY THEN JUMP + LD A,01H + JR ALPH1 + +DEL: EX DE,HL ; LD HL,(DSPXY) + LD A,H ; HOME ? + OR L + JR Z,QRSTR + LD A,L + OR A + JR NZ,DEL1 ; LEFT SIDE ? + CALL PMANG + JR C,DEL1 + CALL QPONT + DEC HL + LD (HL),0 + JR L0F33 ; JUMP CURSL + +DEL1: CALL PMANG + RRCA + LD A,COLW + JR NC,L0F17 + RLCA ; ACC=80 +L0F17: SUB L + LD B,A ; TRNS. BYTE + CALL QPONT +DEL2: LD A,(HL) ; CHANGE FROM ADDRESS + DEC HL + LD (HL),A ; TO + INC HL + SET 3,H ; COLOR RAM + LD A,(HL) + DEC HL + LD (HL),A + RES 3,H ; CHANGE + INC HL + INC HL ; NEXT + DJNZ DEL2 + DEC HL ; ADDRESS ADJUST + LD (HL),0 + SET 3,H + LD HL,71H ; BLUE + WHITE +L0F33: LD A,0C4H ; JP CURSL + JP L0DE0 + +INST: CALL PMANG + RRCA + LD L,COLW - 1 + LD A,L + JR NC,L0F42 + INC H +L0F42: CALL QPNT1 + PUSH HL + LD HL,(DSPXY) + JR NC,L0F4D + LD A,(COLW*2) - 1 +L0F4D: SUB L + LD B,0 + LD C,A + POP DE + JR Z,QRSTR + LD A,(DE) + OR A + JR NZ,QRSTR + LD H,D ; HL<-DE + LD L,E + DEC HL + JP INST2 ; JUMP NEXT (BYPASS) + + ; PROGRAM SAVE + ; COMMAND "S" + +SAVE: CALL HEXIY ; START ADDRESS + LD (DTADR),HL ; DATA ADDRESS BUFFER + LD B,H + LD C,L + CALL P4DE + CALL HEXIY ; END ADDRESS + SBC HL,BC ; BYTE SIZE + INC HL + LD (SIZE),HL ; BYTE SIZE BUFFER + CALL P4DE + CALL HEXIY ; EXECUTE ADDRESS + LD (EXADR),HL ; BUFFER + CALL NL + LD DE,MSGSV ; SAVED FILENAME + RST 18H ; CALL MSGX + CALL BGETL ; FILENAME INPUT + CALL P4DE + CALL P4DE + LD HL,NAME ; NAME BUFFER +SAV1: INC DE + LD A,(DE) + LD (HL),A ; FILENAME TRANS. + INC HL + CP 0DH ; END CODE + JR NZ,SAV1 + LD A,01H ; ATTRIBUTE: OBJECT CODE + LD (ATRB),A + CALL QWRI + JP C,QER ; WRITE ERROR + CALL QWRD ; DATA + JP C,QER + CALL NL + LD DE,MSGOK ; OK MESSAGE + RST 18H ; CALL MSGX + JP ST1 + + ; COMPUTE POINT ADDRESS + ; HL=SCREEN COORDINATE + ; EXIT HL=POINT ADDRESS ON SCREEN + +QPONT: LD HL,(DSPXY) +QPNT1: PUSH AF + PUSH BC + PUSH DE + PUSH HL + POP BC + LD DE,COLW ; 40 + LD HL,SCRN-COLW +QPNT2: ADD HL,DE + DEC B + JP P,QPNT2 + LD B,0 + ADD HL,BC + POP DE + POP BC + POP AF + RET + + ; VERIFYING COMMAND "V" + +VRFY: CALL QVRFY + JP C,QER + LD DE,MSGOK + RST 18H + JP ST1 + + ; CLER + ; B=SIZE + ; HL=LOW ADDRESS + +QCLER: XOR A + JR QDINT + +QCLRFF: LD A,0FFH +QDINT: LD (HL),A + INC HL + DJNZ QDINT + RET + + ; GAP CHECK + +GAPCK: PUSH BC + PUSH DE + PUSH HL + LD BC,KEYPB + LD DE,CSTR +GAPCK1: LD H,100 +GAPCK2: CALL EDGE + JR C,GAPCK3 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR NZ,GAPCK1 + DEC H + JR NZ,GAPCK2 +GAPCK3: JP RET3 + + ; MONITOR WORK AREA + ; (MZ700) + + ORG 10F0H +SPV: +IBUFE: ; TAPE BUFFER (128 BYTES) +ATRB: DS virtual 1 ; ATTRIBUTE +NAME: DS virtual 17 ; FILE NAME +SIZE: DS virtual 2 ; BYTESIZE +DTADR: DS virtual 2 ; DATA ADDRESS +EXADR: DS virtual 2 ; EXECUTION ADDRESS +COMNT: DS virtual 104 ; COMMENT +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 27 ; COLUMN MANAGEMENT +FLASH: DS virtual 1 ; FLASHING DATA +FLPST: DS virtual 2 ; FLASHING POSITION +FLSST: DS virtual 1 ; FLASHING STATUS +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER + + ; EQU TABLE I/O REPORT + +KEYPA: EQU 0E000H +KEYPB: EQU 0E001H +KEYPC: EQU 0E002H +KEYPF: EQU 0E003H +CSTR: EQU 0E002H +CSTPT: EQU 0E003H +CONT0: EQU 0E004H +CONT1: EQU 0E005H +CONT2: EQU 0E006H +CONTF: EQU 0E007H +SUNDG: EQU 0E008H +TEMP: EQU 0E008H + ; MONITOR WORK AREA + +SCRN: EQU 0D000H +KANST: EQU 0E003H ; KANA STATUS REPORT + + diff --git a/asm/1Z-013A_80c.asm b/asm/1Z-013A_80c.asm new file mode 100644 index 0000000..8c72138 --- /dev/null +++ b/asm/1Z-013A_80c.asm @@ -0,0 +1,3274 @@ + ; MONITOR PROGRAM 1Z-013A + ; (MZ700) FOR PAL + ; REV. 83.4.7 + ; Tuesday, 02 of June 1998 at 10:02 PM + ; Tuesday, 09 of June 1998 at 07:17 AM + + ORG 0000h ; 0000h Entrypoint + +MONIT: JP START ; MONITOR ON +GETL: JP QGETL ; GET LINE (END "CR") +LETNL: JP QLTNL ; NEW LINE +NL: JP QNL ; +PRNTS: JP QPRTS ; PRINT SPACE +PRNTT: JP QPRTT ; PRINT TAB +PRNT: JP QPRNT ; 1 CHARACTER PRINT +MSG: JP QMSG ; 1 LINE PRINT (END "0DH") +MSGX: JP QMSGX ; RST 18H +GETKY: JP QGET ; GET KEY +BRKEY: JP QBRK ; GET BREAK +WRINF: JP QWRI ; WRITE INFORMATION +WRDAT: JP QWRD ; WRITE DATA +RDINF: JP QRDI ; READ INFORMATION +RDDAT: JP QRDD ; READ DATA +VERFY: JP QVRFY ; VERIFYING CMT +MELDY: JP QMLDY ; RST 30H +TIMST: JP QTMST ; TIME SET + NOP + NOP + JP 1038H ; INTERRUPT ROUTINE (8253) +TIMRD: JP QTMRD ; TIME READ +BELL: JP QBEL ; BELL ON +XTEMP: JP QTEMP ; TEMPO SET (1 - 7) +MSTA: JP MLDST ; MELODY START +MSTP: JP MLDSP ; MELODY STOP + +START: LD SP,SPV ; STACK SET (10F0H) + IM 1 ; IM 1 SET + CALL QMODE ; 8255 MODE SET + CALL QBRK ; CTRL ? + JR NC,ST0 + CP 20H ; KEY IS CTRL KEY + JR NZ,ST0 +CMY0: OUT (0E1H),A ; D000-FFFFH IS DRAM + LD DE,0FFF0H ; TRANS. ADR. + LD HL,DMCP ; MEMORY CHANG PROGRAM + LD BC,05H ; BYTE SIZE + LDIR + JP 0FFF0H ; JUMP $FFF0 + +DMCP: OUT (0E0H),A ; 0000H-0FFFH IS DRAM + JP 0000H + +ST0: LD B,0FFH ; BUFFER CLEAR + LD HL,NAME ; 10F1H-11F0H CLEAR + CALL QCLER + LD A,16H ; LASTER CLR. + CALL PRNT + LD A,71H ; BACK:BLUE CHA.:WRITE + LD HL,0D800H ; COLOR ADDRESS + CALL NCLR8 + LD HL,TIMIN ; INTERRUPT JUMP ROUTINE + LD A,0C3H + LD (1038H),A + LD (1039H),HL + LD A,04H ; NORMAL TEMPO + LD (TEMPW),A + CALL MLDSP ; MELODY STOP + CALL NL + LD DE,MSGQ3 ; ** MONITOR 1Z-013A ** + RST 18H ; CALL MGX + CALL QBEL +SS: LD A,01H + LD (SWRK),A ; KEY IN SILENT + LD HL,0E800H ; USR ROM? + LD (HL),A ; ROM CHECK + JR FD2 + +ST1: CALL NL + LD A,2AH ; "*" PRINT + CALL PRNT + LD DE,BUFER ; GET LINE WORK (11A3H) + CALL GETL +ST2: LD A,(DE) + INC DE + CP 0DH + JR Z,ST1 + CP 'J' ; JUMP + JR Z,GOTO + CP 'L' ; LOAD PROGRAM + JR Z,LOAD + CP 'F' ; FLOPPY ACCESS + JR Z,FD + CP 'B' ; KEY IN BELL + JR Z,SG + CP '#' ; CHANG MEMORY + JR Z,CMY0 + CP 'P' ; PRINTER TEST + JR Z,PTEST + CP 'M' ; MEMORY CORRECTION + JP Z,MCOR + CP 'S' ; SAVE DATA + JP Z,SAVE + CP 'V' ; VERIFYING DATA + JP Z,VRFY + CP 'D' ; DUMP DATA + JP Z,DUMP + NOP + NOP + NOP + NOP + JR ST2 ; NO COMMAND + + ; JUMP COMMAND + +GOTO: CALL HEXIY + JP (HL) + + ; KEY SOUND ON/OFF + +SG: LD A,(SWRK) ; D0=SOUND WORK + RRA + CCF ; CHANGE MODE + RLA + JR SS+2 + + ; FLOPPY + +FD: LD HL,0F000H ; FLOPPY I/O CHECK +FD2: LD A,(HL) + OR A + JR NZ,ST1 +FD1: JP (HL) + + ; ERROR (LOADING) + +QER: CP 02H ; A=02H : BREAK IN + JR Z,ST1 + LD DE,MSGE1 ; CHECK SUM ERROR + RST 18H ; CALL MSGX +L010F: JR ST1 + + ; LOAD COMMAND + +LOAD: CALL QRDI + JR C,QER +LOA0: CALL NL + LD DE,MSGQ2 ; LOADING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + CALL QRDD + JR C,QER + LD HL,(EXADR) ; EXECUTE ADDRESS + LD A,H + CP 12H ; EXECUTE CHECK + JR C,L010F + JP (HL) + + ; GETLINE AND BREAK IN CHECK + ; + ; EXIT BREAK IN THEN JUMP (ST1) + ; ACC=TOP OF LINE DATA + +BGETL: EX (SP),HL + POP BC ; STACK LOAD + LD DE,BUFER ; MONITOR GETLINE BUFF + CALL GETL + LD A,(DE) + CP 1BH ; BREAK CODE + JR Z,L010F ; JP Z,ST1 + JP (HL) + + ; ASCII TO HEX CONVERT + ; INPUT (DE)=ASCII + ; CY=1 THEN JUMP (ST1) + +HEXIY: EX (SP),IY + POP AF + CALL HLHEX + JR C,L010F ; JP C,ST1 + JP (IY) + +MSGE1: DB "CHECK SUM ER.\r" + + ; PLOTTER PRINTER TEST COMMAND + ; (DPG23) + ; &=CONTROL COMMANDS GROUP + ; C=PEN CHANGE + ; G=GRAPH MODE + ; S=80 CHA. IN 1 LINE + ; L=40 CHA. IN 1 LINE + ; T=PLOTTER TEST + ; IN (DE)=PRINT DATA + +PTEST: LD A,(DE) + CP '&' + JR NZ,PTST1 +PTST0: INC DE + LD A,(DE) + CP 'L' ; 40 IN 1 LINE + JR Z,PLPT + CP 'S' ; 80 IN 1 LINE + JR Z,PPLPT + CP 'C' ; PEN CHANGE + JR Z,PEN + CP 'G' ; GRAPH MODE + JR Z,PLOT + CP 'T' ; TEST + JR Z,PTRN +PTST1: CALL PMSG ; PLOT MESSAGE + JP ST1 + +PLPT: LD DE,LLPT ; 01-09-09-0B-0D + JR PTST1 + +PPLPT: LD DE,SLPT ; 01-09-09-09-0D + JR PTST1 + +PTRN: LD A,04H ; TEST PATTERN + JR PLOT+2 + +PLOT: LD A,02H ; GRAPH CODE + CALL LPRNT + JR PTST0 + +PEN: LD A,1DH ; 1 CHANGE CODE (TEXT MODE) + JR PLOT+2 + + ; 1CHA. PRINT TO $LPT + ; IN: ACC PRINT DATA + +LPRNT: LD C,0 ; RDA TEST (READY? RDA=0) + LD B,A ; PRINT DATA STORE + CALL RDA + LD A,B + OUT (0FFH),A ; DATA OUT + LD A,80H ; RDP HIGH + OUT (0FEH),A + LD C,01H ; RDA TEST + CALL RDA + XOR A ; RDP LOW + OUT (0FEH),A + RET + + ; $LPT MSG + ; IN: DE DATA LOW ADDRESS + ; 0DH MSG END + +PMSG: PUSH DE + PUSH BC + PUSH AF +PMSG1: LD A,(DE) ; ACC=DATA + CALL LPRNT + LD A,(DE) + INC DE + CP 0DH ; END? + JR NZ,PMSG1 + POP AF + POP BC + POP DE + RET + + ; RDA CHECK + ; BRKEY IN TO MONITOR RETURN + ; IN: C RDA CODE + +RDA: IN A,(0FEH) + AND 0DH ; RDA ONLY + CP C + RET Z + CALL BRKEY + JR NZ,RDA + LD SP,SPV + JP ST1 + + ; MELODY + ; DE=DATA LOW ADDRESS + ; EXIT CF=1 BREAK + ; CF=0 OK + +QMLDY: PUSH BC + PUSH DE + PUSH HL + LD A,02H + LD (OCTV),A + LD B,01H +MLD1: LD A,(DE) + CP 0DH ; CR + JR Z,MLD4 + CP 0C8H ; END MARK + JR Z,MLD4 + CP 0CFH ; UNDER OCTAVE + JR Z,MLD2 + CP 2DH ; "-" + JR Z,MLD2 + CP 2BH ; "+" + JR Z,MLD3 + CP 0D7H ; UPPER OCTAVE + JR Z,MLD3 + CP 23H ; "#" HANON + LD HL,MTBL + JR NZ,L01F5 + LD HL,MNTBL + INC DE +L01F5: CALL ONPU ; ONTYO SET + JR C,MLD1 + CALL RYTHM + JR C,MLD5 + CALL MLDST ; MELODY START + LD B,C + JR MLD1 + +MLD2: LD A,3 +L0207: LD (OCTV),A + INC DE + JR MLD1 + +MLD3: LD A,01H + JR L0207 + +MLD4: CALL RYTHM +MLD5: PUSH AF + CALL MLDSP + POP AF + JP RET3 + + ; ONPU TO RATIO CONV + ; EXIT (RATIO)=RATIO VALUE + ; C=ONTYO*TEMPO + +ONPU: PUSH BC + LD B,8 +ONP1: LD A,(DE) +L0220: CP (HL) + JR Z,ONP2 + INC HL + INC HL + INC HL + DJNZ L0220 + SCF + INC DE + POP BC + RET + +ONP2: INC HL + PUSH DE + LD E,(HL) + INC HL + LD D,(HL) + EX DE,HL + LD A,H + OR A + JR Z,L023F + LD A,(OCTV) ; 11A0H OCTAVE WORK +L0239: DEC A + JR Z,L023F + ADD HL,HL + JR L0239 + +L023F: LD (RATIO),HL ; 11A1H ONPU RATIO + LD HL,OCTV + LD (HL),02H + DEC HL + POP DE + INC DE + LD A,(DE) + LD B,A + AND 0F0H ; ONTYO ? + CP 30H + JR Z,L0255 + LD A,(HL) ; HL=ONTYO + JR L025A + +L0255: INC DE + LD A,B + AND 0FH + LD (HL),A ; HL=ONTYO +L025A: LD HL,OPTBL + ADD A,L + LD L,A + LD C,(HL) + LD A,(TEMPW) + LD B,A + XOR A +ONP3: ADD A,C + DJNZ ONP3 + POP BC + LD C,A + XOR A + RET + +MTBL: DB "C" + DW 0846H + DB "D" + DW 075FH + DB "E" + DW 0691H + DB "F" + DW 0633H + DB "G" + DW 0586H + DB "A" + DW 04ECH + DB "B" + DW 0464H + DB "R" + DW 0000H +MNTBL: DB "C" ; #C + DW 07CFH + DB "D" ; #D + DW 06F5H + DB "E" ; #E + DW 0633H + DB "F" ; #F + DW 05DAH + DB "G" ; #G + DW 0537H + DB "A" ; #A + DW 04A5H + DB "B" ; #B + DW 0423H + DB "R" ; #R + DW 0000H +OPTBL: DB 01H + DB 02H + DB 03H + DB 04H + DB 06H + DB 08H + DB 0CH + DB 10H + DB 18H + DB 20H + + ; INCREMENT DE REG. + +P4DE: INC DE + INC DE + INC DE + INC DE + RET + + ; MELODY START & STOP + +MLDST: LD HL,(RATIO) + LD A,H + OR A + JR Z,MLDSP + PUSH DE + EX DE,HL + LD HL,CONT0 + LD (HL),E + LD (HL),D + LD A,01H + POP DE + JR MLDS1 + +MLDSP: LD A,36H ; MODE SET (8253 C0) + LD (CONTF),A ; E007H + XOR A +MLDS1: LD (SUNDG),A ; E008H + RET ; TEHRO SET + + ; RHYTHM + ; B=COUNT DATA + ; IN + ; EXIT CF=1 BREAK + ; CF=0 OK + +RYTHM: LD HL,KEYPA ; E000H + LD (HL),0F8H + INC HL + LD A,(HL) + AND 81H ; BREAK IN CHECK + JR NZ,L02D5 + SCF + RET + +L02D5: LD A,(TEMP) ; E008H + RRCA ; TEMPO OUT + JR C,L02D5 +L02DB: LD A,(TEMP) + RRCA + JR NC,L02DB + DJNZ L02D5 + XOR A + RET + + ; TEMPO SET + ; ACC=VALUE (1-7) + +QTEMP: PUSH AF + PUSH BC + AND 0FH + LD B,A + LD A,8 + SUB B + LD (TEMPW),A + POP BC + POP AF + RET + + ; CRT MANAGEMENT + ; EXIT HL:DSPXY H=Y,L=X + ; DE:MANG ADR. (ON DSPXY) + ; A :MANG DATA + ; CY:MANG=1 + +PMANG: LD HL,MANG ; CRT MANG POINTER + LD A,(1172H) ; DSPXY+1 + ADD A,L + LD L,A + LD A,(HL) + INC HL + RL (HL) + OR (HL) + RR (HL) + RRCA + EX DE,HL + LD HL,(DSPXY) + RET + + ; TIME SET + ; ACC=0 : AM + ; =1 : PM + ; DE=SEC: BINARY + +QTMST: DI + PUSH BC + PUSH DE + PUSH HL + LD (AMPM),A ; AMPM DATA + LD A,0F0H + LD (TIMFG),A ; TIME FLAG + LD HL,0A8C0H ; 12 HOURS (43200 SECONDS) + XOR A + SBC HL,DE ; COUNT DATA = 12H-IN DATA + PUSH HL + NOP + EX DE,HL + LD HL,CONTF ; E007H + LD (HL),74H ; C1 + LD (HL),0B0H ; C2 + DEC HL ; CONT2 + LD (HL),E ; E006H + LD (HL),D + DEC HL ; CONT1 + LD (HL),0AH ; E005H STROBE 640,6µSECONDS COUNT2 + LD (HL),0 + INC HL + INC HL ; CONTF + LD (HL),80H ; E007H + DEC HL ; CONT2 +QTMS1: LD C,(HL) ; E006H + LD A,(HL) + CP D + JR NZ,QTMS1 + LD A,C + CP E + JR NZ,QTMS1 + DEC HL ; E005H + NOP + NOP + NOP + LD (HL),0FBH ; 1 SECOND (15611HZ) E005H + LD (HL),3CH + INC HL + POP DE +QTMS2: LD C,(HL) ; E006H + LD A,(HL) + CP D + JR NZ,QTMS2 + LD A,C + CP E + JR NZ,QTMS2 + POP HL + POP DE + POP BC + EI + RET + + ; BELL DATA + ; +QBELD: DB 0D7H + DB "A0" + DB 0DH + NOP + NOP + + ; TIME READ + ; EXIT ACC=0 :AM + ; =1 :PM + ; DE=SEC. BINARY + +QTMRD: PUSH HL + LD HL,CONTF + LD (HL),80H ; E007H C2 + DEC HL ; CONT2 + DI + LD E,(HL) + LD D,(HL) ; e006H C2 MODE0 + EI +L0363: LD A,E + OR D + JR Z,QTMR1 + XOR A + LD HL,0A8C0H ; 12 HOURS + SBC HL,DE + JR C,QTMR2 + EX DE,HL + LD A,(AMPM) + POP HL + RET + +QTMR1: LD DE,0A8C0H +L0378: LD A,(AMPM) + XOR 01H + POP HL + RET + +QTMR2: DI + LD HL,CONT2 + LD A,(HL) + CPL + LD E,A + LD A,(HL) + CPL + LD D,A + EI + INC DE + JR L0378 + + ; TIME INTERRUPT + +TIMIN: PUSH AF + PUSH BC + PUSH DE + PUSH HL + LD HL,AMPM + LD A,(HL) + XOR 01H + LD (HL),A + LD HL,CONTF + LD (HL),80H ; CONT2 + DEC HL + PUSH HL + LD E,(HL) + LD D,(HL) + LD HL,0A8C0H + ADD HL,DE + DEC HL + DEC HL + EX DE,HL + POP HL + LD (HL),E + LD (HL),D + POP HL + POP DE + POP BC + POP AF + EI + RET + + ; SPACE PRINT AND DISP ACC + ; INPUT:HL=DISP. ADR. + +SPHEX: CALL QPRTS ; SPACE PRINT + LD A,(HL) + CALL PRTHX ; DSP OF ACC (ASCII) + LD A,(HL) + RET + + ; (ASCII PRINT) FOR HL + +PRTHL: LD A,H + CALL PRTHX + LD A,L + JR PRTHX + + NOP + NOP + + ; (ASCII PRINT) FOR ACC + +PRTHX: PUSH AF + RRCA + RRCA + RRCA + RRCA + CALL ASC + CALL PRNT + POP AF + CALL ASC + JP PRNT + + ; 80 CHA. 1 LINE CODE (DATA) + +SLPT: DB 01H ; TEXT MODE + DB 09H + DB 09H + DB 09H + DB 0DH + + ; HEXADECIMAL TO ASCII + ; IN : ACC (D3-D0)=HEXADECIMAL + ; EXIT: ACC = ASCII +ASC: AND 0FH + CP 0AH + JR C,NOADD + ADD A,07H +NOADD: ADD A,30H + RET + + ; ASCII TO HEXADECIMAL + ; IN : ACC = ASCII + ; EXIT: ACC = HEXADECIMAL + ; CY = 1 ERROR + +HEXJ: SUB 30H + RET C ; <0 + CP 0AH + CCF + RET NC ; 0-9 + SUB 07H + CP 10H + CCF + RET C + CP 0AH + RET + + NOP + NOP + NOP + NOP + +HEX: JR HEXJ + + ; PRESS PLAY MESSAGE + +MSGN1: DW 207FH +MSGN2: DB "PLAY\r" +MSGN3: DW 207FH + DB "RECORD.\r" ; PRESS RECORD + + NOP + NOP + NOP + NOP + + ; 4 ASCII TO (HL) + ; IN DE=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : OUT + +HLHEX: PUSH DE + CALL L2HEX + JR C,L041D + LD H,A + CALL L2HEX + JR C,L041D + LD L,A +L041D: POP DE + RET + + ; 2 ASCII TO (ACC) + ; IN DE=DATA LOW ADRRESS + ; EXIT CF=0 : OK + ; =1 : OUT + +L2HEX: PUSH BC + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + RRCA + RRCA + RRCA + RRCA + LD C,A + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + OR C +L0434: POP BC + RET + + ; WRITE INFORMATION + +QWRI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,0CCH ; "L" + LD HL,IBUFE ; 10F0H + LD BC,80H ; WRITE BYTE SIZE +WRI1: CALL CKSUM ; CHECK SUM + CALL MOTOR ; MOTOR ON + JR C,WRI3 + LD A,E + CP 0CCH ; "L" + JR NZ,WRI2 + CALL NL + PUSH DE + LD DE,MSGN7 ; WRITING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + POP DE +WRI2: CALL GAP + CALL WTAPE +WRI3: JP RET2 + +MSGN7: DB "WRITING \r" + + ; 40 CHA. IN 1 LINE CODE (DATA) + +LLPT: DB 01H ; TEXT MODE + DB 09H + DB 09H + DB 0BH + DB 0DH + + ; WRITE DATA + ; EXIT CF=0 : OK + ; =1 : BREAK + +QWRD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,53H ; "S" +L047D: LD BC,(SIZE) ; WRITE DATA BYTE SIZE + LD HL,(DTADR) ; WRITE DATA ADDRESS + LD A,B + OR C + JR Z,RET1 + JR WRI1 + + ; TAPE WRITE + ; BC=BYTE SIZE + ; HL=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : BREAK + +WTAPE: PUSH DE + PUSH BC + PUSH HL + LD D,02H + LD A,0F8H ; 88H WOULD BE BETTER!! + LD (KEYPA),A ; E000H +WTAP1: LD A,(HL) + CALL WBYTE ; 1 BYTE WRITE + LD A,(KEYPB) ; E001H + AND 81H ; SHIFT & BREAK + JP NZ,WTAP2 + LD A,02H ; BREAK IN CODE + SCF + JR WTAP3 + +WTAP2: INC HL + DEC BC + LD A,B + OR C + JP NZ,WTAP1 + LD HL,(SUMDT) ; SUM DATA SET + LD A,H + CALL WBYTE + LD A,L + CALL WBYTE + CALL LONG + DEC D + JP NZ,L04C2 + OR A + JP WTAP3 + +L04C2: LD B,0 +L04C4: CALL SHORT + DEC B + JP NZ,L04C4 + POP HL + POP BC + PUSH BC + PUSH HL + JP WTAP1 + +WTAP3: +RET1: POP HL + POP BC + POP DE + RET + + DB 2FH + DB 4EH + + ; READ INFORMATION (FROM $CMT) + ; EXIT ACC=0: OK CF=0 + ; =1: ER CF=1 + ; =2: BREAK CF=1 + +QRDI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H ; "R" + LD E,0CCH ; "L" + LD BC,80H + LD HL,IBUFE +RD1: CALL MOTOR + JP C,RTP6 + CALL TMARK + JP C,RTP6 + CALL RTAPE + JP RTP4 + + ; READ DATA (FROM $CMT) + ; EXIT SAME UP + +QRDD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H ; "R" + LD E,53H ; "S" + LD BC,(SIZE) + LD HL,(DTADR) + LD A,B + OR C + JP Z,RTP4 + JR RD1 + + ; READ TAPE + ; IN BC=SIZE + ; DE=LOAD ADDRESS + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK=1 + +RTAPE: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; TWICE WRITE +RTP1: LD BC,KEYPB + LD DE,CSTR +RTP2: CALL EDGE ; 1-->0 EDGE DETECT + JR C,RTP6 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) ; DATA (1 BIT) READ + AND 20H + JP Z,RTP2 + LD D,H + LD HL,0 + LD (SUMDT),HL + POP HL + POP BC + PUSH BC + PUSH HL +RTP3: CALL RBYTE ; 1 BYTE READ + JR C,RTP6 + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JR NZ,RTP3 + LD HL,(SUMDT) ; CHECK SUM + CALL RBYTE ; CHECK SUM DATA + JR C,RTP6 + LD E,A + CALL RBYTE ; CHECK SUM DATA + JR C,RTP6 + CP L + JR NZ,RTP5 + LD A,E + CP H + JR NZ,RTP5 +RTP8: XOR A +RTP4: +RET2: POP HL + POP BC + POP DE + CALL MSTOP + PUSH AF + LD A,(TIMFG) ; INT. CHECK + CP 0F0H + JR NZ,L0563 + EI +L0563: POP AF + RET + +RTP5: DEC D + JR Z,RTP7 + LD H,D + CALL GAPCK + JR RTP1 + +RTP7: LD A,01H + JR RTP9 + +RTP6: LD A,02H +RTP9: SCF + JR RTP4 + + ; BELL + +QBEL: PUSH DE + LD DE,QBELD + RST 30H ; CALL MELODY + POP DE + RET + + ; FLASHING AND KEYIN + ; EXIT: ACC INPUT KEY DATA (DSP.CODE) + ; H=F0H THEN NO KEYIN (Z FLAG) + +FLKEY: CALL QFLAS + CALL QKEY + CP 0F0H + RET + + NOP + + ; VERIFY (FROM $CMT) + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER CF=1 + ; =2 : BREAK CF=1 + +QVRFY: DI + PUSH DE + PUSH BC + PUSH HL + LD BC,(SIZE) + LD HL,(DTADR) + LD D,0D2H ; "R" + LD E,53H ; "S" + LD A,B + OR C + JR Z,RTP4 ; END + CALL CKSUM + CALL MOTOR + JR C,RTP6 ; BRK + CALL TMARK ; TAPE MARK DETECT + JR C,RTP6 ; BRK + CALL TVRFY + JR RTP4 + + ; DATA VERIFY + ; BC=SIZE + ; HL=DATA LOW ADDRESS + ; CSMDT=CHECK SUM + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK =1 + +TVRFY: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; COMPARE TWICE +TVF1: LD BC,KEYPB + LD DE,CSTR +TVF2: CALL EDGE + JP C,RTP6 ; BRK + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JP Z,TVF2 + LD D,H + POP HL + POP BC + PUSH BC + PUSH HL + ; COMPARE TAPE DATA AND STORAGE +TVF3: CALL RBYTE + JR C,RTP6 ; BRK + CP (HL) + JR NZ,RTP7 ; ERROR, NOT EQUAL + INC HL ; STORAGE ADDRESS + 1 + DEC BC ; SIZE - 1 + LD A,B + OR C + JR NZ,TVF3 + ; COMPARE CHECK SUM (1199H/CSMDT) AND TAPE + LD HL,(CSMDT) + CALL RBYTE + CP H + JR NZ,RTP7 ; ERROR, NOT EQUAL + CALL RBYTE + CP L + JR NZ,RTP7 ; ERROR, NOT EQUAL + DEC D ; NUMBER OF COMPARES (2) - 1 + JP Z,RTP8 ; OK, 2 COMPARES + LD H,D ; (-->05C7H), SAVE NUMBER OF COMPARES + JR TVF1 ; NEXT COMPARE + + ; FLASHING DATA LOAD + +QLOAD: PUSH AF + LD A,(FLASH) + CALL QPONT + LD (HL),A + POP AF + RET + + ; NEW LINE AND PRINT HL REG (ASCII) + +NLPHL: CALL NL + CALL PRTHL + RET + + ; EDGE (TAPE DATA EDGE DETECT) + ; BC=KEYPB (E001H) + ; DE=CSTR (E002H) + ; EXIT CF=0 OK CF=1 BREAK + +EDGE: LD A,0F8H ; BREAK KEY IN (88H WOULD BE BETTER!!) + LD (KEYPA),A + NOP +EDG1: LD A,(BC) + AND 81H ; SHIFT & BREAK + JR NZ,L060E + SCF + RET + +L060E: LD A,(DE) + AND 20H + JR NZ,EDG1 ; CSTR D5 = 0 +EDG2: LD A,(BC) ; 8 + AND 81H ; 9 + JR NZ,L061A ; 10/14 + SCF + RET + +L061A: LD A,(DE) ; 8 + AND 20H ; 9 + JR Z,EDG2 ; CSTR D5 = 1 10/14 + RET ; 11 + + NOP + NOP + NOP + NOP + ; 1 BYTE READ + ; EXIT SUMDT=STORE + ; CF=1 : BREAK + ; CF=0 : DATA=ACC + +RBYTE: PUSH BC + PUSH DE + PUSH HL + LD HL,0800H ; 8 BITS + LD BC,KEYPB ; KEY DATA E001H + LD DE,CSTR ; $TAPE DATA E002H +RBY1: CALL EDGE ; 41 OR 101 + JP C,RBY3 ; 13 (SHIFT & BREAK) + CALL DLY3 ; 20+18*63+33 + LD A,(DE) ; DATA READ :8 + AND 20H + JP Z,RBY2 ; 0 + PUSH HL + LD HL,(SUMDT) + INC HL ; CHECK SUM ; COUNT HIGH BITS ON TAPE + LD (SUMDT),HL + POP HL + SCF +RBY2: LD A,L ; BUILD CHAR + RLA + LD L,A + DEC H ; BITCOUNT-1 + JP NZ,RBY1 + CALL EDGE + LD A,L ; CHAR READ +RBY3: POP HL + POP DE + POP BC + RET + + NOP + NOP + NOP + + ; TAPE MARK DETECT + ; E=@L@ : INFORMATION + ; =@S@ : DATA + ; EXIT CF=0 OK + ; =1 BREAK + +TMARK: CALL GAPCK + PUSH BC + PUSH DE + PUSH HL + LD HL,2828H + LD A,E + CP 0CCH ; "L" + JR Z,L066C + LD HL,1414H +L066C: LD (TMCNT),HL + LD BC,KEYPB + LD DE,CSTR +TM1: LD HL,(TMCNT) +TM2: CALL EDGE + JR C,TM4 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR Z,TM1 + DEC H + JR NZ,TM2 +TM3: CALL EDGE + JR C,TM4 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR NZ,TM1 + DEC L + JR NZ,TM3 + CALL EDGE +TM4: +RET3: POP HL + POP DE + POP BC + RET + + ; MOTOR ON + ; IN D=@W@ :WRITE + ; =@R@ :READ + ; EXIT CF=0 OK + ; =1 BREAK + ; + ; If the button is pressed, + +MOTOR: PUSH BC + PUSH DE + PUSH HL + LD B,0AH ; Pulse motor upto 10 times if sense is low. Each pulse flips on->off or off->on +MOT1: LD A,(CSTR) ; Check sense, if low then pulse motor to switch it on. + AND 10H + JR Z,MOT4 ; If NZ (bit PC4 is high), then wait a bit and return, motor running. + ; If Z then pulse the motor on circuit. +MOT2: LD B,0FFH ; 2 SEC DELAY +L06AD: CALL DLY12 ; 7 MSEC DELAY + JR L06B4 ; MOTOR ENTRY ADJUST + + JR MOTOR ; ORG 06B2H + +L06B4: DJNZ L06AD + XOR A +MOT7: JR RET3 + +MOT4: LD A,06H ; + LD HL,CSTPT ; 8255 Control register + LD (HL),A ; Set PC3 low + INC A + LD (HL),A ; Set PC3 high + DJNZ MOT1 ; Check to see if sense now active. + CALL NL ; Sense not active so play button hasnt been pressed. + LD A,D ; Determine if we are Loading or Saving, display correct message. + CP 0D7H ; "W" + JR Z,MOT8 + LD DE,MSGN1 ; PLAY MARK + JR MOT9 + +MOT8: LD DE,MSGN3 ; "RECORD." + RST 18H ; CALL MSGX + LD DE,MSGN2 ; "PLAY" +MOT9: RST 18H ; CALL MSGX +MOT5: LD A,(CSTR) ; Check sense input and wait until it is high. + AND 10H + JR NZ,MOT2 + CALL QBRK ; If sense is low, check for User Key Break entry. + JR NZ,MOT5 + SCF + JR MOT7 + + ; INITIAL MESSAGE + +MSGQ3: DB "** MONITOR 1Z-013A **\r" + NOP + + ; MOTOR STOP + +MSTOP: PUSH AF + PUSH BC + PUSH DE + LD B,0AH +MST1: LD A,(CSTR) + AND 10H + JR Z,MST3 + LD A,06H + LD (CSTPT),A + INC A + LD (CSTPT),A + DJNZ MST1 +MST3: JP QRSTR1 + + ; CHECK SUM + ; IN BC=SIZE + ; HL=DATA ADDRESS + ; EXIT SUMDT=STORE + ; CSMDT=STORE + +CKSUM: PUSH BC + PUSH DE +L071C: PUSH HL + LD DE,0 +CKS1: LD A,B + OR C + JR NZ,CKS2 + EX DE,HL +L0725: LD (SUMDT),HL ; NUMBER OF HIGHBITS IN DATA + LD (CSMDT),HL + POP HL + POP DE + POP BC + RET + +CKS2: LD A,(HL) + PUSH BC + LD B,8 +CKS3: RLCA + JR NC,L0737 + INC DE +L0737: DJNZ CKS3 +L0739: POP BC + INC HL + DEC BC + JR CKS1 + + ; MODE SET OF KEYPORT + +QMODE: LD HL,KEYPF + LD (HL),8AH ; 10001010 CTRL WORD MODE0 + LD (HL),07H ; PC3=1 M-ON + LD (HL),05H ; PC2=1 INTMSK + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; 107 MICRO SEC DELAY + +DLY1: LD A,15H ; 18*21+20 +L075B: DEC A + JP NZ,L075B + RET + +DLY2: LD A,13H ; 18*19+20 +L0762: DEC A + JP NZ,L0762 + RET + + ; 1 BYTE WRITE + +WBYTE: PUSH BC + LD B,8 + CALL LONG +WBY1: RLCA + CALL C,LONG + CALL NC,SHORT + DEC B + JP NZ,WBY1 + POP BC + RET + + ; GAP + TAPEMARK + ; E=@L@ LONG GAP + ; =@s@ SHORT GAP + +GAP: PUSH BC + PUSH DE + LD A,E + LD BC,55F0H + LD DE,2828H + CP 0CCH ; "L" + JP Z,GAP1 + LD BC,2AF8H + LD DE,1414H +GAP1: CALL SHORT + DEC BC + LD A,B + OR C + JR NZ,GAP1 +GAP2: CALL LONG + DEC D + JR NZ,GAP2 +GAP3: CALL SHORT + DEC E + JR NZ,GAP3 + CALL LONG + POP DE + POP BC + RET + + ; MEMORY CORRECTION + ; COMMAND "M" + +MCOR: CALL HEXIY ; CORRECTION ADDRESS +MCR1: CALL NLPHL ; CORRECTION ADDRESS PRINT + CALL SPHEX ; ACC-->ASCII DISP. + CALL QPRTS ; SPACE PRINT + CALL BGETL ; GET DATA & CHECK DATA + CALL HLHEX ; HL<--ASCII(DE) + JR C,MCR3 + CALL P4DE ; (INC DE)*4 + INC DE + CALL L2HEX ; DATA CHECK + JR C,MCR1 + CP (HL) + JR NZ,MCR1 + INC DE + LD A,(DE) + CP 0DH ; NOT CORRECTION ? + JR Z,MCR2 + CALL L2HEX ; ACC<--HL(ASCII) + JR C,MCR1 + LD (HL),A ; DATA CORRECT +MCR2: INC HL + JR MCR1 + +MCR3: LD H,B ; MEMORY ADDRESS + LD L,C + JR MCR1 + + DB "(HL)" + DB 0F1H + DB 9EH + DB "SUB (" + + ; GET 1 LINE STATEMENT * + ; DE=DATA STORE LOW ADDRESS + ; (END=CR) + +QGETL: PUSH AF + PUSH BC + PUSH HL + PUSH DE +GETL1: CALL QQKEY ; ENTRY KEY +AUTO3: PUSH AF ; IN KEY DATA SAVE + LD B,A + LD A,(SWRK) ; BELL WORK + RRCA + CALL NC,QBEL ; ENTRY BELL + LD A,B + LD HL,KANAF ; KANA & GRAPH FLAGS + AND 0F0H + CP 0C0H + POP DE ; EREG=FLAGREG + LD A,B + JR NZ,GETL2 ; NOT C0H + CP 0CDH ; CR + JR Z,GETL3 + CP 0CBH ; BREAK + JP Z,GETLC + CP 0CFH ; NIKO MARK WH. + JR Z,GETL2 + CP 0C7H ; CRT EDITION + JR NC,GETL5 ; <=C7H + RR E ; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL. + LD A,B + JR NC,GETL5 +GETL2: CALL QDSP ; DISPL. + JR GETL1 + +GETL5: CALL QDPCT ; CRT CONTROL + JR GETL1 + + ; BREAK IN + +GETLC: POP HL + PUSH HL + LD (HL),1BH ; BREAK CODE + INC HL + LD (HL),0DH + JR GETLR + + ; GETLA + +GETLA: RRCA ; CY<--D7 + JR NC,GETL6 + JR GETLB + + ; DELAY 7 MSEC AND SWEP + +DSWEP: CALL DLY12 + CALL QSWEP + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +GETL3: CALL PMANG ; CR + LD B,80 ; 1 LINE + JR NC,GETLA + DEC H ; BEFORE LINE +GETLB: LD B,160 ; 2 LINE +GETL6: LD L,0 + CALL QPNT1 + POP DE ; STORE TOP ADDRESS + PUSH DE +GETLZ: LD A,(HL) + CALL QDACN + LD (DE),A + INC HL + INC DE + DJNZ GETLZ + EX DE,HL +GETLU: LD (HL),0DH + DEC HL + LD A,(HL) + CP 20H ; SPACE THEN CR + + ; CR AND NEW LINE + + JR Z,GETLU + + ; NEW LINE RETURN + +GETLR: CALL QLTNL + POP DE + POP HL + POP BC + POP AF + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; MESSAGE PRINT + ; DE PRINT DATA LOW ADDRESS + ; END=CR + +QMSG: PUSH AF + PUSH BC + PUSH DE +MSG1: LD A,(DE) + CP 0DH ; CR + JR Z,MSGX2 + CALL QPRNT + INC DE + JR MSG1 + + ; ALL PRINT MESSAGE + +QMSGX: PUSH AF + PUSH BC + PUSH DE +MSGX1: LD A,(DE) + CP 0DH +MSGX2: JP Z,QRSTR1 + CALL QADCN + CALL PRNT3 + INC DE + JR MSGX1 + + ; TOP OF KEYTBLS + +QKYSM: LD DE,KTBLS ; SHIFT ALSO + JR QKY5 + + ; BREAK CODE IN + +NBRK: LD A,0CBH ; BREAK CODE + OR A + JR QKY1 + + ; GETKEY + ; NO ECHO BACK + ; EXIT ACC=ASCII CODE + +QGET: CALL QKEY ; KEY IN (DISPLAY CODE) + SUB 0F0H ; NOT KEYIN CODE + RET Z + ADD A,0F0H + JP QDACN ; DISPLAY TO ASCII CODE + + NOP + NOP + + ; 1 KEY INPUT + ; IN B=KEY MODE (SHIFT, CTRL, BREAK) + ; C=KEY DATA (COLUMN & ROW) + ; EXIT ACC=DISPLAY CODE + ; IF NO KEY ACC=F0H + ; IF CY=1 THEN ATTRIBUTE ON + ; (SMALL, HIRAKANA) + +QKEY: PUSH BC + PUSH DE + PUSH HL + CALL DSWEP ; DELAY AND KEY SWEP + LD A,B + RLCA + JR C,QKY2 + LD A,0F0H ; SHIFT OR CTRL HERE +QKY1: POP HL + POP DE + POP BC + RET + +QKY2: LD DE,KTBL ; NORMAL KEY TABLE + LD A,B + CP 88H ; BREAK IN (SHIFT & BRK) + JR Z,NBRK + LD H,0 ; HL=ROW & COLUMN + LD L,C + BIT 5,A ; CTRL CHECK + JR NZ,L08F7 ; YES, CTRL + LD A,(KANAF) ; 0=NR., 1=GRAPH + RRCA + JP C,QKYGRP ; GRAPH MODE + LD A,B ; CTRL KEY CHECK + RLA + RLA + JR C,QKYSM + JR QKY5 + +L08F7: LD DE,KTBLC ; CONTROL KEY TABLE +QKY5: ADD HL,DE ; TABLE +QKY55: LD A,(HL) + JR QKY1 + +QKYGRP: BIT 6,B + JR Z,QKYGRS + LD DE,KTBLG + ADD HL,DE + SCF + JR QKY55 + +QKYGRS: LD DE,KTBLGS + JR QKY5 + + ; NEWLINE + +QLTNL: XOR A + LD (DPRNT),A ; ROW POINTER + LD A,0CDH ; CR + JR PRNT5 + + NOP + NOP + +QNL: LD A,(DPRNT) + OR A + RET Z + JR QLTNL + + NOP + + ; PRINT SPACE + +QPRTS: LD A,20H + JR QPRNT + + ; PRINT TAB + +QPRTT: CALL PRNTS + LD A,(DPRNT) + OR A + RET Z +L092C: SUB 10 + JR C,QPRTT + JR NZ,L092C + NOP + NOP + NOP + + ; PRINT + ; IN ACC=PRINT DATA (ASCII) + +QPRNT: CP 0DH ; CR + JR Z,QLTNL + PUSH BC + LD C,A + LD B,A + CALL QPRT + LD A,B + POP BC + RET + +MSGOK: DB "OK!\r" + + ; PRINT ROUTINE + ; 1 CHARACTER + ; INPUT:C=ASCII DATA (QDSP+QDPCT) + +QPRT: LD A,C + CALL QADCN ; ASCII TO DSPLAY + LD C,A + CP 0F0H + RET Z ; ZERO=ILLEGAL DATA + AND 0F0H ; MSD CHECK + CP 0C0H + LD A,C + JR NZ,PRNT3 + CP 0C7H + JR NC,PRNT3 ; CRT EDITOR +PRNT5: CALL QDPCT + CP 0C3H ; "->" + JR Z,PRNT4 + CP 0C5H ; HOME + JR Z,PRNT2 + CP 0C6H ; CLR + RET NZ +PRNT2: XOR A +L0968: LD (DPRNT),A + RET + +PRNT3: CALL QDSP +PRNT4: LD A,(DPRNT) ; TAB POINT+1 + INC A + CP 80 + JR C,L0968 + SUB 80 + JR L0968 + + ; FLASHING BYPASS 1 + +FLAS1: LD A,(FLASH) + JR FLAS2 + + ; BREAK SUBROUTINE BYPASS 1 + ; CTRL OR NOT KEY + +QBRK2: BIT 5,A ; NOT OR CTRL + JR Z,QBRK3 ; CTRL + OR A ; NOTKEY A=7FH + RET + +QBRK3: LD A,20H ; CTRL D5=1 + OR A ; ZERO FLG CLR + SCF + RET + +MSGSV: DB "FILENAME? " + DB 0DH + + ; DLY 7 MSEC +DLY12: PUSH BC + LD B,15H +L0999: CALL DLY3 + DJNZ L0999 + POP BC + RET + + ; LOADING MESSAGE + +MSGQ2: DB "LOADING \r" + + ; DELAY FOR LONG PULSE + +DLY4: LD A,59H ; 18*89+20 +L09AB: DEC A + JP NZ,L09AB + RET + + NOP + NOP + NOP + + ; KEY BOARD SEARCH + ; & DISPLAY CODE CONVERSION + ; EXIT A=DISPLAY CODE + ; CY=GRAPH MODE + ; WITH CURSOR DISPLAY + +QQKEY: PUSH HL + CALL QSAVE +KSL1: CALL FLKEY ; KEY + JR NZ,KSL1 ; KEY IN THEN JUMP +KSL2: CALL FLKEY + JR Z,KSL2 ; NOT KEY IN THEN JUMP + LD H,A + CALL DLY12 ; DELAY CHATTER + CALL QKEY + PUSH AF + CP H ; CHATTER CHECK + POP HL + JR NZ,KSL2 + PUSH HL + POP AF ; IN KEY DATA + CALL QLOAD ; FLASHING DATA LOAD + POP HL + RET + + ; CLEAR 2 + +NCLR08: XOR A ; CY FLAG +NCLR8: LD BC,0800H +CLEAR: PUSH DE ; BC=CLR BYTE SIZE, A=CLR DATA + LD D,A +CLEAR1: LD (HL),D + INC HL + DEC BC + LD A,B + OR C + JR NZ,CLEAR1 + POP DE + RET + + ; FLASHING 2 + +QFLS: PUSH AF + PUSH HL + LD A,(KEYPC) + RLCA + RLCA + JR C,FLAS1 + LD A,(FLSDT) +FLAS2: CALL QPONT ; DISPLAY POSITION + LD (HL),A + POP HL + POP AF + RET + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +QFLAS: JR QFLS + + ; SHORT AND LONG PULSE FOR 1 BIT WRITE + +SHORT: PUSH AF ; 12 + LD A,03H ; 9 + LD (CSTPT),A ; E003H PC3=1:16 + CALL DLY1 ; 20+18*21+20 + CALL DLY1 ; 20+18*21+20 + LD A,02H ; 9 + LD (CSTPT),A ; E003H PC3=0:16 + CALL DLY1 ; 20+18*21+20 + CALL DLY1 ; 20+18*21+20 + POP AF ; 11 + RET ; 11 + +LONG: PUSH AF ; 11 + LD A,03H ; 9 + LD (CSTPT),A ; 16 + CALL DLY4 ; 20+18*89+20 + LD A,02H ; 9 + LD (CSTPT),A ; 16 + CALL DLY4 ; 20+18*89+20 + POP AF ; 11 + RET ; 11 + + NOP + NOP + NOP + NOP + NOP + + ; BREAK KEY CHECK + ; AND SHIFT, CTRL KEY CHECK + ; EXIT BREAK ON : ZERO=1 + ; OFF: ZERO=0 + ; NO KEY : CY =0 + ; KEY IN : CY =1 + ; A D6=1 : SHIFT ON + ; =0 : OFF + ; D5=1 : CTRL ON + ; =0 : OFF + ; D4=1 : SHIFT+CNT ON + ; =0 : OFF + +QBRK: LD A,0F8H ; LINE 8SWEEP + LD (KEYPA),A + NOP + LD A,(KEYPB) + OR A + RRA + JP C,QBRK2 ; SHIFT ? + RLA + RLA + JR NC,QBRK1 ; BREAK ? + LD A,40H ; SHIFT D6=1 + SCF + RET + +QBRK1: XOR A ; SHIFT ? + RET + + ; 320 U SEC DELAY + +DLY3: LD A,3FH ; 18*63+33 + JP L0762 ; JP DLY2+2 + + NOP + + ; KEY BOARD SWEEP + ; EXIT B,D7=0 NO DATA + ; =1 DATA + ; D6=0 SHIFT OFF + ; =1 SHIFT ON + ; D5=0 CTRL OFF + ; =1 CTRL ON + ; D4=0 SHIFT+CTRL OFF + ; =1 SHIFT+CTRL ON + ; C = ROW & COLUMN + ; 7 6 5 4 3 2 1 0 + ; * * ^ ^ ^ < < < + +QSWEP: PUSH DE + PUSH HL + XOR A + LD B,0F8H + LD D,A + CALL QBRK + JR NZ,SWEP6 + LD D,88H ; BREAK ON + JR SWEP9 + +SWEP6: JR NC,SWEP0 + LD D,A + JR SWEP0 + +SWEP01: SET 7,D +SWEP0: DEC B + LD A,B + LD (KEYPA),A + CP 0EFH ; MAP SWEEP END ? + JR NZ,SWEP3 + CP 0F8H ; BREAK KEY ROW + JR Z,SWEP0 +SWEP9: LD B,D + POP HL + POP DE + RET + +SWEP3: LD A,(KEYPB) + CPL + OR A + JR Z,SWEP0 + LD E,A +SWEP2: LD H,8 + LD A,B + AND 0FH + RLCA + RLCA + RLCA + LD C,A + LD A,E +L0A89: DEC H + RRCA + JR NC,L0A89 + LD A,H + ADD A,C + LD C,A + JR SWEP01 + ; + ; + ; ASCII TO DISPLAY CODE TABL + ; +ATBL: + ; 00 - 0F + DB 0F0H ; ^ @ + DB 0F0H ; ^ A + DB 0F0H ; ^ B + DB 0F3H ; ^ C + DB 0F0H ; ^ D + DB 0F5H ; ^ E + DB 0F0H ; ^ F + DB 0F0H ; ^ G + DB 0F0H ; ^ H + DB 0F0H ; ^ I + DB 0F0H ; ^ J + DB 0F0H ; ^ K + DB 0F0H ; ^ L + DB 0F0H ; ^ M + DB 0F0H ; ^ N + DB 0F0H ; ^ O + ; 10 - 1F + DB 0F0H ; ^ P + DB 0C1H ; ^ Q CUR. DOWN + DB 0C2H ; ^ R CUR. UP + DB 0C3H ; ^ S CUR. RIGHT + DB 0C4H ; ^ T CUR. LEFT + DB 0C5H ; ^ U HOME + DB 0C6H ; ^ V CLEAR + DB 0F0H ; ^ W + DB 0F0H ; ^ X + DB 0F0H ; ^ Y + DB 0F0H ; ^ Z SEP. + DB 0F0H ; ^ [ + DB 0F0H ; ^ \ + DB 0F0H ; ^ ] + DB 0F0H ; ^ ^ + DB 0F0H ; ^ - + ; 20 - 2F + DB 00H ; SPACE + DB 61H ; ! + DB 62H ; " + DB 63H ; # + DB 64H ; $ + DB 65H ; % + DB 66H ; & + DB 67H ; ' + DB 68H ; ( + DB 69H ; ) + DB 6BH ; * + DB 6AH ; + + DB 2FH ; , + DB 2AH ; - + DB 2EH ; . + DB 2DH ; / + ; 30 - 3F + DB 20H ; 0 + DB 21H ; 1 + DB 22H ; 2 + DB 23H ; 3 + DB 24H ; 4 + DB 25H ; 5 + DB 26H ; 6 + DB 27H ; 7 + DB 28H ; 8 + DB 29H ; 9 + DB 4FH ; : + DB 2CH ; ; + DB 51H ; < + DB 2BH ; = + DB 57H ; > + DB 49H ; ? + ; 40 - 4F + DB 55H ; @ + DB 01H ; A + DB 02H ; B + DB 03H ; C + DB 04H ; D + DB 05H ; E + DB 06H ; F + DB 07H ; G + DB 08H ; H + DB 09H ; I + DB 0AH ; J + DB 0BH ; K + DB 0CH ; L + DB 0DH ; M + DB 0EH ; N + DB 0FH ; O + ; 50 - 5F + DB 10H ; P + DB 11H ; Q + DB 12H ; R + DB 13H ; S + DB 14H ; T + DB 15H ; U + DB 16H ; V + DB 17H ; W + DB 18H ; X + DB 19H ; Y + DB 1AH ; Z + DB 52H ; [ + DB 59H ; \ + DB 54H ; ] + DB 50H ; + DB 45H ; + ; 60 - 6F + DB 0C7H ; UFO + DB 0C8H + DB 0C9H + DB 0CAH + DB 0CBH + DB 0CCH + DB 0CDH + DB 0CEH + DB 0CFH + DB 0DFH + DB 0E7H + DB 0E8H + DB 0E5H + DB 0E9H + DB 0ECH + DB 0EDH + ; 70 - 7F + DB 0D0H + DB 0D1H + DB 0D2H + DB 0D3H + DB 0D4H + DB 0D5H + DB 0D6H + DB 0D7H + DB 0D8H + DB 0D9H + DB 0DAH + DB 0DBH + DB 0DCH + DB 0DDH + DB 0DEH + DB 0C0H + ; 80 - 8F + DB 80H ; } + DB 0BDH + DB 9DH + DB 0B1H + DB 0B5H + DB 0B9H + DB 0B4H + DB 9EH + DB 0B2H + DB 0B6H + DB 0BAH + DB 0BEH + DB 9FH + DB 0B3H + DB 0B7H + DB 0BBH + ; 90 - 9F + DB 0BFH ; _ + DB 0A3H + DB 85H + DB 0A4H ; ` + DB 0A5H ; ~ + DB 0A6H + DB 94H + DB 87H + DB 88H + DB 9CH + DB 82H + DB 98H + DB 84H + DB 92H + DB 90H + DB 83H + ; A0 - AF + DB 91H + DB 81H + DB 9AH + DB 97H + DB 93H + DB 95H + DB 89H + DB 0A1H + DB 0AFH + DB 8BH + DB 86H + DB 96H + DB 0A2H + DB 0ABH + DB 0AAH + DB 8AH + ; B0 - BF + DB 8EH + DB 0B0H + DB 0ADH + DB 8DH + DB 0A7H + DB 0A8H + DB 0A9H + DB 8FH + DB 8CH + DB 0AEH + DB 0ACH + DB 9BH + DB 0A0H + DB 99H + DB 0BCH ; { + DB 0B8H + ; C0 - CF + DB 40H + DB 3BH + DB 3AH + DB 70H + DB 3CH + DB 71H + DB 5AH + DB 3DH + DB 43H + DB 56H + DB 3FH + DB 1EH + DB 4AH + DB 1CH + DB 5DH + DB 3EH + ; D0 - DF + DB 5CH + DB 1FH + DB 5FH + DB 5EH + DB 37H + DB 7BH + DB 7FH + DB 36H + DB 7AH + DB 7EH + DB 33H + DB 4BH + DB 4CH + DB 1DH + DB 6CH + DB 5BH + ; E0 - EF + DB 78H + DB 41H + DB 35H + DB 34H + DB 74H + DB 30H + DB 38H + DB 75H + DB 39H + DB 4DH + DB 6FH + DB 6EH + DB 32H + DB 77H + DB 76H + DB 72H + ; F0 - FF + DB 73H + DB 47H + DB 7CH + DB 53H + DB 31H + DB 4EH + DB 6DH + DB 48H + DB 46H + DB 7DH + DB 44H + DB 1BH + DB 58H + DB 79H + DB 42H + DB 60H + + ; FLASHING DATA SAVE + +QSAVE: LD HL,FLSDT + LD (HL),0EFH ; NORMAL CURSOR + LD A,(KANAF) + RRCA + JR C,L0BA0 ; GRAPH MODE + RRCA + JR NC,SV0 ; NORMAL MODE +L0BA0: LD (HL),0FFH ; GRAPH CURSOR +SV0: LD A,(HL) + PUSH AF + CALL QPONT ; FLASHING POSITION + LD A,(HL) + LD (FLASH),A + POP AF + LD (HL),A + XOR A + LD HL,KEYPA +L0BB1: LD (HL),A + CPL ; OH NO! UNUSED BITS WERE TOUCHED TOO!!! + LD (HL),A + RET + +SV1: LD (HL),43H ; KANA CURSOR + JR SV0 + + ; ASCII TO DISPLAY CODE CONVERT + ; IN ACC:ASCII + ; EXIT ACC:DISPLAY CODE + +QADCN: PUSH BC + PUSH HL + LD HL,ATBL + LD C,A + LD B,0 + ADD HL,BC + LD A,(HL) + JR DACN3 + +VRNS: DB "V1.0A\r" ; VERSION MANAGEMENT + NOP + NOP + NOP + + ; DISPLAY CODE TO ASCII CONVERSION + ; IN ACC=DISPLAY CODE + ; EXIT ACC=ASCII + +QDACN: PUSH BC + PUSH HL + PUSH DE + LD HL,ATBL + LD D,H + LD E,L + LD BC,0100H + CPIR + JR Z,DACN1 + LD A,0F0H +DACN2: POP DE +DACN3: POP HL + POP BC + RET + +DACN1: OR A + DEC HL + SBC HL,DE + LD A,L + JR DACN2 + + ; + ; + ; KEY MATRIX TO DISPLAY CODE TABL + ; +KTBL: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0CAH ; GRAPH + DB 58H ; + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 2CH ; ; + DB 4FH ; : + DB 0CDH ; CR + ;S1 08 - 0F + DB 19H ; Y + DB 1AH ; Z + DB 55H ; @ + DB 52H ; [ + DB 54H ; ] + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 0F0H ; NULL + ;S2 10 - 17 + DB 11H ; Q + DB 12H ; R + DB 13H ; S + DB 14H ; T + DB 15H ; U + DB 16H ; V + DB 17H ; W + DB 18H ; X + ;S3 18 - 1F + DB 09H ; I + DB 0AH ; J + DB 0BH ; K + DB 0CH ; L + DB 0DH ; M + DB 0EH ; N + DB 0FH ; O + DB 10H ; P + ;S4 20 - 27 + DB 01H ; A + DB 02H ; B + DB 03H ; C + DB 04H ; D + DB 05H ; E + DB 06H ; F + DB 07H ; G + DB 08H ; H + ;S5 28 - 2F + DB 21H ; 1 + DB 22H ; 2 + DB 23H ; 3 + DB 24H ; 4 + DB 25H ; 5 + DB 26H ; 6 + DB 27H ; 7 + DB 28H ; 8 + ;S6 30 - 37 + DB 59H ; \ + DB 50H ; + DB 2AH ; - + DB 00H ; SPACE + DB 20H ; 0 + DB 29H ; 9 + DB 2FH ; , + DB 2EH ; . + ;S7 38 - 3F + DB 0C8H ; INST. + DB 0C7H ; DEL. + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 49H ; ? + DB 2DH ; / + ; + ; + ; KTBL SHIFT ON + ; +KTBLS: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0CAH ; GRAPH + DB 1BH ; POND + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 6AH ; + + DB 6BH ; * + DB 0CDH ; CR + ;S1 08 - 0F + DB 99H ; y + DB 9AH ; z + DB 0A4H ; ` + DB 0BCH ; { + DB 40H ; } + DB 0F0H ; NULL + DB 0F0H ; NULL + DB 0F0H ; NULL + ;S2 10 - 17 + DB 91H ; q + DB 92H ; r + DB 93H ; s + DB 94H ; t + DB 95H ; u + DB 96H ; v + DB 97H ; w + DB 98H ; x + ;S3 18 - 1F + DB 89H ; i + DB 8AH ; j + DB 8BH ; k + DB 8CH ; l + DB 8DH ; m + DB 8EH ; n + DB 8FH ; o + DB 90H ; p + ;S4 20 - 27 + DB 81H ; a + DB 82H ; b + DB 83H ; c + DB 84H ; d + DB 85H ; e + DB 86H ; f + DB 87H ; g + DB 88H ; h + ;S5 28 - 2F + DB 61H ; ! + DB 62H ; " + DB 63H ; # + DB 64H ; $ + DB 65H ; % + DB 66H ; & + DB 67H ; ' + DB 68H ; ( + ;S6 30 - 37 + DB 80H ; \ + DB 0A5H ; POND MARK + DB 2BH ; YEN + DB 00H ; SPACE + DB 60H ; ¶ + DB 69H ; ) + DB 51H ; < + DB 57H ; > + ;S7 38 - 3F + DB 0C6H ; CLR + DB 0C5H ; HOME + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 5AH ; + DB 45H ; + ; + ; + ; GRAPHIC + ; +KTBLGS: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0F0H ; GRAPH BUT NULL + DB 0E5H ; # + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 42H ; # ; + DB 0B6H ; #: + DB 0CDH ; CR + ;S1 08 - 0F + DB 75H ; #Y + DB 76H ; #Z + DB 0B2H ; #@ + DB 0D8H ; #[ + DB 4EH ; #] + DB 0F0H ; #NULL + DB 0F0H ; #NULL + DB 0F0H ; #NULL + ;S2 10 - 17 + DB 3CH ; #Q + DB 30H ; #R + DB 44H ; #S + DB 71H ; #T + DB 79H ; #U + DB 0DAH ; #V + DB 38H ; #W + DB 6DH ; #X + ;S3 18 - 1F + DB 7DH ; #I + DB 5CH ; #J + DB 5BH ; #K + DB 0B4H ; #L + DB 1CH ; #M + DB 32H ; #N + DB 0B0H ; #O + DB 0D6H ; #P + ;S4 20 - 27 + DB 53H ; #A + DB 6FH ; #B + DB 0DEH ; #C + DB 47H ; #D + DB 34H ; #E + DB 4AH ; #F + DB 4BH ; #G + DB 72H ; #H + ;S5 28 - 2F + DB 37H ; #1 + DB 3EH ; #2 + DB 7FH ; #3 + DB 7BH ; #4 + DB 3AH ; #5 + DB 5EH ; #6 + DB 1FH ; #7 + DB 0BDH ; #8 + ;S6 30 - 37 + DB 0D4H ; #YEN + DB 9EH ; #+ + DB 0D2H ; #- + DB 00H ; SPACE + DB 9CH ; #0 + DB 0A1H ; #9 + DB 0CAH ; #, + DB 0B8H ; #. + ;S7 38 - 3F + DB 0C8H ; INST + DB 0C7H ; DEL. + DB 0C2H ; CURSOR UP + DB 0C1H ; CURSOR DOWN + DB 0C3H ; CURSOR RIGHT + DB 0C4H ; CURSOR LEFT + DB 0BAH ; #? + DB 0DBH ; #/ + ; + ; + ; CONTROL CODE + ; +KTBLC: + ;S0 00 - 07 + DB 0F0H + DB 0F0H + DB 0F0H ; ^ + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + ;S1 08 - 0F + DB 0F0H ; ^Y E3 + DB 5AH ; ^Z E4 (CHECKER) + DB 0F0H ; ^@ + DB 0F0H ; ^[ EB/E5 + DB 0F0H ; ^] EA/E7 + DB 0F0H ; #NULL + DB 0F0H ; #NULL + DB 0F0H ; #NULL + ;S2 10 - 17 + DB 0C1H ; ^Q + DB 0C2H ; ^R + DB 0C3H ; ^S + DB 0C4H ; ^T + DB 0C5H ; ^U + DB 0C6H ; ^V + DB 0F0H ; ^W E1 + DB 0F0H ; ^X E2 + ;S3 18 - 1F + DB 0F0H ; ^I F9 + DB 0F0H ; ^J FA + DB 0F0H ; ^K FB + DB 0F0H ; ^L FC + DB 0F0H ; ^M CD + DB 0F0H ; ^N FE + DB 0F0H ; ^O FF + DB 0F0H ; ^P E0 + ;S4 20 - 27 + DB 0F0H ; ^A F1 + DB 0F0H ; ^B F2 + DB 0F0H ; ^C F3 + DB 0F0H ; ^D F4 + DB 0F0H ; ^E F5 + DB 0F0H ; ^F F6 + DB 0F0H ; ^G F7 + DB 0F0H ; ^H F8 + ;S5 28 - 2F + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + ;S6 30 - 37 (ERROR? 7 VALUES ONLY!!) + DB 0F0H ; ^YEN E6 + DB 0F0H ; ^ EF + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H ; ^, + DB 0F0H + ;S7 38 - 3F + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H ; ^/ EE + ; + ; + ; KANA + ; +KTBLG: + ;S0 00 - 07 + DB 0BFH ; SPARE + DB 0F0H ; GRAPH BUT NULL + DB 0CFH ; NIKO WH. + DB 0C9H ; ALPHA + DB 0F0H ; NO + DB 0B5H ; MO + DB 4DH ; DAKU TEN + DB 0CDH ; CR + ;S1 08 - 0F + DB 35H ; HA + DB 77H ; TA + DB 0D7H ; WA + DB 0B3H ; YO + DB 0B7H ; HANDAKU + DB 0F0H + DB 0F0H + DB 0F0H + ;S2 10 - 17 + DB 7CH ; KA + DB 70H ; KE + DB 41H ; SHI + DB 31H ; KO + DB 39H ; HI + DB 0A6H ; TE + DB 78H ; KI + DB 0DDH ; CHI + ;S3 18 - 1F + DB 3DH ; FU + DB 5DH ; MI + DB 6CH ; MU + DB 56H ; ME + DB 1DH ; RHI + DB 33H ; RA + DB 0D5H ; HE + DB 0B1H ; HO + ;S4 20 - 27 + DB 46H ; SA + DB 6EH ; TO + DB 0D9H ; THU + DB 48H ; SU + DB 74H ; KU + DB 43H ; SE + DB 4CH ; SO + DB 73H ; MA + ;S5 28 - 2F + DB 3FH ; A + DB 36H ; I + DB 7EH ; U + DB 3BH ; E + DB 7AH ; O + DB 1EH ; NA + DB 5FH ; NI + DB 0A2H ; NU + ;S6 30 - 37 + DB 0D3H ; YO + DB 9FH ; YU + DB 0D1H ; YA + DB 00H ; SPACE + DB 9DH ; NO + DB 0A3H ; NE + DB 0D0H ; RU + DB 0B9H ; RE + ;S7 38 - 3F + DB 0C6H ; ?CLR + DB 0C5H ; ?HOME + DB 0C2H ; ?CURSOR UP + DB 0C1H ; ?CURSOR DOWN + DB 0C3H ; ?CURSOR RIGHT + DB 0C4H ; ?CURSOR LEFT + DB 0BBH ; DASH + DB 0BEH ; RO + + ; MEMORY DUMP COMMAND "D" + +DUMP: CALL HEXIY ; START ADDRESS + CALL P4DE + PUSH HL + CALL HLHEX ; END ADDRESS + POP DE + JR C,DUM1 ; DATA ERROR THEN +L0D36: EX DE,HL +DUM3: LD B,08H ; DISPLAY 8 BYTES + LD C,23 ; CHANGE PRINT BIAS + CALL NLPHL ; NEWLINE PRINT +DUM2: CALL SPHEX ; SPACE PRINT + ACC PRINT + INC HL + PUSH AF + LD A,(DSPXY) ; DISPLAY POINT + ADD A,C + LD (DSPXY),A ; X AXIS=X+CREG + POP AF + CP 20H + JR NC,L0D51 + LD A,2EH ; "." +L0D51: CALL QADCN ; ASCII TO DISPLAY CODE + CALL PRNT3 + LD A,(DSPXY) + INC C + SUB C ; ASCII DISPLAY POSITION + LD (DSPXY),A + DEC C + DEC C + DEC C + PUSH HL + SBC HL,DE + POP HL + JR Z,L0D85 + LD A,0F8H + LD (KEYPA),A + NOP + LD A,(KEYPB) + CP 0FEH ; SHIFT KEY ? + JR NZ,L0D78 + CALL QBLNK ; 64MSEC DELAY +L0D78: DJNZ DUM2 +L0D7A: CALL QKEY ; STOP DISPLAY + OR A + JR Z,L0D7A ; SPACE KEY THEN STOP + CALL QBRK ; BREAK IN ? + JR NZ,DUM3 +L0D85: JP ST1 ; COMMAND IN ! + +DUM1: LD HL,160 ; 20*8 BYTES + ADD HL,DE + JR L0D36 + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; V-BLANK CHECK + +QBLNK: PUSH AF +L0DA7: LD A,(KEYPC) ; V-BLANK + RLCA + JR NC,L0DA7 +L0DAD: LD A,(KEYPC) ; 64 + RLCA ; + JR C,L0DAD ; MSEC + POP AF + RET + ; DISPLAY ON POINTER + ; ACC=DISPLAY CODE + ; EXCEPT F0H + +QDSP: PUSH AF + PUSH BC + PUSH DE + PUSH HL +DSP01: CALL QPONT ; DISPLAY POSITION + LD (HL),A + LD HL,(DSPXY) + LD A,L + CP 79 + JR NZ,DSP04 + CALL PMANG + JR C,DSP04 + EX DE,HL + LD (HL),1 ; LOGICAL 1ST COLUMN + INC HL + LD (HL),0 ; LOGICAL 2ND COLUMN +DSP04: LD A,0C3H ; CURSL + JR L0DE0 + + ; GRAPHIC STATUS CHECK + +GRSTAS: LD A,(KANAF) + CP 01H + LD A,0CAH + RET + + ; DISPLAY CONTROL + ; ACC=CONTROL CODE + +QDPCT: PUSH AF + PUSH BC + PUSH DE + PUSH HL +L0DE0: LD B,A + AND 0F0H + CP 0C0H + JR NZ,CURS5 + XOR B + RLCA + LD C,A + LD B,0 + LD HL,CTBL ; PAGE MODE1 + ADD HL,BC + LD E,(HL) + INC HL + LD D,(HL) + LD HL,(DSPXY) + EX DE,HL + JP (HL) + +CURSD: EX DE,HL ; LD HL,(DSPXY) + LD A,H + CP 24 + JR Z,CURS4 + INC H +CURS1: +CURS3: LD (DSPXY),HL +CURS5: JP QRSTR + +CURSU: EX DE,HL ; LD HL,(DSPXY) + LD A,H + OR A + JR Z,CURS5 + DEC H +CURSU1: JR CURS3 + +CURSR: EX DE,HL ; LD HL,(DSPXY) + LD A,L + CP 79 + JR NC,CURS2 + INC L + JR CURS3 + +CURS2: LD L,0 + INC H + LD A,H + CP 25 + JR C,CURS1 + LD H,24 + LD (DSPXY),HL +CURS4: JR SCROL + +CURSL: EX DE,HL ; LD HL,(DSPXY) + LD A,L + OR A + JR Z,L0E2D + DEC L + JR CURS3 + +L0E2D: LD L,79 + DEC H + JP P,CURSU1 + LD H,0 + LD (DSPXY),HL + JR CURS5 + +CLRS: LD HL,MANG + LD B,27 + CALL QCLER + LD HL,0D000H ; SCRN TOP + CALL NCLR08 + LD A,71H ; COLOR DATA + CALL NCLR8 ; D800H-DFFFH CLEAR +HOME: LD HL,0 ; DSPXY:0 X=0,Y=0 + JR CURS3 + + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + ; CR + +CR: CALL PMANG + RRCA + JR NC,CURS2 + LD L,0 + INC H + CP 24 + JR Z,CR1 + INC H + JR CURS1 + +CR1: LD (DSPXY),HL + + ; SCROLL + +SCROL: LD BC,2000 - 80 ; Scroll all lines except top. + LD DE,SCRN ; TOP OF $CRT ADDRESS + LD HL,SCRN+80 ; COLUMN + PUSH BC ; 1000 STORE + LDIR + POP BC + PUSH DE + LD DE,SCRN+800H ; COLOR RAM SCROLL + LD HL,SCRN+850H ; SCROLL TOP + 80 + LDIR + LD B,80 ; ONE LINE + EX DE,HL + LD A,71H ; COLOR RAM INITIAL DATA + CALL QDINT + POP HL + LD B,80 + CALL QCLER ; LAST LINE CLEAR + LD BC,26 ; ROW NUMBER+1 + LD DE,MANG ; LOGICAL MANAGEMENT + LD HL,MANG+1 + LDIR + LD (HL),0 + LD A,(MANG) + OR A + JR Z,QRSTR + LD HL,DSPXY+1 + DEC (HL) + JR SCROL + + ; CONTROL CODE TABLE + +CTBL: DW SCROL ; SCROLLING 10H + DW CURSD ; CURSOR DOWN 11H + DW CURSU ; CURSOR UP 12H + DW CURSR ; CURSOR RIGHT 13H + DW CURSL ; CURSOR LEFT 14H + DW HOME ; 15H + DW CLRS ; 16H + DW DEL ; 17H + DW INST ; 18H + DW ALPHA ; 19H + DW KANA ; GRAPHIC 1AH + DW QRSTR ; 1BH + DW QRSTR ; 1CH + DW CR ; 1DH + DW QRSTR ; 1EH + DW QRSTR ; 1FH + + ; INST BYPASS + +INST2: SET 3,H ; COLOR RAM + LD A,(HL) ; FROM + INC HL + LD (HL),A ; TO + DEC HL ; ADDRESS ADJUST + RES 3,H + LDD ; CHANGE TRNS. + LD A,C + OR B ; BC=0 ? + JR NZ,INST2 + EX DE,HL + LD (HL),0 + SET 3,H ; COLOR RAM + LD (HL),71H + JR QRSTR + +ALPHA: XOR A +ALPH1: LD (KANAF),A + + ; RESTORE + +QRSTR: POP HL +QRSTR1: POP DE + POP BC + POP AF + RET + + NOP + NOP + NOP + NOP + +KANA: CALL GRSTAS + JP Z,DSP01 ; NOT GRAPH KEY THEN JUMP + LD A,01H + JR ALPH1 + +DEL: EX DE,HL ; LD HL,(DSPXY) + LD A,H ; HOME ? + OR L + JR Z,QRSTR + LD A,L + OR A + JR NZ,DEL1 ; LEFT SIDE ? + CALL PMANG + JR C,DEL1 + CALL QPONT + DEC HL + LD (HL),0 + JR L0F33 ; JUMP CURSL + +DEL1: CALL PMANG + RRCA + LD A,80 + JR NC,L0F17 + RLCA ; ACC=80 +L0F17: SUB L + LD B,A ; TRNS. BYTE + CALL QPONT +DEL2: LD A,(HL) ; CHANGE FROM ADDRESS + DEC HL + LD (HL),A ; TO + INC HL + SET 3,H ; COLOR RAM + LD A,(HL) + DEC HL + LD (HL),A + RES 3,H ; CHANGE + INC HL + INC HL ; NEXT + DJNZ DEL2 + DEC HL ; ADDRESS ADJUST + LD (HL),0 + SET 3,H + LD HL,71H ; BLUE + WHITE +L0F33: LD A,0C4H ; JP CURSL + JP L0DE0 + +INST: CALL PMANG + RRCA + LD L,79 + LD A,L + JR NC,L0F42 + INC H +L0F42: CALL QPNT1 + PUSH HL + LD HL,(DSPXY) + JR NC,L0F4D + LD A,79 +L0F4D: SUB L + LD B,0 + LD C,A + POP DE + JR Z,QRSTR + LD A,(DE) + OR A + JR NZ,QRSTR + LD H,D ; HL<-DE + LD L,E + DEC HL + JP INST2 ; JUMP NEXT (BYPASS) + + ; PROGRAM SAVE + ; COMMAND "S" + +SAVE: CALL HEXIY ; START ADDRESS + LD (DTADR),HL ; DATA ADDRESS BUFFER + LD B,H + LD C,L + CALL P4DE + CALL HEXIY ; END ADDRESS + SBC HL,BC ; BYTE SIZE + INC HL + LD (SIZE),HL ; BYTE SIZE BUFFER + CALL P4DE + CALL HEXIY ; EXECUTE ADDRESS + LD (EXADR),HL ; BUFFER + CALL NL + LD DE,MSGSV ; SAVED FILENAME + RST 18H ; CALL MSGX + CALL BGETL ; FILENAME INPUT + CALL P4DE + CALL P4DE + LD HL,NAME ; NAME BUFFER +SAV1: INC DE + LD A,(DE) + LD (HL),A ; FILENAME TRANS. + INC HL + CP 0DH ; END CODE + JR NZ,SAV1 + LD A,01H ; ATTRIBUTE: OBJECT CODE + LD (ATRB),A + CALL QWRI + JP C,QER ; WRITE ERROR + CALL QWRD ; DATA + JP C,QER + CALL NL + LD DE,MSGOK ; OK MESSAGE + RST 18H ; CALL MSGX + JP ST1 + + ; COMPUTE POINT ADDRESS + ; HL=SCREEN COORDINATE + ; EXIT HL=POINT ADDRESS ON SCREEN + +QPONT: LD HL,(DSPXY) +QPNT1: PUSH AF + PUSH BC + PUSH DE + PUSH HL + POP BC + LD DE,0050H ; 80 + LD HL,SCRN-80 +QPNT2: ADD HL,DE + DEC B + JP P,QPNT2 + LD B,0 + ADD HL,BC + POP DE + POP BC + POP AF + RET + + ; VERIFYING COMMAND "V" + +VRFY: CALL QVRFY + JP C,QER + LD DE,MSGOK + RST 18H + JP ST1 + + ; CLER + ; B=SIZE + ; HL=LOW ADDRESS + +QCLER: XOR A + JR QDINT + +QCLRFF: LD A,0FFH +QDINT: LD (HL),A + INC HL + DJNZ QDINT + RET + + ; GAP CHECK + +GAPCK: PUSH BC + PUSH DE + PUSH HL + LD BC,KEYPB + LD DE,CSTR +GAPCK1: LD H,100 +GAPCK2: CALL EDGE + JR C,GAPCK3 + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JR NZ,GAPCK1 + DEC H + JR NZ,GAPCK2 +GAPCK3: JP RET3 + + ; MONITOR WORK AREA + ; (MZ700) + + ORG 10F0H +SPV: +IBUFE: ; TAPE BUFFER (128 BYTES) +ATRB: DS virtual 1 ; ATTRIBUTE +NAME: DS virtual 17 ; FILE NAME +SIZE: DS virtual 2 ; BYTESIZE +DTADR: DS virtual 2 ; DATA ADDRESS +EXADR: DS virtual 2 ; EXECUTION ADDRESS +COMNT: DS virtual 104 ; COMMENT +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 27 ; COLUMN MANAGEMENT +FLASH: DS virtual 1 ; FLASHING DATA +FLPST: DS virtual 2 ; FLASHING POSITION +FLSST: DS virtual 1 ; FLASHING STATUS +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER + + ; EQU TABLE I/O REPORT + +KEYPA: EQU 0E000H +KEYPB: EQU 0E001H +KEYPC: EQU 0E002H +KEYPF: EQU 0E003H +CSTR: EQU 0E002H +CSTPT: EQU 0E003H +CONT0: EQU 0E004H +CONT1: EQU 0E005H +CONT2: EQU 0E006H +CONTF: EQU 0E007H +SUNDG: EQU 0E008H +TEMP: EQU 0E008H +SCRN: EQU 0D000H +KANST: EQU 0E003H ; KANA STATUS REPORT + diff --git a/asm/MZ700.LST b/asm/MZ700.LST new file mode 100644 index 0000000..20cec33 --- /dev/null +++ b/asm/MZ700.LST @@ -0,0 +1,5170 @@ + AS V1.40r8 - Quelle MZ700.ASM - Seite 1 - 9.6.1998 9:06:29 + + + 1/ 0 : ; MONITOR PROGRAM 1Z-013A + 2/ 0 : ; (MZ700) FOR PAL + 3/ 0 : ; REV. 83.4.7 + 4/ 0 : ; Tuesday, 02 of June 1998 at 10:02 PM + 5/ 0 : ; Tuesday, 09 of June 1998 at 07:17 AM + 6/ 0 : CPU Z80 + 7/ 0 : org 0000h ; 0000h Entrypoint + 8/ 0 : C3 4A 00 MONIT: JP START ; MONITOR ON + 9/ 3 : C3 E6 07 GETL: JP QGETL ; GET LINE (END "CR") + 10/ 6 : C3 0E 09 LETNL: JP QLTNL ; NEW LINE + 11/ 9 : C3 18 09 NL: JP QNL ; + 12/ C : C3 20 09 PRNTS: JP QPRTS ; PRINT SPACE + 13/ F : C3 24 09 PRNTT: JP QPRTT ; PRINT TAB + 14/ 12 : C3 35 09 PRNT: JP QPRNT ; 1 CHARACTER PRINT + 15/ 15 : C3 93 08 MSG: JP QMSG ; 1 LINE PRINT (END "0DH") + 16/ 18 : C3 A1 08 MSGX: JP QMSGX ; RST 18H + 17/ 1B : C3 BD 08 GETKY: JP QGET ; GET KEY + 18/ 1E : C3 32 0A BRKEY: JP QBRK ; GET BREAK + 19/ 21 : C3 36 04 WRINF: JP QWRI ; WRITE INFORMATION + 20/ 24 : C3 75 04 WRDAT: JP QWRD ; WRITE DATA + 21/ 27 : C3 D8 04 RDINF: JP QRDI ; READ INFORMATION + 22/ 2A : C3 F8 04 RDDAT: JP QRDD ; READ DATA + 23/ 2D : C3 88 05 VERFY: JP QVRFY ; VERIFYING CMT + 24/ 30 : C3 C7 01 MELDY: JP QMLDY ; RST 30H + 25/ 33 : C3 08 03 TIMST: JP QTMST ; TIME SET + 26/ 36 : 00 NOP + 27/ 37 : 00 NOP + 28/ 38 : C3 38 10 JP 1038H ; INTERRUPT ROUTINE (8253) + 29/ 3B : C3 58 03 TIMRD: JP QTMRD ; TIME READ + 30/ 3E : C3 77 05 BELL: JP QBEL ; BELL ON + 31/ 41 : C3 E5 02 XTEMP: JP QTEMP ; TEMPO SET (1 - 7) + 32/ 44 : C3 AB 02 MSTA: JP MLDST ; MELODY START + 33/ 47 : C3 BE 02 MSTP: JP MLDSP ; MELODY STOP + 34/ 4A : + 35/ 4A : 31 F0 10 START: LD SP,SPV ; STACK SET (10F0H) + 36/ 4D : ED 56 IM 1 ; IM 1 SET + 37/ 4F : CD 3E 07 CALL QMODE ; 8255 MODE SET + 38/ 52 : CD 32 0A CALL QBRK ; CTRL ? + 39/ 55 : 30 19 JR NC,ST0 + 40/ 57 : FE 20 CP 20H ; KEY IS CTRL KEY + 41/ 59 : 20 15 JR NZ,ST0 + 42/ 5B : D3 E1 CMY0: OUT (0E1H),A ; D000-FFFFH IS DRAM + 43/ 5D : 11 F0 FF LD DE,0FFF0H ; TRANS. ADR. + 44/ 60 : 21 6B 00 LD HL,DMCP ; MEMORY CHANG PROGRAM + 45/ 63 : 01 05 00 LD BC,05H ; BYTE SIZE + 46/ 66 : ED B0 LDIR + 47/ 68 : C3 F0 FF JP 0FFF0H ; JUMP $FFF0 + 48/ 6B : + 49/ 6B : D3 E0 DMCP: OUT (0E0H),A ; 0000H-0FFFH IS DRAM + 50/ 6D : C3 00 00 JP 0000H + 51/ 70 : + 52/ 70 : 06 FF ST0: LD B,0FFH ; BUFFER CLEAR + 53/ 72 : 21 F1 10 LD HL,NAME ; 10F1H-11F0H CLEAR + 54/ 75 : CD D8 0F CALL QCLER + 55/ 78 : 3E 16 LD A,16H ; LASTER CLR. + 56/ 7A : CD 12 00 CALL PRNT + 57/ 7D : 3E 71 LD A,71H ; BACK:BLUE CHA.:WRITE + 58/ 7F : 21 00 D8 LD HL,0D800H ; COLOR ADDRESS + 59/ 82 : CD D5 09 CALL NCLR8 + 60/ 85 : 21 8D 03 LD HL,TIMIN ; INTERRUPT JUMP ROUTINE + AS V1.40r8 - Quelle MZ700.ASM - Seite 2 - 9.6.1998 9:06:29 + + + 61/ 88 : 3E C3 LD A,0C3H + 62/ 8A : 32 38 10 LD (1038H),A + 63/ 8D : 22 39 10 LD (1039H),HL + 64/ 90 : 3E 04 LD A,04H ; NORMAL TEMPO + 65/ 92 : 32 9E 11 LD (TEMPW),A + 66/ 95 : CD BE 02 CALL MLDSP ; MELODY STOP + 67/ 98 : CD 09 00 CALL NL + 68/ 9B : 11 E7 06 LD DE,MSGQ3 ; ** MONITOR 1Z-013A ** + 69/ 9E : DF RST 18H ; CALL MGX + 70/ 9F : CD 77 05 CALL QBEL + 71/ A2 : 3E 01 SS: LD A,01H + 72/ A4 : 32 9D 11 LD (SWRK),A ; KEY IN SILENT + 73/ A7 : 21 00 E8 LD HL,0E800H ; USR ROM? + 74/ AA : 77 LD (HL),A ; ROM CHECK + 75/ AB : 18 55 JR FD2 + 76/ AD : + 77/ AD : CD 09 00 ST1: CALL NL + 78/ B0 : 3E 2A LD A,2AH ; "*" PRINT + 79/ B2 : CD 12 00 CALL PRNT + 80/ B5 : 11 A3 11 LD DE,BUFER ; GET LINE WORK (11A3H) + 81/ B8 : CD 03 00 CALL GETL + 82/ BB : 1A ST2: LD A,(DE) + 83/ BC : 13 INC DE + 84/ BD : FE 0D CP 0DH + 85/ BF : 28 EC JR Z,ST1 + 86/ C1 : FE 4A CP 'J' ; JUMP + 87/ C3 : 28 2E JR Z,GOTO + 88/ C5 : FE 4C CP 'L' ; LOAD PROGRAM + 89/ C7 : 28 48 JR Z,LOAD + 90/ C9 : FE 46 CP 'F' ; FLOPPY ACCESS + 91/ CB : 28 32 JR Z,FD + 92/ CD : FE 42 CP 'B' ; KEY IN BELL + 93/ CF : 28 26 JR Z,SG + 94/ D1 : FE 23 CP '#' ; CHANG MEMORY + 95/ D3 : 28 86 JR Z,CMY0 + 96/ D5 : FE 50 CP 'P' ; PRINTER TEST + 97/ D7 : 28 7C JR Z,PTEST + 98/ D9 : FE 4D CP 'M' ; MEMORY CORRECTION + 99/ DB : CA A8 07 JP Z,MCOR + 100/ DE : FE 53 CP 'S' ; SAVE DATA + 101/ E0 : CA 5E 0F JP Z,SAVE + 102/ E3 : FE 56 CP 'V' ; VERIFYING DATA + 103/ E5 : CA CB 0F JP Z,VRFY + 104/ E8 : FE 44 CP 'D' ; DUMP DATA + 105/ EA : CA 29 0D JP Z,DUMP + 106/ ED : 00 NOP + 107/ EE : 00 NOP + 108/ EF : 00 NOP + 109/ F0 : 00 NOP + 110/ F1 : 18 C8 JR ST2 ; NO COMMAND + 111/ F3 : + 112/ F3 : ; JUMP COMMAND + 113/ F3 : + 114/ F3 : CD 3D 01 GOTO: CALL HEXIY + 115/ F6 : E9 JP (HL) + 116/ F7 : + 117/ F7 : ; KEY SOUND ON/OFF + 118/ F7 : + 119/ F7 : 3A 9D 11 SG: LD A,(SWRK) ; D0=SOUND WORK + 120/ FA : 1F RRA + AS V1.40r8 - Quelle MZ700.ASM - Seite 3 - 9.6.1998 9:06:29 + + + 121/ FB : 3F CCF ; CHANGE MODE + 122/ FC : 17 RLA + 123/ FD : 18 A5 JR SS+2 + 124/ FF : + 125/ FF : ; FLOPPY + 126/ FF : + 127/ FF : 21 00 F0 FD: LD HL,0F000H ; FLOPPY I/O CHECK + 128/ 102 : 7E FD2: LD A,(HL) + 129/ 103 : B7 OR A + 130/ 104 : 20 A7 JR NZ,ST1 + 131/ 106 : E9 FD1: JP (HL) + 132/ 107 : + 133/ 107 : ; ERROR (LOADING) + 134/ 107 : + 135/ 107 : FE 02 QER: CP 02H ; A=02H : BREAK IN + 136/ 109 : 28 A2 JR Z,ST1 + 137/ 10B : 11 47 01 LD DE,MSGE1 ; CHECK SUM ERROR + 138/ 10E : DF RST 18H ; CALL MSGX + 139/ 10F : 18 9C L010F: JR ST1 + 140/ 111 : + 141/ 111 : ; LOAD COMMAND + 142/ 111 : + 143/ 111 : CD D8 04 LOAD: CALL QRDI + 144/ 114 : 38 F1 JR C,QER + 145/ 116 : CD 09 00 LOA0: CALL NL + 146/ 119 : 11 A0 09 LD DE,MSGQ2 ; LOADING + 147/ 11C : DF RST 18H ; CALL MSGX + 148/ 11D : 11 F1 10 LD DE,NAME ; FILE NAME + 149/ 120 : DF RST 18H ; CALL MSGX + 150/ 121 : CD F8 04 CALL QRDD + 151/ 124 : 38 E1 JR C,QER + 152/ 126 : 2A 06 11 LD HL,(EXADR) ; EXECUTE ADDRESS + 153/ 129 : 7C LD A,H + 154/ 12A : FE 12 CP 12H ; EXECUTE CHECK + 155/ 12C : 38 E1 JR C,L010F + 156/ 12E : E9 JP (HL) + 157/ 12F : + 158/ 12F : ; GETLINE AND BREAK IN CHECK + 159/ 12F : ; + 160/ 12F : ; EXIT BREAK IN THEN JUMP (ST1) + 161/ 12F : ; ACC=TOP OF LINE DATA + 162/ 12F : + 163/ 12F : E3 BGETL: EX (SP),HL + 164/ 130 : C1 POP BC ; STACK LOAD + 165/ 131 : 11 A3 11 LD DE,BUFER ; MONITOR GETLINE BUFF + 166/ 134 : CD 03 00 CALL GETL + 167/ 137 : 1A LD A,(DE) + 168/ 138 : FE 1B CP 1BH ; BREAK CODE + 169/ 13A : 28 D3 JR Z,L010F ; JP Z,ST1 + 170/ 13C : E9 JP (HL) + 171/ 13D : + 172/ 13D : ; ASCII TO HEX CONVERT + 173/ 13D : ; INPUT (DE)=ASCII + 174/ 13D : ; CY=1 THEN JUMP (ST1) + 175/ 13D : + 176/ 13D : FD E3 HEXIY: EX (SP),IY + 177/ 13F : F1 POP AF + 178/ 140 : CD 10 04 CALL HLHEX + 179/ 143 : 38 CA JR C,L010F ; JP C,ST1 + 180/ 145 : FD E9 JP (IY) + AS V1.40r8 - Quelle MZ700.ASM - Seite 4 - 9.6.1998 9:06:29 + + + 181/ 147 : + 182/ 147 : 43 48 45 43 4B 20 MSGE1: DB "CHECK SUM ER.\r" + 53 55 4D 20 45 52 + 2E 0D + 183/ 155 : + 184/ 155 : ; PLOTTER PRINTER TEST COMMAND + 185/ 155 : ; (DPG23) + 186/ 155 : ; &=CONTROL COMMANDS GROUP + 187/ 155 : ; C=PEN CHANGE + 188/ 155 : ; G=GRAPH MODE + 189/ 155 : ; S=80 CHA. IN 1 LINE + 190/ 155 : ; L=40 CHA. IN 1 LINE + 191/ 155 : ; T=PLOTTER TEST + 192/ 155 : ; IN (DE)=PRINT DATA + 193/ 155 : + 194/ 155 : 1A PTEST: LD A,(DE) + 195/ 156 : FE 26 CP '&' + 196/ 158 : 20 16 JR NZ,PTST1 + 197/ 15A : 13 PTST0: INC DE + 198/ 15B : 1A LD A,(DE) + 199/ 15C : FE 4C CP 'L' ; 40 IN 1 LINE + 200/ 15E : 28 16 JR Z,PLPT + 201/ 160 : FE 53 CP 'S' ; 80 IN 1 LINE + 202/ 162 : 28 17 JR Z,PPLPT + 203/ 164 : FE 43 CP 'C' ; PEN CHANGE + 204/ 166 : 28 23 JR Z,PEN + 205/ 168 : FE 47 CP 'G' ; GRAPH MODE + 206/ 16A : 28 18 JR Z,PLOT + 207/ 16C : FE 54 CP 'T' ; TEST + 208/ 16E : 28 10 JR Z,PTRN + 209/ 170 : CD A5 01 PTST1: CALL PMSG ; PLOT MESSAGE + 210/ 173 : C3 AD 00 JP ST1 + 211/ 176 : + 212/ 176 : 11 70 04 PLPT: LD DE,LLPT ; 01-09-09-0B-0D + 213/ 179 : 18 F5 JR PTST1 + 214/ 17B : + 215/ 17B : 11 D5 03 PPLPT: LD DE,SLPT ; 01-09-09-09-0D + 216/ 17E : 18 F0 JR PTST1 + 217/ 180 : + 218/ 180 : 3E 04 PTRN: LD A,04H ; TEST PATTERN + 219/ 182 : 18 02 JR PLOT+2 + 220/ 184 : + 221/ 184 : 3E 02 PLOT: LD A,02H ; GRAPH CODE + 222/ 186 : CD 8F 01 CALL LPRNT + 223/ 189 : 18 CF JR PTST0 + 224/ 18B : + 225/ 18B : 3E 1D PEN: LD A,1DH ; 1 CHANGE CODE (TEXT MODE) + 226/ 18D : 18 F7 JR PLOT+2 + 227/ 18F : + 228/ 18F : ; 1CHA. PRINT TO $LPT + 229/ 18F : ; IN: ACC PRINT DATA + 230/ 18F : + 231/ 18F : 0E 00 LPRNT: LD C,0 ; RDA TEST (READY? RDA=0) + 232/ 191 : 47 LD B,A ; PRINT DATA STORE + 233/ 192 : CD B6 01 CALL RDA + 234/ 195 : 78 LD A,B + 235/ 196 : D3 FF OUT (0FFH),A ; DATA OUT + 236/ 198 : 3E 80 LD A,80H ; RDP HIGH + 237/ 19A : D3 FE OUT (0FEH),A + 238/ 19C : 0E 01 LD C,01H ; RDA TEST + AS V1.40r8 - Quelle MZ700.ASM - Seite 5 - 9.6.1998 9:06:29 + + + 239/ 19E : CD B6 01 CALL RDA + 240/ 1A1 : AF XOR A ; RDP LOW + 241/ 1A2 : D3 FE OUT (0FEH),A + 242/ 1A4 : C9 RET + 243/ 1A5 : + 244/ 1A5 : ; $LPT MSG + 245/ 1A5 : ; IN: DE DATA LOW ADDRESS + 246/ 1A5 : ; 0DH MSG END + 247/ 1A5 : + 248/ 1A5 : D5 PMSG: PUSH DE + 249/ 1A6 : C5 PUSH BC + 250/ 1A7 : F5 PUSH AF + 251/ 1A8 : 1A PMSG1: LD A,(DE) ; ACC=DATA + 252/ 1A9 : CD 8F 01 CALL LPRNT + 253/ 1AC : 1A LD A,(DE) + 254/ 1AD : 13 INC DE + 255/ 1AE : FE 0D CP 0DH ; END? + 256/ 1B0 : 20 F6 JR NZ,PMSG1 + 257/ 1B2 : F1 POP AF + 258/ 1B3 : C1 POP BC + 259/ 1B4 : D1 POP DE + 260/ 1B5 : C9 RET + 261/ 1B6 : + 262/ 1B6 : ; RDA CHECK + 263/ 1B6 : ; BRKEY IN TO MONITOR RETURN + 264/ 1B6 : ; IN: C RDA CODE + 265/ 1B6 : + 266/ 1B6 : DB FE RDA: IN A,(0FEH) + 267/ 1B8 : E6 0D AND 0DH ; RDA ONLY + 268/ 1BA : B9 CP C + 269/ 1BB : C8 RET Z + 270/ 1BC : CD 1E 00 CALL BRKEY + 271/ 1BF : 20 F5 JR NZ,RDA + 272/ 1C1 : 31 F0 10 LD SP,SPV + 273/ 1C4 : C3 AD 00 JP ST1 + 274/ 1C7 : + 275/ 1C7 : ; MELODY + 276/ 1C7 : ; DE=DATA LOW ADDRESS + 277/ 1C7 : ; EXIT CF=1 BREAK + 278/ 1C7 : ; CF=0 OK + 279/ 1C7 : + 280/ 1C7 : C5 QMLDY: PUSH BC + 281/ 1C8 : D5 PUSH DE + 282/ 1C9 : E5 PUSH HL + 283/ 1CA : 3E 02 LD A,02H + 284/ 1CC : 32 A0 11 LD (OCTV),A + 285/ 1CF : 06 01 LD B,01H + 286/ 1D1 : 1A MLD1: LD A,(DE) + 287/ 1D2 : FE 0D CP 0DH ; CR + 288/ 1D4 : 28 3B JR Z,MLD4 + 289/ 1D6 : FE C8 CP 0C8H ; END MARK + 290/ 1D8 : 28 37 JR Z,MLD4 + 291/ 1DA : FE CF CP 0CFH ; UNDER OCTAVE + 292/ 1DC : 28 27 JR Z,MLD2 + 293/ 1DE : FE 2D CP 2DH ; "-" + 294/ 1E0 : 28 23 JR Z,MLD2 + 295/ 1E2 : FE 2B CP 2BH ; "+" + 296/ 1E4 : 28 27 JR Z,MLD3 + 297/ 1E6 : FE D7 CP 0D7H ; UPPER OCTAVE + 298/ 1E8 : 28 23 JR Z,MLD3 + AS V1.40r8 - Quelle MZ700.ASM - Seite 6 - 9.6.1998 9:06:29 + + + 299/ 1EA : FE 23 CP 23H ; "#" HANON + 300/ 1EC : 21 6C 02 LD HL,MTBL + 301/ 1EF : 20 04 JR NZ,L01F5 + 302/ 1F1 : 21 84 02 LD HL,MNTBL + 303/ 1F4 : 13 INC DE + 304/ 1F5 : CD 1C 02 L01F5: CALL ONPU ; ONTYO SET + 305/ 1F8 : 38 D7 JR C,MLD1 + 306/ 1FA : CD C8 02 CALL RYTHM + 307/ 1FD : 38 15 JR C,MLD5 + 308/ 1FF : CD AB 02 CALL MLDST ; MELODY START + 309/ 202 : 41 LD B,C + 310/ 203 : 18 CC JR MLD1 + 311/ 205 : + 312/ 205 : 3E 03 MLD2: LD A,3 + 313/ 207 : 32 A0 11 L0207: LD (OCTV),A + 314/ 20A : 13 INC DE + 315/ 20B : 18 C4 JR MLD1 + 316/ 20D : + 317/ 20D : 3E 01 MLD3: LD A,01H + 318/ 20F : 18 F6 JR L0207 + 319/ 211 : + 320/ 211 : CD C8 02 MLD4: CALL RYTHM + 321/ 214 : F5 MLD5: PUSH AF + 322/ 215 : CD BE 02 CALL MLDSP + 323/ 218 : F1 POP AF + 324/ 219 : C3 9B 06 JP RET3 + 325/ 21C : + 326/ 21C : ; ONPU TO RATIO CONV + 327/ 21C : ; EXIT (RATIO)=RATIO VALUE + 328/ 21C : ; C=ONTYO*TEMPO + 329/ 21C : + 330/ 21C : C5 ONPU: PUSH BC + 331/ 21D : 06 08 LD B,8 + 332/ 21F : 1A ONP1: LD A,(DE) + 333/ 220 : BE L0220: CP (HL) + 334/ 221 : 28 09 JR Z,ONP2 + 335/ 223 : 23 INC HL + 336/ 224 : 23 INC HL + 337/ 225 : 23 INC HL + 338/ 226 : 10 F8 DJNZ L0220 + 339/ 228 : 37 SCF + 340/ 229 : 13 INC DE + 341/ 22A : C1 POP BC + 342/ 22B : C9 RET + 343/ 22C : + 344/ 22C : 23 ONP2: INC HL + 345/ 22D : D5 PUSH DE + 346/ 22E : 5E LD E,(HL) + 347/ 22F : 23 INC HL + 348/ 230 : 56 LD D,(HL) + 349/ 231 : EB EX DE,HL + 350/ 232 : 7C LD A,H + 351/ 233 : B7 OR A + 352/ 234 : 28 09 JR Z,L023F + 353/ 236 : 3A A0 11 LD A,(OCTV) ; 11A0H OCTAVE WORK + 354/ 239 : 3D L0239: DEC A + 355/ 23A : 28 03 JR Z,L023F + 356/ 23C : 29 ADD HL,HL + 357/ 23D : 18 FA JR L0239 + 358/ 23F : + AS V1.40r8 - Quelle MZ700.ASM - Seite 7 - 9.6.1998 9:06:29 + + + 359/ 23F : 22 A1 11 L023F: LD (RATIO),HL ; 11A1H ONPU RATIO + 360/ 242 : 21 A0 11 LD HL,OCTV + 361/ 245 : 36 02 LD (HL),02H + 362/ 247 : 2B DEC HL + 363/ 248 : D1 POP DE + 364/ 249 : 13 INC DE + 365/ 24A : 1A LD A,(DE) + 366/ 24B : 47 LD B,A + 367/ 24C : E6 F0 AND 0F0H ; ONTYO ? + 368/ 24E : FE 30 CP 30H + 369/ 250 : 28 03 JR Z,L0255 + 370/ 252 : 7E LD A,(HL) ; HL=ONTYO + 371/ 253 : 18 05 JR L025A + 372/ 255 : + 373/ 255 : 13 L0255: INC DE + 374/ 256 : 78 LD A,B + 375/ 257 : E6 0F AND 0FH + 376/ 259 : 77 LD (HL),A ; HL=ONTYO + 377/ 25A : 21 9C 02 L025A: LD HL,OPTBL + 378/ 25D : 85 ADD A,L + 379/ 25E : 6F LD L,A + 380/ 25F : 4E LD C,(HL) + 381/ 260 : 3A 9E 11 LD A,(TEMPW) + 382/ 263 : 47 LD B,A + 383/ 264 : AF XOR A + 384/ 265 : 81 ONP3: ADD A,C + 385/ 266 : 10 FD DJNZ ONP3 + 386/ 268 : C1 POP BC + 387/ 269 : 4F LD C,A + 388/ 26A : AF XOR A + 389/ 26B : C9 RET + 390/ 26C : + 391/ 26C : 43 MTBL: DB "C" + 392/ 26D : 46 08 DW 0846H + 393/ 26F : 44 DB "D" + 394/ 270 : 5F 07 DW 075FH + 395/ 272 : 45 DB "E" + 396/ 273 : 91 06 DW 0691H + 397/ 275 : 46 DB "F" + 398/ 276 : 33 06 DW 0633H + 399/ 278 : 47 DB "G" + 400/ 279 : 86 05 DW 0586H + 401/ 27B : 41 DB "A" + 402/ 27C : EC 04 DW 04ECH + 403/ 27E : 42 DB "B" + 404/ 27F : 64 04 DW 0464H + 405/ 281 : 52 DB "R" + 406/ 282 : 00 00 DW 0000H + 407/ 284 : 43 MNTBL: DB "C" ; #C + 408/ 285 : CF 07 DW 07CFH + 409/ 287 : 44 DB "D" ; #D + 410/ 288 : F5 06 DW 06F5H + 411/ 28A : 45 DB "E" ; #E + 412/ 28B : 33 06 DW 0633H + 413/ 28D : 46 DB "F" ; #F + 414/ 28E : DA 05 DW 05DAH + 415/ 290 : 47 DB "G" ; #G + 416/ 291 : 37 05 DW 0537H + 417/ 293 : 41 DB "A" ; #A + 418/ 294 : A5 04 DW 04A5H + AS V1.40r8 - Quelle MZ700.ASM - Seite 8 - 9.6.1998 9:06:29 + + + 419/ 296 : 42 DB "B" ; #B + 420/ 297 : 23 04 DW 0423H + 421/ 299 : 52 DB "R" ; #R + 422/ 29A : 00 00 DW 0000H + 423/ 29C : 01 OPTBL: DB 01H + 424/ 29D : 02 DB 02H + 425/ 29E : 03 DB 03H + 426/ 29F : 04 DB 04H + 427/ 2A0 : 06 DB 06H + 428/ 2A1 : 08 DB 08H + 429/ 2A2 : 0C DB 0CH + 430/ 2A3 : 10 DB 10H + 431/ 2A4 : 18 DB 18H + 432/ 2A5 : 20 DB 20H + 433/ 2A6 : + 434/ 2A6 : ; INCREMENT DE REG. + 435/ 2A6 : + 436/ 2A6 : 13 P4DE: INC DE + 437/ 2A7 : 13 INC DE + 438/ 2A8 : 13 INC DE + 439/ 2A9 : 13 INC DE + 440/ 2AA : C9 RET + 441/ 2AB : + 442/ 2AB : ; MELODY START & STOP + 443/ 2AB : + 444/ 2AB : 2A A1 11 MLDST: LD HL,(RATIO) + 445/ 2AE : 7C LD A,H + 446/ 2AF : B7 OR A + 447/ 2B0 : 28 0C JR Z,MLDSP + 448/ 2B2 : D5 PUSH DE + 449/ 2B3 : EB EX DE,HL + 450/ 2B4 : 21 04 E0 LD HL,CONT0 + 451/ 2B7 : 73 LD (HL),E + 452/ 2B8 : 72 LD (HL),D + 453/ 2B9 : 3E 01 LD A,01H + 454/ 2BB : D1 POP DE + 455/ 2BC : 18 06 JR MLDS1 + 456/ 2BE : + 457/ 2BE : 3E 36 MLDSP: LD A,36H ; MODE SET (8253 C0) + 458/ 2C0 : 32 07 E0 LD (CONTF),A ; E007H + 459/ 2C3 : AF XOR A + 460/ 2C4 : 32 08 E0 MLDS1: LD (SUNDG),A ; E008H + 461/ 2C7 : C9 RET ; TEHRO SET + 462/ 2C8 : + 463/ 2C8 : ; RHYTHM + 464/ 2C8 : ; B=COUNT DATA + 465/ 2C8 : ; IN + 466/ 2C8 : ; EXIT CF=1 BREAK + 467/ 2C8 : ; CF=0 OK + 468/ 2C8 : + 469/ 2C8 : 21 00 E0 RYTHM: LD HL,KEYPA ; E000H + 470/ 2CB : 36 F8 LD (HL),0F8H + 471/ 2CD : 23 INC HL + 472/ 2CE : 7E LD A,(HL) + 473/ 2CF : E6 81 AND 81H ; BREAK IN CHECK + 474/ 2D1 : 20 02 JR NZ,L02D5 + 475/ 2D3 : 37 SCF + 476/ 2D4 : C9 RET + 477/ 2D5 : + 478/ 2D5 : 3A 08 E0 L02D5: LD A,(TEMP) ; E008H + AS V1.40r8 - Quelle MZ700.ASM - Seite 9 - 9.6.1998 9:06:29 + + + 479/ 2D8 : 0F RRCA ; TEMPO OUT + 480/ 2D9 : 38 FA JR C,L02D5 + 481/ 2DB : 3A 08 E0 L02DB: LD A,(TEMP) + 482/ 2DE : 0F RRCA + 483/ 2DF : 30 FA JR NC,L02DB + 484/ 2E1 : 10 F2 DJNZ L02D5 + 485/ 2E3 : AF XOR A + 486/ 2E4 : C9 RET + 487/ 2E5 : + 488/ 2E5 : ; TEMPO SET + 489/ 2E5 : ; ACC=VALUE (1-7) + 490/ 2E5 : + 491/ 2E5 : F5 QTEMP: PUSH AF + 492/ 2E6 : C5 PUSH BC + 493/ 2E7 : E6 0F AND 0FH + 494/ 2E9 : 47 LD B,A + 495/ 2EA : 3E 08 LD A,8 + 496/ 2EC : 90 SUB B + 497/ 2ED : 32 9E 11 LD (TEMPW),A + 498/ 2F0 : C1 POP BC + 499/ 2F1 : F1 POP AF + 500/ 2F2 : C9 RET + 501/ 2F3 : + 502/ 2F3 : ; CRT MANAGEMENT + 503/ 2F3 : ; EXIT HL:DSPXY H=Y,L=X + 504/ 2F3 : ; DE:MANG ADR. (ON DSPXY) + 505/ 2F3 : ; A :MANG DATA + 506/ 2F3 : ; CY:MANG=1 + 507/ 2F3 : + 508/ 2F3 : 21 73 11 PMANG: LD HL,MANG ; CRT MANG POINTER + 509/ 2F6 : 3A 72 11 LD A,(1172H) ; DSPXY+1 + 510/ 2F9 : 85 ADD A,L + 511/ 2FA : 6F LD L,A + 512/ 2FB : 7E LD A,(HL) + 513/ 2FC : 23 INC HL + 514/ 2FD : CB 16 RL (HL) + 515/ 2FF : B6 OR (HL) + 516/ 300 : CB 1E RR (HL) + 517/ 302 : 0F RRCA + 518/ 303 : EB EX DE,HL + 519/ 304 : 2A 71 11 LD HL,(DSPXY) + 520/ 307 : C9 RET + 521/ 308 : + 522/ 308 : ; TIME SET + 523/ 308 : ; ACC=0 : AM + 524/ 308 : ; =1 : PM + 525/ 308 : ; DE=SEC: BINARY + 526/ 308 : + 527/ 308 : F3 QTMST: DI + 528/ 309 : C5 PUSH BC + 529/ 30A : D5 PUSH DE + 530/ 30B : E5 PUSH HL + 531/ 30C : 32 9B 11 LD (AMPM),A ; AMPM DATA + 532/ 30F : 3E F0 LD A,0F0H + 533/ 311 : 32 9C 11 LD (TIMFG),A ; TIME FLAG + 534/ 314 : 21 C0 A8 LD HL,0A8C0H ; 12 HOURS (43200 SECONDS) + 535/ 317 : AF XOR A + 536/ 318 : ED 52 SBC HL,DE ; COUNT DATA = 12H-IN DATA + 537/ 31A : E5 PUSH HL + 538/ 31B : 00 NOP + AS V1.40r8 - Quelle MZ700.ASM - Seite 10 - 9.6.1998 9:06:29 + + + 539/ 31C : EB EX DE,HL + 540/ 31D : 21 07 E0 LD HL,CONTF ; E007H + 541/ 320 : 36 74 LD (HL),74H ; C1 + 542/ 322 : 36 B0 LD (HL),0B0H ; C2 + 543/ 324 : 2B DEC HL ; CONT2 + 544/ 325 : 73 LD (HL),E ; E006H + 545/ 326 : 72 LD (HL),D + 546/ 327 : 2B DEC HL ; CONT1 + 547/ 328 : 36 0A LD (HL),0AH ; E005H STROBE 640,6µSECONDS COUNT2 + 548/ 32A : 36 00 LD (HL),0 + 549/ 32C : 23 INC HL + 550/ 32D : 23 INC HL ; CONTF + 551/ 32E : 36 80 LD (HL),80H ; E007H + 552/ 330 : 2B DEC HL ; CONT2 + 553/ 331 : 4E QTMS1: LD C,(HL) ; E006H + 554/ 332 : 7E LD A,(HL) + 555/ 333 : BA CP D + 556/ 334 : 20 FB JR NZ,QTMS1 + 557/ 336 : 79 LD A,C + 558/ 337 : BB CP E + 559/ 338 : 20 F7 JR NZ,QTMS1 + 560/ 33A : 2B DEC HL ; E005H + 561/ 33B : 00 NOP + 562/ 33C : 00 NOP + 563/ 33D : 00 NOP + 564/ 33E : 36 FB LD (HL),0FBH ; 1 SECOND (15611HZ) E005H + 565/ 340 : 36 3C LD (HL),3CH + 566/ 342 : 23 INC HL + 567/ 343 : D1 POP DE + 568/ 344 : 4E QTMS2: LD C,(HL) ; E006H + 569/ 345 : 7E LD A,(HL) + 570/ 346 : BA CP D + 571/ 347 : 20 FB JR NZ,QTMS2 + 572/ 349 : 79 LD A,C + 573/ 34A : BB CP E + 574/ 34B : 20 F7 JR NZ,QTMS2 + 575/ 34D : E1 POP HL + 576/ 34E : D1 POP DE + 577/ 34F : C1 POP BC + 578/ 350 : FB EI + 579/ 351 : C9 RET + 580/ 352 : + 581/ 352 : ; BELL DATA + 582/ 352 : ; + 583/ 352 : D7 QBELD: DB 0D7H + 584/ 353 : 41 30 DB "A0" + 585/ 355 : 0D DB 0DH + 586/ 356 : 00 NOP + 587/ 357 : 00 NOP + 588/ 358 : + 589/ 358 : ; TIME READ + 590/ 358 : ; EXIT ACC=0 :AM + 591/ 358 : ; =1 :PM + 592/ 358 : ; DE=SEC. BINARY + 593/ 358 : + 594/ 358 : E5 QTMRD: PUSH HL + 595/ 359 : 21 07 E0 LD HL,CONTF + 596/ 35C : 36 80 LD (HL),80H ; E007H C2 + 597/ 35E : 2B DEC HL ; CONT2 + 598/ 35F : F3 DI + AS V1.40r8 - Quelle MZ700.ASM - Seite 11 - 9.6.1998 9:06:29 + + + 599/ 360 : 5E LD E,(HL) + 600/ 361 : 56 LD D,(HL) ; e006H C2 MODE0 + 601/ 362 : FB EI + 602/ 363 : 7B L0363: LD A,E + 603/ 364 : B2 OR D + 604/ 365 : 28 0E JR Z,QTMR1 + 605/ 367 : AF XOR A + 606/ 368 : 21 C0 A8 LD HL,0A8C0H ; 12 HOURS + 607/ 36B : ED 52 SBC HL,DE + 608/ 36D : 38 10 JR C,QTMR2 + 609/ 36F : EB EX DE,HL + 610/ 370 : 3A 9B 11 LD A,(AMPM) + 611/ 373 : E1 POP HL + 612/ 374 : C9 RET + 613/ 375 : + 614/ 375 : 11 C0 A8 QTMR1: LD DE,0A8C0H + 615/ 378 : 3A 9B 11 L0378: LD A,(AMPM) + 616/ 37B : EE 01 XOR 01H + 617/ 37D : E1 POP HL + 618/ 37E : C9 RET + 619/ 37F : + 620/ 37F : F3 QTMR2: DI + 621/ 380 : 21 06 E0 LD HL,CONT2 + 622/ 383 : 7E LD A,(HL) + 623/ 384 : 2F CPL + 624/ 385 : 5F LD E,A + 625/ 386 : 7E LD A,(HL) + 626/ 387 : 2F CPL + 627/ 388 : 57 LD D,A + 628/ 389 : FB EI + 629/ 38A : 13 INC DE + 630/ 38B : 18 EB JR L0378 + 631/ 38D : + 632/ 38D : ; TIME INTERRUPT + 633/ 38D : + 634/ 38D : F5 TIMIN: PUSH AF + 635/ 38E : C5 PUSH BC + 636/ 38F : D5 PUSH DE + 637/ 390 : E5 PUSH HL + 638/ 391 : 21 9B 11 LD HL,AMPM + 639/ 394 : 7E LD A,(HL) + 640/ 395 : EE 01 XOR 01H + 641/ 397 : 77 LD (HL),A + 642/ 398 : 21 07 E0 LD HL,CONTF + 643/ 39B : 36 80 LD (HL),80H ; CONT2 + 644/ 39D : 2B DEC HL + 645/ 39E : E5 PUSH HL + 646/ 39F : 5E LD E,(HL) + 647/ 3A0 : 56 LD D,(HL) + 648/ 3A1 : 21 C0 A8 LD HL,0A8C0H + 649/ 3A4 : 19 ADD HL,DE + 650/ 3A5 : 2B DEC HL + 651/ 3A6 : 2B DEC HL + 652/ 3A7 : EB EX DE,HL + 653/ 3A8 : E1 POP HL + 654/ 3A9 : 73 LD (HL),E + 655/ 3AA : 72 LD (HL),D + 656/ 3AB : E1 POP HL + 657/ 3AC : D1 POP DE + 658/ 3AD : C1 POP BC + AS V1.40r8 - Quelle MZ700.ASM - Seite 12 - 9.6.1998 9:06:29 + + + 659/ 3AE : F1 POP AF + 660/ 3AF : FB EI + 661/ 3B0 : C9 RET + 662/ 3B1 : + 663/ 3B1 : ; SPACE PRINT AND DISP ACC + 664/ 3B1 : ; INPUT:HL=DISP. ADR. + 665/ 3B1 : + 666/ 3B1 : CD 20 09 SPHEX: CALL QPRTS ; SPACE PRINT + 667/ 3B4 : 7E LD A,(HL) + 668/ 3B5 : CD C3 03 CALL PRTHX ; DSP OF ACC (ASCII) + 669/ 3B8 : 7E LD A,(HL) + 670/ 3B9 : C9 RET + 671/ 3BA : + 672/ 3BA : ; (ASCII PRINT) FOR HL + 673/ 3BA : + 674/ 3BA : 7C PRTHL: LD A,H + 675/ 3BB : CD C3 03 CALL PRTHX + 676/ 3BE : 7D LD A,L + 677/ 3BF : 18 02 JR PRTHX + 678/ 3C1 : + 679/ 3C1 : 00 NOP + 680/ 3C2 : 00 NOP + 681/ 3C3 : + 682/ 3C3 : ; (ASCII PRINT) FOR ACC + 683/ 3C3 : + 684/ 3C3 : F5 PRTHX: PUSH AF + 685/ 3C4 : 0F RRCA + 686/ 3C5 : 0F RRCA + 687/ 3C6 : 0F RRCA + 688/ 3C7 : 0F RRCA + 689/ 3C8 : CD DA 03 CALL ASC + 690/ 3CB : CD 12 00 CALL PRNT + 691/ 3CE : F1 POP AF + 692/ 3CF : CD DA 03 CALL ASC + 693/ 3D2 : C3 12 00 JP PRNT + 694/ 3D5 : + 695/ 3D5 : ; 80 CHA. 1 LINE CODE (DATA) + 696/ 3D5 : + 697/ 3D5 : 01 SLPT: DB 01H ; TEXT MODE + 698/ 3D6 : 09 DB 09H + 699/ 3D7 : 09 DB 09H + 700/ 3D8 : 09 DB 09H + 701/ 3D9 : 0D DB 0DH + 702/ 3DA : + 703/ 3DA : ; HEXADECIMAL TO ASCII + 704/ 3DA : ; IN : ACC (D3-D0)=HEXADECIMAL + 705/ 3DA : ; EXIT: ACC = ASCII + 706/ 3DA : E6 0F ASC: AND 0FH + 707/ 3DC : FE 0A CP 0AH + 708/ 3DE : 38 02 JR C,NOADD + 709/ 3E0 : C6 07 ADD A,07H + 710/ 3E2 : C6 30 NOADD: ADD A,30H + 711/ 3E4 : C9 RET + 712/ 3E5 : + 713/ 3E5 : ; ASCII TO HEXADECIMAL + 714/ 3E5 : ; IN : ACC = ASCII + 715/ 3E5 : ; EXIT: ACC = HEXADECIMAL + 716/ 3E5 : ; CY = 1 ERROR + 717/ 3E5 : + 718/ 3E5 : D6 30 HEXJ: SUB 30H + AS V1.40r8 - Quelle MZ700.ASM - Seite 13 - 9.6.1998 9:06:29 + + + 719/ 3E7 : D8 RET C ; <0 + 720/ 3E8 : FE 0A CP 0AH + 721/ 3EA : 3F CCF + 722/ 3EB : D0 RET NC ; 0-9 + 723/ 3EC : D6 07 SUB 07H + 724/ 3EE : FE 10 CP 10H + 725/ 3F0 : 3F CCF + 726/ 3F1 : D8 RET C + 727/ 3F2 : FE 0A CP 0AH + 728/ 3F4 : C9 RET + 729/ 3F5 : + 730/ 3F5 : 00 NOP + 731/ 3F6 : 00 NOP + 732/ 3F7 : 00 NOP + 733/ 3F8 : 00 NOP + 734/ 3F9 : + 735/ 3F9 : 18 EA HEX: JR HEXJ + 736/ 3FB : + 737/ 3FB : ; PRESS PLAY MESSAGE + 738/ 3FB : + 739/ 3FB : 7F 20 MSGN1: DW 207FH + 740/ 3FD : 50 4C 41 59 0D MSGN2: DB "PLAY\r" + 741/ 402 : 7F 20 MSGN3: DW 207FH + 742/ 404 : 52 45 43 4F 52 44 DB "RECORD.\r" ; PRESS RECORD + 2E 0D + 743/ 40C : + 744/ 40C : 00 NOP + 745/ 40D : 00 NOP + 746/ 40E : 00 NOP + 747/ 40F : 00 NOP + 748/ 410 : + 749/ 410 : ; 4 ASCII TO (HL) + 750/ 410 : ; IN DE=DATA LOW ADDRESS + 751/ 410 : ; EXIT CF=0 : OK + 752/ 410 : ; =1 : OUT + 753/ 410 : + 754/ 410 : D5 HLHEX: PUSH DE + 755/ 411 : CD 1F 04 CALL L2HEX + 756/ 414 : 38 07 JR C,L041D + 757/ 416 : 67 LD H,A + 758/ 417 : CD 1F 04 CALL L2HEX + 759/ 41A : 38 01 JR C,L041D + 760/ 41C : 6F LD L,A + 761/ 41D : D1 L041D: POP DE + 762/ 41E : C9 RET + 763/ 41F : + 764/ 41F : ; 2 ASCII TO (ACC) + 765/ 41F : ; IN DE=DATA LOW ADRRESS + 766/ 41F : ; EXIT CF=0 : OK + 767/ 41F : ; =1 : OUT + 768/ 41F : + 769/ 41F : C5 L2HEX: PUSH BC + 770/ 420 : 1A LD A,(DE) + 771/ 421 : 13 INC DE + 772/ 422 : CD F9 03 CALL HEX + 773/ 425 : 38 0D JR C,L0434 + 774/ 427 : 0F RRCA + 775/ 428 : 0F RRCA + 776/ 429 : 0F RRCA + 777/ 42A : 0F RRCA + AS V1.40r8 - Quelle MZ700.ASM - Seite 14 - 9.6.1998 9:06:29 + + + 778/ 42B : 4F LD C,A + 779/ 42C : 1A LD A,(DE) + 780/ 42D : 13 INC DE + 781/ 42E : CD F9 03 CALL HEX + 782/ 431 : 38 01 JR C,L0434 + 783/ 433 : B1 OR C + 784/ 434 : C1 L0434: POP BC + 785/ 435 : C9 RET + 786/ 436 : + 787/ 436 : ; WRITE INFORMATION + 788/ 436 : + 789/ 436 : F3 QWRI: DI + 790/ 437 : D5 PUSH DE + 791/ 438 : C5 PUSH BC + 792/ 439 : E5 PUSH HL + 793/ 43A : 16 D7 LD D,0D7H ; "W" + 794/ 43C : 1E CC LD E,0CCH ; "L" + 795/ 43E : 21 F0 10 LD HL,IBUFE ; 10F0H + 796/ 441 : 01 80 00 LD BC,80H ; WRITE BYTE SIZE + 797/ 444 : CD 1A 07 WRI1: CALL CKSUM ; CHECK SUM + 798/ 447 : CD 9F 06 CALL MOTOR ; MOTOR ON + 799/ 44A : 38 18 JR C,WRI3 + 800/ 44C : 7B LD A,E + 801/ 44D : FE CC CP 0CCH ; "L" + 802/ 44F : 20 0D JR NZ,WRI2 + 803/ 451 : CD 09 00 CALL NL + 804/ 454 : D5 PUSH DE + 805/ 455 : 11 67 04 LD DE,MSGN7 ; WRITING + 806/ 458 : DF RST 18H ; CALL MSGX + 807/ 459 : 11 F1 10 LD DE,NAME ; FILE NAME + 808/ 45C : DF RST 18H ; CALL MSGX + 809/ 45D : D1 POP DE + 810/ 45E : CD 7A 07 WRI2: CALL GAP + 811/ 461 : CD 8A 04 CALL WTAPE + 812/ 464 : C3 54 05 WRI3: JP RET2 + 813/ 467 : + 814/ 467 : 57 52 49 54 49 4E MSGN7: DB "WRITING \r" + 47 20 0D + 815/ 470 : + 816/ 470 : ; 40 CHA. IN 1 LINE CODE (DATA) + 817/ 470 : + 818/ 470 : 01 LLPT: DB 01H ; TEXT MODE + 819/ 471 : 09 DB 09H + 820/ 472 : 09 DB 09H + 821/ 473 : 0B DB 0BH + 822/ 474 : 0D DB 0DH + 823/ 475 : + 824/ 475 : ; WRITE DATA + 825/ 475 : ; EXIT CF=0 : OK + 826/ 475 : ; =1 : BREAK + 827/ 475 : + 828/ 475 : F3 QWRD: DI + 829/ 476 : D5 PUSH DE + 830/ 477 : C5 PUSH BC + 831/ 478 : E5 PUSH HL + 832/ 479 : 16 D7 LD D,0D7H ; "W" + 833/ 47B : 1E 53 LD E,53H ; "S" + 834/ 47D : ED 4B 02 11 L047D: LD BC,(SIZE) ; WRITE DATA BYTE SIZE + 835/ 481 : 2A 04 11 LD HL,(DTADR) ; WRITE DATA ADDRESS + 836/ 484 : 78 LD A,B + AS V1.40r8 - Quelle MZ700.ASM - Seite 15 - 9.6.1998 9:06:29 + + + 837/ 485 : B1 OR C + 838/ 486 : 28 4A JR Z,RET1 + 839/ 488 : 18 BA JR WRI1 + 840/ 48A : + 841/ 48A : ; TAPE WRITE + 842/ 48A : ; BC=BYTE SIZE + 843/ 48A : ; HL=DATA LOW ADDRESS + 844/ 48A : ; EXIT CF=0 : OK + 845/ 48A : ; =1 : BREAK + 846/ 48A : + 847/ 48A : D5 WTAPE: PUSH DE + 848/ 48B : C5 PUSH BC + 849/ 48C : E5 PUSH HL + 850/ 48D : 16 02 LD D,02H + 851/ 48F : 3E F8 LD A,0F8H ; 88H WOULD BE BETTER!! + 852/ 491 : 32 00 E0 LD (KEYPA),A ; E000H + 853/ 494 : 7E WTAP1: LD A,(HL) + 854/ 495 : CD 67 07 CALL WBYTE ; 1 BYTE WRITE + 855/ 498 : 3A 01 E0 LD A,(KEYPB) ; E001H + 856/ 49B : E6 81 AND 81H ; SHIFT & BREAK + 857/ 49D : C2 A5 04 JP NZ,WTAP2 + 858/ 4A0 : 3E 02 LD A,02H ; BREAK IN CODE + 859/ 4A2 : 37 SCF + 860/ 4A3 : 18 2D JR WTAP3 + 861/ 4A5 : + 862/ 4A5 : 23 WTAP2: INC HL + 863/ 4A6 : 0B DEC BC + 864/ 4A7 : 78 LD A,B + 865/ 4A8 : B1 OR C + 866/ 4A9 : C2 94 04 JP NZ,WTAP1 + 867/ 4AC : 2A 97 11 LD HL,(SUMDT) ; SUM DATA SET + 868/ 4AF : 7C LD A,H + 869/ 4B0 : CD 67 07 CALL WBYTE + 870/ 4B3 : 7D LD A,L + 871/ 4B4 : CD 67 07 CALL WBYTE + 872/ 4B7 : CD 1A 0A CALL LONG + 873/ 4BA : 15 DEC D + 874/ 4BB : C2 C2 04 JP NZ,L04C2 + 875/ 4BE : B7 OR A + 876/ 4BF : C3 D2 04 JP WTAP3 + 877/ 4C2 : + 878/ 4C2 : 06 00 L04C2: LD B,0 + 879/ 4C4 : CD 01 0A L04C4: CALL SHORT + 880/ 4C7 : 05 DEC B + 881/ 4C8 : C2 C4 04 JP NZ,L04C4 + 882/ 4CB : E1 POP HL + 883/ 4CC : C1 POP BC + 884/ 4CD : C5 PUSH BC + 885/ 4CE : E5 PUSH HL + 886/ 4CF : C3 94 04 JP WTAP1 + 887/ 4D2 : + 888/ 4D2 : WTAP3: + 889/ 4D2 : E1 RET1: POP HL + 890/ 4D3 : C1 POP BC + 891/ 4D4 : D1 POP DE + 892/ 4D5 : C9 RET + 893/ 4D6 : + 894/ 4D6 : 2F DB 2FH + 895/ 4D7 : 4E DB 4EH + 896/ 4D8 : + AS V1.40r8 - Quelle MZ700.ASM - Seite 16 - 9.6.1998 9:06:29 + + + 897/ 4D8 : ; READ INFORMATION (FROM $CMT) + 898/ 4D8 : ; EXIT ACC=0: OK CF=0 + 899/ 4D8 : ; =1: ER CF=1 + 900/ 4D8 : ; =2: BREAK CF=1 + 901/ 4D8 : + 902/ 4D8 : F3 QRDI: DI + 903/ 4D9 : D5 PUSH DE + 904/ 4DA : C5 PUSH BC + 905/ 4DB : E5 PUSH HL + 906/ 4DC : 16 D2 LD D,0D2H ; "R" + 907/ 4DE : 1E CC LD E,0CCH ; "L" + 908/ 4E0 : 01 80 00 LD BC,80H + 909/ 4E3 : 21 F0 10 LD HL,IBUFE + 910/ 4E6 : CD 9F 06 RD1: CALL MOTOR + 911/ 4E9 : DA 72 05 JP C,RTP6 + 912/ 4EC : CD 5B 06 CALL TMARK + 913/ 4EF : DA 72 05 JP C,RTP6 + 914/ 4F2 : CD 0E 05 CALL RTAPE + 915/ 4F5 : C3 54 05 JP RTP4 + 916/ 4F8 : + 917/ 4F8 : ; READ DATA (FROM $CMT) + 918/ 4F8 : ; EXIT SAME UP + 919/ 4F8 : + 920/ 4F8 : F3 QRDD: DI + 921/ 4F9 : D5 PUSH DE + 922/ 4FA : C5 PUSH BC + 923/ 4FB : E5 PUSH HL + 924/ 4FC : 16 D2 LD D,0D2H ; "R" + 925/ 4FE : 1E 53 LD E,53H ; "S" + 926/ 500 : ED 4B 02 11 LD BC,(SIZE) + 927/ 504 : 2A 04 11 LD HL,(DTADR) + 928/ 507 : 78 LD A,B + 929/ 508 : B1 OR C + 930/ 509 : CA 54 05 JP Z,RTP4 + 931/ 50C : 18 D8 JR RD1 + 932/ 50E : + 933/ 50E : ; READ TAPE + 934/ 50E : ; IN BC=SIZE + 935/ 50E : ; DE=LOAD ADDRESS + 936/ 50E : ; EXIT ACC=0 : OK CF=0 + 937/ 50E : ; =1 : ER =1 + 938/ 50E : ; =2 : BREAK=1 + 939/ 50E : + 940/ 50E : D5 RTAPE: PUSH DE + 941/ 50F : C5 PUSH BC + 942/ 510 : E5 PUSH HL + 943/ 511 : 26 02 LD H,02H ; TWICE WRITE + 944/ 513 : 01 01 E0 RTP1: LD BC,KEYPB + 945/ 516 : 11 02 E0 LD DE,CSTR + 946/ 519 : CD 01 06 RTP2: CALL EDGE ; 1-->0 EDGE DETECT + 947/ 51C : 38 54 JR C,RTP6 + 948/ 51E : CD 4A 0A CALL DLY3 ; CALL DLY2*3 + 949/ 521 : 1A LD A,(DE) ; DATA (1 BIT) READ + 950/ 522 : E6 20 AND 20H + 951/ 524 : CA 19 05 JP Z,RTP2 + 952/ 527 : 54 LD D,H + 953/ 528 : 21 00 00 LD HL,0 + 954/ 52B : 22 97 11 LD (SUMDT),HL + 955/ 52E : E1 POP HL + 956/ 52F : C1 POP BC + AS V1.40r8 - Quelle MZ700.ASM - Seite 17 - 9.6.1998 9:06:29 + + + 957/ 530 : C5 PUSH BC + 958/ 531 : E5 PUSH HL + 959/ 532 : CD 24 06 RTP3: CALL RBYTE ; 1 BYTE READ + 960/ 535 : 38 3B JR C,RTP6 + 961/ 537 : 77 LD (HL),A + 962/ 538 : 23 INC HL + 963/ 539 : 0B DEC BC + 964/ 53A : 78 LD A,B + 965/ 53B : B1 OR C + 966/ 53C : 20 F4 JR NZ,RTP3 + 967/ 53E : 2A 97 11 LD HL,(SUMDT) ; CHECK SUM + 968/ 541 : CD 24 06 CALL RBYTE ; CHECK SUM DATA + 969/ 544 : 38 2C JR C,RTP6 + 970/ 546 : 5F LD E,A + 971/ 547 : CD 24 06 CALL RBYTE ; CHECK SUM DATA + 972/ 54A : 38 26 JR C,RTP6 + 973/ 54C : BD CP L + 974/ 54D : 20 16 JR NZ,RTP5 + 975/ 54F : 7B LD A,E + 976/ 550 : BC CP H + 977/ 551 : 20 12 JR NZ,RTP5 + 978/ 553 : AF RTP8: XOR A + 979/ 554 : RTP4: + 980/ 554 : E1 RET2: POP HL + 981/ 555 : C1 POP BC + 982/ 556 : D1 POP DE + 983/ 557 : CD 00 07 CALL MSTOP + 984/ 55A : F5 PUSH AF + 985/ 55B : 3A 9C 11 LD A,(TIMFG) ; INT. CHECK + 986/ 55E : FE F0 CP 0F0H + 987/ 560 : 20 01 JR NZ,L0563 + 988/ 562 : FB EI + 989/ 563 : F1 L0563: POP AF + 990/ 564 : C9 RET + 991/ 565 : + 992/ 565 : 15 RTP5: DEC D + 993/ 566 : 28 06 JR Z,RTP7 + 994/ 568 : 62 LD H,D + 995/ 569 : CD E2 0F CALL GAPCK + 996/ 56C : 18 A5 JR RTP1 + 997/ 56E : + 998/ 56E : 3E 01 RTP7: LD A,01H + 999/ 570 : 18 02 JR RTP9 + 1000/ 572 : + 1001/ 572 : 3E 02 RTP6: LD A,02H + 1002/ 574 : 37 RTP9: SCF + 1003/ 575 : 18 DD JR RTP4 + 1004/ 577 : + 1005/ 577 : ; BELL + 1006/ 577 : + 1007/ 577 : D5 QBEL: PUSH DE + 1008/ 578 : 11 52 03 LD DE,QBELD + 1009/ 57B : F7 RST 30H ; CALL MELODY + 1010/ 57C : D1 POP DE + 1011/ 57D : C9 RET + 1012/ 57E : + 1013/ 57E : ; FLASHING AND KEYIN + 1014/ 57E : ; EXIT: ACC INPUT KEY DATA (DSP.CODE) + 1015/ 57E : ; H=F0H THEN NO KEYIN (Z FLAG) + 1016/ 57E : + AS V1.40r8 - Quelle MZ700.ASM - Seite 18 - 9.6.1998 9:06:29 + + + 1017/ 57E : CD FF 09 FLKEY: CALL QFLAS + 1018/ 581 : CD CA 08 CALL QKEY + 1019/ 584 : FE F0 CP 0F0H + 1020/ 586 : C9 RET + 1021/ 587 : + 1022/ 587 : 00 NOP + 1023/ 588 : + 1024/ 588 : ; VERIFY (FROM $CMT) + 1025/ 588 : ; EXIT ACC=0 : OK CF=0 + 1026/ 588 : ; =1 : ER CF=1 + 1027/ 588 : ; =2 : BREAK CF=1 + 1028/ 588 : + 1029/ 588 : F3 QVRFY: DI + 1030/ 589 : D5 PUSH DE + 1031/ 58A : C5 PUSH BC + 1032/ 58B : E5 PUSH HL + 1033/ 58C : ED 4B 02 11 LD BC,(SIZE) + 1034/ 590 : 2A 04 11 LD HL,(DTADR) + 1035/ 593 : 16 D2 LD D,0D2H ; "R" + 1036/ 595 : 1E 53 LD E,53H ; "S" + 1037/ 597 : 78 LD A,B + 1038/ 598 : B1 OR C + 1039/ 599 : 28 B9 JR Z,RTP4 ; END + 1040/ 59B : CD 1A 07 CALL CKSUM + 1041/ 59E : CD 9F 06 CALL MOTOR + 1042/ 5A1 : 38 CF JR C,RTP6 ; BRK + 1043/ 5A3 : CD 5B 06 CALL TMARK ; TAPE MARK DETECT + 1044/ 5A6 : 38 CA JR C,RTP6 ; BRK + 1045/ 5A8 : CD AD 05 CALL TVRFY + 1046/ 5AB : 18 A7 JR RTP4 + 1047/ 5AD : + 1048/ 5AD : ; DATA VERIFY + 1049/ 5AD : ; BC=SIZE + 1050/ 5AD : ; HL=DATA LOW ADDRESS + 1051/ 5AD : ; CSMDT=CHECK SUM + 1052/ 5AD : ; EXIT ACC=0 : OK CF=0 + 1053/ 5AD : ; =1 : ER =1 + 1054/ 5AD : ; =2 : BREAK =1 + 1055/ 5AD : + 1056/ 5AD : D5 TVRFY: PUSH DE + 1057/ 5AE : C5 PUSH BC + 1058/ 5AF : E5 PUSH HL + 1059/ 5B0 : 26 02 LD H,02H ; COMPARE TWICE + 1060/ 5B2 : 01 01 E0 TVF1: LD BC,KEYPB + 1061/ 5B5 : 11 02 E0 LD DE,CSTR + 1062/ 5B8 : CD 01 06 TVF2: CALL EDGE + 1063/ 5BB : DA 72 05 JP C,RTP6 ; BRK + 1064/ 5BE : CD 4A 0A CALL DLY3 ; CALL DLY2*3 + 1065/ 5C1 : 1A LD A,(DE) + 1066/ 5C2 : E6 20 AND 20H + 1067/ 5C4 : CA B8 05 JP Z,TVF2 + 1068/ 5C7 : 54 LD D,H + 1069/ 5C8 : E1 POP HL + 1070/ 5C9 : C1 POP BC + 1071/ 5CA : C5 PUSH BC + 1072/ 5CB : E5 PUSH HL + 1073/ 5CC : ; COMPARE TAPE DATA AND STORAGE + 1074/ 5CC : CD 24 06 TVF3: CALL RBYTE + 1075/ 5CF : 38 A1 JR C,RTP6 ; BRK + 1076/ 5D1 : BE CP (HL) + AS V1.40r8 - Quelle MZ700.ASM - Seite 19 - 9.6.1998 9:06:29 + + + 1077/ 5D2 : 20 9A JR NZ,RTP7 ; ERROR, NOT EQUAL + 1078/ 5D4 : 23 INC HL ; STORAGE ADDRESS + 1 + 1079/ 5D5 : 0B DEC BC ; SIZE - 1 + 1080/ 5D6 : 78 LD A,B + 1081/ 5D7 : B1 OR C + 1082/ 5D8 : 20 F2 JR NZ,TVF3 + 1083/ 5DA : ; COMPARE CHECK SUM (1199H/CSMDT) AND TAPE + 1084/ 5DA : 2A 99 11 LD HL,(CSMDT) + 1085/ 5DD : CD 24 06 CALL RBYTE + 1086/ 5E0 : BC CP H + 1087/ 5E1 : 20 8B JR NZ,RTP7 ; ERROR, NOT EQUAL + 1088/ 5E3 : CD 24 06 CALL RBYTE + 1089/ 5E6 : BD CP L + 1090/ 5E7 : 20 85 JR NZ,RTP7 ; ERROR, NOT EQUAL + 1091/ 5E9 : 15 DEC D ; NUMBER OF COMPARES (2) - 1 + 1092/ 5EA : CA 53 05 JP Z,RTP8 ; OK, 2 COMPARES + 1093/ 5ED : 62 LD H,D ; (-->05C7H), SAVE NUMBER OF COMPARES + 1094/ 5EE : 18 C2 JR TVF1 ; NEXT COMPARE + 1095/ 5F0 : + 1096/ 5F0 : ; FLASHING DATA LOAD + 1097/ 5F0 : + 1098/ 5F0 : F5 QLOAD: PUSH AF + 1099/ 5F1 : 3A 8E 11 LD A,(FLASH) + 1100/ 5F4 : CD B1 0F CALL QPONT + 1101/ 5F7 : 77 LD (HL),A + 1102/ 5F8 : F1 POP AF + 1103/ 5F9 : C9 RET + 1104/ 5FA : + 1105/ 5FA : ; NEW LINE AND PRINT HL REG (ASCII) + 1106/ 5FA : + 1107/ 5FA : CD 09 00 NLPHL: CALL NL + 1108/ 5FD : CD BA 03 CALL PRTHL + 1109/ 600 : C9 RET + 1110/ 601 : + 1111/ 601 : ; EDGE (TAPE DATA EDGE DETECT) + 1112/ 601 : ; BC=KEYPB (E001H) + 1113/ 601 : ; DE=CSTR (E002H) + 1114/ 601 : ; EXIT CF=0 OK CF=1 BREAK + 1115/ 601 : + 1116/ 601 : 3E F8 EDGE: LD A,0F8H ; BREAK KEY IN (88H WOULD BE BETTER!!) + 1117/ 603 : 32 00 E0 LD (KEYPA),A + 1118/ 606 : 00 NOP + 1119/ 607 : 0A EDG1: LD A,(BC) + 1120/ 608 : E6 81 AND 81H ; SHIFT & BREAK + 1121/ 60A : 20 02 JR NZ,L060E + 1122/ 60C : 37 SCF + 1123/ 60D : C9 RET + 1124/ 60E : + 1125/ 60E : 1A L060E: LD A,(DE) + 1126/ 60F : E6 20 AND 20H + 1127/ 611 : 20 F4 JR NZ,EDG1 ; CSTR D5 = 0 + 1128/ 613 : 0A EDG2: LD A,(BC) ; 8 + 1129/ 614 : E6 81 AND 81H ; 9 + 1130/ 616 : 20 02 JR NZ,L061A ; 10/14 + 1131/ 618 : 37 SCF + 1132/ 619 : C9 RET + 1133/ 61A : + 1134/ 61A : 1A L061A: LD A,(DE) ; 8 + 1135/ 61B : E6 20 AND 20H ; 9 + 1136/ 61D : 28 F4 JR Z,EDG2 ; CSTR D5 = 1 10/14 + AS V1.40r8 - Quelle MZ700.ASM - Seite 20 - 9.6.1998 9:06:29 + + + 1137/ 61F : C9 RET ; 11 + 1138/ 620 : + 1139/ 620 : 00 NOP + 1140/ 621 : 00 NOP + 1141/ 622 : 00 NOP + 1142/ 623 : 00 NOP + 1143/ 624 : ; 1 BYTE READ + 1144/ 624 : ; EXIT SUMDT=STORE + 1145/ 624 : ; CF=1 : BREAK + 1146/ 624 : ; CF=0 : DATA=ACC + 1147/ 624 : + 1148/ 624 : C5 RBYTE: PUSH BC + 1149/ 625 : D5 PUSH DE + 1150/ 626 : E5 PUSH HL + 1151/ 627 : 21 00 08 LD HL,0800H ; 8 BITS + 1152/ 62A : 01 01 E0 LD BC,KEYPB ; KEY DATA E001H + 1153/ 62D : 11 02 E0 LD DE,CSTR ; $TAPE DATA E002H + 1154/ 630 : CD 01 06 RBY1: CALL EDGE ; 41 OR 101 + 1155/ 633 : DA 54 06 JP C,RBY3 ; 13 (SHIFT & BREAK) + 1156/ 636 : CD 4A 0A CALL DLY3 ; 20+18*63+33 + 1157/ 639 : 1A LD A,(DE) ; DATA READ :8 + 1158/ 63A : E6 20 AND 20H + 1159/ 63C : CA 49 06 JP Z,RBY2 ; 0 + 1160/ 63F : E5 PUSH HL + 1161/ 640 : 2A 97 11 LD HL,(SUMDT) + 1162/ 643 : 23 INC HL ; CHECK SUM; COUNT HIGH BITS ON TAPE + 1163/ 644 : 22 97 11 LD (SUMDT),HL + 1164/ 647 : E1 POP HL + 1165/ 648 : 37 SCF + 1166/ 649 : 7D RBY2: LD A,L ; BUILD CHAR + 1167/ 64A : 17 RLA + 1168/ 64B : 6F LD L,A + 1169/ 64C : 25 DEC H ; BITCOUNT-1 + 1170/ 64D : C2 30 06 JP NZ,RBY1 + 1171/ 650 : CD 01 06 CALL EDGE + 1172/ 653 : 7D LD A,L ; CHAR READ + 1173/ 654 : E1 RBY3: POP HL + 1174/ 655 : D1 POP DE + 1175/ 656 : C1 POP BC + 1176/ 657 : C9 RET + 1177/ 658 : + 1178/ 658 : 00 NOP + 1179/ 659 : 00 NOP + 1180/ 65A : 00 NOP + 1181/ 65B : + 1182/ 65B : ; TAPE MARK DETECT + 1183/ 65B : ; E=@L@ : INFORMATION + 1184/ 65B : ; =@S@ : DATA + 1185/ 65B : ; EXIT CF=0 OK + 1186/ 65B : ; =1 BREAK + 1187/ 65B : + 1188/ 65B : CD E2 0F TMARK: CALL GAPCK + 1189/ 65E : C5 PUSH BC + 1190/ 65F : D5 PUSH DE + 1191/ 660 : E5 PUSH HL + 1192/ 661 : 21 28 28 LD HL,2828H + 1193/ 664 : 7B LD A,E + 1194/ 665 : FE CC CP 0CCH ; "L" + 1195/ 667 : 28 03 JR Z,L066C + 1196/ 669 : 21 14 14 LD HL,1414H + AS V1.40r8 - Quelle MZ700.ASM - Seite 21 - 9.6.1998 9:06:29 + + + 1197/ 66C : 22 95 11 L066C: LD (TMCNT),HL + 1198/ 66F : 01 01 E0 LD BC,KEYPB + 1199/ 672 : 11 02 E0 LD DE,CSTR + 1200/ 675 : 2A 95 11 TM1: LD HL,(TMCNT) + 1201/ 678 : CD 01 06 TM2: CALL EDGE + 1202/ 67B : 38 1E JR C,TM4 + 1203/ 67D : CD 4A 0A CALL DLY3 ; CALL DLY2*3 + 1204/ 680 : 1A LD A,(DE) + 1205/ 681 : E6 20 AND 20H + 1206/ 683 : 28 F0 JR Z,TM1 + 1207/ 685 : 25 DEC H + 1208/ 686 : 20 F0 JR NZ,TM2 + 1209/ 688 : CD 01 06 TM3: CALL EDGE + 1210/ 68B : 38 0E JR C,TM4 + 1211/ 68D : CD 4A 0A CALL DLY3 ; CALL DLY2*3 + 1212/ 690 : 1A LD A,(DE) + 1213/ 691 : E6 20 AND 20H + 1214/ 693 : 20 E0 JR NZ,TM1 + 1215/ 695 : 2D DEC L + 1216/ 696 : 20 F0 JR NZ,TM3 + 1217/ 698 : CD 01 06 CALL EDGE + 1218/ 69B : TM4: + 1219/ 69B : E1 RET3: POP HL + 1220/ 69C : D1 POP DE + 1221/ 69D : C1 POP BC + 1222/ 69E : C9 RET + 1223/ 69F : + 1224/ 69F : ; MOTOR ON + 1225/ 69F : ; IN D=@W@ :WRITE + 1226/ 69F : ; =@R@ :READ + 1227/ 69F : ; EXIT CF=0 OK + 1228/ 69F : ; =1 BREAK + 1229/ 69F : + 1230/ 69F : C5 MOTOR: PUSH BC + 1231/ 6A0 : D5 PUSH DE + 1232/ 6A1 : E5 PUSH HL + 1233/ 6A2 : 06 0A LD B,0AH + 1234/ 6A4 : 3A 02 E0 MOT1: LD A,(CSTR) + 1235/ 6A7 : E6 10 AND 10H + 1236/ 6A9 : 28 0E JR Z,MOT4 + 1237/ 6AB : 06 FF MOT2: LD B,0FFH ; 2 SEC DELAY + 1238/ 6AD : CD 96 09 L06AD: CALL DLY12 ; 7 MSEC DELAY + 1239/ 6B0 : 18 02 JR L06B4 ; MOTOR ENTRY ADJUST + 1240/ 6B2 : + 1241/ 6B2 : 18 EB JR MOTOR ; ORG 06B2H + 1242/ 6B4 : + 1243/ 6B4 : 10 F7 L06B4: DJNZ L06AD + 1244/ 6B6 : AF XOR A + 1245/ 6B7 : 18 E2 MOT7: JR RET3 + 1246/ 6B9 : + 1247/ 6B9 : 3E 06 MOT4: LD A,06H + 1248/ 6BB : 21 03 E0 LD HL,CSTPT + 1249/ 6BE : 77 LD (HL),A + 1250/ 6BF : 3C INC A + 1251/ 6C0 : 77 LD (HL),A + 1252/ 6C1 : 10 E1 DJNZ MOT1 + 1253/ 6C3 : CD 09 00 CALL NL + 1254/ 6C6 : 7A LD A,D + 1255/ 6C7 : FE D7 CP 0D7H ; "W" + 1256/ 6C9 : 28 05 JR Z,MOT8 + AS V1.40r8 - Quelle MZ700.ASM - Seite 22 - 9.6.1998 9:06:29 + + + 1257/ 6CB : 11 FB 03 LD DE,MSGN1 ; PLAY MARK + 1258/ 6CE : 18 07 JR MOT9 + 1259/ 6D0 : + 1260/ 6D0 : 11 02 04 MOT8: LD DE,MSGN3 ; "RECORD." + 1261/ 6D3 : DF RST 18H ; CALL MSGX + 1262/ 6D4 : 11 FD 03 LD DE,MSGN2 ; "PLAY" + 1263/ 6D7 : DF MOT9: RST 18H ; CALL MSGX + 1264/ 6D8 : 3A 02 E0 MOT5: LD A,(CSTR) + 1265/ 6DB : E6 10 AND 10H + 1266/ 6DD : 20 CC JR NZ,MOT2 + 1267/ 6DF : CD 32 0A CALL QBRK + 1268/ 6E2 : 20 F4 JR NZ,MOT5 + 1269/ 6E4 : 37 SCF + 1270/ 6E5 : 18 D0 JR MOT7 + 1271/ 6E7 : + 1272/ 6E7 : ; INITIAL MESSAGE + 1273/ 6E7 : + 1274/ 6E7 : 2A 2A 20 20 4D 4F MSGQ3: DB "** MONITOR 1Z-013A **\r" + 4E 49 54 4F 52 20 + 31 5A 2D 30 31 33 + 41 20 20 2A 2A 0D + 1275/ 6FF : 00 NOP + 1276/ 700 : + 1277/ 700 : ; MOTOR STOP + 1278/ 700 : + 1279/ 700 : F5 MSTOP: PUSH AF + 1280/ 701 : C5 PUSH BC + 1281/ 702 : D5 PUSH DE + 1282/ 703 : 06 0A LD B,0AH + 1283/ 705 : 3A 02 E0 MST1: LD A,(CSTR) + 1284/ 708 : E6 10 AND 10H + 1285/ 70A : 28 0B JR Z,MST3 + 1286/ 70C : 3E 06 LD A,06H + 1287/ 70E : 32 03 E0 LD (CSTPT),A + 1288/ 711 : 3C INC A + 1289/ 712 : 32 03 E0 LD (CSTPT),A + 1290/ 715 : 10 EE DJNZ MST1 + 1291/ 717 : C3 E6 0E MST3: JP QRSTR1 + 1292/ 71A : + 1293/ 71A : ; CHECK SUM + 1294/ 71A : ; IN BC=SIZE + 1295/ 71A : ; HL=DATA ADDRESS + 1296/ 71A : ; EXIT SUMDT=STORE + 1297/ 71A : ; CSMDT=STORE + 1298/ 71A : + 1299/ 71A : C5 CKSUM: PUSH BC + 1300/ 71B : D5 PUSH DE + 1301/ 71C : E5 L071C: PUSH HL + 1302/ 71D : 11 00 00 LD DE,0 + 1303/ 720 : 78 CKS1: LD A,B + 1304/ 721 : B1 OR C + 1305/ 722 : 20 0B JR NZ,CKS2 + 1306/ 724 : EB EX DE,HL + 1307/ 725 : 22 97 11 L0725: LD (SUMDT),HL ; NUMBER OF HIGHBITS IN DATA + 1308/ 728 : 22 99 11 LD (CSMDT),HL + 1309/ 72B : E1 POP HL + 1310/ 72C : D1 POP DE + 1311/ 72D : C1 POP BC + 1312/ 72E : C9 RET + 1313/ 72F : + AS V1.40r8 - Quelle MZ700.ASM - Seite 23 - 9.6.1998 9:06:29 + + + 1314/ 72F : 7E CKS2: LD A,(HL) + 1315/ 730 : C5 PUSH BC + 1316/ 731 : 06 08 LD B,8 + 1317/ 733 : 07 CKS3: RLCA + 1318/ 734 : 30 01 JR NC,L0737 + 1319/ 736 : 13 INC DE + 1320/ 737 : 10 FA L0737: DJNZ CKS3 + 1321/ 739 : C1 L0739: POP BC + 1322/ 73A : 23 INC HL + 1323/ 73B : 0B DEC BC + 1324/ 73C : 18 E2 JR CKS1 + 1325/ 73E : + 1326/ 73E : ; MODE SET OF KEYPORT + 1327/ 73E : + 1328/ 73E : 21 03 E0 QMODE: LD HL,KEYPF + 1329/ 741 : 36 8A LD (HL),8AH ; 10001010 CTRL WORD MODE0 + 1330/ 743 : 36 07 LD (HL),07H ; PC3=1 M-ON + 1331/ 745 : 36 05 LD (HL),05H ; PC2=1 INTMSK + 1332/ 747 : C9 RET + 1333/ 748 : + 1334/ 748 : 00 NOP + 1335/ 749 : 00 NOP + 1336/ 74A : 00 NOP + 1337/ 74B : 00 NOP + 1338/ 74C : 00 NOP + 1339/ 74D : 00 NOP + 1340/ 74E : 00 NOP + 1341/ 74F : 00 NOP + 1342/ 750 : 00 NOP + 1343/ 751 : 00 NOP + 1344/ 752 : 00 NOP + 1345/ 753 : 00 NOP + 1346/ 754 : 00 NOP + 1347/ 755 : 00 NOP + 1348/ 756 : 00 NOP + 1349/ 757 : 00 NOP + 1350/ 758 : 00 NOP + 1351/ 759 : + 1352/ 759 : ; 107 MICRO SEC DELAY + 1353/ 759 : + 1354/ 759 : 3E 15 DLY1: LD A,15H ; 18*21+20 + 1355/ 75B : 3D L075B: DEC A + 1356/ 75C : C2 5B 07 JP NZ,L075B + 1357/ 75F : C9 RET + 1358/ 760 : + 1359/ 760 : 3E 13 DLY2: LD A,13H ; 18*19+20 + 1360/ 762 : 3D L0762: DEC A + 1361/ 763 : C2 62 07 JP NZ,L0762 + 1362/ 766 : C9 RET + 1363/ 767 : + 1364/ 767 : ; 1 BYTE WRITE + 1365/ 767 : + 1366/ 767 : C5 WBYTE: PUSH BC + 1367/ 768 : 06 08 LD B,8 + 1368/ 76A : CD 1A 0A CALL LONG + 1369/ 76D : 07 WBY1: RLCA + 1370/ 76E : DC 1A 0A CALL C,LONG + 1371/ 771 : D4 01 0A CALL NC,SHORT + 1372/ 774 : 05 DEC B + 1373/ 775 : C2 6D 07 JP NZ,WBY1 + AS V1.40r8 - Quelle MZ700.ASM - Seite 24 - 9.6.1998 9:06:29 + + + 1374/ 778 : C1 POP BC + 1375/ 779 : C9 RET + 1376/ 77A : + 1377/ 77A : ; GAP + TAPEMARK + 1378/ 77A : ; E=@L@ LONG GAP + 1379/ 77A : ; =@s@ SHORT GAP + 1380/ 77A : + 1381/ 77A : C5 GAP: PUSH BC + 1382/ 77B : D5 PUSH DE + 1383/ 77C : 7B LD A,E + 1384/ 77D : 01 F0 55 LD BC,55F0H + 1385/ 780 : 11 28 28 LD DE,2828H + 1386/ 783 : FE CC CP 0CCH ; "L" + 1387/ 785 : CA 8E 07 JP Z,GAP1 + 1388/ 788 : 01 F8 2A LD BC,2AF8H + 1389/ 78B : 11 14 14 LD DE,1414H + 1390/ 78E : CD 01 0A GAP1: CALL SHORT + 1391/ 791 : 0B DEC BC + 1392/ 792 : 78 LD A,B + 1393/ 793 : B1 OR C + 1394/ 794 : 20 F8 JR NZ,GAP1 + 1395/ 796 : CD 1A 0A GAP2: CALL LONG + 1396/ 799 : 15 DEC D + 1397/ 79A : 20 FA JR NZ,GAP2 + 1398/ 79C : CD 01 0A GAP3: CALL SHORT + 1399/ 79F : 1D DEC E + 1400/ 7A0 : 20 FA JR NZ,GAP3 + 1401/ 7A2 : CD 1A 0A CALL LONG + 1402/ 7A5 : D1 POP DE + 1403/ 7A6 : C1 POP BC + 1404/ 7A7 : C9 RET + 1405/ 7A8 : + 1406/ 7A8 : ; MEMORY CORRECTION + 1407/ 7A8 : ; COMMAND "M" + 1408/ 7A8 : + 1409/ 7A8 : CD 3D 01 MCOR: CALL HEXIY ; CORRECTION ADDRESS + 1410/ 7AB : CD FA 05 MCR1: CALL NLPHL ; CORRECTION ADDRESS PRINT + 1411/ 7AE : CD B1 03 CALL SPHEX ; ACC-->ASCII DISP. + 1412/ 7B1 : CD 20 09 CALL QPRTS ; SPACE PRINT + 1413/ 7B4 : CD 2F 01 CALL BGETL ; GET DATA & CHECK DATA + 1414/ 7B7 : CD 10 04 CALL HLHEX ; HL<--ASCII(DE) + 1415/ 7BA : 38 1B JR C,MCR3 + 1416/ 7BC : CD A6 02 CALL P4DE ; (INC DE)*4 + 1417/ 7BF : 13 INC DE + 1418/ 7C0 : CD 1F 04 CALL L2HEX ; DATA CHECK + 1419/ 7C3 : 38 E6 JR C,MCR1 + 1420/ 7C5 : BE CP (HL) + 1421/ 7C6 : 20 E3 JR NZ,MCR1 + 1422/ 7C8 : 13 INC DE + 1423/ 7C9 : 1A LD A,(DE) + 1424/ 7CA : FE 0D CP 0DH ; NOT CORRECTION ? + 1425/ 7CC : 28 06 JR Z,MCR2 + 1426/ 7CE : CD 1F 04 CALL L2HEX ; ACC<--HL(ASCII) + 1427/ 7D1 : 38 D8 JR C,MCR1 + 1428/ 7D3 : 77 LD (HL),A ; DATA CORRECT + 1429/ 7D4 : 23 MCR2: INC HL + 1430/ 7D5 : 18 D4 JR MCR1 + 1431/ 7D7 : + 1432/ 7D7 : 60 MCR3: LD H,B ; MEMORY ADDRESS + 1433/ 7D8 : 69 LD L,C + AS V1.40r8 - Quelle MZ700.ASM - Seite 25 - 9.6.1998 9:06:29 + + + 1434/ 7D9 : 18 D0 JR MCR1 + 1435/ 7DB : + 1436/ 7DB : 28 48 4C 29 DB "(HL)" + 1437/ 7DF : F1 DB 0F1H + 1438/ 7E0 : 9E DB 9EH + 1439/ 7E1 : 53 55 42 20 28 DB "SUB (" + 1440/ 7E6 : + 1441/ 7E6 : ; GET 1 LINE STATEMENT * + 1442/ 7E6 : ; DE=DATA STORE LOW ADDRESS + 1443/ 7E6 : ; (END=CR) + 1444/ 7E6 : + 1445/ 7E6 : F5 QGETL: PUSH AF + 1446/ 7E7 : C5 PUSH BC + 1447/ 7E8 : E5 PUSH HL + 1448/ 7E9 : D5 PUSH DE + 1449/ 7EA : CD B3 09 GETL1: CALL QQKEY ; ENTRY KEY + 1450/ 7ED : F5 AUTO3: PUSH AF ; IN KEY DATA SAVE + 1451/ 7EE : 47 LD B,A + 1452/ 7EF : 3A 9D 11 LD A,(SWRK) ; BELL WORK + 1453/ 7F2 : 0F RRCA + 1454/ 7F3 : D4 77 05 CALL NC,QBEL ; ENTRY BELL + 1455/ 7F6 : 78 LD A,B + 1456/ 7F7 : 21 70 11 LD HL,KANAF ; KANA & GRAPH FLAGS + 1457/ 7FA : E6 F0 AND 0F0H + 1458/ 7FC : FE C0 CP 0C0H + 1459/ 7FE : D1 POP DE ; EREG=FLAGREG + 1460/ 7FF : 78 LD A,B + 1461/ 800 : 20 16 JR NZ,GETL2 ; NOT C0H + 1462/ 802 : FE CD CP 0CDH ; CR + 1463/ 804 : 28 55 JR Z,GETL3 + 1464/ 806 : FE CB CP 0CBH ; BREAK + 1465/ 808 : CA 22 08 JP Z,GETLC + 1466/ 80B : FE CF CP 0CFH ; NIKO MARK WH. + 1467/ 80D : 28 09 JR Z,GETL2 + 1468/ 80F : FE C7 CP 0C7H ; CRT EDITION + 1469/ 811 : 30 0A JR NC,GETL5 ; <=C7H + 1470/ 813 : CB 1B RR E ; >C7H & CFLAG, CY ? GRAPHIC MODE,CURS.DISPL. + 1471/ 815 : 78 LD A,B + 1472/ 816 : 30 05 JR NC,GETL5 + 1473/ 818 : CD B5 0D GETL2: CALL QDSP ; DISPL. + 1474/ 81B : 18 CD JR GETL1 + 1475/ 81D : + 1476/ 81D : CD DC 0D GETL5: CALL QDPCT ; CRT CONTROL + 1477/ 820 : 18 C8 JR GETL1 + 1478/ 822 : + 1479/ 822 : ; BREAK IN + 1480/ 822 : + 1481/ 822 : E1 GETLC: POP HL + 1482/ 823 : E5 PUSH HL + 1483/ 824 : 36 1B LD (HL),1BH ; BREAK CODE + 1484/ 826 : 23 INC HL + 1485/ 827 : 36 0D LD (HL),0DH + 1486/ 829 : 18 53 JR GETLR + 1487/ 82B : + 1488/ 82B : ; GETLA + 1489/ 82B : + 1490/ 82B : 0F GETLA: RRCA ; CY<--D7 + 1491/ 82C : 30 37 JR NC,GETL6 + 1492/ 82E : 18 33 JR GETLB + 1493/ 830 : + AS V1.40r8 - Quelle MZ700.ASM - Seite 26 - 9.6.1998 9:06:29 + + + 1494/ 830 : ; DELAY 7 MSEC AND SWEP + 1495/ 830 : + 1496/ 830 : CD 96 09 DSWEP: CALL DLY12 + 1497/ 833 : CD 50 0A CALL QSWEP + 1498/ 836 : C9 RET + 1499/ 837 : + 1500/ 837 : 00 NOP + 1501/ 838 : 00 NOP + 1502/ 839 : 00 NOP + 1503/ 83A : 00 NOP + 1504/ 83B : 00 NOP + 1505/ 83C : 00 NOP + 1506/ 83D : 00 NOP + 1507/ 83E : 00 NOP + 1508/ 83F : 00 NOP + 1509/ 840 : 00 NOP + 1510/ 841 : 00 NOP + 1511/ 842 : 00 NOP + 1512/ 843 : 00 NOP + 1513/ 844 : 00 NOP + 1514/ 845 : 00 NOP + 1515/ 846 : 00 NOP + 1516/ 847 : 00 NOP + 1517/ 848 : 00 NOP + 1518/ 849 : 00 NOP + 1519/ 84A : 00 NOP + 1520/ 84B : 00 NOP + 1521/ 84C : 00 NOP + 1522/ 84D : 00 NOP + 1523/ 84E : 00 NOP + 1524/ 84F : 00 NOP + 1525/ 850 : 00 NOP + 1526/ 851 : 00 NOP + 1527/ 852 : 00 NOP + 1528/ 853 : 00 NOP + 1529/ 854 : 00 NOP + 1530/ 855 : 00 NOP + 1531/ 856 : 00 NOP + 1532/ 857 : 00 NOP + 1533/ 858 : 00 NOP + 1534/ 859 : 00 NOP + 1535/ 85A : 00 NOP + 1536/ 85B : + 1537/ 85B : CD F3 02 GETL3: CALL PMANG ; CR + 1538/ 85E : 06 28 LD B,40 ; 1 LINE + 1539/ 860 : 30 C9 JR NC,GETLA + 1540/ 862 : 25 DEC H ; BEFORE LINE + 1541/ 863 : 06 50 GETLB: LD B,80 ; 2 LINE + 1542/ 865 : 2E 00 GETL6: LD L,0 + 1543/ 867 : CD B4 0F CALL QPNT1 + 1544/ 86A : D1 POP DE ; STORE TOP ADDRESS + 1545/ 86B : D5 PUSH DE + 1546/ 86C : 7E GETLZ: LD A,(HL) + 1547/ 86D : CD CE 0B CALL QDACN + 1548/ 870 : 12 LD (DE),A + 1549/ 871 : 23 INC HL + 1550/ 872 : 13 INC DE + 1551/ 873 : 10 F7 DJNZ GETLZ + 1552/ 875 : EB EX DE,HL + 1553/ 876 : 36 0D GETLU: LD (HL),0DH + AS V1.40r8 - Quelle MZ700.ASM - Seite 27 - 9.6.1998 9:06:29 + + + 1554/ 878 : 2B DEC HL + 1555/ 879 : 7E LD A,(HL) + 1556/ 87A : FE 20 CP 20H ; SPACE THEN CR + 1557/ 87C : + 1558/ 87C : ; CR AND NEW LINE + 1559/ 87C : + 1560/ 87C : 28 F8 JR Z,GETLU + 1561/ 87E : + 1562/ 87E : ; NEW LINE RETURN + 1563/ 87E : + 1564/ 87E : CD 0E 09 GETLR: CALL QLTNL + 1565/ 881 : D1 POP DE + 1566/ 882 : E1 POP HL + 1567/ 883 : C1 POP BC + 1568/ 884 : F1 POP AF + 1569/ 885 : C9 RET + 1570/ 886 : + 1571/ 886 : 00 NOP + 1572/ 887 : 00 NOP + 1573/ 888 : 00 NOP + 1574/ 889 : 00 NOP + 1575/ 88A : 00 NOP + 1576/ 88B : 00 NOP + 1577/ 88C : 00 NOP + 1578/ 88D : 00 NOP + 1579/ 88E : 00 NOP + 1580/ 88F : 00 NOP + 1581/ 890 : 00 NOP + 1582/ 891 : 00 NOP + 1583/ 892 : 00 NOP + 1584/ 893 : + 1585/ 893 : ; MESSAGE PRINT + 1586/ 893 : ; DE PRINT DATA LOW ADDRESS + 1587/ 893 : ; END=CR + 1588/ 893 : + 1589/ 893 : F5 QMSG: PUSH AF + 1590/ 894 : C5 PUSH BC + 1591/ 895 : D5 PUSH DE + 1592/ 896 : 1A MSG1: LD A,(DE) + 1593/ 897 : FE 0D CP 0DH ; CR + 1594/ 899 : 28 0C JR Z,MSGX2 + 1595/ 89B : CD 35 09 CALL QPRNT + 1596/ 89E : 13 INC DE + 1597/ 89F : 18 F5 JR MSG1 + 1598/ 8A1 : + 1599/ 8A1 : ; ALL PRINT MESSAGE + 1600/ 8A1 : + 1601/ 8A1 : F5 QMSGX: PUSH AF + 1602/ 8A2 : C5 PUSH BC + 1603/ 8A3 : D5 PUSH DE + 1604/ 8A4 : 1A MSGX1: LD A,(DE) + 1605/ 8A5 : FE 0D CP 0DH + 1606/ 8A7 : CA E6 0E MSGX2: JP Z,QRSTR1 + 1607/ 8AA : CD B9 0B CALL QADCN + 1608/ 8AD : CD 6C 09 CALL PRNT3 + 1609/ 8B0 : 13 INC DE + 1610/ 8B1 : 18 F1 JR MSGX1 + 1611/ 8B3 : + 1612/ 8B3 : ; TOP OF KEYTBLS + 1613/ 8B3 : + AS V1.40r8 - Quelle MZ700.ASM - Seite 28 - 9.6.1998 9:06:30 + + + 1614/ 8B3 : 11 2A 0C QKYSM: LD DE,KTBLS ; SHIFT ALSO + 1615/ 8B6 : 18 42 JR QKY5 + 1616/ 8B8 : + 1617/ 8B8 : ; BREAK CODE IN + 1618/ 8B8 : + 1619/ 8B8 : 3E CB NBRK: LD A,0CBH ; BREAK CODE + 1620/ 8BA : B7 OR A + 1621/ 8BB : 18 19 JR QKY1 + 1622/ 8BD : + 1623/ 8BD : ; GETKEY + 1624/ 8BD : ; NO ECHO BACK + 1625/ 8BD : ; EXIT ACC=ASCII CODE + 1626/ 8BD : + 1627/ 8BD : CD CA 08 QGET: CALL QKEY ; KEY IN (DISPLAY CODE) + 1628/ 8C0 : D6 F0 SUB 0F0H ; NOT KEYIN CODE + 1629/ 8C2 : C8 RET Z + 1630/ 8C3 : C6 F0 ADD A,0F0H + 1631/ 8C5 : C3 CE 0B JP QDACN ; DISPLAY TO ASCII CODE + 1632/ 8C8 : + 1633/ 8C8 : 00 NOP + 1634/ 8C9 : 00 NOP + 1635/ 8CA : + 1636/ 8CA : ; 1 KEY INPUT + 1637/ 8CA : ; IN B=KEY MODE (SHIFT, CTRL, BREAK) + 1638/ 8CA : ; C=KEY DATA (COLUMN & ROW) + 1639/ 8CA : ; EXIT ACC=DISPLAY CODE + 1640/ 8CA : ; IF NO KEY ACC=F0H + 1641/ 8CA : ; IF CY=1 THEN ATTRIBUTE ON + 1642/ 8CA : ; (SMALL, HIRAKANA) + 1643/ 8CA : + 1644/ 8CA : C5 QKEY: PUSH BC + 1645/ 8CB : D5 PUSH DE + 1646/ 8CC : E5 PUSH HL + 1647/ 8CD : CD 30 08 CALL DSWEP ; DELAY AND KEY SWEP + 1648/ 8D0 : 78 LD A,B + 1649/ 8D1 : 07 RLCA + 1650/ 8D2 : 38 06 JR C,QKY2 + 1651/ 8D4 : 3E F0 LD A,0F0H ; SHIFT OR CTRL HERE + 1652/ 8D6 : E1 QKY1: POP HL + 1653/ 8D7 : D1 POP DE + 1654/ 8D8 : C1 POP BC + 1655/ 8D9 : C9 RET + 1656/ 8DA : + 1657/ 8DA : 11 EA 0B QKY2: LD DE,KTBL ; NORMAL KEY TABLE + 1658/ 8DD : 78 LD A,B + 1659/ 8DE : FE 88 CP 88H ; BREAK IN (SHIFT & BRK) + 1660/ 8E0 : 28 D6 JR Z,NBRK + 1661/ 8E2 : 26 00 LD H,0 ; HL=ROW & COLUMN + 1662/ 8E4 : 69 LD L,C + 1663/ 8E5 : CB 6F BIT 5,A ; CTRL CHECK + 1664/ 8E7 : 20 0E JR NZ,L08F7 ; YES, CTRL + 1665/ 8E9 : 3A 70 11 LD A,(KANAF) ; 0=NR., 1=GRAPH + 1666/ 8EC : 0F RRCA + 1667/ 8ED : DA FE 08 JP C,QKYGRP ; GRAPH MODE + 1668/ 8F0 : 78 LD A,B ; CTRL KEY CHECK + 1669/ 8F1 : 17 RLA + 1670/ 8F2 : 17 RLA + 1671/ 8F3 : 38 BE JR C,QKYSM + 1672/ 8F5 : 18 03 JR QKY5 + 1673/ 8F7 : + AS V1.40r8 - Quelle MZ700.ASM - Seite 29 - 9.6.1998 9:06:30 + + + 1674/ 8F7 : 11 AA 0C L08F7: LD DE,KTBLC ; CONTROL KEY TABLE + 1675/ 8FA : 19 QKY5: ADD HL,DE ; TABLE + 1676/ 8FB : 7E QKY55: LD A,(HL) + 1677/ 8FC : 18 D8 JR QKY1 + 1678/ 8FE : + 1679/ 8FE : CB 70 QKYGRP: BIT 6,B + 1680/ 900 : 28 07 JR Z,QKYGRS + 1681/ 902 : 11 E9 0C LD DE,KTBLG + 1682/ 905 : 19 ADD HL,DE + 1683/ 906 : 37 SCF + 1684/ 907 : 18 F2 JR QKY55 + 1685/ 909 : + 1686/ 909 : 11 6A 0C QKYGRS: LD DE,KTBLGS + 1687/ 90C : 18 EC JR QKY5 + 1688/ 90E : + 1689/ 90E : ; NEWLINE + 1690/ 90E : + 1691/ 90E : AF QLTNL: XOR A + 1692/ 90F : 32 94 11 LD (DPRNT),A ; ROW POINTER + 1693/ 912 : 3E CD LD A,0CDH ; CR + 1694/ 914 : 18 43 JR PRNT5 + 1695/ 916 : + 1696/ 916 : 00 NOP + 1697/ 917 : 00 NOP + 1698/ 918 : + 1699/ 918 : 3A 94 11 QNL: LD A,(DPRNT) + 1700/ 91B : B7 OR A + 1701/ 91C : C8 RET Z + 1702/ 91D : 18 EF JR QLTNL + 1703/ 91F : + 1704/ 91F : 00 NOP + 1705/ 920 : + 1706/ 920 : ; PRINT SPACE + 1707/ 920 : + 1708/ 920 : 3E 20 QPRTS: LD A,20H + 1709/ 922 : 18 11 JR QPRNT + 1710/ 924 : + 1711/ 924 : ; PRINT TAB + 1712/ 924 : + 1713/ 924 : CD 0C 00 QPRTT: CALL PRNTS + 1714/ 927 : 3A 94 11 LD A,(DPRNT) + 1715/ 92A : B7 OR A + 1716/ 92B : C8 RET Z + 1717/ 92C : D6 0A L092C: SUB 10 + 1718/ 92E : 38 F4 JR C,QPRTT + 1719/ 930 : 20 FA JR NZ,L092C + 1720/ 932 : 00 NOP + 1721/ 933 : 00 NOP + 1722/ 934 : 00 NOP + 1723/ 935 : + 1724/ 935 : ; PRINT + 1725/ 935 : ; IN ACC=PRINT DATA (ASCII) + 1726/ 935 : + 1727/ 935 : FE 0D QPRNT: CP 0DH ; CR + 1728/ 937 : 28 D5 JR Z,QLTNL + 1729/ 939 : C5 PUSH BC + 1730/ 93A : 4F LD C,A + 1731/ 93B : 47 LD B,A + 1732/ 93C : CD 46 09 CALL QPRT + 1733/ 93F : 78 LD A,B + AS V1.40r8 - Quelle MZ700.ASM - Seite 30 - 9.6.1998 9:06:30 + + + 1734/ 940 : C1 POP BC + 1735/ 941 : C9 RET + 1736/ 942 : + 1737/ 942 : 4F 4B 21 0D MSGOK: DB "OK!\r" + 1738/ 946 : + 1739/ 946 : ; PRINT ROUTINE + 1740/ 946 : ; 1 CHARACTER + 1741/ 946 : ; INPUT:C=ASCII DATA (QDSP+QDPCT) + 1742/ 946 : + 1743/ 946 : 79 QPRT: LD A,C + 1744/ 947 : CD B9 0B CALL QADCN ; ASCII TO DSPLAY + 1745/ 94A : 4F LD C,A + 1746/ 94B : FE F0 CP 0F0H + 1747/ 94D : C8 RET Z ; ZERO=ILLEGAL DATA + 1748/ 94E : E6 F0 AND 0F0H ; MSD CHECK + 1749/ 950 : FE C0 CP 0C0H + 1750/ 952 : 79 LD A,C + 1751/ 953 : 20 17 JR NZ,PRNT3 + 1752/ 955 : FE C7 CP 0C7H + 1753/ 957 : 30 13 JR NC,PRNT3 ; CRT EDITOR + 1754/ 959 : CD DC 0D PRNT5: CALL QDPCT + 1755/ 95C : FE C3 CP 0C3H ; "->" + 1756/ 95E : 28 0F JR Z,PRNT4 + 1757/ 960 : FE C5 CP 0C5H ; HOME + 1758/ 962 : 28 03 JR Z,PRNT2 + 1759/ 964 : FE C6 CP 0C6H ; CLR + 1760/ 966 : C0 RET NZ + 1761/ 967 : AF PRNT2: XOR A + 1762/ 968 : 32 94 11 L0968: LD (DPRNT),A + 1763/ 96B : C9 RET + 1764/ 96C : + 1765/ 96C : CD B5 0D PRNT3: CALL QDSP + 1766/ 96F : 3A 94 11 PRNT4: LD A,(DPRNT) ; TAB POINT+1 + 1767/ 972 : 3C INC A + 1768/ 973 : FE 50 CP 80 + 1769/ 975 : 38 F1 JR C,L0968 + 1770/ 977 : D6 50 SUB 80 + 1771/ 979 : 18 ED JR L0968 + 1772/ 97B : + 1773/ 97B : ; FLASHING BYPASS 1 + 1774/ 97B : + 1775/ 97B : 3A 8E 11 FLAS1: LD A,(FLASH) + 1776/ 97E : 18 6F JR FLAS2 + 1777/ 980 : + 1778/ 980 : ; BREAK SUBROUTINE BYPASS 1 + 1779/ 980 : ; CTRL OR NOT KEY + 1780/ 980 : + 1781/ 980 : CB 6F QBRK2: BIT 5,A ; NOT OR CTRL + 1782/ 982 : 28 02 JR Z,QBRK3 ; CTRL + 1783/ 984 : B7 OR A ; NOTKEY A=7FH + 1784/ 985 : C9 RET + 1785/ 986 : + 1786/ 986 : 3E 20 QBRK3: LD A,20H ; CTRL D5=1 + 1787/ 988 : B7 OR A ; ZERO FLG CLR + 1788/ 989 : 37 SCF + 1789/ 98A : C9 RET + 1790/ 98B : + 1791/ 98B : 46 49 4C 45 4E 41 MSGSV: DB "FILENAME? " + 4D 45 3F 20 + 1792/ 995 : 0D DB 0DH + AS V1.40r8 - Quelle MZ700.ASM - Seite 31 - 9.6.1998 9:06:30 + + + 1793/ 996 : + 1794/ 996 : ; DLY 7 MSEC + 1795/ 996 : C5 DLY12: PUSH BC + 1796/ 997 : 06 15 LD B,15H + 1797/ 999 : CD 4A 0A L0999: CALL DLY3 + 1798/ 99C : 10 FB DJNZ L0999 + 1799/ 99E : C1 POP BC + 1800/ 99F : C9 RET + 1801/ 9A0 : + 1802/ 9A0 : ; LOADING MESSAGE + 1803/ 9A0 : + 1804/ 9A0 : 4C 4F 41 44 49 4E MSGQ2: DB "LOADING \r" + 47 20 0D + 1805/ 9A9 : + 1806/ 9A9 : ; DELAY FOR LONG PULSE + 1807/ 9A9 : + 1808/ 9A9 : 3E 59 DLY4: LD A,59H ; 18*89+20 + 1809/ 9AB : 3D L09AB: DEC A + 1810/ 9AC : C2 AB 09 JP NZ,L09AB + 1811/ 9AF : C9 RET + 1812/ 9B0 : + 1813/ 9B0 : 00 NOP + 1814/ 9B1 : 00 NOP + 1815/ 9B2 : 00 NOP + 1816/ 9B3 : + 1817/ 9B3 : ; KEY BOARD SEARCH + 1818/ 9B3 : ; & DISPLAY CODE CONVERSION + 1819/ 9B3 : ; EXIT A=DISPLAY CODE + 1820/ 9B3 : ; CY=GRAPH MODE + 1821/ 9B3 : ; WITH CURSOR DISPLAY + 1822/ 9B3 : + 1823/ 9B3 : E5 QQKEY: PUSH HL + 1824/ 9B4 : CD 92 0B CALL QSAVE + 1825/ 9B7 : CD 7E 05 KSL1: CALL FLKEY ; KEY + 1826/ 9BA : 20 FB JR NZ,KSL1 ; KEY IN THEN JUMP + 1827/ 9BC : CD 7E 05 KSL2: CALL FLKEY + 1828/ 9BF : 28 FB JR Z,KSL2 ; NOT KEY IN THEN JUMP + 1829/ 9C1 : 67 LD H,A + 1830/ 9C2 : CD 96 09 CALL DLY12 ; DELAY CHATTER + 1831/ 9C5 : CD CA 08 CALL QKEY + 1832/ 9C8 : F5 PUSH AF + 1833/ 9C9 : BC CP H ; CHATTER CHECK + 1834/ 9CA : E1 POP HL + 1835/ 9CB : 20 EF JR NZ,KSL2 + 1836/ 9CD : E5 PUSH HL + 1837/ 9CE : F1 POP AF ; IN KEY DATA + 1838/ 9CF : CD F0 05 CALL QLOAD ; FLASHING DATA LOAD + 1839/ 9D2 : E1 POP HL + 1840/ 9D3 : C9 RET + 1841/ 9D4 : + 1842/ 9D4 : ; CLEAR 2 + 1843/ 9D4 : + 1844/ 9D4 : AF NCLR08: XOR A ; CY FLAG + 1845/ 9D5 : 01 00 08 NCLR8: LD BC,0800H + 1846/ 9D8 : D5 CLEAR: PUSH DE ; BC=CLR BYTE SIZE, A=CLR DATA + 1847/ 9D9 : 57 LD D,A + 1848/ 9DA : 72 CLEAR1: LD (HL),D + 1849/ 9DB : 23 INC HL + 1850/ 9DC : 0B DEC BC + 1851/ 9DD : 78 LD A,B + AS V1.40r8 - Quelle MZ700.ASM - Seite 32 - 9.6.1998 9:06:30 + + + 1852/ 9DE : B1 OR C + 1853/ 9DF : 20 F9 JR NZ,CLEAR1 + 1854/ 9E1 : D1 POP DE + 1855/ 9E2 : C9 RET + 1856/ 9E3 : + 1857/ 9E3 : ; FLASHING 2 + 1858/ 9E3 : + 1859/ 9E3 : F5 QFLS: PUSH AF + 1860/ 9E4 : E5 PUSH HL + 1861/ 9E5 : 3A 02 E0 LD A,(KEYPC) + 1862/ 9E8 : 07 RLCA + 1863/ 9E9 : 07 RLCA + 1864/ 9EA : 38 8F JR C,FLAS1 + 1865/ 9EC : 3A 92 11 LD A,(FLSDT) + 1866/ 9EF : CD B1 0F FLAS2: CALL QPONT ; DISPLAY POSITION + 1867/ 9F2 : 77 LD (HL),A + 1868/ 9F3 : E1 POP HL + 1869/ 9F4 : F1 POP AF + 1870/ 9F5 : C9 RET + 1871/ 9F6 : + 1872/ 9F6 : 00 NOP + 1873/ 9F7 : 00 NOP + 1874/ 9F8 : 00 NOP + 1875/ 9F9 : 00 NOP + 1876/ 9FA : 00 NOP + 1877/ 9FB : 00 NOP + 1878/ 9FC : 00 NOP + 1879/ 9FD : 00 NOP + 1880/ 9FE : 00 NOP + 1881/ 9FF : + 1882/ 9FF : 18 E2 QFLAS: JR QFLS + 1883/ A01 : + 1884/ A01 : ; SHORT AND LONG PULSE FOR 1 BIT WRITE + 1885/ A01 : + 1886/ A01 : F5 SHORT: PUSH AF ; 12 + 1887/ A02 : 3E 03 LD A,03H ; 9 + 1888/ A04 : 32 03 E0 LD (CSTPT),A ; E003H PC3=1:16 + 1889/ A07 : CD 59 07 CALL DLY1 ; 20+18*21+20 + 1890/ A0A : CD 59 07 CALL DLY1 ; 20+18*21+20 + 1891/ A0D : 3E 02 LD A,02H ; 9 + 1892/ A0F : 32 03 E0 LD (CSTPT),A ; E003H PC3=0:16 + 1893/ A12 : CD 59 07 CALL DLY1 ; 20+18*21+20 + 1894/ A15 : CD 59 07 CALL DLY1 ; 20+18*21+20 + 1895/ A18 : F1 POP AF ; 11 + 1896/ A19 : C9 RET ; 11 + 1897/ A1A : + 1898/ A1A : F5 LONG: PUSH AF ; 11 + 1899/ A1B : 3E 03 LD A,03H ; 9 + 1900/ A1D : 32 03 E0 LD (CSTPT),A ; 16 + 1901/ A20 : CD A9 09 CALL DLY4 ; 20+18*89+20 + 1902/ A23 : 3E 02 LD A,02H ; 9 + 1903/ A25 : 32 03 E0 LD (CSTPT),A ; 16 + 1904/ A28 : CD A9 09 CALL DLY4 ; 20+18*89+20 + 1905/ A2B : F1 POP AF ; 11 + 1906/ A2C : C9 RET ; 11 + 1907/ A2D : + 1908/ A2D : 00 NOP + 1909/ A2E : 00 NOP + 1910/ A2F : 00 NOP + 1911/ A30 : 00 NOP + AS V1.40r8 - Quelle MZ700.ASM - Seite 33 - 9.6.1998 9:06:30 + + + 1912/ A31 : 00 NOP + 1913/ A32 : + 1914/ A32 : ; BREAK KEY CHECK + 1915/ A32 : ; AND SHIFT, CTRL KEY CHECK + 1916/ A32 : ; EXIT BREAK ON : ZERO=1 + 1917/ A32 : ; OFF: ZERO=0 + 1918/ A32 : ; NO KEY : CY =0 + 1919/ A32 : ; KEY IN : CY =1 + 1920/ A32 : ; A D6=1 : SHIFT ON + 1921/ A32 : ; =0 : OFF + 1922/ A32 : ; D5=1 : CTRL ON + 1923/ A32 : ; =0 : OFF + 1924/ A32 : ; D4=1 : SHIFT+CNT ON + 1925/ A32 : ; =0 : OFF + 1926/ A32 : + 1927/ A32 : 3E F8 QBRK: LD A,0F8H ; LINE 8SWEEP + 1928/ A34 : 32 00 E0 LD (KEYPA),A + 1929/ A37 : 00 NOP + 1930/ A38 : 3A 01 E0 LD A,(KEYPB) + 1931/ A3B : B7 OR A + 1932/ A3C : 1F RRA + 1933/ A3D : DA 80 09 JP C,QBRK2 ; SHIFT ? + 1934/ A40 : 17 RLA + 1935/ A41 : 17 RLA + 1936/ A42 : 30 04 JR NC,QBRK1 ; BREAK ? + 1937/ A44 : 3E 40 LD A,40H ; SHIFT D6=1 + 1938/ A46 : 37 SCF + 1939/ A47 : C9 RET + 1940/ A48 : + 1941/ A48 : AF QBRK1: XOR A ; SHIFT ? + 1942/ A49 : C9 RET + 1943/ A4A : + 1944/ A4A : ; 320 U SEC DELAY + 1945/ A4A : + 1946/ A4A : 3E 3F DLY3: LD A,3FH ; 18*63+33 + 1947/ A4C : C3 62 07 JP L0762 ; JP DLY2+2 + 1948/ A4F : + 1949/ A4F : 00 NOP + 1950/ A50 : + 1951/ A50 : ; KEY BOARD SWEEP + 1952/ A50 : ; EXIT B,D7=0 NO DATA + 1953/ A50 : ; =1 DATA + 1954/ A50 : ; D6=0 SHIFT OFF + 1955/ A50 : ; =1 SHIFT ON + 1956/ A50 : ; D5=0 CTRL OFF + 1957/ A50 : ; =1 CTRL ON + 1958/ A50 : ; D4=0 SHIFT+CTRL OFF + 1959/ A50 : ; =1 SHIFT+CTRL ON + 1960/ A50 : ; C = ROW & COLUMN + 1961/ A50 : ; 7 6 5 4 3 2 1 0 + 1962/ A50 : ; * * ^ ^ ^ < < < + 1963/ A50 : + 1964/ A50 : D5 QSWEP: PUSH DE + 1965/ A51 : E5 PUSH HL + 1966/ A52 : AF XOR A + 1967/ A53 : 06 F8 LD B,0F8H + 1968/ A55 : 57 LD D,A + 1969/ A56 : CD 32 0A CALL QBRK + 1970/ A59 : 20 04 JR NZ,SWEP6 + 1971/ A5B : 16 88 LD D,88H ; BREAK ON + AS V1.40r8 - Quelle MZ700.ASM - Seite 34 - 9.6.1998 9:06:30 + + + 1972/ A5D : 18 14 JR SWEP9 + 1973/ A5F : + 1974/ A5F : 30 05 SWEP6: JR NC,SWEP0 + 1975/ A61 : 57 LD D,A + 1976/ A62 : 18 02 JR SWEP0 + 1977/ A64 : + 1978/ A64 : CB FA SWEP01: SET 7,D + 1979/ A66 : 05 SWEP0: DEC B + 1980/ A67 : 78 LD A,B + 1981/ A68 : 32 00 E0 LD (KEYPA),A + 1982/ A6B : FE EF CP 0EFH ; MAP SWEEP END ? + 1983/ A6D : 20 08 JR NZ,SWEP3 + 1984/ A6F : FE F8 CP 0F8H ; BREAK KEY ROW + 1985/ A71 : 28 F3 JR Z,SWEP0 + 1986/ A73 : 42 SWEP9: LD B,D + 1987/ A74 : E1 POP HL + 1988/ A75 : D1 POP DE + 1989/ A76 : C9 RET + 1990/ A77 : + 1991/ A77 : 3A 01 E0 SWEP3: LD A,(KEYPB) + 1992/ A7A : 2F CPL + 1993/ A7B : B7 OR A + 1994/ A7C : 28 E8 JR Z,SWEP0 + 1995/ A7E : 5F LD E,A + 1996/ A7F : 26 08 SWEP2: LD H,8 + 1997/ A81 : 78 LD A,B + 1998/ A82 : E6 0F AND 0FH + 1999/ A84 : 07 RLCA + 2000/ A85 : 07 RLCA + 2001/ A86 : 07 RLCA + 2002/ A87 : 4F LD C,A + 2003/ A88 : 7B LD A,E + 2004/ A89 : 25 L0A89: DEC H + 2005/ A8A : 0F RRCA + 2006/ A8B : 30 FC JR NC,L0A89 + 2007/ A8D : 7C LD A,H + 2008/ A8E : 81 ADD A,C + 2009/ A8F : 4F LD C,A + 2010/ A90 : 18 D2 JR SWEP01 + 2011/ A92 : ; + 2012/ A92 : ; + 2013/ A92 : ; ASCII TO DISPLAY CODE TABL + 2014/ A92 : ; + 2015/ A92 : ATBL: + 2016/ A92 : ; 00 - 0F + 2017/ A92 : F0 DB 0F0H ; ^ @ + 2018/ A93 : F0 DB 0F0H ; ^ A + 2019/ A94 : F0 DB 0F0H ; ^ B + 2020/ A95 : F3 DB 0F3H ; ^ C + 2021/ A96 : F0 DB 0F0H ; ^ D + 2022/ A97 : F5 DB 0F5H ; ^ E + 2023/ A98 : F0 DB 0F0H ; ^ F + 2024/ A99 : F0 DB 0F0H ; ^ G + 2025/ A9A : F0 DB 0F0H ; ^ H + 2026/ A9B : F0 DB 0F0H ; ^ I + 2027/ A9C : F0 DB 0F0H ; ^ J + 2028/ A9D : F0 DB 0F0H ; ^ K + 2029/ A9E : F0 DB 0F0H ; ^ L + 2030/ A9F : F0 DB 0F0H ; ^ M + 2031/ AA0 : F0 DB 0F0H ; ^ N + AS V1.40r8 - Quelle MZ700.ASM - Seite 35 - 9.6.1998 9:06:30 + + + 2032/ AA1 : F0 DB 0F0H ; ^ O + 2033/ AA2 : ; 10 - 1F + 2034/ AA2 : F0 DB 0F0H ; ^ P + 2035/ AA3 : C1 DB 0C1H ; ^ Q CUR. DOWN + 2036/ AA4 : C2 DB 0C2H ; ^ R CUR. UP + 2037/ AA5 : C3 DB 0C3H ; ^ S CUR. RIGHT + 2038/ AA6 : C4 DB 0C4H ; ^ T CUR. LEFT + 2039/ AA7 : C5 DB 0C5H ; ^ U HOME + 2040/ AA8 : C6 DB 0C6H ; ^ V CLEAR + 2041/ AA9 : F0 DB 0F0H ; ^ W + 2042/ AAA : F0 DB 0F0H ; ^ X + 2043/ AAB : F0 DB 0F0H ; ^ Y + 2044/ AAC : F0 DB 0F0H ; ^ Z SEP. + 2045/ AAD : F0 DB 0F0H ; ^ [ + 2046/ AAE : F0 DB 0F0H ; ^ \ + 2047/ AAF : F0 DB 0F0H ; ^ ] + 2048/ AB0 : F0 DB 0F0H ; ^ ^ + 2049/ AB1 : F0 DB 0F0H ; ^ - + 2050/ AB2 : ; 20 - 2F + 2051/ AB2 : 00 DB 00H ; SPACE + 2052/ AB3 : 61 DB 61H ; ! + 2053/ AB4 : 62 DB 62H ; " + 2054/ AB5 : 63 DB 63H ; # + 2055/ AB6 : 64 DB 64H ; $ + 2056/ AB7 : 65 DB 65H ; % + 2057/ AB8 : 66 DB 66H ; & + 2058/ AB9 : 67 DB 67H ; ' + 2059/ ABA : 68 DB 68H ; ( + 2060/ ABB : 69 DB 69H ; ) + 2061/ ABC : 6B DB 6BH ; * + 2062/ ABD : 6A DB 6AH ; + + 2063/ ABE : 2F DB 2FH ; , + 2064/ ABF : 2A DB 2AH ; - + 2065/ AC0 : 2E DB 2EH ; . + 2066/ AC1 : 2D DB 2DH ; / + 2067/ AC2 : ; 30 - 3F + 2068/ AC2 : 20 DB 20H ; 0 + 2069/ AC3 : 21 DB 21H ; 1 + 2070/ AC4 : 22 DB 22H ; 2 + 2071/ AC5 : 23 DB 23H ; 3 + 2072/ AC6 : 24 DB 24H ; 4 + 2073/ AC7 : 25 DB 25H ; 5 + 2074/ AC8 : 26 DB 26H ; 6 + 2075/ AC9 : 27 DB 27H ; 7 + 2076/ ACA : 28 DB 28H ; 8 + 2077/ ACB : 29 DB 29H ; 9 + 2078/ ACC : 4F DB 4FH ; : + 2079/ ACD : 2C DB 2CH ; ; + 2080/ ACE : 51 DB 51H ; < + 2081/ ACF : 2B DB 2BH ; = + 2082/ AD0 : 57 DB 57H ; > + 2083/ AD1 : 49 DB 49H ; ? + 2084/ AD2 : ; 40 - 4F + 2085/ AD2 : 55 DB 55H ; @ + 2086/ AD3 : 01 DB 01H ; A + 2087/ AD4 : 02 DB 02H ; B + 2088/ AD5 : 03 DB 03H ; C + 2089/ AD6 : 04 DB 04H ; D + 2090/ AD7 : 05 DB 05H ; E + 2091/ AD8 : 06 DB 06H ; F + AS V1.40r8 - Quelle MZ700.ASM - Seite 36 - 9.6.1998 9:06:30 + + + 2092/ AD9 : 07 DB 07H ; G + 2093/ ADA : 08 DB 08H ; H + 2094/ ADB : 09 DB 09H ; I + 2095/ ADC : 0A DB 0AH ; J + 2096/ ADD : 0B DB 0BH ; K + 2097/ ADE : 0C DB 0CH ; L + 2098/ ADF : 0D DB 0DH ; M + 2099/ AE0 : 0E DB 0EH ; N + 2100/ AE1 : 0F DB 0FH ; O + 2101/ AE2 : ; 50 - 5F + 2102/ AE2 : 10 DB 10H ; P + 2103/ AE3 : 11 DB 11H ; Q + 2104/ AE4 : 12 DB 12H ; R + 2105/ AE5 : 13 DB 13H ; S + 2106/ AE6 : 14 DB 14H ; T + 2107/ AE7 : 15 DB 15H ; U + 2108/ AE8 : 16 DB 16H ; V + 2109/ AE9 : 17 DB 17H ; W + 2110/ AEA : 18 DB 18H ; X + 2111/ AEB : 19 DB 19H ; Y + 2112/ AEC : 1A DB 1AH ; Z + 2113/ AED : 52 DB 52H ; [ + 2114/ AEE : 59 DB 59H ; \ + 2115/ AEF : 54 DB 54H ; ] + 2116/ AF0 : 50 DB 50H ; + 2117/ AF1 : 45 DB 45H ; + 2118/ AF2 : ; 60 - 6F + 2119/ AF2 : C7 DB 0C7H ; UFO + 2120/ AF3 : C8 DB 0C8H + 2121/ AF4 : C9 DB 0C9H + 2122/ AF5 : CA DB 0CAH + 2123/ AF6 : CB DB 0CBH + 2124/ AF7 : CC DB 0CCH + 2125/ AF8 : CD DB 0CDH + 2126/ AF9 : CE DB 0CEH + 2127/ AFA : CF DB 0CFH + 2128/ AFB : DF DB 0DFH + 2129/ AFC : E7 DB 0E7H + 2130/ AFD : E8 DB 0E8H + 2131/ AFE : E5 DB 0E5H + 2132/ AFF : E9 DB 0E9H + 2133/ B00 : EC DB 0ECH + 2134/ B01 : ED DB 0EDH + 2135/ B02 : ; 70 - 7F + 2136/ B02 : D0 DB 0D0H + 2137/ B03 : D1 DB 0D1H + 2138/ B04 : D2 DB 0D2H + 2139/ B05 : D3 DB 0D3H + 2140/ B06 : D4 DB 0D4H + 2141/ B07 : D5 DB 0D5H + 2142/ B08 : D6 DB 0D6H + 2143/ B09 : D7 DB 0D7H + 2144/ B0A : D8 DB 0D8H + 2145/ B0B : D9 DB 0D9H + 2146/ B0C : DA DB 0DAH + 2147/ B0D : DB DB 0DBH + 2148/ B0E : DC DB 0DCH + 2149/ B0F : DD DB 0DDH + 2150/ B10 : DE DB 0DEH + 2151/ B11 : C0 DB 0C0H + AS V1.40r8 - Quelle MZ700.ASM - Seite 37 - 9.6.1998 9:06:30 + + + 2152/ B12 : ; 80 - 8F + 2153/ B12 : 80 DB 80H ; } + 2154/ B13 : BD DB 0BDH + 2155/ B14 : 9D DB 9DH + 2156/ B15 : B1 DB 0B1H + 2157/ B16 : B5 DB 0B5H + 2158/ B17 : B9 DB 0B9H + 2159/ B18 : B4 DB 0B4H + 2160/ B19 : 9E DB 9EH + 2161/ B1A : B2 DB 0B2H + 2162/ B1B : B6 DB 0B6H + 2163/ B1C : BA DB 0BAH + 2164/ B1D : BE DB 0BEH + 2165/ B1E : 9F DB 9FH + 2166/ B1F : B3 DB 0B3H + 2167/ B20 : B7 DB 0B7H + 2168/ B21 : BB DB 0BBH + 2169/ B22 : ; 90 - 9F + 2170/ B22 : BF DB 0BFH ; _ + 2171/ B23 : A3 DB 0A3H + 2172/ B24 : 85 DB 85H + 2173/ B25 : A4 DB 0A4H ; ` + 2174/ B26 : A5 DB 0A5H ; ~ + 2175/ B27 : A6 DB 0A6H + 2176/ B28 : 94 DB 94H + 2177/ B29 : 87 DB 87H + 2178/ B2A : 88 DB 88H + 2179/ B2B : 9C DB 9CH + 2180/ B2C : 82 DB 82H + 2181/ B2D : 98 DB 98H + 2182/ B2E : 84 DB 84H + 2183/ B2F : 92 DB 92H + 2184/ B30 : 90 DB 90H + 2185/ B31 : 83 DB 83H + 2186/ B32 : ; A0 - AF + 2187/ B32 : 91 DB 91H + 2188/ B33 : 81 DB 81H + 2189/ B34 : 9A DB 9AH + 2190/ B35 : 97 DB 97H + 2191/ B36 : 93 DB 93H + 2192/ B37 : 95 DB 95H + 2193/ B38 : 89 DB 89H + 2194/ B39 : A1 DB 0A1H + 2195/ B3A : AF DB 0AFH + 2196/ B3B : 8B DB 8BH + 2197/ B3C : 86 DB 86H + 2198/ B3D : 96 DB 96H + 2199/ B3E : A2 DB 0A2H + 2200/ B3F : AB DB 0ABH + 2201/ B40 : AA DB 0AAH + 2202/ B41 : 8A DB 8AH + 2203/ B42 : ; B0 - BF + 2204/ B42 : 8E DB 8EH + 2205/ B43 : B0 DB 0B0H + 2206/ B44 : AD DB 0ADH + 2207/ B45 : 8D DB 8DH + 2208/ B46 : A7 DB 0A7H + 2209/ B47 : A8 DB 0A8H + 2210/ B48 : A9 DB 0A9H + 2211/ B49 : 8F DB 8FH + AS V1.40r8 - Quelle MZ700.ASM - Seite 38 - 9.6.1998 9:06:30 + + + 2212/ B4A : 8C DB 8CH + 2213/ B4B : AE DB 0AEH + 2214/ B4C : AC DB 0ACH + 2215/ B4D : 9B DB 9BH + 2216/ B4E : A0 DB 0A0H + 2217/ B4F : 99 DB 99H + 2218/ B50 : BC DB 0BCH ; { + 2219/ B51 : B8 DB 0B8H + 2220/ B52 : ; C0 - CF + 2221/ B52 : 40 DB 40H + 2222/ B53 : 3B DB 3BH + 2223/ B54 : 3A DB 3AH + 2224/ B55 : 70 DB 70H + 2225/ B56 : 3C DB 3CH + 2226/ B57 : 71 DB 71H + 2227/ B58 : 5A DB 5AH + 2228/ B59 : 3D DB 3DH + 2229/ B5A : 43 DB 43H + 2230/ B5B : 56 DB 56H + 2231/ B5C : 3F DB 3FH + 2232/ B5D : 1E DB 1EH + 2233/ B5E : 4A DB 4AH + 2234/ B5F : 1C DB 1CH + 2235/ B60 : 5D DB 5DH + 2236/ B61 : 3E DB 3EH + 2237/ B62 : ; D0 - DF + 2238/ B62 : 5C DB 5CH + 2239/ B63 : 1F DB 1FH + 2240/ B64 : 5F DB 5FH + 2241/ B65 : 5E DB 5EH + 2242/ B66 : 37 DB 37H + 2243/ B67 : 7B DB 7BH + 2244/ B68 : 7F DB 7FH + 2245/ B69 : 36 DB 36H + 2246/ B6A : 7A DB 7AH + 2247/ B6B : 7E DB 7EH + 2248/ B6C : 33 DB 33H + 2249/ B6D : 4B DB 4BH + 2250/ B6E : 4C DB 4CH + 2251/ B6F : 1D DB 1DH + 2252/ B70 : 6C DB 6CH + 2253/ B71 : 5B DB 5BH + 2254/ B72 : ; E0 - EF + 2255/ B72 : 78 DB 78H + 2256/ B73 : 41 DB 41H + 2257/ B74 : 35 DB 35H + 2258/ B75 : 34 DB 34H + 2259/ B76 : 74 DB 74H + 2260/ B77 : 30 DB 30H + 2261/ B78 : 38 DB 38H + 2262/ B79 : 75 DB 75H + 2263/ B7A : 39 DB 39H + 2264/ B7B : 4D DB 4DH + 2265/ B7C : 6F DB 6FH + 2266/ B7D : 6E DB 6EH + 2267/ B7E : 32 DB 32H + 2268/ B7F : 77 DB 77H + 2269/ B80 : 76 DB 76H + 2270/ B81 : 72 DB 72H + 2271/ B82 : ; F0 - FF + AS V1.40r8 - Quelle MZ700.ASM - Seite 39 - 9.6.1998 9:06:30 + + + 2272/ B82 : 73 DB 73H + 2273/ B83 : 47 DB 47H + 2274/ B84 : 7C DB 7CH + 2275/ B85 : 53 DB 53H + 2276/ B86 : 31 DB 31H + 2277/ B87 : 4E DB 4EH + 2278/ B88 : 6D DB 6DH + 2279/ B89 : 48 DB 48H + 2280/ B8A : 46 DB 46H + 2281/ B8B : 7D DB 7DH + 2282/ B8C : 44 DB 44H + 2283/ B8D : 1B DB 1BH + 2284/ B8E : 58 DB 58H + 2285/ B8F : 79 DB 79H + 2286/ B90 : 42 DB 42H + 2287/ B91 : 60 DB 60H + 2288/ B92 : + 2289/ B92 : ; FLASHING DATA SAVE + 2290/ B92 : + 2291/ B92 : 21 92 11 QSAVE: LD HL,FLSDT + 2292/ B95 : 36 EF LD (HL),0EFH ; NORMAL CURSOR + 2293/ B97 : 3A 70 11 LD A,(KANAF) + 2294/ B9A : 0F RRCA + 2295/ B9B : 38 03 JR C,L0BA0 ; GRAPH MODE + 2296/ B9D : 0F RRCA + 2297/ B9E : 30 02 JR NC,SV0 ; NORMAL MODE + 2298/ BA0 : 36 FF L0BA0: LD (HL),0FFH ; GRAPH CURSOR + 2299/ BA2 : 7E SV0: LD A,(HL) + 2300/ BA3 : F5 PUSH AF + 2301/ BA4 : CD B1 0F CALL QPONT ; FLASHING POSITION + 2302/ BA7 : 7E LD A,(HL) + 2303/ BA8 : 32 8E 11 LD (FLASH),A + 2304/ BAB : F1 POP AF + 2305/ BAC : 77 LD (HL),A + 2306/ BAD : AF XOR A + 2307/ BAE : 21 00 E0 LD HL,KEYPA + 2308/ BB1 : 77 L0BB1: LD (HL),A + 2309/ BB2 : 2F CPL ; OH NO! UNUSED BITS WERE TOUCHED TOO!!! + 2310/ BB3 : 77 LD (HL),A + 2311/ BB4 : C9 RET + 2312/ BB5 : + 2313/ BB5 : 36 43 SV1: LD (HL),43H ; KANA CURSOR + 2314/ BB7 : 18 E9 JR SV0 + 2315/ BB9 : + 2316/ BB9 : ; ASCII TO DISPLAY CODE CONVERT + 2317/ BB9 : ; IN ACC:ASCII + 2318/ BB9 : ; EXIT ACC:DISPLAY CODE + 2319/ BB9 : + 2320/ BB9 : C5 QADCN: PUSH BC + 2321/ BBA : E5 PUSH HL + 2322/ BBB : 21 92 0A LD HL,ATBL + 2323/ BBE : 4F LD C,A + 2324/ BBF : 06 00 LD B,0 + 2325/ BC1 : 09 ADD HL,BC + 2326/ BC2 : 7E LD A,(HL) + 2327/ BC3 : 18 1B JR DACN3 + 2328/ BC5 : + 2329/ BC5 : 56 31 2E 30 41 0D VRNS: DB "V1.0A\r" ; VERSION MANAGEMENT + 2330/ BCB : 00 NOP + 2331/ BCC : 00 NOP + AS V1.40r8 - Quelle MZ700.ASM - Seite 40 - 9.6.1998 9:06:30 + + + 2332/ BCD : 00 NOP + 2333/ BCE : + 2334/ BCE : ; DISPLAY CODE TO ASCII CONVERSION + 2335/ BCE : ; IN ACC=DISPLAY CODE + 2336/ BCE : ; EXIT ACC=ASCII + 2337/ BCE : + 2338/ BCE : C5 QDACN: PUSH BC + 2339/ BCF : E5 PUSH HL + 2340/ BD0 : D5 PUSH DE + 2341/ BD1 : 21 92 0A LD HL,ATBL + 2342/ BD4 : 54 LD D,H + 2343/ BD5 : 5D LD E,L + 2344/ BD6 : 01 00 01 LD BC,0100H + 2345/ BD9 : ED B1 CPIR + 2346/ BDB : 28 06 JR Z,DACN1 + 2347/ BDD : 3E F0 LD A,0F0H + 2348/ BDF : D1 DACN2: POP DE + 2349/ BE0 : E1 DACN3: POP HL + 2350/ BE1 : C1 POP BC + 2351/ BE2 : C9 RET + 2352/ BE3 : + 2353/ BE3 : B7 DACN1: OR A + 2354/ BE4 : 2B DEC HL + 2355/ BE5 : ED 52 SBC HL,DE + 2356/ BE7 : 7D LD A,L + 2357/ BE8 : 18 F5 JR DACN2 + 2358/ BEA : + 2359/ BEA : ; + 2360/ BEA : ; + 2361/ BEA : ; KEY MATRIX TO DISPLAY CODE TABL + 2362/ BEA : ; + 2363/ BEA : KTBL: + 2364/ BEA : ;S0 00 - 07 + 2365/ BEA : BF DB 0BFH ; SPARE + 2366/ BEB : CA DB 0CAH ; GRAPH + 2367/ BEC : 58 DB 58H ; + 2368/ BED : C9 DB 0C9H ; ALPHA + 2369/ BEE : F0 DB 0F0H ; NO + 2370/ BEF : 2C DB 2CH ; ; + 2371/ BF0 : 4F DB 4FH ; : + 2372/ BF1 : CD DB 0CDH ; CR + 2373/ BF2 : ;S1 08 - 0F + 2374/ BF2 : 19 DB 19H ; Y + 2375/ BF3 : 1A DB 1AH ; Z + 2376/ BF4 : 55 DB 55H ; @ + 2377/ BF5 : 52 DB 52H ; [ + 2378/ BF6 : 54 DB 54H ; ] + 2379/ BF7 : F0 DB 0F0H ; NULL + 2380/ BF8 : F0 DB 0F0H ; NULL + 2381/ BF9 : F0 DB 0F0H ; NULL + 2382/ BFA : ;S2 10 - 17 + 2383/ BFA : 11 DB 11H ; Q + 2384/ BFB : 12 DB 12H ; R + 2385/ BFC : 13 DB 13H ; S + 2386/ BFD : 14 DB 14H ; T + 2387/ BFE : 15 DB 15H ; U + 2388/ BFF : 16 DB 16H ; V + 2389/ C00 : 17 DB 17H ; W + 2390/ C01 : 18 DB 18H ; X + 2391/ C02 : ;S3 18 - 1F + AS V1.40r8 - Quelle MZ700.ASM - Seite 41 - 9.6.1998 9:06:30 + + + 2392/ C02 : 09 DB 09H ; I + 2393/ C03 : 0A DB 0AH ; J + 2394/ C04 : 0B DB 0BH ; K + 2395/ C05 : 0C DB 0CH ; L + 2396/ C06 : 0D DB 0DH ; M + 2397/ C07 : 0E DB 0EH ; N + 2398/ C08 : 0F DB 0FH ; O + 2399/ C09 : 10 DB 10H ; P + 2400/ C0A : ;S4 20 - 27 + 2401/ C0A : 01 DB 01H ; A + 2402/ C0B : 02 DB 02H ; B + 2403/ C0C : 03 DB 03H ; C + 2404/ C0D : 04 DB 04H ; D + 2405/ C0E : 05 DB 05H ; E + 2406/ C0F : 06 DB 06H ; F + 2407/ C10 : 07 DB 07H ; G + 2408/ C11 : 08 DB 08H ; H + 2409/ C12 : ;S5 28 - 2F + 2410/ C12 : 21 DB 21H ; 1 + 2411/ C13 : 22 DB 22H ; 2 + 2412/ C14 : 23 DB 23H ; 3 + 2413/ C15 : 24 DB 24H ; 4 + 2414/ C16 : 25 DB 25H ; 5 + 2415/ C17 : 26 DB 26H ; 6 + 2416/ C18 : 27 DB 27H ; 7 + 2417/ C19 : 28 DB 28H ; 8 + 2418/ C1A : ;S6 30 - 37 + 2419/ C1A : 59 DB 59H ; \ + 2420/ C1B : 50 DB 50H ; + 2421/ C1C : 2A DB 2AH ; - + 2422/ C1D : 00 DB 00H ; SPACE + 2423/ C1E : 20 DB 20H ; 0 + 2424/ C1F : 29 DB 29H ; 9 + 2425/ C20 : 2F DB 2FH ; , + 2426/ C21 : 2E DB 2EH ; . + 2427/ C22 : ;S7 38 - 3F + 2428/ C22 : C8 DB 0C8H ; INST. + 2429/ C23 : C7 DB 0C7H ; DEL. + 2430/ C24 : C2 DB 0C2H ; CURSOR UP + 2431/ C25 : C1 DB 0C1H ; CURSOR DOWN + 2432/ C26 : C3 DB 0C3H ; CURSOR RIGHT + 2433/ C27 : C4 DB 0C4H ; CURSOR LEFT + 2434/ C28 : 49 DB 49H ; ? + 2435/ C29 : 2D DB 2DH ; / + 2436/ C2A : ; + 2437/ C2A : ; + 2438/ C2A : ; KTBL SHIFT ON + 2439/ C2A : ; + 2440/ C2A : KTBLS: + 2441/ C2A : ;S0 00 - 07 + 2442/ C2A : BF DB 0BFH ; SPARE + 2443/ C2B : CA DB 0CAH ; GRAPH + 2444/ C2C : 1B DB 1BH ; POND + 2445/ C2D : C9 DB 0C9H ; ALPHA + 2446/ C2E : F0 DB 0F0H ; NO + 2447/ C2F : 6A DB 6AH ; + + 2448/ C30 : 6B DB 6BH ; * + 2449/ C31 : CD DB 0CDH ; CR + 2450/ C32 : ;S1 08 - 0F + 2451/ C32 : 99 DB 99H ; y + AS V1.40r8 - Quelle MZ700.ASM - Seite 42 - 9.6.1998 9:06:30 + + + 2452/ C33 : 9A DB 9AH ; z + 2453/ C34 : A4 DB 0A4H ; ` + 2454/ C35 : BC DB 0BCH ; { + 2455/ C36 : 40 DB 40H ; } + 2456/ C37 : F0 DB 0F0H ; NULL + 2457/ C38 : F0 DB 0F0H ; NULL + 2458/ C39 : F0 DB 0F0H ; NULL + 2459/ C3A : ;S2 10 - 17 + 2460/ C3A : 91 DB 91H ; q + 2461/ C3B : 92 DB 92H ; r + 2462/ C3C : 93 DB 93H ; s + 2463/ C3D : 94 DB 94H ; t + 2464/ C3E : 95 DB 95H ; u + 2465/ C3F : 96 DB 96H ; v + 2466/ C40 : 97 DB 97H ; w + 2467/ C41 : 98 DB 98H ; x + 2468/ C42 : ;S3 18 - 1F + 2469/ C42 : 89 DB 89H ; i + 2470/ C43 : 8A DB 8AH ; j + 2471/ C44 : 8B DB 8BH ; k + 2472/ C45 : 8C DB 8CH ; l + 2473/ C46 : 8D DB 8DH ; m + 2474/ C47 : 8E DB 8EH ; n + 2475/ C48 : 8F DB 8FH ; o + 2476/ C49 : 90 DB 90H ; p + 2477/ C4A : ;S4 20 - 27 + 2478/ C4A : 81 DB 81H ; a + 2479/ C4B : 82 DB 82H ; b + 2480/ C4C : 83 DB 83H ; c + 2481/ C4D : 84 DB 84H ; d + 2482/ C4E : 85 DB 85H ; e + 2483/ C4F : 86 DB 86H ; f + 2484/ C50 : 87 DB 87H ; g + 2485/ C51 : 88 DB 88H ; h + 2486/ C52 : ;S5 28 - 2F + 2487/ C52 : 61 DB 61H ; ! + 2488/ C53 : 62 DB 62H ; " + 2489/ C54 : 63 DB 63H ; # + 2490/ C55 : 64 DB 64H ; $ + 2491/ C56 : 65 DB 65H ; % + 2492/ C57 : 66 DB 66H ; & + 2493/ C58 : 67 DB 67H ; ' + 2494/ C59 : 68 DB 68H ; ( + 2495/ C5A : ;S6 30 - 37 + 2496/ C5A : 80 DB 80H ; \ + 2497/ C5B : A5 DB 0A5H ; POND MARK + 2498/ C5C : 2B DB 2BH ; YEN + 2499/ C5D : 00 DB 00H ; SPACE + 2500/ C5E : 60 DB 60H ; ¶ + 2501/ C5F : 69 DB 69H ; ) + 2502/ C60 : 51 DB 51H ; < + 2503/ C61 : 57 DB 57H ; > + 2504/ C62 : ;S7 38 - 3F + 2505/ C62 : C6 DB 0C6H ; CLR + 2506/ C63 : C5 DB 0C5H ; HOME + 2507/ C64 : C2 DB 0C2H ; CURSOR UP + 2508/ C65 : C1 DB 0C1H ; CURSOR DOWN + 2509/ C66 : C3 DB 0C3H ; CURSOR RIGHT + 2510/ C67 : C4 DB 0C4H ; CURSOR LEFT + 2511/ C68 : 5A DB 5AH ; + AS V1.40r8 - Quelle MZ700.ASM - Seite 43 - 9.6.1998 9:06:30 + + + 2512/ C69 : 45 DB 45H ; + 2513/ C6A : ; + 2514/ C6A : ; + 2515/ C6A : ; GRAPHIC + 2516/ C6A : ; + 2517/ C6A : KTBLGS: + 2518/ C6A : ;S0 00 - 07 + 2519/ C6A : BF DB 0BFH ; SPARE + 2520/ C6B : F0 DB 0F0H ; GRAPH BUT NULL + 2521/ C6C : E5 DB 0E5H ; # + 2522/ C6D : C9 DB 0C9H ; ALPHA + 2523/ C6E : F0 DB 0F0H ; NO + 2524/ C6F : 42 DB 42H ; #; + 2525/ C70 : B6 DB 0B6H ; #: + 2526/ C71 : CD DB 0CDH ; CR + 2527/ C72 : ;S1 08 - 0F + 2528/ C72 : 75 DB 75H ; #Y + 2529/ C73 : 76 DB 76H ; #Z + 2530/ C74 : B2 DB 0B2H ; #@ + 2531/ C75 : D8 DB 0D8H ; #[ + 2532/ C76 : 4E DB 4EH ; #] + 2533/ C77 : F0 DB 0F0H ; #NULL + 2534/ C78 : F0 DB 0F0H ; #NULL + 2535/ C79 : F0 DB 0F0H ; #NULL + 2536/ C7A : ;S2 10 - 17 + 2537/ C7A : 3C DB 3CH ; #Q + 2538/ C7B : 30 DB 30H ; #R + 2539/ C7C : 44 DB 44H ; #S + 2540/ C7D : 71 DB 71H ; #T + 2541/ C7E : 79 DB 79H ; #U + 2542/ C7F : DA DB 0DAH ; #V + 2543/ C80 : 38 DB 38H ; #W + 2544/ C81 : 6D DB 6DH ; #X + 2545/ C82 : ;S3 18 - 1F + 2546/ C82 : 7D DB 7DH ; #I + 2547/ C83 : 5C DB 5CH ; #J + 2548/ C84 : 5B DB 5BH ; #K + 2549/ C85 : B4 DB 0B4H ; #L + 2550/ C86 : 1C DB 1CH ; #M + 2551/ C87 : 32 DB 32H ; #N + 2552/ C88 : B0 DB 0B0H ; #O + 2553/ C89 : D6 DB 0D6H ; #P + 2554/ C8A : ;S4 20 - 27 + 2555/ C8A : 53 DB 53H ; #A + 2556/ C8B : 6F DB 6FH ; #B + 2557/ C8C : DE DB 0DEH ; #C + 2558/ C8D : 47 DB 47H ; #D + 2559/ C8E : 34 DB 34H ; #E + 2560/ C8F : 4A DB 4AH ; #F + 2561/ C90 : 4B DB 4BH ; #G + 2562/ C91 : 72 DB 72H ; #H + 2563/ C92 : ;S5 28 - 2F + 2564/ C92 : 37 DB 37H ; #1 + 2565/ C93 : 3E DB 3EH ; #2 + 2566/ C94 : 7F DB 7FH ; #3 + 2567/ C95 : 7B DB 7BH ; #4 + 2568/ C96 : 3A DB 3AH ; #5 + 2569/ C97 : 5E DB 5EH ; #6 + 2570/ C98 : 1F DB 1FH ; #7 + 2571/ C99 : BD DB 0BDH ; #8 + AS V1.40r8 - Quelle MZ700.ASM - Seite 44 - 9.6.1998 9:06:30 + + + 2572/ C9A : ;S6 30 - 37 + 2573/ C9A : D4 DB 0D4H ; #YEN + 2574/ C9B : 9E DB 9EH ; #+ + 2575/ C9C : D2 DB 0D2H ; #- + 2576/ C9D : 00 DB 00H ; SPACE + 2577/ C9E : 9C DB 9CH ; #0 + 2578/ C9F : A1 DB 0A1H ; #9 + 2579/ CA0 : CA DB 0CAH ; #, + 2580/ CA1 : B8 DB 0B8H ; #. + 2581/ CA2 : ;S7 38 - 3F + 2582/ CA2 : C8 DB 0C8H ; INST + 2583/ CA3 : C7 DB 0C7H ; DEL. + 2584/ CA4 : C2 DB 0C2H ; CURSOR UP + 2585/ CA5 : C1 DB 0C1H ; CURSOR DOWN + 2586/ CA6 : C3 DB 0C3H ; CURSOR RIGHT + 2587/ CA7 : C4 DB 0C4H ; CURSOR LEFT + 2588/ CA8 : BA DB 0BAH ; #? + 2589/ CA9 : DB DB 0DBH ; #/ + 2590/ CAA : ; + 2591/ CAA : ; + 2592/ CAA : ; CONTROL CODE + 2593/ CAA : ; + 2594/ CAA : KTBLC: + 2595/ CAA : ;S0 00 - 07 + 2596/ CAA : F0 DB 0F0H + 2597/ CAB : F0 DB 0F0H + 2598/ CAC : F0 DB 0F0H ; ^ + 2599/ CAD : F0 DB 0F0H + 2600/ CAE : F0 DB 0F0H + 2601/ CAF : F0 DB 0F0H + 2602/ CB0 : F0 DB 0F0H + 2603/ CB1 : F0 DB 0F0H + 2604/ CB2 : ;S1 08 - 0F + 2605/ CB2 : F0 DB 0F0H ; ^Y E3 + 2606/ CB3 : 5A DB 5AH ; ^Z E4 (CHECKER) + 2607/ CB4 : F0 DB 0F0H ; ^@ + 2608/ CB5 : F0 DB 0F0H ; ^[ EB/E5 + 2609/ CB6 : F0 DB 0F0H ; ^] EA/E7 + 2610/ CB7 : F0 DB 0F0H ; #NULL + 2611/ CB8 : F0 DB 0F0H ; #NULL + 2612/ CB9 : F0 DB 0F0H ; #NULL + 2613/ CBA : ;S2 10 - 17 + 2614/ CBA : C1 DB 0C1H ; ^Q + 2615/ CBB : C2 DB 0C2H ; ^R + 2616/ CBC : C3 DB 0C3H ; ^S + 2617/ CBD : C4 DB 0C4H ; ^T + 2618/ CBE : C5 DB 0C5H ; ^U + 2619/ CBF : C6 DB 0C6H ; ^V + 2620/ CC0 : F0 DB 0F0H ; ^W E1 + 2621/ CC1 : F0 DB 0F0H ; ^X E2 + 2622/ CC2 : ;S3 18 - 1F + 2623/ CC2 : F0 DB 0F0H ; ^I F9 + 2624/ CC3 : F0 DB 0F0H ; ^J FA + 2625/ CC4 : F0 DB 0F0H ; ^K FB + 2626/ CC5 : F0 DB 0F0H ; ^L FC + 2627/ CC6 : F0 DB 0F0H ; ^M CD + 2628/ CC7 : F0 DB 0F0H ; ^N FE + 2629/ CC8 : F0 DB 0F0H ; ^O FF + 2630/ CC9 : F0 DB 0F0H ; ^P E0 + 2631/ CCA : ;S4 20 - 27 + AS V1.40r8 - Quelle MZ700.ASM - Seite 45 - 9.6.1998 9:06:30 + + + 2632/ CCA : F0 DB 0F0H ; ^A F1 + 2633/ CCB : F0 DB 0F0H ; ^B F2 + 2634/ CCC : F0 DB 0F0H ; ^C F3 + 2635/ CCD : F0 DB 0F0H ; ^D F4 + 2636/ CCE : F0 DB 0F0H ; ^E F5 + 2637/ CCF : F0 DB 0F0H ; ^F F6 + 2638/ CD0 : F0 DB 0F0H ; ^G F7 + 2639/ CD1 : F0 DB 0F0H ; ^H F8 + 2640/ CD2 : ;S5 28 - 2F + 2641/ CD2 : F0 DB 0F0H + 2642/ CD3 : F0 DB 0F0H + 2643/ CD4 : F0 DB 0F0H + 2644/ CD5 : F0 DB 0F0H + 2645/ CD6 : F0 DB 0F0H + 2646/ CD7 : F0 DB 0F0H + 2647/ CD8 : F0 DB 0F0H + 2648/ CD9 : F0 DB 0F0H + 2649/ CDA : ;S6 30 - 37 (ERROR? 7 VALUES ONLY!!) + 2650/ CDA : F0 DB 0F0H ; ^YEN E6 + 2651/ CDB : F0 DB 0F0H ; ^ EF + 2652/ CDC : F0 DB 0F0H + 2653/ CDD : F0 DB 0F0H + 2654/ CDE : F0 DB 0F0H + 2655/ CDF : F0 DB 0F0H ; ^, + 2656/ CE0 : F0 DB 0F0H + 2657/ CE1 : ;S7 38 - 3F + 2658/ CE1 : F0 DB 0F0H + 2659/ CE2 : F0 DB 0F0H + 2660/ CE3 : F0 DB 0F0H + 2661/ CE4 : F0 DB 0F0H + 2662/ CE5 : F0 DB 0F0H + 2663/ CE6 : F0 DB 0F0H + 2664/ CE7 : F0 DB 0F0H + 2665/ CE8 : F0 DB 0F0H ; ^/ EE + 2666/ CE9 : ; + 2667/ CE9 : ; + 2668/ CE9 : ; KANA + 2669/ CE9 : ; + 2670/ CE9 : KTBLG: + 2671/ CE9 : ;S0 00 - 07 + 2672/ CE9 : BF DB 0BFH ; SPARE + 2673/ CEA : F0 DB 0F0H ; GRAPH BUT NULL + 2674/ CEB : CF DB 0CFH ; NIKO WH. + 2675/ CEC : C9 DB 0C9H ; ALPHA + 2676/ CED : F0 DB 0F0H ; NO + 2677/ CEE : B5 DB 0B5H ; MO + 2678/ CEF : 4D DB 4DH ; DAKU TEN + 2679/ CF0 : CD DB 0CDH ; CR + 2680/ CF1 : ;S1 08 - 0F + 2681/ CF1 : 35 DB 35H ; HA + 2682/ CF2 : 77 DB 77H ; TA + 2683/ CF3 : D7 DB 0D7H ; WA + 2684/ CF4 : B3 DB 0B3H ; YO + 2685/ CF5 : B7 DB 0B7H ; HANDAKU + 2686/ CF6 : F0 DB 0F0H + 2687/ CF7 : F0 DB 0F0H + 2688/ CF8 : F0 DB 0F0H + 2689/ CF9 : ;S2 10 - 17 + 2690/ CF9 : 7C DB 7CH ; KA + 2691/ CFA : 70 DB 70H ; KE + AS V1.40r8 - Quelle MZ700.ASM - Seite 46 - 9.6.1998 9:06:30 + + + 2692/ CFB : 41 DB 41H ; SHI + 2693/ CFC : 31 DB 31H ; KO + 2694/ CFD : 39 DB 39H ; HI + 2695/ CFE : A6 DB 0A6H ; TE + 2696/ CFF : 78 DB 78H ; KI + 2697/ D00 : DD DB 0DDH ; CHI + 2698/ D01 : ;S3 18 - 1F + 2699/ D01 : 3D DB 3DH ; FU + 2700/ D02 : 5D DB 5DH ; MI + 2701/ D03 : 6C DB 6CH ; MU + 2702/ D04 : 56 DB 56H ; ME + 2703/ D05 : 1D DB 1DH ; RHI + 2704/ D06 : 33 DB 33H ; RA + 2705/ D07 : D5 DB 0D5H ; HE + 2706/ D08 : B1 DB 0B1H ; HO + 2707/ D09 : ;S4 20 - 27 + 2708/ D09 : 46 DB 46H ; SA + 2709/ D0A : 6E DB 6EH ; TO + 2710/ D0B : D9 DB 0D9H ; THU + 2711/ D0C : 48 DB 48H ; SU + 2712/ D0D : 74 DB 74H ; KU + 2713/ D0E : 43 DB 43H ; SE + 2714/ D0F : 4C DB 4CH ; SO + 2715/ D10 : 73 DB 73H ; MA + 2716/ D11 : ;S5 28 - 2F + 2717/ D11 : 3F DB 3FH ; A + 2718/ D12 : 36 DB 36H ; I + 2719/ D13 : 7E DB 7EH ; U + 2720/ D14 : 3B DB 3BH ; E + 2721/ D15 : 7A DB 7AH ; O + 2722/ D16 : 1E DB 1EH ; NA + 2723/ D17 : 5F DB 5FH ; NI + 2724/ D18 : A2 DB 0A2H ; NU + 2725/ D19 : ;S6 30 - 37 + 2726/ D19 : D3 DB 0D3H ; YO + 2727/ D1A : 9F DB 9FH ; YU + 2728/ D1B : D1 DB 0D1H ; YA + 2729/ D1C : 00 DB 00H ; SPACE + 2730/ D1D : 9D DB 9DH ; NO + 2731/ D1E : A3 DB 0A3H ; NE + 2732/ D1F : D0 DB 0D0H ; RU + 2733/ D20 : B9 DB 0B9H ; RE + 2734/ D21 : ;S7 38 - 3F + 2735/ D21 : C6 DB 0C6H ; ?CLR + 2736/ D22 : C5 DB 0C5H ; ?HOME + 2737/ D23 : C2 DB 0C2H ; ?CURSOR UP + 2738/ D24 : C1 DB 0C1H ; ?CURSOR DOWN + 2739/ D25 : C3 DB 0C3H ; ?CURSOR RIGHT + 2740/ D26 : C4 DB 0C4H ; ?CURSOR LEFT + 2741/ D27 : BB DB 0BBH ; DASH + 2742/ D28 : BE DB 0BEH ; RO + 2743/ D29 : + 2744/ D29 : ; MEMORY DUMP COMMAND "D" + 2745/ D29 : + 2746/ D29 : CD 3D 01 DUMP: CALL HEXIY ; START ADDRESS + 2747/ D2C : CD A6 02 CALL P4DE + 2748/ D2F : E5 PUSH HL + 2749/ D30 : CD 10 04 CALL HLHEX ; END ADDRESS + 2750/ D33 : D1 POP DE + 2751/ D34 : 38 52 JR C,DUM1 ; DATA ERROR THEN + AS V1.40r8 - Quelle MZ700.ASM - Seite 47 - 9.6.1998 9:06:30 + + + 2752/ D36 : EB L0D36: EX DE,HL + 2753/ D37 : 06 08 DUM3: LD B,08H ; DISPLAY 8 BYTES + 2754/ D39 : 0E 17 LD C,23 ; CHANGE PRINT BIAS + 2755/ D3B : CD FA 05 CALL NLPHL ; NEWLINE PRINT + 2756/ D3E : CD B1 03 DUM2: CALL SPHEX ; SPACE PRINT + ACC PRINT + 2757/ D41 : 23 INC HL + 2758/ D42 : F5 PUSH AF + 2759/ D43 : 3A 71 11 LD A,(DSPXY) ; DISPLAY POINT + 2760/ D46 : 81 ADD A,C + 2761/ D47 : 32 71 11 LD (DSPXY),A ; X AXIS=X+CREG + 2762/ D4A : F1 POP AF + 2763/ D4B : FE 20 CP 20H + 2764/ D4D : 30 02 JR NC,L0D51 + 2765/ D4F : 3E 2E LD A,2EH ; "." + 2766/ D51 : CD B9 0B L0D51: CALL QADCN ; ASCII TO DISPLAY CODE + 2767/ D54 : CD 6C 09 CALL PRNT3 + 2768/ D57 : 3A 71 11 LD A,(DSPXY) + 2769/ D5A : 0C INC C + 2770/ D5B : 91 SUB C ; ASCII DISPLAY POSITION + 2771/ D5C : 32 71 11 LD (DSPXY),A + 2772/ D5F : 0D DEC C + 2773/ D60 : 0D DEC C + 2774/ D61 : 0D DEC C + 2775/ D62 : E5 PUSH HL + 2776/ D63 : ED 52 SBC HL,DE + 2777/ D65 : E1 POP HL + 2778/ D66 : 28 1D JR Z,L0D85 + 2779/ D68 : 3E F8 LD A,0F8H + 2780/ D6A : 32 00 E0 LD (KEYPA),A + 2781/ D6D : 00 NOP + 2782/ D6E : 3A 01 E0 LD A,(KEYPB) + 2783/ D71 : FE FE CP 0FEH ; SHIFT KEY ? + 2784/ D73 : 20 03 JR NZ,L0D78 + 2785/ D75 : CD A6 0D CALL QBLNK ; 64MSEC DELAY + 2786/ D78 : 10 C4 L0D78: DJNZ DUM2 + 2787/ D7A : CD CA 08 L0D7A: CALL QKEY ; STOP DISPLAY + 2788/ D7D : B7 OR A + 2789/ D7E : 28 FA JR Z,L0D7A ; SPACE KEY THEN STOP + 2790/ D80 : CD 32 0A CALL QBRK ; BREAK IN ? + 2791/ D83 : 20 B2 JR NZ,DUM3 + 2792/ D85 : C3 AD 00 L0D85: JP ST1 ; COMMAND IN ! + 2793/ D88 : + 2794/ D88 : 21 A0 00 DUM1: LD HL,160 ; 20*8 BYTES + 2795/ D8B : 19 ADD HL,DE + 2796/ D8C : 18 A8 JR L0D36 + 2797/ D8E : + 2798/ D8E : 00 NOP + 2799/ D8F : 00 NOP + 2800/ D90 : 00 NOP + 2801/ D91 : 00 NOP + 2802/ D92 : 00 NOP + 2803/ D93 : 00 NOP + 2804/ D94 : 00 NOP + 2805/ D95 : 00 NOP + 2806/ D96 : 00 NOP + 2807/ D97 : 00 NOP + 2808/ D98 : 00 NOP + 2809/ D99 : 00 NOP + 2810/ D9A : 00 NOP + 2811/ D9B : 00 NOP + AS V1.40r8 - Quelle MZ700.ASM - Seite 48 - 9.6.1998 9:06:30 + + + 2812/ D9C : 00 NOP + 2813/ D9D : 00 NOP + 2814/ D9E : 00 NOP + 2815/ D9F : 00 NOP + 2816/ DA0 : 00 NOP + 2817/ DA1 : 00 NOP + 2818/ DA2 : 00 NOP + 2819/ DA3 : 00 NOP + 2820/ DA4 : 00 NOP + 2821/ DA5 : 00 NOP + 2822/ DA6 : + 2823/ DA6 : ; V-BLANK CHECK + 2824/ DA6 : + 2825/ DA6 : F5 QBLNK: PUSH AF + 2826/ DA7 : 3A 02 E0 L0DA7: LD A,(KEYPC) ; V-BLANK + 2827/ DAA : 07 RLCA + 2828/ DAB : 30 FA JR NC,L0DA7 + 2829/ DAD : 3A 02 E0 L0DAD: LD A,(KEYPC) ; 64 + 2830/ DB0 : 07 RLCA ; + 2831/ DB1 : 38 FA JR C,L0DAD ; MSEC + 2832/ DB3 : F1 POP AF + 2833/ DB4 : C9 RET + 2834/ DB5 : ; DISPLAY ON POINTER + 2835/ DB5 : ; ACC=DISPLAY CODE + 2836/ DB5 : ; EXCEPT F0H + 2837/ DB5 : + 2838/ DB5 : F5 QDSP: PUSH AF + 2839/ DB6 : C5 PUSH BC + 2840/ DB7 : D5 PUSH DE + 2841/ DB8 : E5 PUSH HL + 2842/ DB9 : CD B1 0F DSP01: CALL QPONT ; DISPLAY POSITION + 2843/ DBC : 77 LD (HL),A + 2844/ DBD : 2A 71 11 LD HL,(DSPXY) + 2845/ DC0 : 7D LD A,L + 2846/ DC1 : FE 27 CP 39 + 2847/ DC3 : 20 0B JR NZ,DSP04 + 2848/ DC5 : CD F3 02 CALL PMANG + 2849/ DC8 : 38 06 JR C,DSP04 + 2850/ DCA : EB EX DE,HL + 2851/ DCB : 36 01 LD (HL),1 ; LOGICAL 1ST COLUMN + 2852/ DCD : 23 INC HL + 2853/ DCE : 36 00 LD (HL),0 ; LOGICAL 2ND COLUMN + 2854/ DD0 : 3E C3 DSP04: LD A,0C3H ; CURSL + 2855/ DD2 : 18 0C JR L0DE0 + 2856/ DD4 : + 2857/ DD4 : ; GRAPHIC STATUS CHECK + 2858/ DD4 : + 2859/ DD4 : 3A 70 11 GRSTAS: LD A,(KANAF) + 2860/ DD7 : FE 01 CP 01H + 2861/ DD9 : 3E CA LD A,0CAH + 2862/ DDB : C9 RET + 2863/ DDC : + 2864/ DDC : ; DISPLAY CONTROL + 2865/ DDC : ; ACC=CONTROL CODE + 2866/ DDC : + 2867/ DDC : F5 QDPCT: PUSH AF + 2868/ DDD : C5 PUSH BC + 2869/ DDE : D5 PUSH DE + 2870/ DDF : E5 PUSH HL + 2871/ DE0 : 47 L0DE0: LD B,A + AS V1.40r8 - Quelle MZ700.ASM - Seite 49 - 9.6.1998 9:06:30 + + + 2872/ DE1 : E6 F0 AND 0F0H + 2873/ DE3 : FE C0 CP 0C0H + 2874/ DE5 : 20 1B JR NZ,CURS5 + 2875/ DE7 : A8 XOR B + 2876/ DE8 : 07 RLCA + 2877/ DE9 : 4F LD C,A + 2878/ DEA : 06 00 LD B,0 + 2879/ DEC : 21 AA 0E LD HL,CTBL ; PAGE MODE1 + 2880/ DEF : 09 ADD HL,BC + 2881/ DF0 : 5E LD E,(HL) + 2882/ DF1 : 23 INC HL + 2883/ DF2 : 56 LD D,(HL) + 2884/ DF3 : 2A 71 11 LD HL,(DSPXY) + 2885/ DF6 : EB EX DE,HL + 2886/ DF7 : E9 JP (HL) + 2887/ DF8 : + 2888/ DF8 : EB CURSD: EX DE,HL ; LD HL,(DSPXY) + 2889/ DF9 : 7C LD A,H + 2890/ DFA : FE 18 CP 24 + 2891/ DFC : 28 25 JR Z,CURS4 + 2892/ DFE : 24 INC H + 2893/ DFF : CURS1: + 2894/ DFF : 22 71 11 CURS3: LD (DSPXY),HL + 2895/ E02 : C3 E5 0E CURS5: JP QRSTR + 2896/ E05 : + 2897/ E05 : EB CURSU: EX DE,HL ; LD HL,(DSPXY) + 2898/ E06 : 7C LD A,H + 2899/ E07 : B7 OR A + 2900/ E08 : 28 F8 JR Z,CURS5 + 2901/ E0A : 25 DEC H + 2902/ E0B : 18 F2 CURSU1: JR CURS3 + 2903/ E0D : + 2904/ E0D : EB CURSR: EX DE,HL ; LD HL,(DSPXY) + 2905/ E0E : 7D LD A,L + 2906/ E0F : FE 27 CP 39 + 2907/ E11 : 30 03 JR NC,CURS2 + 2908/ E13 : 2C INC L + 2909/ E14 : 18 E9 JR CURS3 + 2910/ E16 : + 2911/ E16 : 2E 00 CURS2: LD L,0 + 2912/ E18 : 24 INC H + 2913/ E19 : 7C LD A,H + 2914/ E1A : FE 19 CP 25 + 2915/ E1C : 38 E1 JR C,CURS1 + 2916/ E1E : 26 18 LD H,24 + 2917/ E20 : 22 71 11 LD (DSPXY),HL + 2918/ E23 : 18 48 CURS4: JR SCROL + 2919/ E25 : + 2920/ E25 : EB CURSL: EX DE,HL ; LD HL,(DSPXY) + 2921/ E26 : 7D LD A,L + 2922/ E27 : B7 OR A + 2923/ E28 : 28 03 JR Z,L0E2D + 2924/ E2A : 2D DEC L + 2925/ E2B : 18 D2 JR CURS3 + 2926/ E2D : + 2927/ E2D : 2E 27 L0E2D: LD L,39 + 2928/ E2F : 25 DEC H + 2929/ E30 : F2 0B 0E JP P,CURSU1 + 2930/ E33 : 26 00 LD H,0 + 2931/ E35 : 22 71 11 LD (DSPXY),HL + AS V1.40r8 - Quelle MZ700.ASM - Seite 50 - 9.6.1998 9:06:30 + + + 2932/ E38 : 18 C8 JR CURS5 + 2933/ E3A : + 2934/ E3A : 21 73 11 CLRS: LD HL,MANG + 2935/ E3D : 06 1B LD B,27 + 2936/ E3F : CD D8 0F CALL QCLER + 2937/ E42 : 21 00 D0 LD HL,0D000H ; SCRN TOP + 2938/ E45 : CD D4 09 CALL NCLR08 + 2939/ E48 : 3E 71 LD A,71H ; COLOR DATA + 2940/ E4A : CD D5 09 CALL NCLR8 ; D800H-DFFFH CLEAR + 2941/ E4D : 21 00 00 HOME: LD HL,0 ; DSPXY:0 X=0,Y=0 + 2942/ E50 : 18 AD JR CURS3 + 2943/ E52 : + 2944/ E52 : 00 NOP + 2945/ E53 : 00 NOP + 2946/ E54 : 00 NOP + 2947/ E55 : 00 NOP + 2948/ E56 : 00 NOP + 2949/ E57 : 00 NOP + 2950/ E58 : 00 NOP + 2951/ E59 : 00 NOP + 2952/ E5A : + 2953/ E5A : ; CR + 2954/ E5A : + 2955/ E5A : CD F3 02 CR: CALL PMANG + 2956/ E5D : 0F RRCA + 2957/ E5E : 30 B6 JR NC,CURS2 + 2958/ E60 : 2E 00 LD L,0 + 2959/ E62 : 24 INC H + 2960/ E63 : FE 18 CP 24 + 2961/ E65 : 28 03 JR Z,CR1 + 2962/ E67 : 24 INC H + 2963/ E68 : 18 95 JR CURS1 + 2964/ E6A : + 2965/ E6A : 22 71 11 CR1: LD (DSPXY),HL + 2966/ E6D : + 2967/ E6D : ; SCROLL + 2968/ E6D : + 2969/ E6D : 01 C0 03 SCROL: LD BC,03C0H + 2970/ E70 : 11 00 D0 LD DE,SCRN ; TOP OF $CRT ADDRESS + 2971/ E73 : 21 28 D0 LD HL,SCRN+40 ; COLUMN + 2972/ E76 : C5 PUSH BC ; 1000 STORE + 2973/ E77 : ED B0 LDIR + 2974/ E79 : C1 POP BC + 2975/ E7A : D5 PUSH DE + 2976/ E7B : 11 00 D8 LD DE,SCRN+800H ; COLOR RAM SCROLL + 2977/ E7E : 21 28 D8 LD HL,SCRN+828H ; SCROLL TOP + 40 + 2978/ E81 : ED B0 LDIR + 2979/ E83 : 06 28 LD B,40 ; ONE LINE + 2980/ E85 : EB EX DE,HL + 2981/ E86 : 3E 71 LD A,71H ; COLOR RAM INITIAL DATA + 2982/ E88 : CD DD 0F CALL QDINT + 2983/ E8B : E1 POP HL + 2984/ E8C : 06 28 LD B,40 + 2985/ E8E : CD D8 0F CALL QCLER ; LAST LINE CLEAR + 2986/ E91 : 01 1A 00 LD BC,26 ; ROW NUMBER+1 + 2987/ E94 : 11 73 11 LD DE,MANG ; LOGICAL MANAGEMENT + 2988/ E97 : 21 74 11 LD HL,MANG+1 + 2989/ E9A : ED B0 LDIR + 2990/ E9C : 36 00 LD (HL),0 + 2991/ E9E : 3A 73 11 LD A,(MANG) + AS V1.40r8 - Quelle MZ700.ASM - Seite 51 - 9.6.1998 9:06:30 + + + 2992/ EA1 : B7 OR A + 2993/ EA2 : 28 41 JR Z,QRSTR + 2994/ EA4 : 21 72 11 LD HL,DSPXY+1 + 2995/ EA7 : 35 DEC (HL) + 2996/ EA8 : 18 C3 JR SCROL + 2997/ EAA : + 2998/ EAA : ; CONTROL CODE TABLE + 2999/ EAA : + 3000/ EAA : 6D 0E CTBL: DW SCROL ; SCROLLING 10H + 3001/ EAC : F8 0D DW CURSD ; CURSOR DOWN 11H + 3002/ EAE : 05 0E DW CURSU ; CURSOR UP 12H + 3003/ EB0 : 0D 0E DW CURSR ; CURSOR RIGHT 13H + 3004/ EB2 : 25 0E DW CURSL ; CURSOR LEFT 14H + 3005/ EB4 : 4D 0E DW HOME ; 15H + 3006/ EB6 : 3A 0E DW CLRS ; 16H + 3007/ EB8 : F8 0E DW DEL ; 17H + 3008/ EBA : 38 0F DW INST ; 18H + 3009/ EBC : E1 0E DW ALPHA ; 19H + 3010/ EBE : EE 0E DW KANA ; GRAPHIC 1AH + 3011/ EC0 : E5 0E DW QRSTR ; 1BH + 3012/ EC2 : E5 0E DW QRSTR ; 1CH + 3013/ EC4 : 5A 0E DW CR ; 1DH + 3014/ EC6 : E5 0E DW QRSTR ; 1EH + 3015/ EC8 : E5 0E DW QRSTR ; 1FH + 3016/ ECA : + 3017/ ECA : ; INST BYPASS + 3018/ ECA : + 3019/ ECA : CB DC INST2: SET 3,H ; COLOR RAM + 3020/ ECC : 7E LD A,(HL) ; FROM + 3021/ ECD : 23 INC HL + 3022/ ECE : 77 LD (HL),A ; TO + 3023/ ECF : 2B DEC HL ; ADDRESS ADJUST + 3024/ ED0 : CB 9C RES 3,H + 3025/ ED2 : ED A8 LDD ; CHANGE TRNS. + 3026/ ED4 : 79 LD A,C + 3027/ ED5 : B0 OR B ; BC=0 ? + 3028/ ED6 : 20 F2 JR NZ,INST2 + 3029/ ED8 : EB EX DE,HL + 3030/ ED9 : 36 00 LD (HL),0 + 3031/ EDB : CB DC SET 3,H ; COLOR RAM + 3032/ EDD : 36 71 LD (HL),71H + 3033/ EDF : 18 04 JR QRSTR + 3034/ EE1 : + 3035/ EE1 : AF ALPHA: XOR A + 3036/ EE2 : 32 70 11 ALPH1: LD (KANAF),A + 3037/ EE5 : + 3038/ EE5 : ; RESTORE + 3039/ EE5 : + 3040/ EE5 : E1 QRSTR: POP HL + 3041/ EE6 : D1 QRSTR1: POP DE + 3042/ EE7 : C1 POP BC + 3043/ EE8 : F1 POP AF + 3044/ EE9 : C9 RET + 3045/ EEA : + 3046/ EEA : 00 NOP + 3047/ EEB : 00 NOP + 3048/ EEC : 00 NOP + 3049/ EED : 00 NOP + 3050/ EEE : + 3051/ EEE : ; MONITOR WORK AREA + AS V1.40r8 - Quelle MZ700.ASM - Seite 52 - 9.6.1998 9:06:30 + + + 3052/ EEE : + 3053/ EEE : =D000H SCRN: EQU 0D000H + 3054/ EEE : =E003H KANST: EQU 0E003H ; KANA STATUS REPORT + 3055/ EEE : + 3056/ EEE : CD D4 0D KANA: CALL GRSTAS + 3057/ EF1 : CA B9 0D JP Z,DSP01 ; NOT GRAPH KEY THEN JUMP + 3058/ EF4 : 3E 01 LD A,01H + 3059/ EF6 : 18 EA JR ALPH1 + 3060/ EF8 : + 3061/ EF8 : EB DEL: EX DE,HL ; LD HL,(DSPXY) + 3062/ EF9 : 7C LD A,H ; HOME ? + 3063/ EFA : B5 OR L + 3064/ EFB : 28 E8 JR Z,QRSTR + 3065/ EFD : 7D LD A,L + 3066/ EFE : B7 OR A + 3067/ EFF : 20 0D JR NZ,DEL1 ; LEFT SIDE ? + 3068/ F01 : CD F3 02 CALL PMANG + 3069/ F04 : 38 08 JR C,DEL1 + 3070/ F06 : CD B1 0F CALL QPONT + 3071/ F09 : 2B DEC HL + 3072/ F0A : 36 00 LD (HL),0 + 3073/ F0C : 18 25 JR L0F33 ; JUMP CURSL + 3074/ F0E : + 3075/ F0E : CD F3 02 DEL1: CALL PMANG + 3076/ F11 : 0F RRCA + 3077/ F12 : 3E 28 LD A,40 + 3078/ F14 : 30 01 JR NC,L0F17 + 3079/ F16 : 07 RLCA ; ACC=80 + 3080/ F17 : 95 L0F17: SUB L + 3081/ F18 : 47 LD B,A ; TRNS. BYTE + 3082/ F19 : CD B1 0F CALL QPONT + 3083/ F1C : 7E DEL2: LD A,(HL) ; CHANGE FROM ADDRESS + 3084/ F1D : 2B DEC HL + 3085/ F1E : 77 LD (HL),A ; TO + 3086/ F1F : 23 INC HL + 3087/ F20 : CB DC SET 3,H ; COLOR RAM + 3088/ F22 : 7E LD A,(HL) + 3089/ F23 : 2B DEC HL + 3090/ F24 : 77 LD (HL),A + 3091/ F25 : CB 9C RES 3,H ; CHANGE + 3092/ F27 : 23 INC HL + 3093/ F28 : 23 INC HL ; NEXT + 3094/ F29 : 10 F1 DJNZ DEL2 + 3095/ F2B : 2B DEC HL ; ADDRESS ADJUST + 3096/ F2C : 36 00 LD (HL),0 + 3097/ F2E : CB DC SET 3,H + 3098/ F30 : 21 71 00 LD HL,71H ; BLUE + WHITE + 3099/ F33 : 3E C4 L0F33: LD A,0C4H ; JP CURSL + 3100/ F35 : C3 E0 0D JP L0DE0 + 3101/ F38 : + 3102/ F38 : CD F3 02 INST: CALL PMANG + 3103/ F3B : 0F RRCA + 3104/ F3C : 2E 27 LD L,39 + 3105/ F3E : 7D LD A,L + 3106/ F3F : 30 01 JR NC,L0F42 + 3107/ F41 : 24 INC H + 3108/ F42 : CD B4 0F L0F42: CALL QPNT1 + 3109/ F45 : E5 PUSH HL + 3110/ F46 : 2A 71 11 LD HL,(DSPXY) + 3111/ F49 : 30 02 JR NC,L0F4D + AS V1.40r8 - Quelle MZ700.ASM - Seite 53 - 9.6.1998 9:06:30 + + + 3112/ F4B : 3E 4F LD A,79 + 3113/ F4D : 95 L0F4D: SUB L + 3114/ F4E : 06 00 LD B,0 + 3115/ F50 : 4F LD C,A + 3116/ F51 : D1 POP DE + 3117/ F52 : 28 91 JR Z,QRSTR + 3118/ F54 : 1A LD A,(DE) + 3119/ F55 : B7 OR A + 3120/ F56 : 20 8D JR NZ,QRSTR + 3121/ F58 : 62 LD H,D ; HL<-DE + 3122/ F59 : 6B LD L,E + 3123/ F5A : 2B DEC HL + 3124/ F5B : C3 CA 0E JP INST2 ; JUMP NEXT (BYPASS) + 3125/ F5E : + 3126/ F5E : ; PROGRAM SAVE + 3127/ F5E : ; COMMAND "S" + 3128/ F5E : + 3129/ F5E : CD 3D 01 SAVE: CALL HEXIY ; START ADDRESS + 3130/ F61 : 22 04 11 LD (DTADR),HL ; DATA ADDRESS BUFFER + 3131/ F64 : 44 LD B,H + 3132/ F65 : 4D LD C,L + 3133/ F66 : CD A6 02 CALL P4DE + 3134/ F69 : CD 3D 01 CALL HEXIY ; END ADDRESS + 3135/ F6C : ED 42 SBC HL,BC ; BYTE SIZE + 3136/ F6E : 23 INC HL + 3137/ F6F : 22 02 11 LD (SIZE),HL ; BYTE SIZE BUFFER + 3138/ F72 : CD A6 02 CALL P4DE + 3139/ F75 : CD 3D 01 CALL HEXIY ; EXECUTE ADDRESS + 3140/ F78 : 22 06 11 LD (EXADR),HL ; BUFFER + 3141/ F7B : CD 09 00 CALL NL + 3142/ F7E : 11 8B 09 LD DE,MSGSV ; SAVED FILENAME + 3143/ F81 : DF RST 18H ; CALL MSGX + 3144/ F82 : CD 2F 01 CALL BGETL ; FILENAME INPUT + 3145/ F85 : CD A6 02 CALL P4DE + 3146/ F88 : CD A6 02 CALL P4DE + 3147/ F8B : 21 F1 10 LD HL,NAME ; NAME BUFFER + 3148/ F8E : 13 SAV1: INC DE + 3149/ F8F : 1A LD A,(DE) + 3150/ F90 : 77 LD (HL),A ; FILENAME TRANS. + 3151/ F91 : 23 INC HL + 3152/ F92 : FE 0D CP 0DH ; END CODE + 3153/ F94 : 20 F8 JR NZ,SAV1 + 3154/ F96 : 3E 01 LD A,01H ; ATTRIBUTE: OBJECT CODE + 3155/ F98 : 32 F0 10 LD (ATRB),A + 3156/ F9B : CD 36 04 CALL QWRI + 3157/ F9E : DA 07 01 JP C,QER ; WRITE ERROR + 3158/ FA1 : CD 75 04 CALL QWRD ; DATA + 3159/ FA4 : DA 07 01 JP C,QER + 3160/ FA7 : CD 09 00 CALL NL + 3161/ FAA : 11 42 09 LD DE,MSGOK ; OK MESSAGE + 3162/ FAD : DF RST 18H ; CALL MSGX + 3163/ FAE : C3 AD 00 JP ST1 + 3164/ FB1 : + 3165/ FB1 : ; COMPUTE POINT ADDRESS + 3166/ FB1 : ; HL=SCREEN COORDINATE + 3167/ FB1 : ; EXIT HL=POINT ADDRESS ON SCREEN + 3168/ FB1 : + 3169/ FB1 : 2A 71 11 QPONT: LD HL,(DSPXY) + 3170/ FB4 : F5 QPNT1: PUSH AF + 3171/ FB5 : C5 PUSH BC + AS V1.40r8 - Quelle MZ700.ASM - Seite 54 - 9.6.1998 9:06:30 + + + 3172/ FB6 : D5 PUSH DE + 3173/ FB7 : E5 PUSH HL + 3174/ FB8 : C1 POP BC + 3175/ FB9 : 11 28 00 LD DE,0028H ; 40 + 3176/ FBC : 21 D8 CF LD HL,SCRN-40 + 3177/ FBF : 19 QPNT2: ADD HL,DE + 3178/ FC0 : 05 DEC B + 3179/ FC1 : F2 BF 0F JP P,QPNT2 + 3180/ FC4 : 06 00 LD B,0 + 3181/ FC6 : 09 ADD HL,BC + 3182/ FC7 : D1 POP DE + 3183/ FC8 : C1 POP BC + 3184/ FC9 : F1 POP AF + 3185/ FCA : C9 RET + 3186/ FCB : + 3187/ FCB : ; VERIFYING COMMAND "V" + 3188/ FCB : + 3189/ FCB : CD 88 05 VRFY: CALL QVRFY + 3190/ FCE : DA 07 01 JP C,QER + 3191/ FD1 : 11 42 09 LD DE,MSGOK + 3192/ FD4 : DF RST 18H + 3193/ FD5 : C3 AD 00 JP ST1 + 3194/ FD8 : + 3195/ FD8 : ; CLER + 3196/ FD8 : ; B=SIZE + 3197/ FD8 : ; HL=LOW ADDRESS + 3198/ FD8 : + 3199/ FD8 : AF QCLER: XOR A + 3200/ FD9 : 18 02 JR QDINT + 3201/ FDB : + 3202/ FDB : 3E FF QCLRFF: LD A,0FFH + 3203/ FDD : 77 QDINT: LD (HL),A + 3204/ FDE : 23 INC HL + 3205/ FDF : 10 FC DJNZ QDINT + 3206/ FE1 : C9 RET + 3207/ FE2 : + 3208/ FE2 : ; GAP CHECK + 3209/ FE2 : + 3210/ FE2 : C5 GAPCK: PUSH BC + 3211/ FE3 : D5 PUSH DE + 3212/ FE4 : E5 PUSH HL + 3213/ FE5 : 01 01 E0 LD BC,KEYPB + 3214/ FE8 : 11 02 E0 LD DE,CSTR + 3215/ FEB : 26 64 GAPCK1: LD H,100 + 3216/ FED : CD 01 06 GAPCK2: CALL EDGE + 3217/ FF0 : 38 0B JR C,GAPCK3 + 3218/ FF2 : CD 4A 0A CALL DLY3 ; CALL DLY2*3 + 3219/ FF5 : 1A LD A,(DE) + 3220/ FF6 : E6 20 AND 20H + 3221/ FF8 : 20 F1 JR NZ,GAPCK1 + 3222/ FFA : 25 DEC H + 3223/ FFB : 20 F0 JR NZ,GAPCK2 + 3224/ FFD : C3 9B 06 GAPCK3: JP RET3 + 3225/ 1000 : + 3226/ 1000 : ; MONITOR WORK AREA + 3227/ 1000 : ; (MZ700) + 3228/ 1000 : + 3229/ 10F0 : ORG 10F0H + 3230/ 10F0 : SPV: + 3231/ 10F0 : IBUFE: ; TAPE BUFFER (128 BYTES) + AS V1.40r8 - Quelle MZ700.ASM - Seite 55 - 9.6.1998 9:06:30 + + + 3232/ 10F0 : ATRB: DB ? ; ATTRIBUTE + 3233/ 10F1 : NAME: DB 17 DUP ? ; FILE NAME + 3234/ 1102 : SIZE: DB 2 DUP ? ; BYTESIZE + 3235/ 1104 : DTADR: DB 2 DUP ? ; DATA ADDRESS + 3236/ 1106 : EXADR: DB 2 DUP ? ; EXECUTION ADDRESS + 3237/ 1108 : COMNT: DB 104 DUP ? ; COMMENT + 3238/ 1170 : KANAF: DB ? ; KANA FLAG (01=GRAPHIC MODE) + 3239/ 1171 : DSPXY: DB 2 DUP ? ; DISPLAY COORDINATES + 3240/ 1173 : MANG: DB 27 DUP ? ; COLUMN MANAGEMENT + 3241/ 118E : FLASH: DB ? ; FLASHING DATA + 3242/ 118F : FLPST: DB 2 DUP ? ; FLASHING POSITION + 3243/ 1191 : FLSST: DB ? ; FLASHING STATUS + 3244/ 1192 : FLSDT: DB ? ; CURSOR DATA + 3245/ 1193 : STRGF: DB ? ; STRING FLAG + 3246/ 1194 : DPRNT: DB ? ; TAB COUNTER + 3247/ 1195 : TMCNT: DB 2 DUP ? ; TAPE MARK COUNTER + 3248/ 1197 : SUMDT: DB 2 DUP ? ; CHECK SUM DATA + 3249/ 1199 : CSMDT: DB 2 DUP ? ; FOR COMPARE SUM DATA + 3250/ 119B : AMPM: DB ? ; AMPM DATA + 3251/ 119C : TIMFG: DB ? ; TIME FLAG + 3252/ 119D : SWRK: DB ? ; KEY SOUND FLAG + 3253/ 119E : TEMPW: DB ? ; TEMPO WORK + 3254/ 119F : ONTYO: DB ? ; ONTYO WORK + 3255/ 11A0 : OCTV: DB ? ; OCTAVE WORK + 3256/ 11A1 : RATIO: DB 2 DUP ? ; ONPU RATIO + 3257/ 11A3 : BUFER: DB 81 DUP ? ; GET LINE BUFFER + 3258/ 11F4 : + 3259/ 11F4 : ; EQU TABLE I/O REPORT + 3260/ 11F4 : + 3261/ 11F4 : =E000H KEYPA: EQU 0E000H + 3262/ 11F4 : =E001H KEYPB: EQU 0E001H + 3263/ 11F4 : =E002H KEYPC: EQU 0E002H + 3264/ 11F4 : =E003H KEYPF: EQU 0E003H + 3265/ 11F4 : =E002H CSTR: EQU 0E002H + 3266/ 11F4 : =E003H CSTPT: EQU 0E003H + 3267/ 11F4 : =E004H CONT0: EQU 0E004H + 3268/ 11F4 : =E005H CONT1: EQU 0E005H + 3269/ 11F4 : =E006H CONT2: EQU 0E006H + 3270/ 11F4 : =E007H CONTF: EQU 0E007H + 3271/ 11F4 : =E008H SUNDG: EQU 0E008H + 3272/ 11F4 : =E008H TEMP: EQU 0E008H + AS V1.40r8 - Quelle MZ700.ASM - Seite 56 - 9.6.1998 9:06:30 + + + Symboltabelle: + -------------- + +ALPH1 : EE2 C | ALPHA : EE1 C +AMPM : 119B C | ASC : 3DA C +ATBL : A92 C | ATRB : 10F0 C +AUTO3 : 7ED C | BELL : 3E C +BGETL : 12F C | BRKEY : 1E C +BUFER : 11A3 C | CKS1 : 720 C +CKS2 : 72F C | CKS3 : 733 C +CKSUM : 71A C | CLEAR : 9D8 C +CLEAR1 : 9DA C | CLRS : E3A C +CMY0 : 5B C | COMNT : 1108 C +CONSTPI : 3.14159265358979 - | CONT0 : E004 - +CONT1 : E005 - | CONT2 : E006 - +CONTF : E007 - | CR : E5A C +CR1 : E6A C | CSMDT : 1199 C +CSTPT : E003 - | CSTR : E002 - +CTBL : EAA C | CURS1 : DFF C +CURS2 : E16 C | CURS3 : DFF C +CURS4 : E23 C | CURS5 : E02 C +CURSD : DF8 C | CURSL : E25 C +CURSR : E0D C | CURSU : E05 C +CURSU1 : E0B C | DACN1 : BE3 C +DACN2 : BDF C | DACN3 : BE0 C +DATE : 9.6.1998 - | DEL : EF8 C +DEL1 : F0E C | DEL2 : F1C C +DLY1 : 759 C | DLY12 : 996 C +DLY2 : 760 C | DLY3 : A4A C +DLY4 : 9A9 C | DMCP : 6B C +DPRNT : 1194 C | DSP01 : DB9 C +DSP04 : DD0 C | DSPXY : 1171 C +DSWEP : 830 C | DTADR : 1104 C +DUM1 : D88 C | DUM2 : D3E C +DUM3 : D37 C | DUMP : D29 C +EDG1 : 607 C | EDG2 : 613 C +EDGE : 601 C | EXADR : 1106 C +FALSE : 0 - | FD : FF C +FD1 : 106 C | FD2 : 102 C +FLAS1 : 97B C | FLAS2 : 9EF C +FLASH : 118E C | FLKEY : 57E C +FLPST : 118F C | FLSDT : 1192 C +FLSST : 1191 C | GAP : 77A C +GAP1 : 78E C | GAP2 : 796 C +GAP3 : 79C C | GAPCK : FE2 C +GAPCK1 : FEB C | GAPCK2 : FED C +GAPCK3 : FFD C | GETKY : 1B C +GETL : 3 C | GETL1 : 7EA C +GETL2 : 818 C | GETL3 : 85B C +GETL5 : 81D C | GETL6 : 865 C +GETLA : 82B C | GETLB : 863 C +GETLC : 822 C | GETLR : 87E C +GETLU : 876 C | GETLZ : 86C C +GOTO : F3 C | GRSTAS : DD4 C +HASFPU : 0 - | HASPMMU : 0 - +HEX : 3F9 C | HEXIY : 13D C +HEXJ : 3E5 C | HLHEX : 410 C +HOME : E4D C | IBUFE : 10F0 C +INMAXMODE : 0 - | INST : F38 C +INST2 : ECA C | INSUPMODE : 0 - + AS V1.40r8 - Quelle MZ700.ASM - Seite 57 - 9.6.1998 9:06:30 + + +KANA : EEE C | KANAF : 1170 C +KANST : E003 - | KEYPA : E000 - +KEYPB : E001 - | KEYPC : E002 - +KEYPF : E003 - | KSL1 : 9B7 C +KSL2 : 9BC C | KTBL : BEA C +KTBLC : CAA C | KTBLG : CE9 C +KTBLGS : C6A C | KTBLS : C2A C +L010F : 10F C | L01F5 : 1F5 C +L0207 : 207 C | L0220 : 220 C +L0239 : 239 C | L023F : 23F C +L0255 : 255 C | L025A : 25A C +L02D5 : 2D5 C | L02DB : 2DB C +L0363 : 363 C | L0378 : 378 C +L041D : 41D C | L0434 : 434 C +L047D : 47D C | L04C2 : 4C2 C +L04C4 : 4C4 C | L0563 : 563 C +L060E : 60E C | L061A : 61A C +L066C : 66C C | L06AD : 6AD C +L06B4 : 6B4 C | L071C : 71C C +L0725 : 725 C | L0737 : 737 C +L0739 : 739 C | L075B : 75B C +L0762 : 762 C | L08F7 : 8F7 C +L092C : 92C C | L0968 : 968 C +L0999 : 999 C | L09AB : 9AB C +L0A89 : A89 C | L0BA0 : BA0 C +L0BB1 : BB1 C | L0D36 : D36 C +L0D51 : D51 C | L0D78 : D78 C +L0D7A : D7A C | L0D85 : D85 C +L0DA7 : DA7 C | L0DAD : DAD C +L0DE0 : DE0 C | L0E2D : E2D C +L0F17 : F17 C | L0F33 : F33 C +L0F42 : F42 C | L0F4D : F4D C +L2HEX : 41F C | LETNL : 6 C +LISTON : 1 - | LLPT : 470 C +LOA0 : 116 C | LOAD : 111 C +LONG : A1A C | LPRNT : 18F C +MACEXP : 1 - | MANG : 1173 C +MCOR : 7A8 C | MCR1 : 7AB C +MCR2 : 7D4 C | MCR3 : 7D7 C +MELDY : 30 C | MLD1 : 1D1 C +MLD2 : 205 C | MLD3 : 20D C +MLD4 : 211 C | MLD5 : 214 C +MLDS1 : 2C4 C | MLDSP : 2BE C +MLDST : 2AB C | MNTBL : 284 C +MOMCPU : 80 - | MONIT : 0 C +MOT1 : 6A4 C | MOT2 : 6AB C +MOT4 : 6B9 C | MOT5 : 6D8 C +MOT7 : 6B7 C | MOT8 : 6D0 C +MOT9 : 6D7 C | MOTOR : 69F C +MSG : 15 C | MSG1 : 896 C +MSGE1 : 147 C | MSGN1 : 3FB C +MSGN2 : 3FD C | MSGN3 : 402 C +MSGN7 : 467 C | MSGOK : 942 C +MSGQ2 : 9A0 C | MSGQ3 : 6E7 C +MSGSV : 98B C | MSGX : 18 C +MSGX1 : 8A4 C | MSGX2 : 8A7 C +MST1 : 705 C | MST3 : 717 C +MSTA : 44 C | MSTOP : 700 C +MSTP : 47 C | MTBL : 26C C +NAME : 10F1 C | NBRK : 8B8 C + AS V1.40r8 - Quelle MZ700.ASM - Seite 58 - 9.6.1998 9:06:30 + + +NCLR08 : 9D4 C | NCLR8 : 9D5 C +NL : 9 C | NLPHL : 5FA C +NOADD : 3E2 C | OCTV : 11A0 C +ONP1 : 21F C | ONP2 : 22C C +ONP3 : 265 C | ONPU : 21C C +ONTYO : 119F C | OPTBL : 29C C +P4DE : 2A6 C | PADDING : 1 - +PEN : 18B C | PLOT : 184 C +PLPT : 176 C | PMANG : 2F3 C +PMSG : 1A5 C | PMSG1 : 1A8 C +PPLPT : 17B C | PRNT : 12 C +PRNT2 : 967 C | PRNT3 : 96C C +PRNT4 : 96F C | PRNT5 : 959 C +PRNTS : C C | PRNTT : F C +PRTHL : 3BA C | PRTHX : 3C3 C +PTEST : 155 C | PTRN : 180 C +PTST0 : 15A C | PTST1 : 170 C +QADCN : BB9 C | QBEL : 577 C +QBELD : 352 C | QBLNK : DA6 C +QBRK : A32 C | QBRK1 : A48 C +QBRK2 : 980 C | QBRK3 : 986 C +QCLER : FD8 C | QCLRFF : FDB C +QDACN : BCE C | QDINT : FDD C +QDPCT : DDC C | QDSP : DB5 C +QER : 107 C | QFLAS : 9FF C +QFLS : 9E3 C | QGET : 8BD C +QGETL : 7E6 C | QKEY : 8CA C +QKY1 : 8D6 C | QKY2 : 8DA C +QKY5 : 8FA C | QKY55 : 8FB C +QKYGRP : 8FE C | QKYGRS : 909 C +QKYSM : 8B3 C | QLOAD : 5F0 C +QLTNL : 90E C | QMLDY : 1C7 C +QMODE : 73E C | QMSG : 893 C +QMSGX : 8A1 C | QNL : 918 C +QPNT1 : FB4 C | QPNT2 : FBF C +QPONT : FB1 C | QPRNT : 935 C +QPRT : 946 C | QPRTS : 920 C +QPRTT : 924 C | QQKEY : 9B3 C +QRDD : 4F8 C | QRDI : 4D8 C +QRSTR : EE5 C | QRSTR1 : EE6 C +QSAVE : B92 C | QSWEP : A50 C +QTEMP : 2E5 C | QTMR1 : 375 C +QTMR2 : 37F C | QTMRD : 358 C +QTMS1 : 331 C | QTMS2 : 344 C +QTMST : 308 C | QVRFY : 588 C +QWRD : 475 C | QWRI : 436 C +RATIO : 11A1 C | RBY1 : 630 C +RBY2 : 649 C | RBY3 : 654 C +RBYTE : 624 C | RD1 : 4E6 C +RDA : 1B6 C | RDDAT : 2A C +RDINF : 27 C | RELAXED : 0 - +RET1 : 4D2 C | RET2 : 554 C +RET3 : 69B C | RTAPE : 50E C +RTP1 : 513 C | RTP2 : 519 C +RTP3 : 532 C | RTP4 : 554 C +RTP5 : 565 C | RTP6 : 572 C +RTP7 : 56E C | RTP8 : 553 C +RTP9 : 574 C | RYTHM : 2C8 C +SAV1 : F8E C | SAVE : F5E C +SCRN : D000 - | SCROL : E6D C + AS V1.40r8 - Quelle MZ700.ASM - Seite 59 - 9.6.1998 9:06:30 + + +SG : F7 C | SHORT : A01 C +SIZE : 1102 C | SLPT : 3D5 C +SPHEX : 3B1 C | SPV : 10F0 C +SS : A2 C | ST0 : 70 C +ST1 : AD C | ST2 : BB C +START : 4A C | STRGF : 1193 C +SUMDT : 1197 C | SUNDG : E008 - +SV0 : BA2 C | SV1 : BB5 C +SWEP0 : A66 C | SWEP01 : A64 C +SWEP2 : A7F C | SWEP3 : A77 C +SWEP6 : A5F C | SWEP9 : A73 C +SWRK : 119D C | TEMP : E008 - +TEMPW : 119E C | TIME : 9:06:28 - +TIMFG : 119C C | TIMIN : 38D C +TIMRD : 3B C | TIMST : 33 C +TM1 : 675 C | TM2 : 678 C +TM3 : 688 C | TM4 : 69B C +TMARK : 65B C | TMCNT : 1195 C +TRUE : 1 - | TVF1 : 5B2 C +TVF2 : 5B8 C | TVF3 : 5CC C +TVRFY : 5AD C | VERFY : 2D C +VERSION : 1408 - | VRFY : FCB C +VRNS : BC5 C | WBY1 : 76D C +WBYTE : 767 C | WRDAT : 24 C +WRI1 : 444 C | WRI2 : 45E C +WRI3 : 464 C | WRINF : 21 C +WTAP1 : 494 C | WTAP2 : 4A5 C +WTAP3 : 4D2 C | WTAPE : 48A C +XTEMP : 41 C + + AS V1.40r8 - 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Quelle MZ700.ASM - Seite 83 - 9.6.1998 9:06:30 + + + +Symbol TVF3 (=5CC,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1074): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 1082 + +Symbol TVRFY (=5AD,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1056): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 1045 + +Symbol VRFY (=FCB,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/3189): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 103 + +Symbol WBY1 (=76D,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1369): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 1373 + +Symbol WBYTE (=767,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/1366): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 854 869 871 + +Symbol WRI1 (=444,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/797): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 839 + +Symbol WRI2 (=45E,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/810): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 802 + +Symbol WRI3 (=464,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/812): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 799 + +Symbol WTAP1 (=494,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/853): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 866 886 + +Symbol WTAP2 (=4A5,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/862): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 857 + +Symbol WTAP3 (=4D2,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/888): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 860 876 + +Symbol WTAPE (=48A,E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM/847): + Datei E:\EIGENE~1\8BIT\SHARP\MZ-EMUL\MZ700.ASM : + 811 + + diff --git a/asm/hi-ramcheck.asm b/asm/hi-ramcheck.asm new file mode 100644 index 0000000..4a00c5e --- /dev/null +++ b/asm/hi-ramcheck.asm @@ -0,0 +1,241 @@ + +KEYPC: EQU 0E002h +KEYPF: EQU 0E003h +CSTR: EQU 0E002h +CSTPT: EQU 0E003h +CONT0: EQU 0E004h +CONT1: EQU 0E005h +CONT2: EQU 0E006h +CONTF: EQU 0E007h +SUNDG: EQU 0E008h +TEMP: EQU 0E008h +LETNL: EQU 0006h +NL: EQU 0009h +PRNTS: EQU 000Ch +PRNT: EQU 0012h +MSG: EQU 0015h +MSGX: EQU 0018h +MONIT: EQU 0086h +ST1: EQU 0095h +PRTHL: EQU 03BAh +PRTHX: EQU 03C3h +DPCT: EQU 0DDCh +?BRK: EQU 0D11h +?RSTR1: EQU 0EE6h +GRAMSTART: EQU 0C000h +GRAMEND: EQU 0FFFFh +TPSTART: EQU 10F0h +MEMSTART: EQU 1200h +MSTART: EQU 0BE00h + + ORG TPSTART + +SPV: +IBUFE: ; TAPE BUFFER (128 BYTES) +;ATRB: DS virtual 1 ; ATTRIBUTE +ATRB: DB 01h ; Code Type, 01 = Machine Code. +;NAME: DS virtual 17 ; FILE NAME +NAME: DB "TAPE CHECK V1.0", 0Dh, 00h ; Title/Name (17 bytes). +;SIZE: DS virtual 2 ; BYTESIZE +SIZE: DW MEND - MSTART ; Size of program. +;DTADR: DS virtual 2 ; DATA ADDRESS +DTADR: DW MSTART ; Load address of program. +;EXADR: DS virtual 2 ; EXECUTION ADDRESS +EXADR: DW MSTART ; Exec address of program. +COMNT: DS 104 ; COMMENT +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 27 ; COLUMN MANAGEMENT +FLASH: DS virtual 1 ; FLASHING DATA +FLPST: DS virtual 2 ; FLASHING POSITION +FLSST: DS virtual 1 ; FLASHING STATUS +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER + + ORG MSTART + +START: LD A,0FFh ; Set Red filter. + OUT (0EBh),A + LD A,000h ; Set Green filter. + OUT (0ECh),A + LD A,000h ; Set Blue filter. + OUT (0EDh),A + LD A,000h + CALL GRAMINIT + LD A,005h + CALL GRAMINIT + LD A,00Ah + CALL GRAMINIT + LD A, 0CCh ; Set graphics mode to Indirect Page write. + OUT (0EAh),A + LD HL,0DE00h + LD (GRPHPOS),HL + JR SIGNON + + +GRAMINIT: LD HL,GRAMSTART + LD BC,GRAMEND - GRAMSTART +GRAM0: OUT (0EAh),A + OUT (0E8h),A +GRAM1: LD A,000h + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JR NZ,GRAM1 + OUT (0E9h),A + RET + + +SIGNON: CALL LETNL + LD DE,TITLE + CALL MSG + CALL LETNL + LD B,240 ; Number of loops +LOOP: LD HL,MEMSTART ; Start of checked memory, + LD D,0BEh ; End memory check BE00 +LOOP1: LD A,000h + CP L + JR NZ,LOOP1b + CALL PRTHL ; Print HL as 4digit hex. + LD A,0C4h ; Move cursor left. + LD E,004h ; 4 times. +LOOP1a: CALL DPCT + DEC E + JR NZ,LOOP1a +LOOP1b: INC HL + LD A,H + CP D ; Have we reached end of memory. + JR Z,LOOP3 ; Yes, exit. + LD A,(HL) ; Read memory location under test, ie. 0. + CPL ; Subtract, ie. FF - A, ie FF - 0 = FF. + LD (HL),A ; Write it back, ie. FF. + SUB (HL) ; Subtract written memory value from A, ie. should be 0. + JR NZ,LOOP2 ; Not zero, we have an error. + LD A,(HL) ; Reread memory location, ie. FF + CPL ; Subtract FF - FF + LD (HL),A ; Write 0 + SUB (HL) ; Subtract 0 + JR Z,LOOP1 ; Loop if the same, ie. 0 +LOOP2: LD A,16h + CALL PRNT ; Print A + CALL PRTHX ; Print HL as 4 digit hex. + CALL PRNTS ; Print space. + XOR A + LD (HL),A + LD A,(HL) ; Get into A the failing bits. + CALL PRTHX ; Print A as 2 digit hex. + CALL PRNTS ; Print space. + LD A,0FFh ; Repeat but first load FF into memory + LD (HL),A + LD A,(HL) + CALL PRTHX ; Print A as 2 digit hex. + NOP + JR LOOP4 + +LOOP3: CALL PRTHL + LD DE,OKCHECK + CALL MSG ; Print check message in DE + LD A,B ; Print loop count. + CALL PRTHX + LD DE,OKMSG + CALL MSG ; Print ok message in DE + CALL NL + LD HL,(GRPHPOS) ; Get position of graphics progress line. + OUT (0E8h),A ; Enable graphics memory. + LD A,0FFh + LD (HL),A + OUT (0E9h),A ; Disable graphics memory. + INC HL + LD (GRPHPOS),HL + DEC B + JR NZ,LOOP + LD DE,DONEMSG + CALL MSG ; Print check message in DE + JP MONIT + +LOOP4: LD B,09h + CALL PRNTS ; Print space. + XOR A ; Zero A + SCF ; Set Carry +LOOP5: PUSH AF ; Store A and Flags + LD (HL),A ; Store 0 to bad location. + LD A,(HL) ; Read back + CALL PRTHX ; Print A as 2 digit hex. + CALL PRNTS ; Print space + POP AF ; Get back A (ie. 0 + C) + RLA ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB + DJNZ LOOP5 ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit. + XOR A ; Zero A, clears flags. + LD A,80h + LD B,08h +LOOP6: PUSH AF ; Repeat above but AND memory location with original A (ie. 80) + LD C,A ; Basically walk through all the bits to find which one is stuck. + LD (HL),A + LD A,(HL) + AND C + NOP + JR Z,LOOP8 ; If zero then print out the bit number + NOP + NOP + LD A,C + CPL + LD (HL),A + LD A,(HL) + AND C + JR NZ,LOOP8 ; As above, if the compliment doesnt yield zero, print out the bit number. +LOOP7: POP AF + RRCA + NOP + DJNZ LOOP6 + JP MONIT + +LOOP8: CALL LETNL ; New line. + LD DE,BITMSG ; BIT message + CALL MSG ; Print message in DE + LD A,B + DEC A + CALL PRTHX ; Print A as 2 digit hex, ie. BIT number. + CALL LETNL ; New line + LD DE,BANKMSG ; BANK message + CALL MSG ; Print message in DE + LD A,H + CP 50h ; 'P' + JR NC,LOOP9 ; Work out bank number, 1, 2 or 3. + LD A,01h + JR LOOP11 + +LOOP9: CP 90h + JR NC,LOOP10 + LD A,02h + JR LOOP11 + +LOOP10: LD A,03h +LOOP11: CALL PRTHX ; Print A as 2 digit hex, ie. BANK number. + JR LOOP7 + +OKCHECK: DB ", CHECK: ", 0Dh +OKMSG: DB " OK.", 0Dh +DONEMSG: DB 11h + DB "RAM TEST COMPLETE.", 0Dh + +BITMSG: DB " BIT: ", 0Dh +BANKMSG: DB " BANK: ", 0Dh + +TITLE: DB "SHARPMZ RAM TEST (C) P. SMART 2018", 0Dh, 00h +GRPHPOS: DB 00h, 00h + +MEND: diff --git a/asm/monitor_1Z-013A.asm b/asm/monitor_1Z-013A.asm new file mode 100644 index 0000000..7bb488b --- /dev/null +++ b/asm/monitor_1Z-013A.asm @@ -0,0 +1,7 @@ +; Configurable parameters. +COLW: EQU 40 ; Width of the display screen (ie. columns). +ROW: EQU 25 ; Number of rows on display screen. +SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. +MODE80C:EQU 0 + + INCLUDE "1Z-013A.asm" diff --git a/asm/monitor_80c_1Z-013A.asm b/asm/monitor_80c_1Z-013A.asm new file mode 100644 index 0000000..3c1f57e --- /dev/null +++ b/asm/monitor_80c_1Z-013A.asm @@ -0,0 +1,7 @@ +; Configurable parameters. +COLW: EQU 80 ; Width of the display screen (ie. columns). +ROW: EQU 25 ; Number of rows on display screen. +SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. +MODE80C:EQU 1 + + INCLUDE "1Z-013A.asm" diff --git a/asm/monitor_80c_SA1510.asm b/asm/monitor_80c_SA1510.asm new file mode 100644 index 0000000..ff7288c --- /dev/null +++ b/asm/monitor_80c_SA1510.asm @@ -0,0 +1,7 @@ +; Configurable parameters. +COLW: EQU 80 ; Width of the display screen (ie. columns). +ROW: EQU 25 ; Number of rows on display screen. +SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. +MODE80C:EQU 1 + + INCLUDE "sa1510.asm" diff --git a/asm/monitor_SA1510.asm b/asm/monitor_SA1510.asm new file mode 100644 index 0000000..e137e14 --- /dev/null +++ b/asm/monitor_SA1510.asm @@ -0,0 +1,7 @@ +; Configurable parameters. +COLW: EQU 40 ; Width of the display screen (ie. columns). +ROW: EQU 25 ; Number of rows on display screen. +SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. +MODE80C:EQU 0 + + INCLUDE "sa1510.asm" diff --git a/asm/monitor_mz-1r12.asm b/asm/monitor_mz-1r12.asm new file mode 100644 index 0000000..0912cc6 --- /dev/null +++ b/asm/monitor_mz-1r12.asm @@ -0,0 +1,401 @@ +; V1.00 +; +; To compile use: +; +; GLASS Z80 Assembler +; +; java -jar ../tools/glass.jar mz-1r12.asm mz-1r12.obj mz-1r12.sym + + + +LETNL EQU 00006h +PRNT EQU 00012h +MSG EQU 00015h +GETKY EQU 0001Bh +RDINF EQU 00027h +RDDAT EQU 0002Ah +ST1 EQU 000ADh +QNL EQU 00918h + +NAME EQU 010F1h +SIZE EQU 01102h +DTADR EQU 01104h +COMNT EQU 01108h + +; Macro to align boundaries. +ALIGN: MACRO ?boundary, ?fill + DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, ?fill + ENDM + + ORG 0E800h + +MZ1R12: + NOP + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL +ST1X: + CALL LETNL + CALL LETNL + LD DE,LE83B ; 'PRESS R, W OR M' + CALL MSG + CALL LETNL + CALL LETNL + LD DE,LE85B ; 'R: READ S-RAM' + CALL MSG + CALL LETNL + LD DE,LE877 ; 'W: WRITE S-RAM' + CALL MSG + CALL LETNL + LD DE,LE893 ; 'M: MONITOR' + CALL MSG + CALL LETNL + JR LE8AB + + +LE83B: DB " P",005h,"RESS",005h," R , W ",005h,"OR",005h," M",00Dh +LE85B: DB " R:",005h,"READ",005h," S-RAM",00Dh +LE877: DB " W:",005h,"WRITE",005h," S-RAM",00Dh +LE893: DB " M:",005h,"MONITOR",005h,00Dh + + +LE8AB: + NOP + CALL GETKY + CP 'M' + JP Z,MON + CP 'W' + JP Z,LE96A + CP 'R' + JP Z,LE8C1 + JP NZ,LE8AB + +LE8C1: + NOP + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL + CALL LETNL + LD DE,LEB1B ; 'LOADING PROGRAM FROM S-RAM' + CALL MSG + CALL LETNL + CALL LETNL + CALL CHECK + IN A,(0F8h) ; Counter reset + IN A,(0F9h) + LD C,A + IN A,(0F9h) + LD B,A + IN A,(0F9h) + LD L,A + IN A,(0F9h) + LD H,A + IN A,(0F9h) + LD E,A + IN A,(0F9h) + LD D,A + PUSH DE + LD D,B + LD E,C + IN A,(0F9h) + LD C,A + IN A,(0F9h) + LD B,A + IN A,(0F9h) + PUSH BC + PUSH DE + PUSH HL + LD C,0F9h + LD A,E + OR A + JR Z,LE90A + LD B,A +LE908: + INIR +LE90A: + LD B,000h + DEC D + JP P,LE908 + POP DE ; Data adr + POP BC ; Size + CALL SUM + POP DE + OR A + SBC HL,DE + JR NZ,LE956 + POP HL + JP (HL) + + +; +; sum check +; +; IN BC=Size +; DE=Data adr +; EXIT HL=Check sum +; +SUM: + PUSH BC + PUSH DE + EXX + LD HL,00000h ; HL'= Check sum clr + LD C,008h ; C' = Loop count + EXX +SUMCK1: + LD A,B ; BC = Size + OR C + JR Z,SUMCK2 + LD A,(DE) ; DE = Data adrs + EXX + LD B,C ; BC' +SUMCK3: + RLCA + JR NC,LE931 + INC HL ; HL' = Check sum data +LE931: + DJNZ SUMCK3 + EXX + INC DE ; DE + DEC BC ; BC + JP SUMCK1 +SUMCK2: + EXX + POP DE + POP BC + RET + + + +; +; Information's sum check +; +CHECK: + IN A,(0F8h) ; Counter reset + LD BC,00800h ; B=Byte Counter C=Sum Counter +CK1: + IN A,(0F9h) ; Counter=Counter+1 + PUSH BC + LD B,008h ; Bit Counter +CK2: + RLCA + JR NC,LE94B + INC C +LE94B: + DJNZ CK2 + LD A,C + POP BC + LD C,A + DJNZ CK1 + IN A,(0F9h) + CP C + RET + + +LE956: + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL + LD DE,LEA8F ; 'CHECK SUM ERROR' + CALL LEA3D + JP ST1X + +LE96A: + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL + CALL LETNL + LD DE,LEAAC ; 'S-RAM PROGRAMMING' + CALL LEA36 + LD DE,LEACB ; 'SET MASTER TAPE PLAY' + LD A,011h + LD HL,0D8F0h + CALL LEA4A + CALL LETNL + CALL LEA39 + CALL RDINF + PUSH AF + PUSH BC + LD BC,(SIZE) + LD A,07Fh + CP B + JR C,LE9A8 + JR NZ,LE9A4 + LD A,0F6h + CP C + JR C,LE9A8 +LE9A4: + POP BC + POP AF + JR LE9AD +LE9A8: + POP BC + POP AF + JP LEA74 + +LE9AD: + LD A,000h + LD HL,0D0F0h + CALL LEA4A + LD A,071h + LD HL,0D8F0h + CALL LEA4A + LD A,002h + JP C,LEA42 + CALL LETNL + LD DE,LEAF1 ; 'FOUND : ' + CALL LEA3D + LD DE,NAME + PUSH DE + RST 018h + CALL LETNL + LD DE,LEB06 ; 'LOADING : ' + CALL LEA3D + POP DE + RST 018h +; +; Read data block +; + CALL RDDAT + JR C,LEA42 +; +; Counter reset +; + IN A,(0F8h) +; +; Sum check for data +; + LD DE,(DTADR) + LD BC,(SIZE) + PUSH DE + PUSH BC + CALL SUM + LD (COMNT),HL +; +; Write information (8Byte) +; + LD HL,SIZE + LD BC,008FAh ; B=Byte Counter + PUSH HL + PUSH BC + OTIR + POP BC + POP HL +; +; Sum check for information block +; AccCheck sum data +; + PUSH DE ; DE Size + LD D,000h ; Sum Counter +WCK1: + PUSH BC + LD B,008h + LD A,(HL) +WCK2: + RLCA + JR NC,WCK3 + INC D +WCK3: + DJNZ WCK2 + INC HL + POP BC + DJNZ WCK1 + LD A,D + POP DE + OUT (0FAh),A +; +; Write data block +; + POP DE ; DE Size + POP HL ; HL Data adrs + LD A,E + OR A + JR Z,LEA1C + LD B,E +LEA1A: + OTIR +LEA1C: + LD B,000h + DEC D + JP P,LEA1A + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL + LD DE,LEB8C ; 'WRITING S-RAM O.K.!' + CALL MSG + JP ST1X + + +LEA36: + CALL QNL +LEA39: + RST 018h + JP QNL + +LEA3D: + CALL QNL + RST 018h + RET + +LEA42: + CP 002h + JP Z,LEA60 + JP LE956 + +LEA4A: + LD B,006h +LEA4C: + LD (HL),A + INC HL + DEC B + JR NZ,LEA4C + RET + +MON: + LD A,016h + CALL PRNT + LD DE,LEB3E ; '** MONITOR 1Z-009A **' + CALL MSG + JP ST1 + +LEA60: + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL + LD DE,LEB77 ; 'BREAK !' + CALL MSG + JP ST1X + +LEA74: + LD DE,00000h + LD (SIZE),DE + LD A,016h + CALL PRNT + CALL LETNL + CALL LETNL + LD DE,LEBAD ; 'FILE IS TOO LONG' + CALL MSG + JP ST1X + + +LEA8F: DB " C",005h,"HECK SUM ERROR",005h,00Dh +LEAAC: DB " S-RAM ",005h,"PROGRAMMING",005h,00Dh +LEACB: DB " S",005h,"ET MASTER TAPE",005h," ",07Fh,"P",005h,"LAY",005h," ",00Dh +LEAF1: DB " F",005h,"OUND",005h," : ",00Dh +LEB06: DB " L",005h,"OADING",005h,": ",00Dh +LEB1B: DB " L",005h,"OADING PROGRAM FROM ",005h,"S-RAM",00Dh +LEB3E: DB "** MONITOR 1Z-009A **",00Dh +LEB56: DB " R",005h,"EADING",005h," S-RAM O.K.!",00Dh +LEB77: DB " B",005h,"REAK",005h," !",00Dh +LEB8C: DB " W",005h,"RITING",005h," S-RAM O.K.!",00Dh +LEBAD: DB " F",005h,"ILE IS TOO LONG",005h,00Dh + +; the following is only to get the original length of 4096 bytes + + ALIGN 0F7FFh, 0FFh + DB 0FFh diff --git a/asm/mz-1e14.asm b/asm/mz-1e14.asm new file mode 100644 index 0000000..7f7484c --- /dev/null +++ b/asm/mz-1e14.asm @@ -0,0 +1,1483 @@ +; V1.01 +; +; To compile use: +; +; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor. +; +; Available from: +; - http://www.falstaff.demon.co.uk/cross.html +; - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip +; - and many Simtel mirrors. +; +; as80 -i -l -n -x2 -v mz-1e14.asm + + + + +SIOAD EQU 0F4h +SIOBD EQU 0F5h +SIOAC EQU 0F6h +SIOBC EQU 0F7h + + + +; RxD_A <- RDDT (ReaDDaTa) +; RxC_A <- (read data clock) +; TxD_A -> #WRDT (WRiteDaTa) +; TxC_A <- 6.5MHz / 4 / 16 = 101562,5Hz +; CTS_A <- #WRPR (WRitePRotect) +; RTS_A -> #WRGA (WRiteGAte) +; DCD_A <- #HDST (HeaDSeT (disk test) +; +; RTS_B -> (?) +; DCD_B <- #HOME () +; DTR_B -> #MTON (MoTorON) + + + + +GETL EQU 00003h +NL EQU 00009h +PRNT EQU 00012h +GETKY EQU 0001Bh +BRKEY EQU 0001Eh +CMY0 EQU 0005Bh +MSGE1 EQU 00147h +DOT4DE EQU 002A6h +?TMST EQU 00308h +SPHEX EQU 003B1h +SLPT EQU 003D5h +HLHEX EQU 00410h +_2HEX EQU 0041Fh +?WRI EQU 00436h +LLPT EQU 00470h +?WRD EQU 00475h +?RDI EQU 004D8h +?RDD EQU 004F8h +?VRFY EQU 00588h +NLPHL EQU 005FAh +?KEY EQU 008CAh +?PRTS EQU 00920h +MSGOK EQU 00942h +PRNT3 EQU 0096Ch +MSGSV EQU 0098Bh +MSG?2 EQU 009A0h +?BRK EQU 00A32h +?ADCN EQU 00BB9h +?BLNK EQU 00DA6h +?DPCT EQU 00DDCh + +BRKCD EQU 00 +NTFECD EQU 40 +HDERCD EQU 41 +WPRTCD EQU 46 +QNTRCD EQU 50 +NFSECD EQU 53 +UNFMCD EQU 54 + +ATRB EQU 010F0h +NAME EQU 010F1h +SIZE EQU 01102h +DTADR EQU 01104h +EXADR EQU 01106h +COMNT EQU 01108h + +NAMSIZ EQU 011h +OBJCD EQU 001h + ; QD command table +QDPA EQU 01130h ; QD code 1 +QDPB EQU 01131h ; QD code 2 +QDPC EQU 01132h ; QD header startaddress +QDPE EQU 01134h ; QD header length +QDCPA EQU 0113Bh ; QD error flag +HDPT EQU 0113Ch ; QD new headpoint possition +HDPT0 EQU 0113Dh ; QD actual headpoint possition +FNUPS EQU 0113Eh +FNUPF EQU 01140h +FNA EQU 01141h ; File Number A (actual file number) +FNB EQU 01142h ; File Number B (next file number) +MTF EQU 01143h ; QD motor flag +RTYF EQU 01144h +SYNCF EQU 01146h ; SyncFlags +RETSP EQU 01147h +DSPXY EQU 01171h +DPRNT EQU 01194h +SWRK EQU 0119Dh +BUFER EQU 011A3h +QDIRBF EQU 0CD90h + +; Macro to align boundaries. +ALIGN: MACRO ?boundary + DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, 0FFh + ENDM + + ORG 0E800h + +MZ1E14: +LE800: + NOP + JP LE80A + JP ST1X +QDIOS: + JP QDIOS1 + +LE80A: + LD A,0C6h ; clear screen + CALL ?DPCT + XOR A + LD (DPRNT),A + DI + XOR A + LD DE,00000h + CALL ?TMST + LD A,001h + OUT (SIOBC),A ; select Write Register 1 + XOR A + OUT (SIOBC),A ; Rx INT DISABLE + CALL GETKY + CP 'M' + JR Z,MON + CP 'Q' + JR Z,QBT + CALL LEB22 ; check ROM at 0xF000 (FDD) + CALL Z,0F006h + JR QBT +; +;=============================== +; +; Quick disk boot-up +; +;=============================== +; +QBT: + CALL IOFRS ; IO Flag ReSet + CALL NL + CALL QDRCK ; QuickDisk Ready ChecK + JR C,LE868 + LD A,00Dh ; set filename to "" + LD (BUFER),A + CALL HDPCL ; HeaD Point CLear +; +; Error return set +; + LD A,001h + LD (QDCPA),A + LD HL,LE86B + LD SP,010EEh + EX (SP),HL +; +; + CALL FILSCH ; filesearch + JP C,LEBAC + LD A,(ATRB) + CP OBJCD ; is it an "OBJ" file + JR NZ,LE871 +; +; Quick disk boot +; + LD DE,LEB27 + RST 018h + JP DSFLNA + +LE868: + LD DE,LEB37 +LE86B: + CALL NL + RST 018h + JR LE87D +LE871: + LD A,006h ; Motor off + LD (QDPA),A + CALL QDIOS + LD DE,LED4C + RST 018h +LE87D: + CALL NL + +MON: + LD DE,DISCLR ; '** MONITOR 9Z-503M **' + RST 018h + + +ST1X: + CALL NL + LD A,'*' + CALL PRNT + LD DE,BUFER + CALL GETL +ST2X: + LD A,(DE) + INC DE + CP 00Dh + JR Z,ST1X + CP 'J' ; JUMP + JR Z,GOTOX + CP 'L' ; Load CMT + JR Z,LOADX + CP 'F' ; Floppy boot + JR Z,FDCK + CP 'B' ; Bell + JP Z,SGX + CP '#' + JP Z,LEA6A + CP 'P' ; Printer test + JP Z,PTESTX + CP 'M' ; Memory correction + JP Z,MCORX + CP 'S' ; Save CMT + JP Z,SAVEX + CP 'V' ; Verify + JP Z,VRFYX + CP 'D' ; Dump memory + JP Z,DUMPX + CP 'Q' ; Quick disk cmd. + JR NZ,ST2X +; +; Quick disk cmd. +; +QUICK: + LD HL,00000h + LD (0113Ah),HL + LD A,(DE) + CP 'L' ; Load QD + JP Z,QL + CP 'D' ; Directory + JP Z,QD +ST1X1: + JR ST1X + + +FDCK: + LD A,(DE) + CP 00Dh + JR NZ,ST1X1 + CALL LEB22 + CALL Z,0F006h + JR ST1X1 +?ERX: + CP 002h + JR Z,ST1X1 + CALL NL + LD DE,MSGE1 ; 'CHECK SUM ER.' + RST 018h + JR ST1X1 +BGETLX: + EX (SP),HL + POP BC + LD DE,BUFER + CALL GETL + LD A,(DE) + CP 01Bh + JR Z,ST1X1 + JP (HL) + +HEXIYX: + EX (SP),IY + POP AF + CALL HLHEX + JR C,ST1X1 + JP (IY) + +GOTOX: + CALL HEXIYX + JP (HL) + + +LOADX: + CALL ?RDI + JR C,?ERX + CALL NL + LD DE,MSG?2 ; 'LOADING ' + RST 018h + LD DE,NAME + RST 018h + XOR A + LD (BUFER),A + LD HL,(DTADR) + LD A,H + OR L + JR NZ,LE941 + LD HL,(EXADR) + LD A,H + OR L + JR NZ,LE941 + LD A,0FFh + LD (BUFER),A + LD HL,01200h + LD (DTADR),HL +LE941: + CALL ?RDD + JR C,?ERX + LD A,(BUFER) + CP 0FFh + JR Z,LE954 + LD BC,00100h + LD HL,(EXADR) + JP (HL) +LE954: + OUT (0E0h),A + LD HL,01200h + LD DE,00000h + LD BC,(SIZE) + LDIR + LD BC,00100h + JP 00000h + +PTESTX: + LD A,(DE) + CP '&' ; plotter test + JR NZ,PTST1X +PTST0X: + INC DE + LD A,(DE) + CP 'L' ; 40 in 1 line + JR Z,.LPTX + CP 'S' ; 80 in 1 line + JR Z,..LPTX + CP 'C' ; Pen change + JR Z,PENX + CP 'G' ; Graph mode + JR Z,PLOTX + CP 'T' ; Test + JR Z,PTRNX +; +PTST1X: + CALL PMSGX +ST1X2: + JP ST1X1 +.LPTX: + LD DE,LLPT ; 01-09-09-0B-0D + JR PTST1X +..LPTX: + LD DE,SLPT ; 01-09-09-09-0D + JR PTST1X +PTRNX: + LD A,004h ; Test pattern + JR LE999 +PLOTX: + LD A,002h ; Graph mode +LE999: + CALL LPRNTX + JR PTST0X +PENX: + LD A,01Dh ; 1 change code (text mode) + JR LE999 +; +; +; 1 char print to $LPT +; +; in: ACC print data +; +; +LPRNTX: + LD C,000h ; RDAX test + LD B,A ; print data store + CALL RDAX + LD A,B + OUT (0FFh),A ; data out + LD A,080h ; RDP high + OUT (0FEh),A + LD C,001h ; RDA test + CALL RDAX + XOR A ; RDP low + OUT (0FEh),A + RET +; +; $LPT msg. +; in: DE data low address +; 0D msg. end +; +PMSGX: + PUSH DE + PUSH BC + PUSH AF +PMSGX1: + LD A,(DE) ; ACC = data + CALL LPRNTX + LD A,(DE) + INC DE + CP 00Dh ; end ? + JR NZ,PMSGX1 + POP AF + POP BC + POP DE + RET +; +; RDA check +; +; BRKEY in to monitor return +; in: C RDA code +; +RDAX: + IN A,(0FEh) + AND 00Dh + CP C + RET Z + CALL BRKEY + JR NZ,RDAX + LD SP,ATRB + JR ST1X2 +; +; Memory correction +; command 'M' +; +MCORX: + CALL HEXIYX ; correction address +MCORX1: + CALL NLPHL ; corr. adr. print + CALL SPHEX ; ACC ASCII display + CALL ?PRTS ; space print + CALL BGETLX ; get data & check data + CALL HLHEX ; HLASCII(DE) + JR C,MCRX3 + CALL DOT4DE ; INC DE * 4 + INC DE + CALL _2HEX ; data check + JR C,MCORX1 + CP (HL) + JR NZ,MCORX1 + INC DE + LD A,(DE) + CP 00Dh ; not correction + JR Z,MCRX2 + CALL _2HEX ; ACCHL(ASCII) + JR C,MCORX1 + LD (HL),A ; data correct +MCRX2: + INC HL + JR MCORX1 +MCRX3: + LD H,B ; memory address + LD L,C + JR MCORX1 +; +; Programm save +; +; cmd. 'S' +; +SAVEX: + CALL HEXIYX ; Start address + LD (DTADR),HL ; data adress buffer + LD B,H + LD C,L + CALL DOT4DE + CALL HEXIYX ; End address + SBC HL,BC ; byte size + INC HL + LD (SIZE),HL ; byte size buffer + CALL DOT4DE + CALL HEXIYX ; execute address + LD (EXADR),HL ; buffer + CALL NL + LD DE,MSGSV ; 'FILENAME? ' + RST 018h + CALL BGETLX ; filename input + CALL DOT4DE + CALL DOT4DE + LD HL,NAME ; name buffer +SAVX1: + INC DE + LD A,(DE) + LD (HL),A ; filename trans. + INC HL + CP 00Dh ; end code + JR NZ,SAVX1 + LD A,OBJCD ; attribute: OBJ + LD (ATRB),A + CALL ?WRI +?ERX1: + JP C,?ERX + CALL ?WRD ; data + JR C,?ERX1 + CALL NL + LD DE,MSGOK ; 'OK!' + RST 018h +LEA5B: + JP ST1X + +VRFYX: + CALL ?VRFY + JP C,?ERX + LD DE,MSGOK ; 'OK!' + RST 018h + JR LEA5B +LEA6A: + JP CMY0 + +SGX: + LD A,(SWRK) + RRA + CCF + RLA + LD (SWRK),A +LEA76: + JR LEA5B + +DUMPX: + CALL HEXIYX + CALL DOT4DE + PUSH HL + CALL HLHEX + POP DE + JR C,LEAD6 +LEA85: + EX DE,HL +LEA86: + LD B,008h + LD C,017h + CALL NLPHL +LEA8D: + CALL SPHEX + INC HL + PUSH AF + LD A,(DSPXY) + ADD A,C + LD (DSPXY),A + POP AF + CP 020h + JR NC,LEAA0 + LD A,02Eh +LEAA0: + CALL ?ADCN + CALL PRNT3 + LD A,(DSPXY) + INC C + SUB C + LD (DSPXY),A + DEC C + DEC C + DEC C + PUSH HL + SBC HL,DE + POP HL + JR Z,LEAD3 + LD A,0F8h + LD (0E000h),A + NOP + LD A,(0E001h) + CP 0FEh + JR NZ,LEAC7 + CALL ?BLNK +LEAC7: + DJNZ LEA8D +LEAC9: + CALL ?KEY + OR A + JR Z,LEAC9 + CALL ?BRK + DB 020h +LEAD3: + DB 0B2h + + JR LEA76 +LEAD6: + LD HL,000A0h + ADD HL,DE + JR LEA85 + +FNINP: + CALL NL + LD DE,MSGSV ; 'FILENAME? ' + RST 018h + LD DE,BUFER + CALL GETL + LD A,(DE) + CP #1B + JR NZ,LEAF3 + LD HL,ST1X + EX (SP),HL + RET + +LEAF3: + LD B,000h + LD DE,011ADh + LD HL,BUFER + LD A,(DE) + CP 00Dh + JR Z,LEB20 +LEB00: + CP 020h + JR NZ,LEB08 + INC DE + LD A,(DE) + JR LEB00 +LEB08: + CP 022h + JR Z,LEB14 +LEB0C: + LD (HL),A + INC HL + INC B + LD A,011h + CP B + JR Z,FNINP +LEB14: + INC DE + LD A,(DE) + CP 022h + JR Z,LEB1E + CP 00Dh + JR NZ,LEB0C +LEB1E: + LD A,00dh +LEB20: + LD (HL),A + RET + +LEB22: + LD A,(0F000h) + OR A + RET + + +LEB27: DB "IPL IS LOADING ",00Dh +LEB37: DB "MAKE READY QD",00Dh +DISCLR: DB "** MONITOR 9Z-503M **",00Dh + +; +;==================================== +; +; QUICK DISK LOAD COMMAND +; +;==================================== +; +QL: + CALL IOFRS + CALL QDRCK ; Ready check + JR C,LEBAC + CALL FNINP ; Input filename + CALL HDPCL ; Head point clear +; +; Disp 'Loading...' +; + LD DE,MSG?2 ; 'LOADING ' + RST 018h +; +; File search +; +FILESH: + CALL FILSCH + JR C,LEBAC +; +; Atribute check +; + LD A,(ATRB) + CP OBJCD + JR NZ,FILESH +; +; +; +DSFLNA: + LD DE,NAME + RST 018h + + LD HL,(EXADR) + LD A,H + OR L + JR NZ,LEB8B + LD HL,(COMNT) + LD A,H + OR L +LEB8B: + JR NZ,LPARA0 + LD A,0FFh + LD (0113Ah),A + + + +; +; Iocs parameter set +; + LD HL,01200h + JR LPARA1 +LPARA0: + LD HL,(EXADR) +LPARA1: + LD (QDPC),HL ; Data adrs set + LD HL,(DTADR) + LD (QDPE),HL + LD HL,00103h ; Read data block cmd. + LD (QDPA),HL ; QDPA = 3 (read from headpoint) + ; QDPB = 1 (data should be read) +; +; Read data block +; + CALL QDIOS ; QD iocs +LEBAC: + JP C,QER04 + LD A,(0113Ah) + CP 0FFh + JR Z,LEBBD +; +; Exec load file +; + LD BC,00300h + LD HL,(COMNT) + JP (HL) + +LEBBD: + OUT (0E0h),A + LD HL,01200h + LD DE,00000h + LD BC,(DTADR) + LDIR + LD BC,00300h + JP 00000h + +; +; Iocs flag reset +; +IOFRS: + XOR A + LD (MTF),A ; Motor Flag = 0 (OFF) + LD (FNUPS),A ; File number flag = 0 + LD (FNUPF),A ; File number up flag = 0 + RET + +; +; +; File search sub. +; +; +FILSCH: +; +; Iocs parameter set +; + LD HL,00003h ; read from headpoint + LD (QDPA),HL ; QDPA = 3 (read from head point) + ; QDPB = 0 (header should be read) + LD HL,ATRB ; Head adrs + LD (QDPC),HL + LD HL,00040h ; Read size + LD (QDPE),HL + +; +; Read information block +; +QLINF: + CALL QDIOS + RET C +; +; File name check +; + LD A,(BUFER) + CP 00Dh + RET Z + LD HL,BUFER + LD DE,NAME + LD B,NAMSIZ +LDFNCK: + LD A,(DE) + CP (HL) + JR NZ,QLINF + CP 00Dh + RET Z + INC DE + INC HL + DJNZ LDFNCK + RET +; +; Quick disk ready check +; +QDRCK: + XOR A + LD (QDPB),A ; QDPB = 0 -> only Ready check + INC A + LD (QDPA),A ; QDPA = 1 + CALL QDIOS + RET +; +;====================================== +; +; Quick disk directory command +; +;====================================== +; +QD: + CALL IOFRS + CALL QDRCK + JR C,QER04 + CALL HDPCL + LD B,000h +; +; Disp 'Directory of QD:' +; + LD DE,DIRMSG + RST 018h +; +; Iocs parameter set +; + LD HL,QDIRBF +DIRIOP: + LD (QDPC),HL + LD HL,00003h + LD (QDPA),HL ; QDPA = 3 (read from headpoint) + ; QDPB = 0 (header should be read) + LD HL,00040h + LD (QDPE),HL ; QDPE = 64 (header length) +; +; Read information block +; + PUSH BC + CALL QDIOS + POP BC + JR C,DIREFC + INC B +; +; Buffer adrs increment +; + LD HL,(QDPC) + LD DE,PRNT + ADD HL,DE + JR DIRIOP +; +; End file check +; +DIREFC: + CP NTFECD + JR Z,DIRMTF + SCF +QER04: + JR C,QERTRT +; +; Motor off +; +DIRMTF: + LD A,006h ; Motor off command + LD (QDPA),A + PUSH BC + CALL QDIOS + POP BC +; +; No file check +; + XOR A + CP B + JR NC,QDOKM +; +; Directory disp +; + CALL NL + LD HL,QDIRBF +; +; Disp atribute +; +DSPATR: + LD A,(HL) + LD DE,MSGQ01 + DEC A + JR Z,LECA4 + LD DE,MSGQ02 + DEC A + JR Z,LECA4 + LD DE,MSGQ03 + DEC A + JR Z,LECA4 + LD DE,MSGQ04 + DEC A + JR Z,LECA4 + LD DE,MSGQ05 + DEC A + JR Z,LECA4 + DEC A + JR Z,LECA1 + LD DE,MSGQ07 + DEC A + JR Z,LECA4 + DEC A + JR Z,LECA1 + DEC A + JR Z,LECA1 + LD DE,MSGQ10 + DEC A + JR Z,LECA4 + LD DE,MSGQ11 + DEC A + JR Z,LECA4 +LECA1: + LD DE,MSGQ?? +LECA4: + RST 018h +; +; Disp file name +; +LECA5: + LD A,'"' + CALL PRNT + INC HL + PUSH HL + POP DE + RST 018h + LD A,'"' + CALL PRNT + CALL NL +; +; Counter decrement +; +LECB6: + LD DE,00011h + ADD HL,DE +LECBA: + CALL ?KEY + OR A + JR Z,LECBA + CALL ?BRK + JP Z,ST1X + DJNZ DSPATR + +QDOKM: + CALL NL + LD DE,MSGQOK + RST 018h + JP ST1X + +; +;====================================== +; +; Error treatment +; +;===================================== +; +QERTRT: + LD DE,MGNFE ; 'Not Found err' + CP NTFECD ; Not found err + JR Z,QERMF + LD DE,MGNRE ; 'Not ready' + CP QNTRCD ; Not ready + JR Z,QERMF + LD DE,MGUFE ; 'Unformat' + CP UNFMCD ; Unformat err + JR Z,QERMF + LD DE,MSGTRM + CP BRKCD ; Break + JR Z,QERMF + LD DE,MGHDE ; 'Hard error' +; +; Motor off +; +QERMF: + LD A,006h ; Motor off cmd. + LD (QDPA),A + CALL QDIOS + CALL HDPCL +; +LECFC: + LD A,(QDCPA) + RRA + RET C ; Boot err + CALL NL + RST 018h + JP ST1X +; +; Header point clear +; +HDPCL: + LD A,005h ; Head point clear cmd. + LD (QDPA),A + CALL QDIOS + RET + +; +;====================================== +; +; Message table +; +;====================================== +; +MSGQOK: DB "OK!" +MSGTRM: DB 00Dh +MGNFE: DB "QD:FILE NOT FOUND",00Dh +MGHDE: DB "QD:HARD ERR",00Dh +MGNRE: DB "QD:NOT READY",00Dh +MGUFE: DB "QD:UNFORMAT",00Dh +LED4C: DB "QD:FILE MODE ERR",00Dh +DIRMSG: DB "DIRECTORY OF QD:",00Dh +MSGQ01: DB " OBJ ",00Dh +MSGQ02: DB " BTX ",00Dh +MSGQ03: DB " BSD ",00Dh +MSGQ04: DB " BRD ",00Dh +MSGQ05: DB " RB ",00Dh +MSGQ07: DB " LIB ",00Dh +MSGQ10: DB " SYS ",00Dh +MSGQ11: DB " GR ",00Dh +MSGQ??: DB " ??? ",00Dh + + +QDIOS1: + LD A,005h ; Retry 4 + LD (RTYF),A +; +RTY: + DI + CALL QMEIN + EI + RET NC + PUSH AF + CP 028h + JR Z,RTY4 + CALL MTOF + POP AF + PUSH AF + CP 029h + JR NZ,RTY4 + LD HL,RTYF + DEC (HL) + JR Z,LEDF3 + POP AF + JR RTY +LEDF3: + CALL QDHPC +RTY4: + POP AF + RET + +QMEIN: + LD (RETSP),SP + LD A,(QDPA) + DEC A ; ready check (1) + JR Z,QDRC + DEC A ; format (2) + ; not implemented + DEC A ; read from headpoint (3) + JR Z,QDRD + DEC A ; save from headpoint (4) + ; not implemented + DEC A ; headpoint clear (5) + JR Z,QDHPC + JP MTOF ; else motor off +; +;====================================== +; +; Head Point Clear +; +;====================================== +; +QDHPC: + PUSH AF + XOR A + LD (HDPT),A + POP AF + RET +; +;================================= +; +; Ready Check +; +;================================= +; +QDRC: + LD A,(QDPB) ; QDPB = 0 -> only Ready check + JP QREDY +; +;================================= +; +; Read +; +;================================= +; +QDRD: + LD A,(MTF) ; A = Motor Flag + OR A ; test Motor Flag + CALL Z,MTON ; if Motor Flag = 0 then Motor On and go to home position + CALL HPS ; head point search + RET C + CALL BRKC ; check break key +; + CALL RDATANRCK ; read low-byte blocksize + LD C,A + CALL RDATANRCK ; read high-byte blocksize + LD B,A + LD HL,(QDPE) + SBC HL,BC ; + JP C,IOE41 + LD HL,(QDPC) +; +; Block Data Read +; +BDR: + CALL RDATANRCK ; read data + LD (HL),A ; save it + INC HL ; inc address + DEC BC ; dec counter + LD A,B + OR C + JR NZ,BDR ; counter not zero than read again + CALL RDCRC ; read checksum (3 bytes) + LD A,(QDPB) + BIT 0,A + JP NZ,MTOF + RET +; +; Head Point Search +; +HPS: + LD HL,FNB ; HL = next file number + DEC (HL) + JR Z,HPNFE ; Not found + CALL SYNCL2 ; read 2 bytes last is in A + LD C,A ; BLocKFLaG => C reg + LD A,(HDPT) ; A = destination head point position + LD HL,HDPT0 ; HL = address of the actual head point position + CP (HL) ; Search ok ? + JR NZ,HPS1 ; no, than make dummy block read + INC A ; HDPT count up + LD (HDPT),A + LD (HL),A ; HDPT0 count up + LD A,(QDPB) ; A = filetype to load + XOR C ; xor with BLocKFLaG which + RRA + RET NC ; same, than ret else ... +; +; Dummy read +; +DMR: + CALL RDATANRCK ; read size low byte + LD C,A + CALL RDATANRCK ; read size high byte + LD B,A +; +DMR1: ; read size bytes + CALL RDATANRCK + DEC BC + LD A,B + OR C + JR NZ,DMR1 + CALL RDCRC ; read checksum (3 bytes) + JR HPS ; next +; +HPS1: + INC (HL) ; increment actual head point position + JR DMR +; +HPNFE: + LD A,NTFECD ; Not Found + SCF + RET + + + +; +; Ready & Write protect +; ACC = 0 : Ready check +; ACC = 1 : & Write Protect +; +QREDY: + LD B,A ; save command + LD A,002h + OUT (SIOBC),A ; select register 2 (IV) + LD A,081h + OUT (SIOBC),A ; write 81h in register 2 + LD A,002h + OUT (SIOBC),A ; select register 2 (IV) + IN A,(SIOBC) ; read back register 2 + AND 081h + CP 081h + JP NZ,IOE50 ; Not ready + LD A,010h + OUT (SIOAC),A ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0 + IN A,(SIOAC) + LD C,A ; save Read Register 0 + AND 008h ; test DCD (HeadSet) + JP Z,IOE50 ; Not ready + LD A,B ; restore command + OR A ; if command = 0 then + RET Z ; return + LD A,C ; else restore Read Register 0 + AND 020h ; test CTS (WriteProtect) + RET NZ ; if CTS then not protected, return + JP IOE46 ; else Write protect + +; +; +; MTON -- QD MOTOR ON +; READ FILE NUMBER +; READ & CHECK CRC,FLAG +; +MTON: + LD HL,SIOLD ; SIO Load Data + LD B,00Bh + CALL LSINT ; load SIO init and motor on and go to home position + + CALL SYNCL1 ; search for sync and read first 2 bytes, last is in A + LD (FNA),A ; save actual file no in File Number A + INC A + LD (FNB),A ; save next file no in File Number B + CALL RDCRC ; read checksum (3 bytes) +FNEND: + LD HL,SYNCF + SET 3,(HL) ; set bit3 of SyncFlags + XOR A ; A = 0 + LD (HDPT0),A ; actual head point position = 0 + RET +; +; sio initial +; +LSINT: + LD C,SIOAC + OTIR + LD A,005h ; 00000101 + LD (MTF),A ; MoTor Flag = 5 + OUT (SIOBC),A ; ch B select register 5 + LD A,080h ; 10000000 + OUT (SIOBC),A ; set DTR_B (Motor On), clear RTS_B + +LREDY: ; check for ready and if so, than goto home position + LD A,010h ; 00010000 + OUT (SIOAC),A ; reset ext/status interrupts, set register 0 + IN A,(SIOAC) ; read register 0 + AND 008h ; test DCD_A (disk inside ?) + JP Z,IOE50 ; Not ready + CALL BRKC ; BReak Key Check + LD A,010h ; 00010000 + OUT (SIOBC),A ; reset ext/status interrupts, set register 0 + IN A,(SIOBC) ; read register 0 + AND 008h ; test DCD_B (Home) + JR Z,LREDY + LD BC,000E9h ; wait 160ms + JP TIMW + +; +; Motor off +; +QDOFF: ; basic call +MTOF: + PUSH AF + LD A,005h + OUT (SIOAC),A ; select Write Register 5 + LD A,060h ; 01100000 + OUT (SIOAC),A ; DTR OFF (Motor Off), Tx DISABLE, RTS OFF (WRGA) + LD A,005h + OUT (SIOBC),A ; select Write Register 5 + XOR A ; 00000000 + LD (MTF),A ; Motor Flag = 0 + OUT (SIOBC),A ; DTR OFF (Motor Off), clear RTS_B + POP AF + RET + +; +; SYNCL1 -- LOAD F.N SYNC ONLY +; (SEND BREAK 110ms) +; SYNCL2 -- LOAD FIRST FILE SYNC +; (SEND BREAK 110ms) +; +SYNCL2: + LD A,058h ; 01011000 + ; RESET Rx CRC CHECKER, CHANNEL RESET, REGISTER 0 + LD B,00Bh ; 11 values to load + LD HL,SIOLD + CALL SYNCA + LD HL,SYNCF + BIT 3,(HL) ; test bit3 of SyncFlags + LD BC,00003h ; WAIT 2ms + JR Z,TMLPL + RES 3,(HL) ; reset bit3 of SyncFlags +SYNCL1: + ld bc,000a0h ; WAIT 110ms +; +TMLPL: ; the motor is switched on + ; and a hunt phase is initiated, + ; that means the incoming datastream + ; is inspected for the programmed + ; sync characters + CALL TIMW + LD A,005h + OUT (SIOBC),A ; select Write Register 5 + LD A,082h ; 10000010 + OUT (SIOBC),A ; DTR ON (Motor On), RTS ON () + LD A,003h + OUT (SIOAC),A ; select Write Register 3 + LD A,0D3h ; 11010011 + OUT (SIOAC),A ; RX 8 BIT, ENTER HUNT PHASE, SYNC, Rx ENABLE + LD BC,02CC0h ; 220ms timeout +; +SYNCW0: ; now the datastream is inspected + ; also a timeout is checked + LD A,010h + OUT (SIOAC),A ; RESET EXT/STATUS INT, select Register 0 + IN A,(SIOAC) + AND 010h ; test SYNC/HUNT + JR Z,SYNCW1 ; first 2 syncbytes found + DEC BC + LD A,B + OR C + JR NZ,SYNCW0 + JP IOE54 ; unformatted +; +SYNCW1: ; now we should ignore further sync characters + LD A,003h + OUT (SIOAC),A ; select Write Register 3 + LD A,0C3h ; 11000011 + OUT (SIOAC),A ; Rx 8 BIT, SYNC CHAR LOAD INHIBIT, Rx ENABLE + LD B,09Fh ; timeout +; +SYNCW2: + ; loop for find the end of syncbytes: + ; rx available is only set if the first + ; byte is found which is not a syncbyte + LD A,010h + OUT (SIOAC),A ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0 + IN A,(SIOAC) + AND 001h ; test Rx CHARACTER AVAILABLE + JR NZ,SYNCW3 + DEC B + JR NZ,SYNCW2 +SYNCW01: + JP IOE54 ; unformated +; +SYNCW3: ; now the datastream is in sync and the + ; first real data is ready to read + LD A,003h + OUT (SIOAC),A ; select Write Register 3 + LD A,0C9h ; 11001001 + OUT (SIOAC),A ; Rx 8 BIT, Rx CRC ENABLE, Rx ENABLE + CALL RDATANRCK + JP RDATANRCK + +; +; +; +SYNCA: + LD C,SIOAC + OUT (C),A + LD A,005h + OUT (SIOBC),A ; select Write Register 5 + LD A,080h + OUT (SIOBC),A ; set DTR_B (Motor On), clear RTS_B + OTIR + RET + +; +; RDCRC -- READ CRC & CHECK +; +RDCRC: + LD B,003h ; 3 retries +RDCR1: + CALL RDATANRCK ; read 3 bytes + DJNZ RDCR1 +RDCR2: ; read REGISTER 0 + IN A,(SIOAC) + RRCA ; test Rx CHARACTER AVAILABLE + JR NC,RDCR2 ; Rx Available + LD A,001h + OUT (SIOAC),A ; select REGISTER 1 + IN A,(SIOAC) ; read REGISTER 1 + AND 040h ; test CRC ERROR + JR NZ,IOE41 ; Hard err + OR A + RET + +RDATANRCK: +NRCK: + LD A,010h + OUT (SIOAC),A ; reset ext/status interrupts, set register 0 + IN A,(SIOAC) ; read register 0 + AND 008h ; test DCD (HeadSet) + JP Z,IOE50 ; Not Ready +; +; Read data (1 chr) +; +RDATA: + IN A,(SIOAC) ; read REGISTER 0 + RLCA + JR C,IOE41 ; test BREAK/ABORT (Hard Err) + RRCA + RRCA + JR NC,NRCK ; test Rx AVAILABLE + IN A,(SIOAD) ; read data + OR A + RET + +; +; i/o err +; +IOE41: + LD A,HDERCD ; Hard err + DB 021h +IOE46: + LD A,WPRTCD ; Write protect + DB 021h +IOE50: + LD A,QNTRCD ; Not ready + DB 021h +IOE53: + LD A,NFSECD ; No file space + DB 021h +IOE54: + LD A,UNFMCD ; Unformat + LD SP,(RETSP) + SCF + RET + + +; +; wait timer +; +; +; BC = 0001H = 0.7ms ( 0.704ms) +; 0003H = 2.0ms ( 2.107ms) +; 001DH = 20.0ms ( 19.938ms) +; 00A0H = 110.0ms (110.050ms) +; 00E9H = 160.0ms (160.140ms) +; 0140H = 220.0ms (219.940ms) +; +; +TIMW: + PUSH AF +TIMW1: + LD A,086h +TIMW2: + DEC A + JR NZ,TIMW2 + DEC BC + LD A,B + OR C + JR NZ,TIMW1 + POP AF + RET + +; +; +; +; SIO CH A COMMAND CHAIN +; +; SIOLD -- LOAD INIT. DATA +; +; +; +; BiSync mode, uses 16h and 16h as sync characters +; the SIO works also in polling mode, no interrupt is generated +; +SIOLD: + DB 058h ; RESET Rx CRC CHECKER, CHANNEL RESET + DB 004h ; select Write Register 4 + DB 010h ; X1 CLOCK mode, 16 bit sync char, sync mode, no parity + DB 005h ; select Write Register 5 + DB 004h ; CRC-16 + DB 003h ; select Write Register 3 + DB 0D0h ; RX 8 BITS, AUTO ENABLES, ENTER HUNT PHASE + DB 006h ; select Write Register 6 + DB 016h ; set SYNC CHR(1) + DB 007h ; select Write Register 7 + DB 016h ; set SYNC CHR(2) + + +; +; +; BREAK CHECK +; +BRKC: + LD A,0E8h + LD (0E000h),A + NOP + LD A,(0E001h) + AND 081h + RET NZ + LD SP,(RETSP) + SCF + RET + + ld l,#41 + +; the following is only to get the original length of 4096 bytes + ALIGN 0F7FFh + DB 0FFh diff --git a/asm/mz80kfdif.asm b/asm/mz80kfdif.asm new file mode 100644 index 0000000..8dd073b --- /dev/null +++ b/asm/mz80kfdif.asm @@ -0,0 +1,661 @@ +; +; MZ-80K FDC ROM +; + ORG F000H +F000 00 NOP +F001 F3 DI +F002 AF XOR A +F003 329C11 LD (#119C),A ;clock off +F006 3EC3 LD A,#C3 ;JP code for error trap +F008 320B10 LD (#100B),A +F00B 215AF0 LD HL,#F05A ;error can't boot +F00E 220C10 LD (#100C),HL ;error trap +F011 11F09F LD DE,#9FF0 ;transfer 9 bytes from +F014 2187F0 LD HL,#F087 ;ROM to RAM for use +; +;IBT1 +; +F017 010900 IBT1: LD BC,#0009 ;by (IX+D) in reader +F01A EDB0 LDIR +F01C CD0900 CALL CRLF ;NL +F01F 117AF0 LD DE,MESS1 +F022 CD1500 CALL MESSAGE ;msg "BOOT DRIVE ?" +F025 11009F LD DE,BUFF2 +F028 CD0300 CALL USER ;get line +F02B 210C00 LD HL,#000C +F02E 19 ADD HL,DE ;skip around msg +F02F 7E LD A,(HL) ;pickup answer to prompt +F030 FE0D CP #0D ;CR ? +F032 2002 JR NZ,#F036 ;Z=CR assume drive 1 +F034 3E31 LD A,#31 ;ASCII for 1 +; +;IBT2 +; +F036 47 IBT2: LD B,A ;save driveno +F037 E6F0 AND #F0 ;take ASCII and convert +F039 FE30 CP #30 ;to numeric having +F03B 20DF JR NZ,IBT1 ;checked >1 & <=4 +F03D 78 LD A,B ;get driveno +F03E E60F AND #0F ;mask +F040 3D DEC A ;-1 00-03 +F041 FE04 CP #04 +F043 30D7 JR NC,IBT1 ;dud key, >=4, try again +F045 32F09F LD (#9FF0),A ;save drive no +F048 321110 LD (#1011),A ;save drive no +F04B DD21F09F LD IX,#9FF0 ;IX pointer to fdc parameters at 9FF0 + ;ready for disk read +F04F CD3BF1 CALL READER ;get boot records +F052 3A0098 LD A,(#9800) ;1st byte of input buffer of boot records +F055 FEC3 CP #C3 ;jump cmd? +F057 CA0098 JP Z,#9800 ;yes, execute to 9800 +; +;IBT3 +; +F05A 31F010 IBT3: LD SP,#10F0 ;no, reset stack +F05D CD0900 CALL CRLF ;NL +F060 116CF0 LD DE,MESS2 ;msg can't boot +F063 CD1500 CALL MESSAGE +F066 CDA7F0 CALL MOTOFF ;motor off +F069 C38200 JP MAINLP ;warm start, ret to monitor +; +;MESS2 +; +F06C 45523A43 MESS2: DB "ER:CAN'T BOOT" +F070 414E2754 +F074 20424F4F +F078 54 +F079 0D DB 0DH +; +;MESS1 +; +F07A 424F4F54 DB "BOOT DRIVE ?" +F07E 20445249 +F082 5645203F +F086 0D DB 0DH +; +;DDATA +;fdc parameters +; +F087 00 DB 00H ;drive no-1 +F088 00 DB 00H ;trk*2 remainder = head +F089 01 DB 01H ;sector no (range: 01 - 10) +F08A 00 DB 00H ;$80 = add 1 record to read to (F08B) +F08B 0700 DB 07H ;07H = 07*2 = 14 sectors to read, add 1 if (F08A = $80) +F08D 0098 DB 00H,98H ;9800H = load addr. +F08F 00 DB 00H ;no meaning +; +;MOTON +; +F090 C5 MOTON: PUSH BC ;starts motors +F091 01F808 LD BC,#08F8 +F094 ED78 IN A,(C) ;start motor +F096 010000 LD BC,#0000 +; +;WAIT1 +; +F099 0B WAIT1: DEC BC ;wait for motor to +F09A 00 NOP ;get up to speed +F09B 00 NOP +F09C 78 LD A,B +F09D B1 OR C +F09E 20F9 JR NZ,WAIT1 +F0A0 3E01 LD A,#01 +F0A2 320210 LD (MOTFLG),A ;01=on 00=off +F0A5 C1 POP BC +F0A6 C9 RET +; +;MOTOFF +; +F0A7 C5 MOTOFF: PUSH BC ;stop motors +F0A8 CDAEF1 CALL LNGDEL ;timed wait +F0AB 01F800 LD BC,#00F8 +F0AE ED78 IN A,(C) +F0B0 C1 POP BC +F0B1 C9 RET +; +;SKZERO +; +F0B2 CDBDF0 SKZERO: CALL DREADY ;seek track 0 +F0B5 AF XOR A +F0B6 D3F9 OUT (#F9),A ;clear track reg +F0B8 320010 LD (#1000),A +F0BB D3FA OUT (#FA),A ;send seek zero code +; +;DREADY +; +F0BD C5 DREADY: PUSH BC +F0BE 010000 LD BC,#0000 +; +;DRY1 +; +F0C1 DBF9 DRY1: IN A,(#F9) ;get DRDY, CRDY, RQM +F0C3 E603 AND #03 ;leave DRDY, CRDY +; +;DRY2 +; +F0C5 FE02 DRY2: CP #02 ;wait for DRDY & CRDY +F0C7 2002 JR NZ,WAIT2 ;no, =03 +F0C9 C1 POP BC ;yes, =02 +F0CA C9 RET +; +;WAIT2 +; +F0CB 0B WAIT2: DEC BC +F0CC 78 LD A,B +F0CD B1 OR C +F0CE 20F1 JR NZ,DRY1 +F0D0 C1 POP BC +F0D1 3E32 LD A,#32 +F0D3 320810 LD (#1008),A ;error 40 (not found) +F0D6 C30B10 JP #100B ;error can't boot +; +;STATUS +; +F0D9 DBFA STATUS: IN A,(#FA) ;read status +F0DB E6F0 AND #F0 +F0DD 07 RLCA +F0DE 30F9 JR NC,STATUS ;wait for CRDY +F0E0 E6F0 AND #F0 ;mask leave CRDY, S1, S2, S3 +F0E2 0F RRCA ;move right until S§ +F0E3 0F RRCA ;is in B0 +F0E4 0F RRCA +F0E5 0F RRCA +F0E6 B7 OR A ;clear flags +F0E7 C8 RET Z ;Z=ok +F0E8 FE0C CP #0C ;0C=drive not ready etc. +F0EA 2004 JR NZ,STS1 +F0EC 3E32 LD A,#32 ;error code 40 (not found) +F0EE 180A JR STS3 +; +STS1 +; +F0F0 FE04 STS1: CP #04 ;04=ID not found +F0F2 2004 JR NZ,STS2 +F0F4 3E36 LD A,#36 ;error code 54 (unformat error) +F0F6 1802 JR STS3 +; +;STS2 +; +F0F8 3E29 STS2: LD A,#29 +F0FA 320810 LD (#1008),A ;error code 41 disk hw error +F0FD 37 SCF +F0FE C9 RET +; +;PRMDRV +; +F0FF C5 PRMDRV: PUSH BC ;prime drive +F100 E5 PUSH HL +F101 CD90F0 CALL MOTON +F104 DD7E00 LD A,(IX+#00) ;get drive no-1 +F107 E603 AND #03 ;form drive code +F109 F61C OR #1C ;set TND, MOTOR, SELECT BIT +F10B 320110 LD (#1001),A ;keep drive code +F10E E60F AND #0F ;mask out TND +F110 47 LD B,A +F111 0EF8 LD C,#F8 +F113 ED60 IN H,(C) ;select drive +F115 3E32 LD A,#32 +; +;PRM1 +; +F117 CDAEF1 PRM1: CALL LNGDEL ;wait for head +F11A 3D DEC A :to load +F11B 20FA JR NZ,PRM1 +F11D 010000 LD BC,#0000 +; +;PRM2 +; +F120 DBF9 PRM2: IN A,(#F9) ;get DRDY, CRDY, RQM +F122 E607 AND #07 ;mask out RUBBISH +F124 FE06 CP #06 ;DRDY & CRDY ? +F126 2006 JR NZ,PRM3 ;NZ=no, keep trying +F128 CDB2F0 CALL SKZERO +F12B E1 POP HL +F12C C1 POP BC +F12D C9 RET ;correct exit +; +;PRM3 +; +F12E 0B PRM3: DEC BC +F12F 78 LD A,B +F130 B1 OR C +F131 20ED JR NZ,PRM2 +F133 3E32 LD A,#32 +F135 320810 LD (#1008),A ;error 40 (not found) +F138 C30B10 JP #100B ;abort; error can't boot +; +;READER +; +F13B 3E0A READER: LD A,#0A ;no. of tries +F13D 320710 LD (#1007),A +; +;RDR1 +; +F140 CDFFF0 RDR1: CALL PRMDRV +F143 3A0110 LD A,(#1001) ;keep drive in use +F146 47 LD B,A +F147 0EF8 LD C,#F8 +F149 D9 EXX ;save all regs +F14A 0EFB LD C,#FB ;port fb?? +F14C DD5E03 LD E,(IX+#03) ;no meaning +F14F DD5604 LD D,(IX+#04) ;get half of numbers to read (7) +F152 CB13 RL E ;B7 to carry +F154 CB12 RL D ;double number of sectors (14), add carry +F156 1E03 LD E,#03 ;no meaning +F158 DD6E05 LD L,(IX+#05) ;get loading address lo +F15B DD6606 LD H,(IX+#06) ;hi into HL +F15E CDBDF0 CALL DREADY +F161 AF XOR A ;no meaning +F162 DD7E01 LD A,(IX+#01) ;get track to read +F165 1F RRA ;divide by 2, remainder to carry = head no. +F166 D3F9 OUT (#F9),A ;send track to FDC +F168 DD7E02 LD A,(IX+#02) ;sector number +F16B 3002 JR NC,RDR2 +F16D F680 OR #80 ;odds/evens for side code +; +;RDR2 +; +F16F D3F8 RDR2: OUT (#F8),A ;send sect+side +F171 CDA6F1 CALL SHTDEL ;short delay +F174 3E70 LD A,#70 ;seek & read code +F176 320010 LD (#1000),A ;keep it +F179 F3 DI +F17A D3FA OUT (#FA),A ;send seek & read code to FDC +; +;RDR3 +; +F17C 0680 RDR3: LD B,#80 ;128 bytes/sector +; +;RDR4 +; +F17E DBF9 RDR4: IN A,(#F9) ;get DRDY, CRDY, RQM +F180 A3 AND E ;mask with 03 +F181 28FB JR Z,RDR4 ;wait for either CRDY/RQM +F183 0F RRCA ;RQM into carry +F184 300C JR NC,RDR5 ;NC=no RQM +F186 EDA2 INI ;get data. port FB to (HL), B=B-1 +F188 C27EF1 JP NZ,RDR4 ;do whole sector +F18B 15 DEC D ;dec sector counter +F18C C27CF1 JP NZ,RDR3 ;NZ=more to do +F18F D9 EXX ;restore all regs +F190 ED78 IN A,(C) ;send TND high +; +;RDR5 +; +F192 CDD9F0 RDR5: CALL STATUS +F195 D0 RET NC ;NC=good read +F196 3A0710 LD A,(#1007) +F199 3D DEC A ;A try gone +F19A 320710 LD (#1007),A ;counter 10times +F19D CA0B10 JP Z,#100B ;can't read at all abort +F1A0 CDB2F0 CALL SKZERO +F1A3 C340F1 JP RDR1 +; +;SHTDEL +; +F1A6 F5 SHTDEL: PUSH AF +F1A7 3E0A LD A,#0A +; +;SDY1 +; +F1A9 3D SDY1: DEC A +F1AA 20FD JR NZ,SDY1 +F1AC F1 POP AF +F1AD C9 RET +; +;LNGDEL +; +F1AE F5 LNGDEL: PUSH AF ;long delay +F1AF 3E0A LD A,#0A +; +;LDY1 +; +F1B1 CDA6F1 LDY1: CALL SHTDEL +F1B4 3D DEC A +F1B5 20FA JR NZ,LDY1 +F1B7 F1 POP AF +F1B8 C9 RET + +CRLF: EQU 00009H +MESSAGE: EQU 00015H +BUFF2: EQU 9F00H +USER: EQU 00003H +MAINLP: EQU 00082H +MOTFLG: EQU 1002H + END + +; +;no meaning !! +; +F1B9 13 INC DE +F1BA 1B DEC DE +F1BB 72 LD (HL),D +F1BC DE42 SBC A,#42 +F1BE FB EI +F1BF 2F CPL +F1C0 58 LD E,B +F1C1 43 LD B,E +F1C2 7C LD A,H +F1C3 52 LD D,D +F1C4 3023 JR NC,#F1E9 ; (35) +F1C6 71 LD (HL),C +F1C7 42 LD B,D +F1C8 1020 DJNZ #F1EA ; (32) +F1CA 74 LD (HL),H +F1CB 40 LD B,B +F1CC 43 LD B,E +F1CD 03 INC BC +F1CE 51 LD D,C +F1CF 00 NOP +F1D0 3C INC A +F1D1 42 LD B,D +F1D2 D8 RET C +F1D3 60 LD H,B +F1D4 FB EI +F1D5 09 ADD HL,BC +F1D6 FC402C CALL M,#2C40 +F1D9 80 ADD A,B +F1DA 79 LD A,C +F1DB 2A4940 LD HL,(#4049) +F1DE 4D LD C,L +F1DF EE3E XOR #3E +F1E1 B2 OR D +F1E2 1EA2 LD E,#A2 +F1E4 58 LD E,B +F1E5 02 LD (BC),A +F1E6 58 LD E,B +F1E7 12 LD (DE),A +F1E8 02 LD (BC),A +F1E9 43 LD B,E +F1EA 02 LD (BC),A +F1EB 220002 LD (#0200),HL +F1EE 2D DEC L +F1EF 4B LD C,E +F1F0 5A LD E,D +F1F1 0A LD A,(BC) +F1F2 40 LD B,B +F1F3 4A LD C,D +F1F4 13 INC DE +F1F5 42 LD B,D +F1F6 45 LD B,L +F1F7 0A LD A,(BC) +F1F8 5B LD E,E +F1F9 6E LD L,(HL) +F1FA 6A LD L,D +F1FB 4E LD C,(HL) +F1FC 4E LD C,(HL) +F1FD 4E LD C,(HL) +F1FE 5D LD E,L +F1FF 7E LD A,(HL) +F200 3011 JR NC,#F213 ; (17) +F202 DD300E JR NC,#F213 ; (14) +F205 067E LD B,#7E +F207 FE3A CP #3A +F209 CAC221 JP Z,#21C2 +F20C 12 LD (DE),A +F20D 23 INC HL +F20E 13 INC DE +F20F 0D DEC C +F210 C20622 JP NZ,#2206 +F213 C3C221 JP #21C2 + +F216 3AB830 LD A,(#30B8) +F219 FEB1 CP #B1 +F21B CA4522 JP Z,#2245 +F21E 2A5030 LD HL,(#3050) +F221 CD1E20 CALL #201E +F224 7E LD A,(HL) +F225 FE27 CP #27 +F227 CA5722 JP Z,#2257 +F22A 3E84 LD A,#84 +F22C 327630 LD (#3076),A +F22F 3E02 LD A,#02 +F231 327730 LD (#3077),A +F234 CDCA13 CALL #13CA +F237 D24A22 JP NC,#224A +F23A 2E00 LD L,#00 +F23C 3EB2 LD A,#B2 +F23E 32C830 LD (#30C8),A +F241 7D LD A,L +F242 326F30 LD (#306F),A +F245 3E01 LD A,#01 +F247 C3C321 JP #21C3 + +F24A 3ABE30 LD A,(#30BE) +F24D FEC5 CP #C5 +F24F C23C22 JP NZ,#223C +F252 3EB0 LD A,#B0 +F254 C33E22 JP #223E + +F257 23 INC HL +F258 7E LD A,(HL) +F259 E67F AND #7F +F25B 6F LD L,A +F25C C33C22 JP #223C + +F25F 3AB830 LD A,(#30B8) +F262 FEB1 CP #B1 +F264 CA9022 JP Z,#2290 +F267 2A5030 LD HL,(#3050) +F26A CD1E20 CALL #201E +F26D 3E80 LD A,#80 +F26F 327630 LD (#3076),A +F272 3E01 LD A,#01 +F274 327730 LD (#3077),A +F277 CDCA13 CALL #13CA +F27A D29522 JP NC,#2295 +F27D 210000 LD HL,#0000 +F280 3E82 LD A,#82 +F282 32C830 LD (#30C8),A +F285 226330 LD (#3063),HL +F288 116F30 LD DE,#306F +F28B 7C LD A,H +F28C 12 LD (DE),A +F28D 13 INC DE +F28E 7D LD A,L +F28F 12 LD (DE),A +F290 3E02 LD A,#02 +F292 C3C321 JP #21C3 + +F295 3ABE30 LD A,(#30BE) +F298 FEC5 CP #C5 +F29A C2A222 JP NZ,#22A2 +F29D 3EB1 LD A,#B1 +F29F C38222 JP #2282 + +F2A2 CDEA1A CALL #1AEA +F2A5 C38222 JP #2282 + +F2A8 2A5030 LD HL,(#3050) +F2AB CD1E20 CALL #201E +F2AE 116F30 LD DE,#306F +F2B1 0600 LD B,#00 +F2B3 0E04 LD C,#04 +F2B5 7E LD A,(HL) +F2B6 23 INC HL +F2B7 FE27 CP #27 +F2B9 C2F822 JP NZ,#22F8 +F2BC 7E LD A,(HL) +F2BD FE27 CP #27 +F2BF C2DE22 JP NZ,#22DE +F2C2 3AB830 LD A,(#30B8) +F2C5 FEB1 CP #B1 +F2C7 CAD522 JP Z,#22D5 +F2CA AF XOR A +F2CB 21C830 LD HL,#30C8 +F2CE B8 CP B +F2CF CAD922 JP Z,#22D9 +F2D2 3EB3 LD A,#B3 +F2D4 77 LD (HL),A +F2D5 78 LD A,B +F2D6 C3C321 JP #21C3 + +F2D9 3EB4 LD A,#B4 +F2DB C3D422 JP #22D4 + +F2DE FE8D CP #8D +F2E0 CAF822 JP Z,#22F8 +F2E3 FE0A CP #0A +F2E5 CAF822 JP Z,#22F8 +F2E8 E67F AND #7F +F2EA 12 LD (DE),A +F2EB 23 INC HL +F2EC 13 INC DE +F2ED 04 INC B +F2EE 0D DEC C +F2EF C2BC22 JP NZ,#22BC +F2F2 117A30 LD DE,#307A +F2F5 C3BC22 JP #22BC + +F2F8 3E53 LD A,#53 +F2FA CD111C CALL #1C11 +F2FD C3C222 JP #22C2 + +F300 CDE511 CALL #11E5 +F303 CD0C20 CALL #200C +F306 FE3A CP #3A +F308 C26423 JP NZ,#2364 +F30B 2A5030 LD HL,(#3050) +F30E CD1E20 CALL #201E +F311 3E80 LD A,#80 +F313 327630 LD (#3076),A +F316 3E02 LD A,#02 +F318 327730 LD (#3077),A +F31B CDCA13 CALL #13CA +F31E DA2E23 JP C,#232E +F321 3ACC30 LD A,(#30CC) +F324 FE01 CP #01 +F326 C23123 JP NZ,#2331 +F329 3ECC LD A,#CC +F32B CD111C CALL #1C11 +F32E 210000 LD HL,#0000 +F331 3AB830 LD A,(#30B8) +F334 FEB1 CP #B1 +F336 CA6E23 JP Z,#236E +F339 FEB2 CP #B2 +F33B CAC221 JP Z,#21C2 +F33E 226330 LD (#3063),HL +F341 3EA2 LD A,#A2 +F343 32C830 LD (#30C8),A +F346 CDB51D CALL #1DB5 +F349 06DD LD B,#DD +F34B 30CD JR NC,#F31A ; (-51) +F34D E5 PUSH HL +F34E 1111DD LD DE,#DD11 +F351 300E JR NC,#F361 ; (14) +F353 067E LD B,#7E +F355 FE3A CP #3A +F357 CAC221 JP Z,#21C2 +F35A 12 LD (DE),A +F35B 23 INC HL +F35C 13 INC DE +F35D 0D DEC C +F35E C25423 JP NZ,#2354 +F361 C3C221 JP #21C2 + +F364 3E4E LD A,#4E +F366 CD111C CALL #1C11 +F369 3EB4 LD A,#B4 +F36B C3BF21 JP #21BF + +F36E EB EX DE,HL +F36F 2A4D31 LD HL,(#314D) +F372 2B DEC HL +F373 2B DEC HL +F374 2B DEC HL +F375 72 LD (HL),D +F376 23 INC HL +F377 73 LD (HL),E +F378 23 INC HL +F379 3680 LD (HL),#80 +F37B C3C221 JP #21C2 + +F37E CC44A0 CALL Z,#A044 +F381 41 LD B,C +F382 AC XOR H +F383 2842 JR Z,#F3C7 ; (66) +F385 C3A9F1 JP #F1A9 + +F388 0A LD A,(BC) +F389 CC44A0 CALL Z,#A044 +F38C 41 LD B,C +F38D AC XOR H +F38E 2844 JR Z,#F3D4 ; (68) +F390 C5 PUSH BC +F391 A9 XOR C +F392 F1 POP AF +F393 1A LD A,(DE) +F394 CC44A0 CALL Z,#A044 +F397 2842 JR Z,#F3DB ; (66) +F399 C3A9AC JP #ACA9 + +F39C 41 LD B,C +F39D F1 POP AF +F39E 02 LD (BC),A +F39F CC44A0 CALL Z,#A044 +F3A2 2844 JR Z,#F3E8 ; (68) +F3A4 C5 PUSH BC +F3A5 A9 XOR C +F3A6 AC XOR H +F3A7 41 LD B,C +F3A8 F1 POP AF +F3A9 12 LD (DE),A +F3AA CC44A0 CALL Z,#A044 +F3AD 41 LD B,C +F3AE AC XOR H +F3AF C9 RET + +F3B0 F2ED57 JP P,#57ED +F3B3 CC44A0 CALL Z,#A044 +F3B6 41 LD B,C +F3B7 AC XOR H +F3B8 D2F2ED JP NC,#EDF2 +F3BB 5F LD E,A +F3BC CC44A0 CALL Z,#A044 +F3BF C9 RET + +F3C0 AC XOR H +F3C1 41 LD B,C +F3C2 F2ED47 JP P,#47ED +F3C5 CC44A0 CALL Z,#A044 +F3C8 D2AC41 JP NC,#41AC +F3CB F2ED4F JP P,#4FED +F3CE CC44A0 CALL Z,#A044 +F3D1 53 LD D,E +F3D2 50 LD D,B +F3D3 AC XOR H +F3D4 48 LD C,B +F3D5 CCF1F9 CALL Z,#F9F1 +F3D8 CC44A0 CALL Z,#A044 +F3DB 53 LD D,E +F3DC 50 LD D,B +F3DD AC XOR H +F3DE C9 RET + +F3DF D8 RET C +F3E0 F2DDF9 JP P,#F9DD +F3E3 CC44A0 CALL Z,#A044 +F3E6 53 LD D,E +F3E7 50 LD D,B +F3E8 AC XOR H +F3E9 C9 RET + +F3EA 59 LD E,C +F3EB F2FDF9 JP P,#F9FD +F3EE 50 LD D,B +F3EF 55 LD D,L +F3F0 53 LD D,E +F3F1 48 LD C,B +F3F2 A0 AND B +F3F3 42 LD B,D +F3F4 C3F1C5 JP #C5F1 + +F3F7 50 LD D,B +F3F8 55 LD D,L +F3F9 53 LD D,E +F3FA 48 LD C,B +F3FB A0 AND B +F3FC 44 LD B,H +F3FD C5 PUSH BC +F3FE F1 POP AF +F3FF D5 PUSH DE \ No newline at end of file diff --git a/asm/quickdisk_mz-1e05.asm b/asm/quickdisk_mz-1e05.asm new file mode 100644 index 0000000..a8374b6 --- /dev/null +++ b/asm/quickdisk_mz-1e05.asm @@ -0,0 +1,620 @@ +; V1.10 +; +; To compile use: +; +; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor. +; +; Available from: +; - http://www.falstaff.demon.co.uk/cross.html +; - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip +; - and many Simtel mirrors. +; +; as80 -i -l -n -x2 -v -z mz-1e05.asm + + + + +; +;----< MFM Minifloppy control >---- +; +; +; Call condition +; +; Case of disk initialize +; Drive N = IX+0 (0 - 3) +; +; +; Case of sequential read & write +; Drive N = IX+0 (0 - 3) +; +; Sector addrs = IX+1,2 (0 - $045F) H C S +; (0 - 1119) -> 70 x 16 sectors -> 2 x 35 x 16 +; Byte size = IX+3,4 +; Address = IX+5,6 +; Next track = IX+7 +; Next sector = IX+8 +; Start track = IX+9 +; Start sector = IX+10 +; +; +; I/O Port address +; +CR EQU 0D8h ; CommandRegister +TR EQU 0D9h ; TrackRegister +SCR EQU 0DAh ; SeCtorRegister +DR EQU 0DBh ; DataRegister +DM EQU 0DCh ; DriveMotor +HS EQU 0DDh ; HeadSelect + + + +TIMST EQU 00033h + +; +; Subroutine work +; +BPRO EQU 0CF00h +BUF EQU 011A3h +BPARA EQU BPRO - 23 ; BootPARAmeter + + +CMD EQU BPARA + 11 ; CoMmanD +MTFG EQU CMD + 1 ; MoTorFlaG +CLBF0 EQU MTFG + 1 +CLBF1 EQU CLBF0 + 1 +CLBF2 EQU CLBF1 + 1 +CLBF3 EQU CLBF2 + 1 +VRFCNT EQU CLBF3 + 1 ; VeRiFyCouNT +STAFG EQU VRFCNT + 1 ; STAtusFlaG + +; Macro to align boundaries. +ALIGN: MACRO ?boundary, ?fill + DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, ?fill + ENDM + +; +; +;--------< Ercode map >-------- +; +; 50 : Not ready +; 41 : Data error +; Track 80 err +; Write protect err +; Seek err +; CRC err +; Lost data +; 54 : Unformat +; Recode not found +; 56 : Invalid data +; +; + + + ORG 0F000h + + +MZ_1E05: + NOP + LD HL,000ADh + JR L_F007 +FDX: + EX (SP),HL +L_F007: + LD (BPARA + 21),HL + XOR A + LD DE,0 + CALL TIMST + CALL FDCC ; FD i/o check + JP NZ,NOTIO + LD DE,BPARA ; destination address + LD HL,BOOT ; source address + LD BC,11 ; 11 bytes + LDIR ; copy +SJP: + LD IX,BPARA + CALL BREAD ; read from drive 0, sector 0, + ; + LD HL,BPRO ; compare this address + LD DE,IPLMC ; with the IPL MasterCode + LD B,7 ; this are 7 bytes : 3,'IPLPRO' +MCHECK: + LD C,(HL) + LD A,(DE) + CP C + JP NZ,MASTE ; not equal than MasterError + INC HL + INC DE + DJNZ MCHECK + ; else Master was found + LD DE,IPLM0 ; 'IPL IS LOADING' + RST 018h + LD DE,BPRO + 7 ; NAME + RST 018h + LD HL,(BPRO + 016h) ; TARGETADDRESS from BootBlock + LD A,H + OR L + JR NZ,L_F051 ; if it is != 0 than normal file + LD HL,(BPRO + 018h) ; TARGETADDRESS from BootBlock + LD A,H + OR L + JR Z,L_F057 ; if it is also 0 than ROM replace file +L_F051: + XOR A ; else normal file, + LD HL,(BPRO + 018h) ; TARGETADDRESS from BootBlock + JR L_F05C +L_F057: + LD A,0FFh ; target is at $0000, bankswitching is needed + LD HL,01200h ; for now use temporary buffer at $1200 +L_F05C: + LD (0CEFDh),A + + LD (IX + 5),L ; set the TargetAddress + LD (IX + 6),H + + LD HL,(BPRO + 014h) ; BYTE SIZE from BootBlock + LD (IX + 3),L + LD (IX + 4),H + + LD HL,(BPRO + 01Eh) ; START SECTOR from BootBlock + LD (IX + 1),L + LD (IX + 2),H +; + CALL BREAD + CALL MOFF + + LD A,(0CEFDh) + CP 0FFh + JR NZ,L_F093 + OUT (0E0h),A + LD HL,01200h ; SourceAddress + LD DE,(BPRO + 016h) ; TargetAddress + LD BC,(BPRO + 014h) ; ByteCounter + LDIR ; copy +L_F093: + LD BC,00200h ; Default code + LD HL,(BPRO + 018h) ; TARGET/EXECUTION ADDRESS from BootBlock + JP (HL) + +MASTE: + CALL MOFF + LD DE,ERRM1 ; 'NOT MASTER' + JR ERRTR1 +ERRTRT: + CP 50 +NOTIO: + LD DE,IPLM3 ; 'MAKE READY FD' + JR Z,ERRTR1 + LD DE,ERRM0 ; 'FD:LOADING ERROR' +ERRTR1: + CALL 00009h + RST 018h + LD SP,010EEh + LD HL,(BPARA + 21) + EX (SP),HL + RET +; +; +; PARAMETER SETTING +; +IPLMC: + DB 003h ; IPL MASTER FLAG + DB "IPLPRO" + +BOOT: + DB 000h ; DRIVE NO. + DW 00000h ; SECTOR ADDR. + DW 00100h ; IFM BYTE SIZE + DW BPRO ; IFM LOADING ADDR. + DW 00000h ; IX+7,8 (track 0, sector 0) + + + +ERRM1: + DB "FD:NOT MASTER",00Dh +IPLM0: + DB "IPL IS LOADING ",00Dh +IPLM3: + DB "MAKE READY FD",00Dh +ERRM0: + DB "FD:LOADING ERROR",00Dh + +FDCC: + LD A,0A5h + LD B,A + OUT (TR),A + CALL DLY80U + IN A,(TR) + CP B + RET + +L_F111: + DB 000h, 000h +; +; +; READY CHECK +; +READY: + LD A,(MTFG) + RRCA + CALL NC,MTON + LD A,(IX + 0) ; DRIVE NO SET + OR 084h + OUT (DM),A ; DRIVE SELECT MOTON + XOR A + LD (CMD),A + CALL DLY60M + LD HL,0 +REDY0: + DEC HL + LD A,H + OR L + JR Z,REDY1 + IN A,(CR) ; STATUS GET + CPL + RLCA + JR C,REDY0 + LD C,(IX + 0) + LD HL,CLBF0 + LD B,000h + ADD HL,BC + BIT 0,(HL) + JR NZ,REDY2 + CALL RCLB + SET 0,(HL) +REDY2: + RET + +REDY1: + LD A,032h + JP ERJMP +; +; +; MOTOR ON +; +MTON: + LD A,080h + OUT (DM),A + LD B,16 +MTD1: + CALL DLY60M + DJNZ MTD1 + LD A,1 + LD (MTFG),A + RET +; +; +; SEEK TREATMENT +; +SEEK: + LD A,01Bh ; 1x = SEEK, + CALL CMDOT1 ; load head, no verify, max stepping rate + AND 099h + RET +; +; +; MOTOR OFF +; +MOFF: + PUSH AF + CALL DLY1M ; 1000 US DELAY + XOR A + OUT (DM),A + LD (CLBF0),A + LD (CLBF1),A + LD (CLBF2),A + LD (CLBF3),A + LD (MTFG),A + POP AF + RET +; +; +; RECALIBRATION +; +RCLB: + LD A,00Bh ; 0x = RESTORE (seek track 0) + CALL CMDOT1 ; load head, no verify, max stepping rate + AND 085h + XOR 004h + RET Z + +L_F189: + JP STERROR +; +; +; COMMAND OUT ROUTINE +; +CMDOT1: + LD (CMD),A + CPL + OUT (CR),A + CALL BSYON + CALL DLY60M + IN A,(CR) + CPL + LD (STAFG),A + RET +; +; +; BUSY AND WAIT +; +BSYON: + PUSH DE + PUSH HL + CALL BSY0 +BSYON2: + LD HL,00000h +BSYON0: + DEC HL + LD A,H + OR L + JR Z,BSYON1 + IN A,(CR) + RRCA + JR NC,BSYON0 + POP HL + POP DE + RET +; +BSYON1: + DEC E + JR NZ,BSYON2 +BSYONE: + LD A,029h + POP HL + POP DE + JP ERJMP +; +BSYOFF: + PUSH DE + PUSH HL + CALL BSY0 +BSYOF2: + LD HL,00000h +BSYOF0: + DEC HL + LD A,H + OR L + JR Z,BSYOF1 + IN A,(CR) ; Status Register + RRCA + JR C,BSYOF0 + POP HL + POP DE + RET +; +BSYOF1: + DEC E + JR NZ,BSYOF2 + JR BSYONE +; +BSY0: + CALL DLY80U + LD E,007h + RET +; +; +; SEQUENTIAL READ +; +BREAD: + CALL CNVRT + CALL PARST1 ; HL = IX + 5,6 (TargetAddress) +RE8: + CALL SIDST + CALL SEEK + JP NZ,ERJMP + CALL PARST2 ; C = DataRegister + DI ; disable interrupts + LD A,094h ; 9x = READ SECTOR, multiple records + CALL CMDOT2 ; compare for side 0, 15ms delay, +RE6: ; disable side select compare + LD B,0 ; ByteCounter = 0, to load 256 bytes of the sector +RE4: + IN A,(CR) + RRCA + JR C,RE3 + RRCA + JR C,RE4 + INI ; (HL) = in(C), B = B - 1 , HL = HL + 1 + JR NZ,RE4 + + INC (IX + 8) ; NextSector = NextSector + 1 + LD A,(IX + 8) + CP 011h ; if NextSector = 17 + JR Z,L_F213 ; than end + DEC D ; else SectorCounter = SectorCounter - 1 + JR NZ,RE6 ; if SectorCounter = 0 + JR L_F214 ; than end +L_F213: + DEC D +L_F214: + CALL INTER +RE3: + EI ; enable interrupts + IN A,(CR) + CPL + LD (STAFG),A + AND 0FFh + JR NZ,STERROR + CALL ADJ ; adjust sector and track + JP Z,REND + LD A,(IX + 7) ; track + JR RE8 +REND: + LD A,080h + OUT (DM),A ; motor on + RET +; +; +; PARAMETER SET +; +; +PARST1: + CALL READY + LD D,(IX + 4) ; D = bytes to read (highbyte) (256 bytes) + LD A,(IX + 3) ; A = bytes to read (lowbyte) + OR A ; if A = 0 + JR Z,L_F23F ; than it's ok + INC D ; else read 256 bytes more (1 sector) +L_F23F: + LD A,(IX + 10) ; NextSector = StartSector + LD (IX + 8),A + + LD A,(IX + 9) ; NextTrack = StartTrack + LD (IX + 7),A + + LD L,(IX + 5) ; HL = TargetAddress + LD H,(IX + 6) + RET + +; +; +; SIZE SEEK SET +; +SIDST: + SRL A + CPL + OUT (DR),A + JR NC,L_F25D ; NC than Head 0 + LD A,1 ; else Head 1 + JR L_F25E +L_F25D: + XOR A +L_F25E: + CPL + OUT (HS),A ; set HeadSelect + RET +; +; +; TRACK & SECTOR SET +; +PARST2: + LD C,DR + LD A,(IX + 7) ; A = NextTrack + SRL A + CPL + OUT (TR),A + LD A,(IX + 8) ; A = NextSector + CPL + OUT (SCR),A + RET +; +; +; ADJUST SECT & TRACK +; +ADJ: + LD A,(IX + 8) ; A = NextSector + CP 17 ; if NextSector = 17 + JR NZ,L_F282 ; than the border is not reached + LD A,001h ; else + LD (IX + 8),A ; NextSector = 1 + INC (IX + 7) ; NextTrack = NextTrack + 1 +L_F282: + LD A,D + OR A + RET +; +; +; COMMAND OUT & WAIT +; +CMDOT2: + LD (CMD),A + CPL + OUT (CR),A + CALL BSYOFF + RET +; +; +; FORCE INTERRUPT +; +INTER: + LD A,0D8h + CPL + OUT (CR),A + CALL BSYON + RET + +; +; +; STATUS CHECK +; +STERROR: + LD A,(CMD) + CP 00Bh ; Restore (seek track 0) + JR Z,ERCK1 + CP 01Bh ; Seek + JR Z,ERCK1 + CP 0F4h ; Write track + JR Z,ERCK1 + LD A,(STAFG) + BIT 7,A + JR NZ,ERRET + BIT 6,A + JR NZ,ERRET1 + BIT 4,A + LD A,54 + JR NZ,ERJMP + JR ERRET1 +ERCK1: + LD A,(STAFG) + BIT 7,A + JR NZ,ERRET +ERRET1: + LD A,41 + JR ERJMP +ERRET: + LD A,50 +ERJMP: + CALL MOFF + JP ERRTRT +; +; +; SECTOR TO TRACK & SECTOR CONVERT +; +CNVRT: + LD B,0 ; TrackCounter = 0 + LD DE,16 ; 16 sectors per track + LD L,(IX + 1) ; HL = SectorAddress + LD H,(IX + 2) + XOR A +TRANS0: + SBC HL,DE ; SectorAddress - SectorPerTrack + JR C,TRANS1 ; if < 0 than ready + INC B ; else TrackCounter = TrackCounter + 1 + JR TRANS0 ; next try + +TRANS1: + ADD HL,DE ; undo the last substraction + LD H,B + INC L ; adjust sector (sector is 1..16 and not 0..15) + LD (IX + 9),H ; set StartTrack + LD (IX + 10),L ; set StartSector + RET + +; +; +; TIME DELAY ( 1m & 60m & 80u ) +; +DLY80U: + PUSH DE + LD DE,15 + JP DLYT + +DLY1M: + PUSH DE + LD DE,160 + JP DLYT + +DLY60M: + PUSH DE + LD DE,8230 +DLYT: + DEC DE + LD A,E + OR D + JR NZ,DLYT + POP DE + RET + + + ALIGN 0FFF0h, 000h + DB " 84.03.14 V1.0A" diff --git a/asm/quickdisk_mz-1e14.asm b/asm/quickdisk_mz-1e14.asm new file mode 100644 index 0000000..cb7910f --- /dev/null +++ b/asm/quickdisk_mz-1e14.asm @@ -0,0 +1,1484 @@ +; V1.01 +; +; To compile use: +; +; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor. +; +; Available from: +; - http://www.falstaff.demon.co.uk/cross.html +; - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip +; - and many Simtel mirrors. +; +; as80 -i -l -n -x2 -v mz-1e14.asm + + + + +SIOAD EQU 0F4h +SIOBD EQU 0F5h +SIOAC EQU 0F6h +SIOBC EQU 0F7h + + + +; RxD_A <- RDDT (ReaDDaTa) +; RxC_A <- (read data clock) +; TxD_A -> #WRDT (WRiteDaTa) +; TxC_A <- 6.5MHz / 4 / 16 = 101562,5Hz +; CTS_A <- #WRPR (WRitePRotect) +; RTS_A -> #WRGA (WRiteGAte) +; DCD_A <- #HDST (HeaDSeT (disk test) +; +; RTS_B -> (?) +; DCD_B <- #HOME () +; DTR_B -> #MTON (MoTorON) + + + + +GETL EQU 00003h +NL EQU 00009h +PRNT EQU 00012h +GETKY EQU 0001Bh +BRKEY EQU 0001Eh +CMY0 EQU 0005Bh +MSGE1 EQU 00147h +DOT4DE EQU 002A6h +?TMST EQU 00308h +SPHEX EQU 003B1h +SLPT EQU 003D5h +HLHEX EQU 00410h +_2HEX EQU 0041Fh +?WRI EQU 00436h +LLPT EQU 00470h +?WRD EQU 00475h +?RDI EQU 004D8h +?RDD EQU 004F8h +?VRFY EQU 00588h +NLPHL EQU 005FAh +?KEY EQU 008CAh +?PRTS EQU 00920h +MSGOK EQU 00942h +PRNT3 EQU 0096Ch +MSGSV EQU 0098Bh +MSG?2 EQU 009A0h +?BRK EQU 00A32h +?ADCN EQU 00BB9h +?BLNK EQU 00DA6h +?DPCT EQU 00DDCh + +BRKCD EQU 00 +NTFECD EQU 40 +HDERCD EQU 41 +WPRTCD EQU 46 +QNTRCD EQU 50 +NFSECD EQU 53 +UNFMCD EQU 54 + +ATRB EQU 010F0h +NAME EQU 010F1h +SIZE EQU 01102h +DTADR EQU 01104h +EXADR EQU 01106h +COMNT EQU 01108h + +NAMSIZ EQU 011h +OBJCD EQU 001h + ; QD command table +QDPA EQU 01130h ; QD code 1 +QDPB EQU 01131h ; QD code 2 +QDPC EQU 01132h ; QD header startaddress +QDPE EQU 01134h ; QD header length +QDCPA EQU 0113Bh ; QD error flag +HDPT EQU 0113Ch ; QD new headpoint possition +HDPT0 EQU 0113Dh ; QD actual headpoint possition +FNUPS EQU 0113Eh +FNUPF EQU 01140h +FNA EQU 01141h ; File Number A (actual file number) +FNB EQU 01142h ; File Number B (next file number) +MTF EQU 01143h ; QD motor flag +RTYF EQU 01144h +SYNCF EQU 01146h ; SyncFlags +RETSP EQU 01147h +DSPXY EQU 01171h +DPRNT EQU 01194h +SWRK EQU 0119Dh +BUFER EQU 011A3h +QDIRBF EQU 0CD90h + + + + ORG 0E800h + +MZ1E14: +LE800: + NOP + JP LE80A + JP ST1X +QDIOS: + JP QDIOS1 + +LE80A: + LD A,0C6h ; clear screen + CALL ?DPCT + XOR A + LD (DPRNT),A + DI + XOR A + LD DE,00000h + CALL ?TMST + LD A,001h + OUT (SIOBC),A ; select Write Register 1 + XOR A + OUT (SIOBC),A ; Rx INT DISABLE + CALL GETKY + CP 'M' + JR Z,MON + CP 'Q' + JR Z,QBT + CALL LEB22 ; check ROM at 0xF000 (FDD) + CALL Z,0F006h + JR QBT +; +;=============================== +; +; Quick disk boot-up +; +;=============================== +; +QBT: + CALL IOFRS ; IO Flag ReSet + CALL NL + CALL QDRCK ; QuickDisk Ready ChecK + JR C,LE868 + LD A,00Dh ; set filename to "" + LD (BUFER),A + CALL HDPCL ; HeaD Point CLear +; +; Error return set +; + LD A,001h + LD (QDCPA),A + LD HL,LE86B + LD SP,010EEh + EX (SP),HL +; +; + CALL FILSCH ; filesearch + JP C,LEBAC + LD A,(ATRB) + CP OBJCD ; is it an "OBJ" file + JR NZ,LE871 +; +; Quick disk boot +; + LD DE,LEB27 + RST 018h + JP DSFLNA + +LE868: + LD DE,LEB37 +LE86B: + CALL NL + RST 018h + JR LE87D +LE871: + LD A,006h ; Motor off + LD (QDPA),A + CALL QDIOS + LD DE,LED4C + RST 018h +LE87D: + CALL NL + +MON: + LD DE,DISCLR ; '** MONITOR 9Z-503M **' + RST 018h + + +ST1X: + CALL NL + LD A,'*' + CALL PRNT + LD DE,BUFER + CALL GETL +ST2X: + LD A,(DE) + INC DE + CP 00Dh + JR Z,ST1X + CP 'J' ; JUMP + JR Z,GOTOX + CP 'L' ; Load CMT + JR Z,LOADX + CP 'F' ; Floppy boot + JR Z,FDCK + CP 'B' ; Bell + JP Z,SGX + CP '#' + JP Z,LEA6A + CP 'P' ; Printer test + JP Z,PTESTX + CP 'M' ; Memory correction + JP Z,MCORX + CP 'S' ; Save CMT + JP Z,SAVEX + CP 'V' ; Verify + JP Z,VRFYX + CP 'D' ; Dump memory + JP Z,DUMPX + CP 'Q' ; Quick disk cmd. + JR NZ,ST2X +; +; Quick disk cmd. +; +QUICK: + LD HL,00000h + LD (0113Ah),HL + LD A,(DE) + CP 'L' ; Load QD + JP Z,QL + CP 'D' ; Directory + JP Z,QD +ST1X1: + JR ST1X + + +FDCK: + LD A,(DE) + CP 00Dh + JR NZ,ST1X1 + CALL LEB22 + CALL Z,0F006h + JR ST1X1 +?ERX: + CP 002h + JR Z,ST1X1 + CALL NL + LD DE,MSGE1 ; 'CHECK SUM ER.' + RST 018h + JR ST1X1 +BGETLX: + EX (SP),HL + POP BC + LD DE,BUFER + CALL GETL + LD A,(DE) + CP 01Bh + JR Z,ST1X1 + JP (HL) + +HEXIYX: + EX (SP),IY + POP AF + CALL HLHEX + JR C,ST1X1 + JP (IY) + +GOTOX: + CALL HEXIYX + JP (HL) + + +LOADX: + CALL ?RDI + JR C,?ERX + CALL NL + LD DE,MSG?2 ; 'LOADING ' + RST 018h + LD DE,NAME + RST 018h + XOR A + LD (BUFER),A + LD HL,(DTADR) + LD A,H + OR L + JR NZ,LE941 + LD HL,(EXADR) + LD A,H + OR L + JR NZ,LE941 + LD A,0FFh + LD (BUFER),A + LD HL,01200h + LD (DTADR),HL +LE941: + CALL ?RDD + JR C,?ERX + LD A,(BUFER) + CP 0FFh + JR Z,LE954 + LD BC,00100h + LD HL,(EXADR) + JP (HL) +LE954: + OUT (0E0h),A + LD HL,01200h + LD DE,00000h + LD BC,(SIZE) + LDIR + LD BC,00100h + JP 00000h + +PTESTX: + LD A,(DE) + CP '&' ; plotter test + JR NZ,PTST1X +PTST0X: + INC DE + LD A,(DE) + CP 'L' ; 40 in 1 line + JR Z,.LPTX + CP 'S' ; 80 in 1 line + JR Z,..LPTX + CP 'C' ; Pen change + JR Z,PENX + CP 'G' ; Graph mode + JR Z,PLOTX + CP 'T' ; Test + JR Z,PTRNX +; +PTST1X: + CALL PMSGX +ST1X2: + JP ST1X1 +.LPTX: + LD DE,LLPT ; 01-09-09-0B-0D + JR PTST1X +..LPTX: + LD DE,SLPT ; 01-09-09-09-0D + JR PTST1X +PTRNX: + LD A,004h ; Test pattern + JR LE999 +PLOTX: + LD A,002h ; Graph mode +LE999: + CALL LPRNTX + JR PTST0X +PENX: + LD A,01Dh ; 1 change code (text mode) + JR LE999 +; +; +; 1 char print to $LPT +; +; in: ACC print data +; +; +LPRNTX: + LD C,000h ; RDAX test + LD B,A ; print data store + CALL RDAX + LD A,B + OUT (0FFh),A ; data out + LD A,080h ; RDP high + OUT (0FEh),A + LD C,001h ; RDA test + CALL RDAX + XOR A ; RDP low + OUT (0FEh),A + RET +; +; $LPT msg. +; in: DE data low address +; 0D msg. end +; +PMSGX: + PUSH DE + PUSH BC + PUSH AF +PMSGX1: + LD A,(DE) ; ACC = data + CALL LPRNTX + LD A,(DE) + INC DE + CP 00Dh ; end ? + JR NZ,PMSGX1 + POP AF + POP BC + POP DE + RET +; +; RDA check +; +; BRKEY in to monitor return +; in: C RDA code +; +RDAX: + IN A,(0FEh) + AND 00Dh + CP C + RET Z + CALL BRKEY + JR NZ,RDAX + LD SP,ATRB + JR ST1X2 +; +; Memory correction +; command 'M' +; +MCORX: + CALL HEXIYX ; correction address +MCORX1: + CALL NLPHL ; corr. adr. print + CALL SPHEX ; ACC ASCII display + CALL ?PRTS ; space print + CALL BGETLX ; get data & check data + CALL HLHEX ; HLASCII(DE) + JR C,MCRX3 + CALL DOT4DE ; INC DE * 4 + INC DE + CALL _2HEX ; data check + JR C,MCORX1 + CP (HL) + JR NZ,MCORX1 + INC DE + LD A,(DE) + CP 00Dh ; not correction + JR Z,MCRX2 + CALL _2HEX ; ACCHL(ASCII) + JR C,MCORX1 + LD (HL),A ; data correct +MCRX2: + INC HL + JR MCORX1 +MCRX3: + LD H,B ; memory address + LD L,C + JR MCORX1 +; +; Programm save +; +; cmd. 'S' +; +SAVEX: + CALL HEXIYX ; Start address + LD (DTADR),HL ; data adress buffer + LD B,H + LD C,L + CALL DOT4DE + CALL HEXIYX ; End address + SBC HL,BC ; byte size + INC HL + LD (SIZE),HL ; byte size buffer + CALL DOT4DE + CALL HEXIYX ; execute address + LD (EXADR),HL ; buffer + CALL NL + LD DE,MSGSV ; 'FILENAME? ' + RST 018h + CALL BGETLX ; filename input + CALL DOT4DE + CALL DOT4DE + LD HL,NAME ; name buffer +SAVX1: + INC DE + LD A,(DE) + LD (HL),A ; filename trans. + INC HL + CP 00Dh ; end code + JR NZ,SAVX1 + LD A,OBJCD ; attribute: OBJ + LD (ATRB),A + CALL ?WRI +?ERX1: + JP C,?ERX + CALL ?WRD ; data + JR C,?ERX1 + CALL NL + LD DE,MSGOK ; 'OK!' + RST 018h +LEA5B: + JP ST1X + +VRFYX: + CALL ?VRFY + JP C,?ERX + LD DE,MSGOK ; 'OK!' + RST 018h + JR LEA5B +LEA6A: + JP CMY0 + +SGX: + LD A,(SWRK) + RRA + CCF + RLA + LD (SWRK),A +LEA76: + JR LEA5B + +DUMPX: + CALL HEXIYX + CALL DOT4DE + PUSH HL + CALL HLHEX + POP DE + JR C,LEAD6 +LEA85: + EX DE,HL +LEA86: + LD B,008h + LD C,017h + CALL NLPHL +LEA8D: + CALL SPHEX + INC HL + PUSH AF + LD A,(DSPXY) + ADD A,C + LD (DSPXY),A + POP AF + CP 020h + JR NC,LEAA0 + LD A,02Eh +LEAA0: + CALL ?ADCN + CALL PRNT3 + LD A,(DSPXY) + INC C + SUB C + LD (DSPXY),A + DEC C + DEC C + DEC C + PUSH HL + SBC HL,DE + POP HL + JR Z,LEAD3 + LD A,0F8h + LD (0E000h),A + NOP + LD A,(0E001h) + CP 0FEh + JR NZ,LEAC7 + CALL ?BLNK +LEAC7: + DJNZ LEA8D +LEAC9: + CALL ?KEY + OR A + JR Z,LEAC9 + CALL ?BRK + DB 020h +LEAD3: + DB 0B2h + + JR LEA76 +LEAD6: + LD HL,000A0h + ADD HL,DE + JR LEA85 + +FNINP: + CALL NL + LD DE,MSGSV ; 'FILENAME? ' + RST 018h + LD DE,BUFER + CALL GETL + LD A,(DE) + CP #1B + JR NZ,LEAF3 + LD HL,ST1X + EX (SP),HL + RET + +LEAF3: + LD B,000h + LD DE,011ADh + LD HL,BUFER + LD A,(DE) + CP 00Dh + JR Z,LEB20 +LEB00: + CP 020h + JR NZ,LEB08 + INC DE + LD A,(DE) + JR LEB00 +LEB08: + CP 022h + JR Z,LEB14 +LEB0C: + LD (HL),A + INC HL + INC B + LD A,011h + CP B + JR Z,FNINP +LEB14: + INC DE + LD A,(DE) + CP 022h + JR Z,LEB1E + CP 00Dh + JR NZ,LEB0C +LEB1E: + LD A,00dh +LEB20: + LD (HL),A + RET + +LEB22: + LD A,(0F000h) + OR A + RET + + +LEB27: DB "IPL IS LOADING ",00Dh +LEB37: DB "MAKE READY QD",00Dh +DISCLR: DB "** MONITOR 9Z-503M **",00Dh + +; +;==================================== +; +; QUICK DISK LOAD COMMAND +; +;==================================== +; +QL: + CALL IOFRS + CALL QDRCK ; Ready check + JR C,LEBAC + CALL FNINP ; Input filename + CALL HDPCL ; Head point clear +; +; Disp 'Loading...' +; + LD DE,MSG?2 ; 'LOADING ' + RST 018h +; +; File search +; +FILESH: + CALL FILSCH + JR C,LEBAC +; +; Atribute check +; + LD A,(ATRB) + CP OBJCD + JR NZ,FILESH +; +; +; +DSFLNA: + LD DE,NAME + RST 018h + + LD HL,(EXADR) + LD A,H + OR L + JR NZ,LEB8B + LD HL,(COMNT) + LD A,H + OR L +LEB8B: + JR NZ,LPARA0 + LD A,0FFh + LD (0113Ah),A + + + +; +; Iocs parameter set +; + LD HL,01200h + JR LPARA1 +LPARA0: + LD HL,(EXADR) +LPARA1: + LD (QDPC),HL ; Data adrs set + LD HL,(DTADR) + LD (QDPE),HL + LD HL,00103h ; Read data block cmd. + LD (QDPA),HL ; QDPA = 3 (read from headpoint) + ; QDPB = 1 (data should be read) +; +; Read data block +; + CALL QDIOS ; QD iocs +LEBAC: + JP C,QER04 + LD A,(0113Ah) + CP 0FFh + JR Z,LEBBD +; +; Exec load file +; + LD BC,00300h + LD HL,(COMNT) + JP (HL) + +LEBBD: + OUT (0E0h),A + LD HL,01200h + LD DE,00000h + LD BC,(DTADR) + LDIR + LD BC,00300h + JP 00000h + +; +; Iocs flag reset +; +IOFRS: + XOR A + LD (MTF),A ; Motor Flag = 0 (OFF) + LD (FNUPS),A ; File number flag = 0 + LD (FNUPF),A ; File number up flag = 0 + RET + +; +; +; File search sub. +; +; +FILSCH: +; +; Iocs parameter set +; + LD HL,00003h ; read from headpoint + LD (QDPA),HL ; QDPA = 3 (read from head point) + ; QDPB = 0 (header should be read) + LD HL,ATRB ; Head adrs + LD (QDPC),HL + LD HL,00040h ; Read size + LD (QDPE),HL + +; +; Read information block +; +QLINF: + CALL QDIOS + RET C +; +; File name check +; + LD A,(BUFER) + CP 00Dh + RET Z + LD HL,BUFER + LD DE,NAME + LD B,NAMSIZ +LDFNCK: + LD A,(DE) + CP (HL) + JR NZ,QLINF + CP 00Dh + RET Z + INC DE + INC HL + DJNZ LDFNCK + RET +; +; Quick disk ready check +; +QDRCK: + XOR A + LD (QDPB),A ; QDPB = 0 -> only Ready check + INC A + LD (QDPA),A ; QDPA = 1 + CALL QDIOS + RET +; +;====================================== +; +; Quick disk directory command +; +;====================================== +; +QD: + CALL IOFRS + CALL QDRCK + JR C,QER04 + CALL HDPCL + LD B,000h +; +; Disp 'Directory of QD:' +; + LD DE,DIRMSG + RST 018h +; +; Iocs parameter set +; + LD HL,QDIRBF +DIRIOP: + LD (QDPC),HL + LD HL,00003h + LD (QDPA),HL ; QDPA = 3 (read from headpoint) + ; QDPB = 0 (header should be read) + LD HL,00040h + LD (QDPE),HL ; QDPE = 64 (header length) +; +; Read information block +; + PUSH BC + CALL QDIOS + POP BC + JR C,DIREFC + INC B +; +; Buffer adrs increment +; + LD HL,(QDPC) + LD DE,PRNT + ADD HL,DE + JR DIRIOP +; +; End file check +; +DIREFC: + CP NTFECD + JR Z,DIRMTF + SCF +QER04: + JR C,QERTRT +; +; Motor off +; +DIRMTF: + LD A,006h ; Motor off command + LD (QDPA),A + PUSH BC + CALL QDIOS + POP BC +; +; No file check +; + XOR A + CP B + JR NC,QDOKM +; +; Directory disp +; + CALL NL + LD HL,QDIRBF +; +; Disp atribute +; +DSPATR: + LD A,(HL) + LD DE,MSGQ01 + DEC A + JR Z,LECA4 + LD DE,MSGQ02 + DEC A + JR Z,LECA4 + LD DE,MSGQ03 + DEC A + JR Z,LECA4 + LD DE,MSGQ04 + DEC A + JR Z,LECA4 + LD DE,MSGQ05 + DEC A + JR Z,LECA4 + DEC A + JR Z,LECA1 + LD DE,MSGQ07 + DEC A + JR Z,LECA4 + DEC A + JR Z,LECA1 + DEC A + JR Z,LECA1 + LD DE,MSGQ10 + DEC A + JR Z,LECA4 + LD DE,MSGQ11 + DEC A + JR Z,LECA4 +LECA1: + LD DE,MSGQ?? +LECA4: + RST 018h +; +; Disp file name +; +LECA5: + LD A,'"' + CALL PRNT + INC HL + PUSH HL + POP DE + RST 018h + LD A,'"' + CALL PRNT + CALL NL +; +; Counter decrement +; +LECB6: + LD DE,00011h + ADD HL,DE +LECBA: + CALL ?KEY + OR A + JR Z,LECBA + CALL ?BRK + JP Z,ST1X + DJNZ DSPATR + +QDOKM: + CALL NL + LD DE,MSGQOK + RST 018h + JP ST1X + +; +;====================================== +; +; Error treatment +; +;===================================== +; +QERTRT: + LD DE,MGNFE ; 'Not Found err' + CP NTFECD ; Not found err + JR Z,QERMF + LD DE,MGNRE ; 'Not ready' + CP QNTRCD ; Not ready + JR Z,QERMF + LD DE,MGUFE ; 'Unformat' + CP UNFMCD ; Unformat err + JR Z,QERMF + LD DE,MSGTRM + CP BRKCD ; Break + JR Z,QERMF + LD DE,MGHDE ; 'Hard error' +; +; Motor off +; +QERMF: + LD A,006h ; Motor off cmd. + LD (QDPA),A + CALL QDIOS + CALL HDPCL +; +LECFC: + LD A,(QDCPA) + RRA + RET C ; Boot err + CALL NL + RST 018h + JP ST1X +; +; Header point clear +; +HDPCL: + LD A,005h ; Head point clear cmd. + LD (QDPA),A + CALL QDIOS + RET + +; +;====================================== +; +; Message table +; +;====================================== +; +MSGQOK: DB "OK!" +MSGTRM: DB 00Dh +MGNFE: DB "QD:FILE NOT FOUND",00Dh +MGHDE: DB "QD:HARD ERR",00Dh +MGNRE: DB "QD:NOT READY",00Dh +MGUFE: DB "QD:UNFORMAT",00Dh +LED4C: DB "QD:FILE MODE ERR",00Dh +DIRMSG: DB "DIRECTORY OF QD:",00Dh +MSGQ01: DB " OBJ ",00Dh +MSGQ02: DB " BTX ",00Dh +MSGQ03: DB " BSD ",00Dh +MSGQ04: DB " BRD ",00Dh +MSGQ05: DB " RB ",00Dh +MSGQ07: DB " LIB ",00Dh +MSGQ10: DB " SYS ",00Dh +MSGQ11: DB " GR ",00Dh +MSGQ??: DB " ??? ",00Dh + + +QDIOS1: + LD A,005h ; Retry 4 + LD (RTYF),A +; +RTY: + DI + CALL QMEIN + EI + RET NC + PUSH AF + CP 028h + JR Z,RTY4 + CALL MTOF + POP AF + PUSH AF + CP 029h + JR NZ,RTY4 + LD HL,RTYF + DEC (HL) + JR Z,LEDF3 + POP AF + JR RTY +LEDF3: + CALL QDHPC +RTY4: + POP AF + RET + +QMEIN: + LD (RETSP),SP + LD A,(QDPA) + DEC A ; ready check (1) + JR Z,QDRC + DEC A ; format (2) + ; not implemented + DEC A ; read from headpoint (3) + JR Z,QDRD + DEC A ; save from headpoint (4) + ; not implemented + DEC A ; headpoint clear (5) + JR Z,QDHPC + JP MTOF ; else motor off +; +;====================================== +; +; Head Point Clear +; +;====================================== +; +QDHPC: + PUSH AF + XOR A + LD (HDPT),A + POP AF + RET +; +;================================= +; +; Ready Check +; +;================================= +; +QDRC: + LD A,(QDPB) ; QDPB = 0 -> only Ready check + JP QREDY +; +;================================= +; +; Read +; +;================================= +; +QDRD: + LD A,(MTF) ; A = Motor Flag + OR A ; test Motor Flag + CALL Z,MTON ; if Motor Flag = 0 then Motor On and go to home position + CALL HPS ; head point search + RET C + CALL BRKC ; check break key +; + CALL RDATANRCK ; read low-byte blocksize + LD C,A + CALL RDATANRCK ; read high-byte blocksize + LD B,A + LD HL,(QDPE) + SBC HL,BC ; + JP C,IOE41 + LD HL,(QDPC) +; +; Block Data Read +; +BDR: + CALL RDATANRCK ; read data + LD (HL),A ; save it + INC HL ; inc address + DEC BC ; dec counter + LD A,B + OR C + JR NZ,BDR ; counter not zero than read again + CALL RDCRC ; read checksum (3 bytes) + LD A,(QDPB) + BIT 0,A + JP NZ,MTOF + RET +; +; Head Point Search +; +HPS: + LD HL,FNB ; HL = next file number + DEC (HL) + JR Z,HPNFE ; Not found + CALL SYNCL2 ; read 2 bytes last is in A + LD C,A ; BLocKFLaG => C reg + LD A,(HDPT) ; A = destination head point position + LD HL,HDPT0 ; HL = address of the actual head point position + CP (HL) ; Search ok ? + JR NZ,HPS1 ; no, than make dummy block read + INC A ; HDPT count up + LD (HDPT),A + LD (HL),A ; HDPT0 count up + LD A,(QDPB) ; A = filetype to load + XOR C ; xor with BLocKFLaG which + RRA + RET NC ; same, than ret else ... +; +; Dummy read +; +DMR: + CALL RDATANRCK ; read size low byte + LD C,A + CALL RDATANRCK ; read size high byte + LD B,A +; +DMR1: ; read size bytes + CALL RDATANRCK + DEC BC + LD A,B + OR C + JR NZ,DMR1 + CALL RDCRC ; read checksum (3 bytes) + JR HPS ; next +; +HPS1: + INC (HL) ; increment actual head point position + JR DMR +; +HPNFE: + LD A,NTFECD ; Not Found + SCF + RET + + + +; +; Ready & Write protect +; ACC = 0 : Ready check +; ACC = 1 : & Write Protect +; +QREDY: + LD B,A ; save command + LD A,002h + OUT (SIOBC),A ; select register 2 (IV) + LD A,081h + OUT (SIOBC),A ; write 81h in register 2 + LD A,002h + OUT (SIOBC),A ; select register 2 (IV) + IN A,(SIOBC) ; read back register 2 + AND 081h + CP 081h + JP NZ,IOE50 ; Not ready + LD A,010h + OUT (SIOAC),A ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0 + IN A,(SIOAC) + LD C,A ; save Read Register 0 + AND 008h ; test DCD (HeadSet) + JP Z,IOE50 ; Not ready + LD A,B ; restore command + OR A ; if command = 0 then + RET Z ; return + LD A,C ; else restore Read Register 0 + AND 020h ; test CTS (WriteProtect) + RET NZ ; if CTS then not protected, return + JP IOE46 ; else Write protect + +; +; +; MTON -- QD MOTOR ON +; READ FILE NUMBER +; READ & CHECK CRC,FLAG +; +MTON: + LD HL,SIOLD ; SIO Load Data + LD B,00Bh + CALL LSINT ; load SIO init and motor on and go to home position + + CALL SYNCL1 ; search for sync and read first 2 bytes, last is in A + LD (FNA),A ; save actual file no in File Number A + INC A + LD (FNB),A ; save next file no in File Number B + CALL RDCRC ; read checksum (3 bytes) +FNEND: + LD HL,SYNCF + SET 3,(HL) ; set bit3 of SyncFlags + XOR A ; A = 0 + LD (HDPT0),A ; actual head point position = 0 + RET +; +; sio initial +; +LSINT: + LD C,SIOAC + OTIR + LD A,005h ; 00000101 + LD (MTF),A ; MoTor Flag = 5 + OUT (SIOBC),A ; ch B select register 5 + LD A,080h ; 10000000 + OUT (SIOBC),A ; set DTR_B (Motor On), clear RTS_B + +LREDY: ; check for ready and if so, than goto home position + LD A,010h ; 00010000 + OUT (SIOAC),A ; reset ext/status interrupts, set register 0 + IN A,(SIOAC) ; read register 0 + AND 008h ; test DCD_A (disk inside ?) + JP Z,IOE50 ; Not ready + CALL BRKC ; BReak Key Check + LD A,010h ; 00010000 + OUT (SIOBC),A ; reset ext/status interrupts, set register 0 + IN A,(SIOBC) ; read register 0 + AND 008h ; test DCD_B (Home) + JR Z,LREDY + LD BC,000E9h ; wait 160ms + JP TIMW + +; +; Motor off +; +QDOFF: ; basic call +MTOF: + PUSH AF + LD A,005h + OUT (SIOAC),A ; select Write Register 5 + LD A,060h ; 01100000 + OUT (SIOAC),A ; DTR OFF (Motor Off), Tx DISABLE, RTS OFF (WRGA) + LD A,005h + OUT (SIOBC),A ; select Write Register 5 + XOR A ; 00000000 + LD (MTF),A ; Motor Flag = 0 + OUT (SIOBC),A ; DTR OFF (Motor Off), clear RTS_B + POP AF + RET + +; +; SYNCL1 -- LOAD F.N SYNC ONLY +; (SEND BREAK 110ms) +; SYNCL2 -- LOAD FIRST FILE SYNC +; (SEND BREAK 110ms) +; +SYNCL2: + LD A,058h ; 01011000 + ; RESET Rx CRC CHECKER, CHANNEL RESET, REGISTER 0 + LD B,00Bh ; 11 values to load + LD HL,SIOLD + CALL SYNCA + LD HL,SYNCF + BIT 3,(HL) ; test bit3 of SyncFlags + LD BC,00003h ; WAIT 2ms + JR Z,TMLPL + RES 3,(HL) ; reset bit3 of SyncFlags +SYNCL1: + ld bc,000a0h ; WAIT 110ms +; +TMLPL: ; the motor is switched on + ; and a hunt phase is initiated, + ; that means the incoming datastream + ; is inspected for the programmed + ; sync characters + CALL TIMW + LD A,005h + OUT (SIOBC),A ; select Write Register 5 + LD A,082h ; 10000010 + OUT (SIOBC),A ; DTR ON (Motor On), RTS ON () + LD A,003h + OUT (SIOAC),A ; select Write Register 3 + LD A,0D3h ; 11010011 + OUT (SIOAC),A ; RX 8 BIT, ENTER HUNT PHASE, SYNC, Rx ENABLE + LD BC,02CC0h ; 220ms timeout +; +SYNCW0: ; now the datastream is inspected + ; also a timeout is checked + LD A,010h + OUT (SIOAC),A ; RESET EXT/STATUS INT, select Register 0 + IN A,(SIOAC) + AND 010h ; test SYNC/HUNT + JR Z,SYNCW1 ; first 2 syncbytes found + DEC BC + LD A,B + OR C + JR NZ,SYNCW0 + JP IOE54 ; unformatted +; +SYNCW1: ; now we should ignore further sync characters + LD A,003h + OUT (SIOAC),A ; select Write Register 3 + LD A,0C3h ; 11000011 + OUT (SIOAC),A ; Rx 8 BIT, SYNC CHAR LOAD INHIBIT, Rx ENABLE + LD B,09Fh ; timeout +; +SYNCW2: + ; loop for find the end of syncbytes: + ; rx available is only set if the first + ; byte is found which is not a syncbyte + LD A,010h + OUT (SIOAC),A ; NULL CODE, RESET EXT/STATUS INT, REGISTER 0 + IN A,(SIOAC) + AND 001h ; test Rx CHARACTER AVAILABLE + JR NZ,SYNCW3 + DEC B + JR NZ,SYNCW2 +SYNCW01: + JP IOE54 ; unformated +; +SYNCW3: ; now the datastream is in sync and the + ; first real data is ready to read + LD A,003h + OUT (SIOAC),A ; select Write Register 3 + LD A,0C9h ; 11001001 + OUT (SIOAC),A ; Rx 8 BIT, Rx CRC ENABLE, Rx ENABLE + CALL RDATANRCK + JP RDATANRCK + +; +; +; +SYNCA: + LD C,SIOAC + OUT (C),A + LD A,005h + OUT (SIOBC),A ; select Write Register 5 + LD A,080h + OUT (SIOBC),A ; set DTR_B (Motor On), clear RTS_B + OTIR + RET + +; +; RDCRC -- READ CRC & CHECK +; +RDCRC: + LD B,003h ; 3 retries +RDCR1: + CALL RDATANRCK ; read 3 bytes + DJNZ RDCR1 +RDCR2: ; read REGISTER 0 + IN A,(SIOAC) + RRCA ; test Rx CHARACTER AVAILABLE + JR NC,RDCR2 ; Rx Available + LD A,001h + OUT (SIOAC),A ; select REGISTER 1 + IN A,(SIOAC) ; read REGISTER 1 + AND 040h ; test CRC ERROR + JR NZ,IOE41 ; Hard err + OR A + RET + +RDATANRCK: +NRCK: + LD A,010h + OUT (SIOAC),A ; reset ext/status interrupts, set register 0 + IN A,(SIOAC) ; read register 0 + AND 008h ; test DCD (HeadSet) + JP Z,IOE50 ; Not Ready +; +; Read data (1 chr) +; +RDATA: + IN A,(SIOAC) ; read REGISTER 0 + RLCA + JR C,IOE41 ; test BREAK/ABORT (Hard Err) + RRCA + RRCA + JR NC,NRCK ; test Rx AVAILABLE + IN A,(SIOAD) ; read data + OR A + RET + +; +; i/o err +; +IOE41: + LD A,HDERCD ; Hard err + DB 021h +IOE46: + LD A,WPRTCD ; Write protect + DB 021h +IOE50: + LD A,QNTRCD ; Not ready + DB 021h +IOE53: + LD A,NFSECD ; No file space + DB 021h +IOE54: + LD A,UNFMCD ; Unformat + LD SP,(RETSP) + SCF + RET + + +; +; wait timer +; +; +; BC = 0001H = 0.7ms ( 0.704ms) +; 0003H = 2.0ms ( 2.107ms) +; 001DH = 20.0ms ( 19.938ms) +; 00A0H = 110.0ms (110.050ms) +; 00E9H = 160.0ms (160.140ms) +; 0140H = 220.0ms (219.940ms) +; +; +TIMW: + PUSH AF +TIMW1: + LD A,086h +TIMW2: + DEC A + JR NZ,TIMW2 + DEC BC + LD A,B + OR C + JR NZ,TIMW1 + POP AF + RET + +; +; +; +; SIO CH A COMMAND CHAIN +; +; SIOLD -- LOAD INIT. DATA +; +; +; +; BiSync mode, uses 16h and 16h as sync characters +; the SIO works also in polling mode, no interrupt is generated +; +SIOLD: + DB 058h ; RESET Rx CRC CHECKER, CHANNEL RESET + DB 004h ; select Write Register 4 + DB 010h ; X1 CLOCK mode, 16 bit sync char, sync mode, no parity + DB 005h ; select Write Register 5 + DB 004h ; CRC-16 + DB 003h ; select Write Register 3 + DB 0D0h ; RX 8 BITS, AUTO ENABLES, ENTER HUNT PHASE + DB 006h ; select Write Register 6 + DB 016h ; set SYNC CHR(1) + DB 007h ; select Write Register 7 + DB 016h ; set SYNC CHR(2) + + +; +; +; BREAK CHECK +; +BRKC: + LD A,0E8h + LD (0E000h),A + NOP + LD A,(0E001h) + AND 081h + RET NZ + LD SP,(RETSP) + SCF + RET + + ld l,#41 + +; the following is only to get the original length of 4096 bytes +ALIGN: MACRO ?boundary + DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, 0FFh + ENDM + + ALIGN 0F7FFh + DB 0FFh diff --git a/asm/ramcheck.asm b/asm/ramcheck.asm new file mode 100644 index 0000000..dce76f5 --- /dev/null +++ b/asm/ramcheck.asm @@ -0,0 +1,155 @@ + +LETNL: EQU 0006h +PRNTS: EQU 000Ch +PRNT: EQU 0012h +MSG: EQU 0015h +MONIT: EQU 0086h +PRTHL: EQU 03BAh +PRTHX: EQU 03C3h +DPCT: EQU 0DDCh +MSTART: EQU 1200h + + ORG 10F0h + + DB 01h ; Code Type, 01 = Machine Code. + DB "RAM TEST V1.0", 0Dh, 00h, 00h ; Title/Name (17 bytes). + DW MSTART - START ; Size of program. + DW START ; Load address of program. + DW START ; Exec address of program. + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h ; Comment (104 bytes). + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h + DB 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h + + ORG 01200h + +START: LD DE,TITLE + CALL MSG + CALL LETNL + LD B, 20 ; Number of loops +LOOP: LD HL,MSTART ; Start of checked memory, + LD D,0CEh ; End memory check CE00 +LOOP1: LD A,000h + CP L + JR NZ,LOOP1b + CALL PRTHL ; Print HL as 4digit hex. + LD A,0C4h ; Move cursor left. + LD E,004h ; 4 times. +LOOP1a: CALL DPCT + DEC E + JR NZ,LOOP1a +LOOP1b: INC HL + LD A,H + CP D ; Have we reached end of memory. + JR Z,LOOP3 ; Yes, exit. + LD A,(HL) ; Read memory location under test, ie. 0. + CPL ; Subtract, ie. FF - A, ie FF - 0 = FF. + LD (HL),A ; Write it back, ie. FF. + SUB (HL) ; Subtract written memory value from A, ie. should be 0. + JR NZ,LOOP2 ; Not zero, we have an error. + LD A,(HL) ; Reread memory location, ie. FF + CPL ; Subtract FF - FF + LD (HL),A ; Write 0 + SUB (HL) ; Subtract 0 + JR Z,LOOP1 ; Loop if the same, ie. 0 +LOOP2: LD A,16h + CALL PRNT ; Print A + CALL PRTHX ; Print HL as 4 digit hex. + CALL PRNTS ; Print space. + XOR A + LD (HL),A + LD A,(HL) ; Get into A the failing bits. + CALL PRTHX ; Print A as 2 digit hex. + CALL PRNTS ; Print space. + LD A,0FFh ; Repeat but first load FF into memory + LD (HL),A + LD A,(HL) + CALL PRTHX ; Print A as 2 digit hex. + NOP + JR LOOP4 + +LOOP3: LD DE,OKCHECK + CALL MSG ; Print check message in DE + LD A,B ; Print loop count. + CALL PRTHX + LD DE,OKMSG + CALL MSG ; Print ok message in DE + DEC B + JR NZ,LOOP + LD DE,DONEMSG + CALL MSG ; Print check message in DE + JP MONIT + +OKCHECK: DB 11h + DB "CHECK: ", 0Dh +OKMSG: DB "OK.", 0Dh +DONEMSG: DB 11h + DB "RAM TEST COMPLETE.", 0Dh + +LOOP4: LD B,09h + CALL PRNTS ; Print space. + XOR A ; Zero A + SCF ; Set Carry +LOOP5: PUSH AF ; Store A and Flags + LD (HL),A ; Store 0 to bad location. + LD A,(HL) ; Read back + CALL PRTHX ; Print A as 2 digit hex. + CALL PRNTS ; Print space + POP AF ; Get back A (ie. 0 + C) + RLA ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB + DJNZ LOOP5 ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit. + XOR A ; Zero A, clears flags. + LD A,80h + LD B,08h +LOOP6: PUSH AF ; Repeat above but AND memory location with original A (ie. 80) + LD C,A ; Basically walk through all the bits to find which one is stuck. + LD (HL),A + LD A,(HL) + AND C + NOP + JR Z,LOOP8 ; If zero then print out the bit number + NOP + NOP + LD A,C + CPL + LD (HL),A + LD A,(HL) + AND C + JR NZ,LOOP8 ; As above, if the compliment doesnt yield zero, print out the bit number. +LOOP7: POP AF + RRCA + NOP + DJNZ LOOP6 + JP MONIT + +LOOP8: CALL LETNL ; New line. + LD DE,BITMSG ; BIT message + CALL MSG ; Print message in DE + LD A,B + DEC A + CALL PRTHX ; Print A as 2 digit hex, ie. BIT number. + CALL LETNL ; New line + LD DE,BANKMSG ; BANK message + CALL MSG ; Print message in DE + LD A,H + CP 50h ; 'P' + JR NC,LOOP9 ; Work out bank number, 1, 2 or 3. + LD A,01h + JR LOOP11 + +LOOP9: CP 90h + JR NC,LOOP10 + LD A,02h + JR LOOP11 + +LOOP10: LD A,03h +LOOP11: CALL PRTHX ; Print A as 2 digit hex, ie. BANK number. + JR LOOP7 + +BITMSG: DB " BIT: ", 0Dh +BANKMSG: DB " BANK: ", 0Dh + +TITLE: DB "SHARPMZ RAM TEST (C) P. SMART 2018", 0Dh, 00h diff --git a/asm/sa1510.asm b/asm/sa1510.asm new file mode 100644 index 0000000..952e62d --- /dev/null +++ b/asm/sa1510.asm @@ -0,0 +1,2788 @@ +; Disassembly of the file "sa1510.rom" +; + +; Configurable parameters. These are set in the wrapper file, ie monitor_SA1510.asm +; +;COLW: EQU 40 ; Width of the display screen (ie. columns). +;ROW: EQU 25 ; Number of rows on display screen. +;SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area. + + ORG 00000H +MONIT: JP START +GETL: JP ?GETL +LETNL: JP ?LTNL +NL: JP ?NL +PRNTS: JP ?PRTS +PRNTT: JP ?PRTT +PRNT: JP ?PRNT +MSG: JP ?MSG +MSGX: JP ?MSGX ; RST 3 +GETKY: JP ?GET +BRKEY: JP ?BRK +WRINF: JP ?WRI +WRDAT: JP ?WRD +RDINF: JP ?RDI +RDDAT: JP ?RDD +VERFY: JP ?VRFY +MELDY: JP ?MLDY +TIMST: JP ?TMST + NOP + NOP + JP 1038H ; Interrupt routine +TIMRD: JP ?TMRD +BELL: JP ?BEL +XTEMP: JP ?TEMP +MSTA: JP MLDST +MSTP: JP MLDSP +START: LD SP,STACK + IM 1 + CALL ?MODE + LD B,0FFH + LD HL,NAME + CALL ?CLER + LD A,016H + CALL PRNT + ;LD A,0CFH ; Original attribute is white background in colour mode. + LD A,071H ; MZ700 Blue background in colour mode. + LD HL,ARAM + JR STRT1 + JP 1035H ; NMI routine. +STRT1: CALL CLR8 + LD HL,TIMIN + LD A,0C3H + LD (1038H),A + LD (01039H),HL + LD A,004H + LD (TEMPW),A + CALL MLDSP + CALL NL + LD DE,00100H + RST 018H + IF MODE80C = 0 ; For 80 char mode we need a hook to setup SPAGE mode. + CALL ?BEL + ELSE + CALL HOOK ; Call new routine to setup SPAGE. + ENDIF +SS: LD A,0FFH +SS1: LD (SWRK),A + LD HL,0E800H + LD (HL),055H + JR FD2 + +ST1: CALL NL + LD A,02AH + CALL PRNT + LD DE,BUFER + CALL GETL +ST2: LD A,(DE) + INC DE + CP 00DH + JR Z,ST1 + CP 'J' ; JUMP? + JR Z,GOTO + CP 'L' ; LOAD? + JR Z,LOAD + CP 'F' ; FLOPPY? + JR Z,FD + CP 'B' ; BELL? + JR Z,SG + JR ST2 + + ; JUMP COMMAND +GOTO: CALL HLHEX + JR C,ST1 + JP (HL) + + ; KEY SOUND ON OFF +SG: LD A,(SWRK) + CPL + JR SS1 + + ; FLOPPY ROM CHECK AND RUN +FD: LD HL,0F000H +FD2: LD A,(HL) + OR A + JR NZ,ST1 + JP (HL) + +?ER: CP 002H + JR Z,ST1 + LD DE,MSGE1 + RST 018H + JR ST1 + + ; LOAD COMMAND +LOAD: CALL ?RDI + JR C,?ER + CALL NL + LD DE,MSG?2 + RST 018H + LD DE,NAME + RST 018H + CALL ?RDD + JR C,?ER + LD HL,(EXADR) + LD A,H + CP 012H + JR C,ST1 + JP (HL) + + ; LOADING +MSG?2: DB 04CH, 0B7H, 0A1H, 09CH + DB 0A6H, 0B0H, 097H, 020H + DB 00DH + + ; SIGN ON BANNER +MSG?3: DB "** MONITOR SA-1510 **", 0DH + + ; For 80 Character mode we need some space, so shorten the Check Sum Error message. + ; + ; CHECK SUM ERROR +MSGE1: IF MODE80C = 0 + DB 043H, 098H, 092H, 09FH, 0A9H, 020H, 0A4H, 0A5H + DB 0B3H, 020H, 092H, 09DH, 09DH, 0B7H, 09DH, 00DH + ELSE + DB "CK SUM?", 0DH + ENDIF + + ; Hook = 7 bytes. +HOOK: IF MODE80C = 1 + LD A,0FFH + LD (SPAGE),A + JP ?BEL ; Original called routine + ENDIF + + ; CR PAGE MODE1 +.CR: CALL .MANG + RRCA + JP NC,CURS2 + LD L,000H + INC H + CP ROW - 1 ; End of line? + JR Z,.CP1 + INC H + JP CURS1 + +.CP1: LD (DSPXY),HL + + ; SCROLLER +.SCROL: LD BC,SCRNSZ - COLW ; Scroll COLW -1 lines + LD DE,SCRN ; Start of the screen. + LD HL,SCRN + COLW ; Start of screen + 1 line. + LDIR + EX DE,HL + LD B,COLW ; Clear last line at bottom of screen. + CALL ?CLER + LD BC,0001AH + LD DE,MANG + LD HL,MANG + 1 + LDIR + LD (HL),000H + LD A,(MANG) + OR A + JP Z,?RSTR + LD HL,DSPXY + 1 + DEC (HL) + JR .SCROL + + + ; CTBL PAGE MODE1 +.CTBL: DW .SCROL + DW CURSD + DW CURSU + DW CURSR + DW CURSL + DW HOM0 + DW CLRS + DW DEL + DW INST + DW ALPHA + DW KANA + DW ?RSTR + DW REV + DW .CR + DW ?RSTR + DW ?RSTR + +?MLDY: PUSH BC + PUSH DE + PUSH HL + LD A,002H + LD (OCTV),A + LD B,001H +MLD1: LD A,(DE) + CP 00DH + JR Z,MLD4 + CP 0C8H + JR Z,MLD4 + CP 0CFH + JR Z,MLD2 + CP 02DH + JR Z,MLD2 + CP 02BH + JR Z,MLD3 + CP 0D7H + JR Z,MLD3 + CP 023H + LD HL,MTBL + JR NZ,MLD1A + LD HL,M?TBL + INC DE +MLD1A: CALL ONPU + JR C,MLD1 + CALL RYTHM + JR C,MLD5 + CALL MLDST + LD B,C + JR MLD1 +MLD2: LD A,003H +MLD2A: LD (OCTV),A + INC DE + JR MLD1 +MLD3: LD A,001H + JR MLD2A +MLD4: CALL RYTHM +MLD5: PUSH AF + CALL MLDSP + POP AF + JP RET3 + +ONPU: PUSH BC + LD B,008H + LD A,(DE) +ONP1A: CP (HL) + JR Z,ONP2 + INC HL + INC HL + INC HL + DJNZ ONP1A + SCF + INC DE + POP BC + RET + +ONP2: INC HL + PUSH DE + LD E,(HL) + INC HL + LD D,(HL) + EX DE,HL + LD A,H + OR A + JR Z,ONP2B + LD A,(OCTV) +ONP2A: DEC A + JR Z,ONP2B + ADD HL,HL + JR ONP2A +ONP2B: LD (RATIO),HL + LD HL,OCTV + LD (HL),002H + DEC HL + POP DE + INC DE + LD A,(DE) + LD B,A + AND 0F0H + CP 030H + JR Z,ONP2C + LD A,(HL) + JR ONP2D +ONP2C: INC DE + LD A,B + AND 00FH + LD (HL),A +ONP2D: LD HL,OPTBL + ADD A,L + LD L,A + LD C,(HL) + LD A,(TEMPW) + LD B,A + XOR A + JP L09AB + +MTBL: DB 043H + DB 077H + DB 007H + DB 044H + DB 0A7H + DB 006H + DB 045H + DB 0EDH + DB 005H + DB 046H + DB 098H + DB 005H + DB 047H + DB 0FCH + DB 004H + DB 041H + DB 071H + DB 004H + DB 042H + DB 0F5H + DB 003H + DB 052H + DB 000H + DB 000H +M?TBL: DB 043H + DB 00CH + DB 007H + DB 044H + DB 047H + DB 006H + DB 045H + DB 098H + DB 005H + DB 046H + DB 048H + DB 005H + DB 047H + DB 0B4H + DB 004H + DB 041H + DB 031H + DB 004H + DB 042H + DB 0BBH + DB 003H + DB 052H + DB 000H + DB 000H + +OPTBL: DB 001H + DB 002H + DB 003H + DB 004H + DB 006H + DB 008H + DB 00CH + DB 010H + DB 018H + DB 020H + +?SAVE: LD HL,FLSDT + LD (HL),0EFH + LD A,(KANAF) + OR A + JR Z,L0270 + LD (HL),0FFH +L0270: LD A,(HL) + PUSH AF + CALL ?PONT + LD A,(HL) + LD (FLASH),A + POP AF + LD (HL),A + XOR A + LD HL,KEYPA + LD (HL),A + CPL + LD (HL),A + RET + +MGP.I: PUSH AF + PUSH HL + LD HL,MGPNT + LD A,(HL) + INC A + CP 033H + JR NZ,L028F + XOR A +L028F: PUSH HL + LD L,A + LD A,(SPAGE) + OR A + LD A,L + POP HL + JR NZ,L029A + LD (HL),A +L029A: POP HL + POP AF + RET + +MGP.D: PUSH AF + PUSH HL + LD HL,MGPNT + LD A,(HL) + DEC A + JP P,L028F + LD A,032H + JR L028F +MLDST: LD HL,(RATIO) + LD A,H + OR A + JR Z,MLDSP + PUSH DE + EX DE,HL + LD HL,CONT0 + LD (HL),E + LD (HL),D + LD A,001H + POP DE + JR L02C4 +MLDSP: LD A,034H + LD (CONTF),A + XOR A +L02C4: LD (SUNDG),A + RET + +RYTHM: LD HL,KEYPA + LD (HL),0F0H + INC HL + LD A,(HL) + AND 081H + JR NZ,L02D5 + SCF + RET + +L02D5: LD A,(SUNDG) + RRCA + JR C,L02D5 +L02DB: LD A,(SUNDG) + RRCA + JR NC,L02DB + DJNZ L02D5 + XOR A + RET + +?BEL: PUSH DE + LD DE,00DB1H + RST 030H + POP DE + RET + +?TEMP: PUSH AF + PUSH BC + AND 00FH + LD B,A + LD A,008H + SUB B + LD (TEMPW),A + POP BC + POP AF + RET + +?TMST: DI + PUSH BC + PUSH DE + PUSH HL + LD (AMPM),A + LD A,0F0H + LD (TIMFG),A + LD HL,0A8C0H + XOR A + SBC HL,DE + PUSH HL + INC HL + EX DE,HL + LD HL,CONTF + LD (HL),074H + LD (HL),0B0H + DEC HL + LD (HL),E + LD (HL),D + DEC HL + LD (HL),00AH + LD (HL),000H + INC HL + INC HL + LD (HL),080H + DEC HL +L0323: LD C,(HL) + LD A,(HL) + CP D + JR NZ,L0323 + LD A,C + CP E + JR NZ,L0323 + DEC HL + NOP + NOP + NOP + LD (HL),00CH + LD (HL),07BH + INC HL + POP DE +L0336: LD C,(HL) + LD A,(HL) + CP D + JR NZ,L0336 + LD A,C + CP E + JR NZ,L0336 + POP HL + POP DE + POP BC + EI + RET + +?TMRD: PUSH HL + LD HL,CONTF + LD (HL),080H + DEC HL + DI + LD E,(HL) + LD D,(HL) + EI + LD A,E + OR D + JR Z,?TMR1 + XOR A + LD HL,0A8C0H + SBC HL,DE + JR C,?TMR2 + EX DE,HL + LD A,(AMPM) + POP HL + RET + +?TMR1: LD DE,0A8C0H +?TMR1A: LD A,(AMPM) + XOR 001H + POP HL + RET + +?TMR2: DI + LD HL,CONT2 + LD A,(HL) + CPL + LD E,A + LD A,(HL) + CPL + LD D,A + EI + INC DE + JR ?TMR1A + +TIMIN: PUSH AF + PUSH BC + PUSH DE + PUSH HL + LD HL,AMPM + LD A,(HL) + XOR 001H + LD (HL),A + LD HL,CONTF + LD (HL),080H + DEC HL + PUSH HL + LD E,(HL) + LD D,(HL) + LD HL,0A8C0H + ADD HL,DE + DEC HL + DEC HL + EX DE,HL + POP HL + LD (HL),E + LD (HL),D + POP HL + POP DE + POP BC + POP AF + EI + RET + +.DSP03: EX DE,HL + LD (HL),001H + INC HL + LD (HL),000H + JP CURSR +.MANG2: LD A,(DSPXY + 1) + ADD A,L + LD L,A + LD A,(HL) + INC HL + RL (HL) + OR (HL) + RR (HL) + RRCA + EX DE,HL + LD HL,(DSPXY) + RET + + LD C,H + POP AF + LD A,H + CALL L03C3 + LD A,L + JR L03C3 + LD B,E + LD B,E +L03C3: PUSH AF + RRCA + RRCA + RRCA + RRCA + CALL ASC + CALL PRNT + POP AF + CALL ASC + JP PRNT +L03D5: POP DE + POP HL + POP BC + POP AF + RET + +ASC: AND 00FH + CP 00AH + JR C,NOADD + ADD A,007H +NOADD: ADD A,030H + RET + +HEXJ: CP 030H + RET C + CP 03AH + JR C,HEX1 + SUB 007H + CP 040H + JR NC,HEX2 +HEX1: AND 00FH + RET +HEX2: SCF + RET + + ; Unused memory. + LD C,B + LD C,H + +HEX: JR HEXJ + +HOME: LD HL,(DSPXY) + LD A,(MGPNT) + SUB H + JR NC,HOM1 + ADD A,032H +HOM1: LD (MGPNT),A +HOM0: LD HL,00000H + JP CURS3 + + ; Unused memory. + INC L + +HLHEX: PUSH DE + CALL L041F + JR C,L041D + LD H,A + CALL L041F + JR C,L041D + LD L,A +L041D: POP DE + RET + +L041F: PUSH BC + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + RRCA + RRCA + RRCA + RRCA + LD C,A + LD A,(DE) + INC DE + CALL HEX + JR C,L0434 + OR C +L0434: POP BC + RET + +?WRI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H + LD E,0CCH + LD HL,STACK + LD BC,00080H +L0444: CALL L071A + CALL MOTOR + JR C,L0464 + LD A,E + CP 0CCH + JR NZ,L045E + CALL NL + PUSH DE + LD DE,MSG?7 ; Writing Message + RST 018H + LD DE,NAME + RST 018H + POP DE +L045E: CALL L077A + CALL L0485 +L0464: JP L0552 + + ; Writing +MSG?7: DB 057H, 09DH, 0A6H, 096H, 0A6H + DB 0B0H, 097H, 020H, 00DH + +?WRD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H + LD E,053H + LD BC,(SIZE) + LD HL,(DTADR) + LD A,B + OR C + JR Z,L04CB + JR L0444 +L0485: PUSH DE + PUSH BC + PUSH HL + LD D,002H + LD A,0F0H + LD (KEYPA),A +L048F: LD A,(HL) + CALL L0767 + LD A,(KEYPB) + AND 081H + JP NZ,L049E + SCF + JR L04CB +L049E: INC HL + DEC BC + LD A,B + OR C + JP NZ,L048F + LD HL,(SUMDT) + LD A,H + CALL L0767 + LD A,L + CALL L0767 + CALL L0D57 + DEC D + JP NZ,L04BB + OR A + JP L04CB +L04BB: LD B,000H +L04BD: CALL L0D3E + DEC B + JP NZ,L04BD + POP HL + POP BC + PUSH BC + PUSH HL + JP L048F +L04CB: POP HL + POP BC + POP DE + RET + +?RDI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H + LD E,0CCH + LD BC,00080H + LD HL,STACK +L04DD: CALL MOTOR + JP C,L0570 + CALL TMARK + JP C,L0570 + CALL L0505 + JP L0552 + +?RDD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2H + LD E,053H + LD BC,(SIZE) + LD HL,(DTADR) + LD A,B + OR C + JP Z,L0552 + JR L04DD +L0505: PUSH DE + PUSH BC + PUSH HL + LD H,002H +L050A: LD BC,KEYPB + LD DE,KEYPC +L0510: CALL EDGE + JP C,L0570 + CALL DLY3 + LD A,(DE) + AND 020H + JP Z,L0510 + LD D,H + LD HL,00000H + LD (SUMDT),HL + POP HL + POP BC + PUSH BC + PUSH HL +L052A: CALL RBYTE + JP C,L0570 + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JP NZ,L052A + LD HL,(SUMDT) + CALL RBYTE + JP C,L0570 + LD E,A + CALL RBYTE + JP C,L0570 + CP L + JP NZ,L0563 + LD A,E + CP H + JP NZ,L0563 +L0551: XOR A +L0552: POP HL + POP BC + POP DE + CALL MSTOP + PUSH AF + LD A,(TIMFG) + CP 0F0H + JR NZ,L0561 + EI +L0561: POP AF + RET + +L0563: DEC D + JR Z,L056C + LD H,D + CALL GAPCK + JR L050A +L056C: LD A,001H + JR L0572 +L0570: LD A,002H +L0572: SCF + JR L0552 + + +?VRFY: DI + PUSH DE + PUSH BC + PUSH HL + LD BC,(SIZE) + LD HL,(DTADR) + LD D,0D2H + LD E,053H + LD A,B + OR C + JR Z,L0552 + CALL L071A + CALL MOTOR + JR C,L0570 + CALL TMARK + JP C,L0570 + CALL TVRFY + JR L0552 + +TVRFY: PUSH DE + PUSH BC + PUSH HL + LD H,002H +TVF1: LD BC,KEYPB + LD DE,KEYPC +TVF2: CALL EDGE + JP C,L0570 + CALL DLY3 + LD A,(DE) + AND 020H + JP Z,TVF2 + LD D,H + POP HL + POP BC + PUSH BC + PUSH HL +TVF3: CALL RBYTE + JP C,L0570 + CP (HL) + JP NZ,L056C + INC HL + DEC BC + LD A,B + OR C + JP NZ,TVF3 + LD HL,(CSMDT) + CALL RBYTE + CP H + JR NZ,L056C + CALL RBYTE + CP L + JR NZ,L056C + DEC D + JP Z,L0551 + LD H,D + JR TVF1 + + ; PRINT '00' +GETLD: LD DE,009FCH + RST 018H + JP AUTO2 + + ; ROLL UP +ROLUP: LD HL,PBIAS + LD A,(ROLEND) + CP (HL) + JP Z,?RSTR + JP ROLU1 + +?LOAD: PUSH AF + LD A,(FLASH) + CALL ?PONT + LD (HL),A + POP AF + RET + + ; Unused memory + XOR E + LD C,A + +EDGE: LD A,0F0H + LD (KEYPA),A + NOP +EDG1: LD A,(BC) + AND 081H + JP NZ,EDG1A + SCF + RET +EDG1A: LD A,(DE) + AND 020H + JP NZ,EDG1 +EDG2: LD A,(BC) + AND 081H + JP NZ,EDG3 + SCF + RET +EDG3: LD A,(DE) + AND 020H + JP Z,EDG2 + RET + +RBYTE: PUSH BC + PUSH DE + PUSH HL + LD HL,00800H + LD BC,KEYPB + LD DE,KEYPC +RBY1: CALL EDGE + JP C,RBY3 + CALL DLY3 + LD A,(DE) + AND 020H + JP Z,RBY2 + PUSH HL + LD HL,(SUMDT) + INC HL + LD (SUMDT),HL + POP HL + SCF +RBY2: LD A,L + RLA + LD L,A + DEC H + JP NZ,RBY1 + CALL EDGE + LD A,L +RBY3: POP HL + POP DE + POP BC + RET + +TMARK: CALL GAPCK + PUSH BC + PUSH DE + PUSH HL + LD HL,02828H ; 40 short and 40 long gap pulses + LD A,E + CP 0CCH + JP Z,TM0 + LD HL,01414H ; 20 short and 20 long tape mark pulses +TM0: LD (TMCNT),HL + LD BC,KEYPB + LD DE,KEYPC +TM1: LD HL,(TMCNT) +TM2: CALL EDGE + JP C,RET3 + CALL DLY3 + LD A,(DE) + AND 020H + JP Z,TM1 + DEC H + JP NZ,TM2 +TM3: CALL EDGE + JP C,RET3 + CALL DLY3 + LD A,(DE) + AND 020H + JP NZ,TM1 + DEC L + JP NZ,TM3 + CALL EDGE +RET3: +TM4: POP HL + POP DE + POP BC + RET + +MOTOR: PUSH BC + PUSH DE + PUSH HL + LD B,00AH +MOT1: LD A,(KEYPC) + AND 010H + JR Z,MOT4 +MOT2: LD B,0A6H +L06B1: CALL DLY12 + DJNZ L06B1 + XOR A +MOT7: JR RET3 +MOT4: LD A,006H + LD HL,KEYPF + LD (HL),A + INC A + LD (HL),A + DJNZ MOT1 + CALL NL + LD A,D + CP 0D7H + JR Z,MOT8 + LD DE,00D9EH + JR MOT9 +MOT8: LD DE,MSG_3 ; RECORD message. + RST 018H + LD DE,00DA0H +MOT9: RST 018H +MOT5: LD A,(KEYPC) + AND 010H + JR NZ,MOT2 + CALL ?BRK + JR NZ,MOT5 + SCF + JR MOT7 + +L06E7: LD B,0C9H + LD A,(KANAF) + OR A + JR NZ,L06F0 + INC B +L06F0: LD A,B + JP ?KY1 + + ; PRESS RECORD message. +MSG_3: DB 07FH, 020H + DB 052H, 045H, 043H, 04FH, 052H + DB 044H, 02EH, 00DH + + ; Padding not used + DB 034H + DB 044H + +MSTOP: PUSH AF + PUSH BC + PUSH DE + LD B,00AH +L0705: LD A,(KEYPC) + AND 010H + JR Z,L0717 + LD A,006H + LD (KEYPF),A + INC A + LD (KEYPF),A + DJNZ L0705 +L0717: JP ?RSTR1 +L071A: PUSH BC + PUSH DE + PUSH HL + LD DE,00000H +L0720: LD A,B + OR C + JR NZ,L072F + EX DE,HL + LD (SUMDT),HL + LD (CSMDT),HL + POP HL + POP DE + POP BC + RET + +L072F: LD A,(HL) + PUSH BC + LD B,008H +L0733: RLCA + JR NC,L0737 + INC DE +L0737: DJNZ L0733 + POP BC + INC HL + DEC BC + JR L0720 +L073E: RLCA + RLCA + RLCA + LD C,A + LD A,E +L0743: DEC H + RRCA + JR NC,L0743 + LD A,H + ADD A,C + LD C,A + JP SWEP01 +?MODE: LD HL,KEYPF + LD (HL),08AH + LD (HL),007H + LD (HL),005H + LD (HL),001H + RET + +L0759: LD A,00EH +L075B: DEC A + JP NZ,L075B + RET + +L0760: LD A,00DH +L0762: DEC A + JP NZ,L0762 + RET + +L0767: PUSH BC + LD B,008H + CALL L0D57 +L076D: RLCA + CALL C,L0D57 + CALL NC,L0D3E + DEC B + JP NZ,L076D + POP BC + RET + +L077A: PUSH BC + PUSH DE + LD A,E + LD BC,055F0H + LD DE,02828H + CP 0CCH + JP Z,L078E + LD BC,02AF8H + LD DE,01414H +L078E: CALL L0D3E + DEC BC + LD A,B + OR C + JR NZ,L078E +L0796: CALL L0D57 + DEC D + JR NZ,L0796 +L079C: CALL L0D3E + DEC E + JR NZ,L079C + CALL L0D57 + POP DE + POP BC + RET + +?GETL: PUSH AF + PUSH BC + PUSH HL + PUSH DE +GETL0: CALL ?SAVE +GETL0A: CALL ?KEY + CP 0CBH + JR Z,GETL0A +GETL0B: CALL ?KEY + CALL ?FLAS + JR Z,GETL0B +GETL0C: PUSH AF + XOR A + LD (STRGF),A + POP AF +AUTO3: LD B,A +GETL0D: CALL ?LOAD + LD A,(SWRK) + OR A + CALL Z,?BEL + LD A,B + CP 0E7H + JP Z,GETLD + CP 0E6H + JR Z,CHGPK + CP 0EEH + JR Z,CHGPA + CP 0E5H + JR Z,DMT + CP 0E0H + JP Z,LOCK + JR NC,GETL0B + AND 0F0H + CP 0C0H + JR NZ,GETL2 + LD A,B + CP 0CDH + JR Z,GETL3 + CP 0CBH + JP Z,GETLC + CP 0C7H + JR NC,GETL5 + LD A,(KANAF) + OR A + LD A,B + JR Z,GETL5 +GETL2: LD A,B + CALL ?DSP +AUTO2: CALL ?SAVE + LD A,(STRGF) + OR A + JR NZ,AUTO5 +AUTOL: LD E,014H +AUTOL1: CALL ?KEY + JR NZ,AUTO3 + CALL AUTCK +GETL1: JR C,GETL0B + DEC E + JR NZ,AUTOL1 + LD A,001H + LD (STRGF),A +AUTO5: CALL DLY12 + CALL DLY12 + CALL ?KEY + CALL ?FLAS + JR NZ,GETL0C + CALL AUTCK + JR C,GETL1 + JR GETL0D +GETL5: CALL ?DPCT + JR AUTO2 + +CHGPA: XOR A + IF MODE80C = 1 + JR CHGPK + ELSE + JR CHGPK1 + ENDIF +CHGPK: LD A,0FFH +CHGPK1: LD (SPAGE),A + LD A,0C6H + CALL ?DPCT +CHGP1: JP GETL0 + +GETLC: POP HL + PUSH HL + LD (HL),01BH + INC HL + LD (HL),00DH + JR GETLR + +DMT: LD B,05AH + JR GETL2 + +GETL3: CALL .MANG + LD B,COLW ; PDS was 028H + JR NC,GETLA + DEC H +GETLB: LD B,COLW*2 ; 050H +GETL6: LD L,000H + CALL ?PNT1 + POP DE + PUSH DE +GETL6A: LD A,(HL) + CALL ?DACN + LD (DE),A + INC HL + RES 3,H + INC DE + DJNZ GETL6A + EX DE,HL +GETL6B: LD (HL),00DH + DEC HL + LD A,(HL) + CP 020H + JR Z,GETL6B +GETLR: CALL ?LTNL + JP L03D5 + +GETLA: RRCA + JR NC,GETL6 + JR GETLB + +LOCK: LD HL,SFTLK + LD A,(HL) + CPL + LD (HL),A + JR CHGP1 + +?MSG: PUSH AF + PUSH BC + PUSH DE +MSG1: LD A,(DE) + CP 00DH + JR Z,MSGX2 + CALL ?PRNT + INC DE + JR MSG1 + +?MSGX: PUSH AF + PUSH BC + PUSH DE +MSGX1: LD A,(DE) + CP 00DH +MSGX2: JP Z,?RSTR1 + CALL ?ADCN + CALL PRNT3 + INC DE + JR MSGX1 + +?GET: PUSH BC + PUSH HL + LD B,009H + LD HL,01165H + CALL ?CLRFF + POP HL + POP BC + CALL ?KEY + SUB 0F0H + RET Z + ADD A,0F0H + JP ?DACN + +?KEY: PUSH BC + PUSH DE + PUSH HL + CALL ?SWEP + LD A,B + RLCA + JR C,?KY2 + LD A,0F0H +?KY1: LD E,A + CALL AUTCK + LD A,(KDATW) + OR A + JR Z,?KY11 + CALL DLY12 + CALL ?SWEP + LD A,B + RLCA + JR C,?KY2 +?KY11: LD A,E + CP 0F0H + JR NZ,?KY9 +?KY10: JP RET3 +?KY2: RLCA + RLCA + RLCA + JP C,L06E7 + RLCA + JP C,_BRK + LD H,000H + LD L,C + LD A,C + CP 038H + JR NC,?KY6 + LD A,(KANAF) + OR A + LD A,B + RLCA + JR NZ,?KY4 + LD B,A + LD A,(SFTLK) + OR A + LD A,B + JR Z,L0917 + RLA + CCF + RRA +L0917: RLA + RLA + JR NC,?KY3 +L091B: LD DE,KTBLC +?KY5: ADD HL,DE + LD A,(HL) + JR ?KY1 +?KY3: RRA + JR NC,?KY6 + LD DE,KTBLS + JR ?KY5 +?KY6: LD DE,KTBL ; 00BEAH + JR ?KY5 +?KY4: RLCA + JR C,?KY7 + RLCA + JR C,L091B + LD DE,KTBLG + JR ?KY5 +?KY7: LD DE,KTBLGS + JR ?KY5 +?KY9: CALL AUTCK + INC A + LD A,E + JR ?KY10 + +?PRT: LD A,C + CALL ?ADCN + LD C,A + AND 0F0H + CP 0F0H + RET Z + + CP 0C0H + LD A,C + JR NZ,PRNT3 +PRNT5: CALL ?DPCT + CP 0C3H + JR Z,PRNT4 + CP 0C5H + JR Z,PRNT2 + CP 0CDH ; CR + JR Z,PRNT2 + CP 0C6H + RET NZ + +PRNT2: XOR A +PRNT2A: LD (DPRNT),A + RET + +PRNT3: CALL ?DSP +PRNT4: LD A,(DPRNT) + INC A + CP COLW*2 ; 050H + JR C,PRNT4A + SUB COLW*2 ; 050H +PRNT4A: JR PRNT2A + +?NL: LD A,(DPRNT) + OR A + RET Z + +?LTNL: LD A,0CDH + JR PRNT5 +?PRTT: CALL PRNTS + LD A,(DPRNT) + OR A + RET Z + +L098C: SUB 00AH + JR C,?PRTT + JR NZ,L098C + RET + +?PRTS: LD A,020H +?PRNT: CP 00DH + JR Z,?LTNL + PUSH BC + LD C,A + LD B,A + CALL ?PRT + LD A,B + POP BC + RET + +DLY3: NEG + NEG + LD A,02AH + JP L0762 +L09AB: ADD A,C + DJNZ L09AB + POP BC + LD C,A + XOR A + RET + + DJNZ PRNT4A + PUSH DE + PUSH HL + CALL ?SAVE +L09B9: CALL ?KEY + CALL ?FLAS + JR Z,L09B9 + CALL ?LOAD + JP RET3 +L09C7: PUSH DE + PUSH HL + LD HL,PBIAS + XOR A + RLD + LD D,A + LD E,(HL) + RRD + XOR A + RR D + RR E + LD HL,SCRN + ADD HL,DE + LD (PAGETP),HL + POP HL + POP DE + RET + +L09E2: XOR A +CLR8: LD BC,00800H + PUSH DE + LD D,A +L09E8: LD (HL),D + INC HL + DEC BC + LD A,B + OR C + JR NZ,L09E8 + POP DE + RET + +AUTCK: LD HL,KDATW + LD A,(HL) + INC HL + LD D,(HL) + LD (HL),A + SUB D + RET NC + INC (HL) + RET + + DB 030H + DB 030H + DB 00DH + +?FLAS: PUSH AF + PUSH HL + LD A,(KEYPC) + RLCA + RLCA + JR C,FLAS1 + LD A,(FLSDT) +FLAS2: CALL ?PONT + LD (HL),A +FLAS3: POP HL + POP AF + RET + +FLAS1: LD A,(FLASH) + JR FLAS2 + +REV: LD HL,REVFLG + LD A,(HL) + OR A + CPL + LD (HL),A + JR Z,REV1 + LD A,(INVDSP) + JR REV2 +REV1: LD A,(NRMDSP) +REV2: JP ?RSTR + +.MANG: LD HL,MANG + LD A,(SPAGE) + OR A + JP NZ,.MANG2 + LD A,(MGPNT) +.MANG3: SUB 008H + INC HL + JR NC,.MANG3 + ADD A,008H + LD C,(HL) + DEC HL + LD B,A + INC B + PUSH BC + LD A,(HL) +.MANG4: RR C + RRA + DJNZ .MANG4 + POP BC + EX DE,HL +.MANG1: LD HL,(DSPXY) + RET + +?SWEP: PUSH DE + PUSH HL + XOR A + LD (KDATW),A + LD B,0FAH + LD D,A + CALL ?BRK + JR NZ,SWEP6 + LD D,088H + JR SWEP9 +SWEP6: LD HL,SWPW + PUSH HL + JR NC,SWEP11 + LD D,A + AND 060H + JR NZ,SWEP11 + LD A,D + XOR (HL) + BIT 4,A + LD (HL),D + JR Z,SWEP0 +SWEP01: SET 7,D +SWEP0: DEC B + POP HL + INC HL + LD A,B + LD (KEYPA),A + CP 0F0H + JR NZ,SWEP3 + LD A,(HL) + CP 003H + JR C,SWEP9 + LD (HL),000H + RES 7,D +SWEP9: LD B,D + POP HL + POP DE + RET + +SWEP11: LD (HL),000H + JR SWEP0 +SWEP3: LD A,(KEYPB) + LD E,A + CPL + AND (HL) + LD (HL),E + PUSH HL + LD HL,KDATW + PUSH BC + LD B,008H +SWEP8: RLC E + JR C,SWEP7 + INC (HL) +SWEP7: DJNZ SWEP8 + POP BC + OR A + JR Z,SWEP0 + LD E,A +SWEP2: LD H,008H + LD A,B + DEC A + AND 00FH + JP L073E + +; ASCII TO DISPLAY CODE TABLE +ATBL: DB 0CCH + DB 0E0H + DB 0F2H + DB 0F3H + DB 0CEH + DB 0CFH + DB 0F6H + DB 0F7H + DB 0F8H + DB 0F9H + DB 0FAH + DB 0FBH + DB 0FCH + DB 0FDH + DB 0FEH + DB 0FFH + DB 0E1H + DB 0C1H + DB 0C2H + DB 0C3H + DB 0C4H + DB 0C5H + DB 0C6H + DB 0E2H + DB 0E3H + DB 0E4H + DB 0E5H + DB 0E6H + DB 0EBH + DB 0EEH + DB 0EFH + DB 0F4H + DB 000H + DB 061H + DB 062H + DB 063H + DB 064H + DB 065H + DB 066H + DB 067H + DB 068H + DB 069H + DB 06BH + DB 06AH + DB 02FH + DB 02AH + DB 02EH + DB 02DH + DB 020H + DB 021H + DB 022H + DB 023H + DB 024H + DB 025H + DB 026H + DB 027H + DB 028H + DB 029H + DB 04FH + DB 02CH + DB 051H + DB 02BH + DB 057H + DB 049H + DB 055H + DB 001H + DB 002H + DB 003H + DB 004H + DB 005H + DB 006H + DB 007H + DB 008H + DB 009H + DB 00AH + DB 00BH + DB 00CH + DB 00DH + DB 00EH + DB 00FH + DB 010H + DB 011H + DB 012H + DB 013H + DB 014H + DB 015H + DB 016H + DB 017H + DB 018H + DB 019H + DB 01AH + DB 052H + DB 059H + DB 054H + DB 050H + DB 045H + DB 0C7H + DB 0C8H + DB 0C9H + DB 0CAH + DB 0CBH + DB 0CCH + DB 0CDH + DB 0CEH + DB 0CFH + DB 0DFH + DB 0E7H + DB 0E8H + DB 0E9H + DB 0EAH + DB 0ECH + DB 0EDH + DB 0D0H + DB 0D1H + DB 0D2H + DB 0D3H + DB 0D4H + DB 0D5H + DB 0D6H + DB 0D7H + DB 0D8H + DB 0D9H + DB 0DAH + DB 0DBH + DB 0DCH + DB 0DDH + DB 0DEH + DB 0C0H + DB 040H + DB 0BDH + DB 09DH + DB 0B1H + DB 0B5H + DB 0B9H + DB 0B4H + DB 09EH + DB 0B2H + DB 0B6H + DB 0BAH + DB 0BEH + DB 09FH + DB 0B3H + DB 0B7H + DB 0BBH + DB 0BFH + DB 0A3H + DB 085H + DB 0A4H + DB 0A5H + DB 0A6H + DB 094H + DB 087H + DB 088H + DB 09CH + DB 082H + DB 098H + DB 084H + DB 092H + DB 090H + DB 083H + DB 091H + DB 081H + DB 09AH + DB 097H + DB 093H + DB 095H + DB 089H + DB 0A1H + DB 0AFH + DB 08BH + DB 086H + DB 096H + DB 0A2H + DB 0ABH + DB 0AAH + DB 08AH + DB 08EH + DB 0B0H + DB 0ADH + DB 08DH + DB 0A7H + DB 0A8H + DB 0A9H + DB 08FH + DB 08CH + DB 0AEH + DB 0ACH + DB 09BH + DB 0A0H + DB 099H + DB 0BCH + DB 0B8H + DB 080H + DB 03BH + DB 03AH + DB 070H + DB 03CH + DB 071H + DB 05AH + DB 03DH + DB 043H + DB 056H + DB 03FH + DB 01EH + DB 04AH + DB 01CH + DB 05DH + DB 03EH + DB 05CH + DB 01FH + DB 05FH + DB 05EH + DB 037H + DB 07BH + DB 07FH + DB 036H + DB 07AH + DB 07EH + DB 033H + DB 04BH + DB 04CH + DB 01DH + DB 06CH + DB 05BH + DB 078H + DB 041H + DB 035H + DB 034H + DB 074H + DB 030H + DB 038H + DB 075H + DB 039H + DB 04DH + DB 06FH + DB 06EH + DB 032H + DB 077H + DB 076H + DB 072H + DB 073H + DB 047H + DB 07CH + DB 053H + DB 031H + DB 04EH + DB 06DH + DB 048H + DB 046H + DB 07DH + DB 044H + DB 01BH + DB 058H + DB 079H + DB 042H + DB 060H + DB 0FDH + DB 0CBH + DB 000H + DB 01EH + +?ADCN: PUSH BC + PUSH HL + LD HL,ATBL ;00AB5H + LD C,A + LD B,000H + ADD HL,BC + LD A,(HL) + JR DACN3 + +_BRK: LD A,0CBH + OR A + JP ?KY10 + + ; Unused memory. + DB 029H + DB 0F4H + DB 0DDH + +?DACN: PUSH BC + PUSH HL + PUSH DE + LD HL,00AB5H + LD D,H + LD E,L + LD BC,00100H + CPIR + JR Z,DACN1 + LD A,0F0H +DACN2: POP DE +DACN3: POP HL + POP BC + RET + +DACN1: OR A + DEC HL + SBC HL,DE + LD A,L + JR DACN2 + +KTBL: DB 022H + DB 021H + DB 017H + DB 011H + DB 001H + DB 0C7H + DB 000H + DB 01AH + DB 024H + DB 023H + DB 012H + DB 005H + DB 004H + DB 013H + DB 018H + DB 003H + DB 026H + DB 025H + DB 019H + DB 014H + DB 007H + DB 006H + DB 016H + DB 002H + DB 028H + DB 027H + DB 009H + DB 015H + DB 00AH + DB 008H + DB 00EH + DB 000H + DB 020H + DB 029H + DB 010H + DB 00FH + DB 00CH + DB 00BH + DB 02FH + DB 00DH + DB 0BEH + DB 02AH + DB 052H + DB 055H + DB 04FH + DB 02CH + DB 02DH + DB 02EH + DB 0C5H + DB 059H + DB 0C3H + DB 0C2H + DB 0CDH + DB 054H + DB 000H + DB 049H + DB 028H + DB 027H + DB 025H + DB 024H + DB 022H + DB 021H + DB 0E7H + DB 020H + DB 06AH + DB 029H + DB 02AH + DB 026H + DB 000H + DB 023H + DB 000H + DB 02EH + +KTBLS: DB 062H + DB 061H + DB 097H + DB 091H + DB 081H + DB 0C8H + DB 000H + DB 09AH + DB 064H + DB 063H + DB 092H + DB 085H + DB 084H + DB 093H + DB 098H + DB 083H + DB 066H + DB 065H + DB 099H + DB 094H + DB 087H + DB 086H + DB 096H + DB 082H + DB 068H + DB 067H + DB 089H + DB 095H + DB 08AH + DB 088H + DB 08EH + DB 000H + DB 0BFH + DB 069H + DB 090H + DB 08FH + DB 08CH + DB 08BH + DB 051H + DB 08DH + DB 0A5H + DB 02BH + DB 0BCH + DB 0A4H + DB 06BH + DB 06AH + DB 045H + DB 057H + DB 0C6H + DB 080H + DB 0C4H + DB 0C1H + DB 0CDH + DB 040H + DB 000H + DB 050H + +KTBLG: DB 03EH + DB 037H + DB 038H + DB 03CH + DB 053H + DB 0C7H + DB 000H + DB 076H + DB 07BH + DB 07FH + DB 030H + DB 034H + DB 047H + DB 044H + DB 06DH + DB 0DEH + DB 05EH + DB 03AH + DB 075H + DB 071H + DB 04BH + DB 04AH + DB 0DAH + DB 06FH + DB 0BDH + DB 01FH + DB 07DH + DB 079H + DB 05CH + DB 072H + DB 032H + DB 000H + DB 09CH + DB 0A1H + DB 0D6H + DB 0B0H + DB 0B4H + DB 05BH + DB 060H + DB 01CH + DB 09EH + DB 0D2H + DB 0D8H + DB 0B2H + DB 0B6H + DB 042H + DB 0DBH + DB 0B8H + DB 0C5H + DB 0D4H + DB 0C3H + DB 0C2H + DB 0CDH + DB 04EH + DB 000H + DB 0BAH + +KTBLGS: DB 036H + DB 03FH + DB 078H + DB 07CH + DB 046H + DB 0C8H + DB 000H + DB 077H + DB 03BH + DB 07EH + DB 070H + DB 074H + DB 048H + DB 041H + DB 0DDH + DB 0D9H + DB 01EH + DB 07AH + DB 035H + DB 031H + DB 04CH + DB 043H + DB 0A6H + DB 06EH + DB 0A2H + DB 05FH + DB 03DH + DB 039H + DB 05DH + DB 073H + DB 033H + DB 000H + DB 09DH + DB 0A3H + DB 0B1H + DB 0D5H + DB 056H + DB 06CH + DB 0D0H + DB 01DH + DB 09FH + DB 0D1H + DB 0B3H + DB 0D7H + DB 04DH + DB 0B5H + DB 01BH + DB 0B9H + DB 0C6H + DB 0D3H + DB 0C4H + DB 0C1H + DB 0CDH + DB 0B7H + DB 000H + DB 0BBH + +KTBLC: DB 0F0H + DB 0F0H + DB 0E2H + DB 0C1H + DB 0E0H + DB 0F0H + DB 000H + DB 0E5H + DB 0F0H + DB 0F0H + DB 0C2H + DB 0CFH + DB 0CEH + DB 0C3H + DB 0E3H + DB 0F3H + DB 0F0H + DB 0F0H + DB 0E4H + DB 0C4H + DB 0F7H + DB 0F6H + DB 0C6H + DB 0F2H + DB 0F0H + DB 0F0H + DB 0F9H + DB 0C5H + DB 0FAH + DB 0F8H + DB 0FEH + DB 0F0H + DB 0F0H + DB 0F0H + DB 0E1H + DB 0FFH + DB 0FCH + DB 0FBH + DB 0F0H + DB 0FDH + DB 0EFH + DB 0F4H + DB 0E6H + DB 0CCH + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0F0H + DB 0EBH + DB 0F0H + DB 0F0H + DB 0F0H + DB 0EEH + DB 0F0H + +?BRK: LD A,0F0H + LD (KEYPA),A + NOP + LD A,(KEYPB) + OR A + RLA + JR NC,L0D37 + RRA + RRA + JR NC,L0D27 + RRA + JR NC,L0D2B + CCF + RET + +L0D27: LD A,040H + SCF + RET + +L0D2B: LD A,(KDATW) + LD A,001H + LD (KDATW),A + LD A,010H + SCF + RET + +L0D37: AND 002H + RET Z + + LD A,020H + SCF + RET + +L0D3E: PUSH AF + LD A,003H + LD (KEYPF),A + CALL L0759 + CALL L0759 + LD A,002H + LD (KEYPF),A + CALL L0759 + CALL L0759 + POP AF + RET + +L0D57: PUSH AF + LD A,003H + LD (KEYPF),A + CALL L0759 + CALL L0759 + CALL L0759 + CALL L0759 + LD A,002H + LD (KEYPF),A + CALL L0759 + CALL L0759 + CALL L0759 + CALL L0760 + POP AF + RET + +?DSPA: CP 008H + JR Z,L0D90 +L0D80: RRC (HL) + DJNZ L0D80 + SET 0,(HL) + RES 1,(HL) + LD B,A +L0D89: RLC (HL) + DJNZ L0D89 +DSP04: JP CURSR +L0D90: INC HL + SET 0,(HL) + RES 1,(HL) + JR DSP04 +DSP02: SET 7,(HL) + INC HL + RES 0,(HL) + JR DSP04 + + +MSG_1: DB 07FH, 020H +MSG_2: DB 050H, 04CH, 041H, 059H, 00DH, 0F3H + +?BLNK: RET + +DLY12: PUSH BC + LD B,023H +DLY12A: CALL DLY3 + DJNZ DLY12A + POP BC + RET + + ; BELL DATA +?BELD: DB 0D7H, 041H, 030H, 00DH + +?DSP: PUSH AF + PUSH BC + PUSH DE + PUSH HL + LD B,A + CALL ?PONT + LD (HL),B + LD HL,(DSPXY) + LD A,L +DSP01: CP COLW - 1 ; End of line. + JR NZ,DSP04 + CALL .MANG + JR C,DSP04 + LD A,(SPAGE) + OR A + JP NZ,.DSP03 + EX DE,HL + LD A,B + CP 007H + JR Z,DSP02 + JR ?DSPA + + ; Unused memory. + INC H + DI + +?DPCT: PUSH AF ; Display control, character is mapped to a function call. + PUSH BC + PUSH DE + PUSH HL + LD B,A + AND 0F0H + CP 0C0H + JP NZ,?RSTR + XOR B + RLCA + LD C,A + LD B,000H + LD HL,CTBL + LD A,(SPAGE) + OR A + JR Z,DPCT1 + LD HL,.CTBL +DPCT1: ADD HL,BC + LD E,(HL) + INC HL + LD D,(HL) + EX DE,HL + JP (HL) + + +CTBL: DW SCROL + DW CURSD + DW CURSU + DW CURSR + DW CURSL + DW HOME + DW CLRS + DW DEL + DW INST + DW ALPHA + DW KANA + DW ?RSTR + DW REV + DW CR + DW ROLUP + DW ROLD + +;.CTBL: DW .SCROL +; DW CURSD +; DW CURSU +; DW CURSR +; DW CURSL +; DW HOM0 +; DW CLRS +; DW DEL +; DW INST +; DW ALPHA +; DW KANA +; DW ?RSTR +; DW REV +; DW .CR +; DW ?RSTR +; DW ?RSTR + +SCROL: LD HL,PBIAS + LD C,005H + LD A,(ROLEND) + ADD A,C + LD (ROLEND),A + LD A,(ROLTOP) + ADD A,C + LD (ROLTOP),A +SCROL1: LD A,C + ADD A,(HL) + LD (HL),A + CALL L09C7 + LD HL,(PAGETP) + LD DE,SCRNSZ + ADD HL,DE ; HL=PAGETOP + 1000/2000 + LD B,COLW + XOR A +SCROL2: RES 3,H + LD (HL),A + INC HL + DJNZ SCROL2 + LD A,(PBIAS) ; PBIAS is the offest for hardware scroll. + LD L,A + LD H,0E2H ; Hardware scroll region, E2 + LD A,(HL) + LD HL,MANGE + OR A + LD B,007H +SCROL3: RR (HL) + DEC HL + DJNZ SCROL3 + JP ?RSTR + +CURSD: LD HL,(DSPXY) + LD A,H + CP ROW - 1 + JR Z,CURS4 + INC H +CURS1: CALL MGP.I +CURS3: LD (DSPXY),HL + JR ?RSTR + +CURSU: LD HL,(DSPXY) + LD A,H + OR A + JR Z,CURS5 + DEC H +CURSU1: CALL MGP.D + JR CURS3 + +CURSR: LD HL,(DSPXY) + LD A,L + CP COLW - 1 ; End of line + JR NC,CURS2 + INC L + JR CURS3 +CURS2: LD L,000H + INC H + LD A,H + CP ROW + JR C,CURS1 + LD H,ROW - 1 + LD (DSPXY),HL +CURS4: JR CURS6 + +CURSL: LD HL,(DSPXY) + LD A,L + OR A + JR Z,CURS5A + DEC L + JR CURS3 +CURS5A: LD L,COLW - 1 ; End of line + DEC H + JP P,CURSU1 + LD H,000H + LD (DSPXY),HL +CURS5: LD A,(SPAGE) + OR A + JR NZ,?RSTR + JP ROLD + +CLRS: LD HL,MANG + LD B,01BH + CALL ?CLER + LD HL,SCRN + PUSH HL + CALL L09E2 + POP HL + LD A,(SPAGE) + OR A + JR NZ,CLRS1 + LD (PAGETP),HL + LD A,07DH + LD (ROLEND),A +CLRS1: LD A,(SCLDSP) +HOM00: JP HOM0 + +CURS6: LD A,(SPAGE) + OR A + JP NZ,.SCROL + JP ROLU + +ALPHA: XOR A +ALPHI: LD (KANAF),A +?RSTR: POP HL +?RSTR1: POP DE + POP BC + POP AF + RET + + ; Unused memory + DEC C + DEC C + DEC C + DEC C + +KANA: LD A,001H + JR ALPHI + +DEL: LD HL,(DSPXY) + LD A,H + OR L + JR Z,?RSTR + LD A,L + OR A + JR NZ,DEL1 + CALL .MANG + JR C,DEL1 + CALL ?PONT + DEC HL + LD (HL),000H + JR CURSL +DEL1: CALL .MANG + RRCA + LD A,COLW + JR NC,L0F13 + RLCA +L0F13: SUB L + LD B,A + CALL ?PONT + PUSH HL + POP DE + DEC DE + SET 4,D +DEL2: RES 3,H + RES 3,D + LD A,(HL) + LD (DE),A + INC HL + INC DE + DJNZ DEL2 + DEC HL + LD (HL),000H + JP CURSL + +INST: CALL .MANG + RRCA + LD L,COLW - 1 ; End of line + LD A,L + JR NC,INST1A + INC H +INST1A: CALL ?PNT1 + PUSH HL + LD HL,(DSPXY) + JR NC,INST2 + LD A,(COLW*2)-1 ; 04FH +INST2: SUB L + LD B,A + POP DE + LD A,(DE) + OR A + JR NZ,?RSTR + CALL ?PONT + LD A,(HL) + LD (HL),000H +INST1: INC HL + RES 3,H + LD E,(HL) + LD (HL),A + LD A,E + DJNZ INST1 + JR ?RSTR + +ROLD: LD HL,PBIAS + LD A,(ROLTOP) + CP (HL) + JR Z,?RSTR + CALL MGP.D + LD A,(HL) + SUB 005H +ROL2: LD (HL),A + LD L,A + LD H,0E2H + LD A,(HL) + CALL L09C7 + JP ?RSTR + +CR: CALL .MANG + RRCA + JP NC,CURS2 + LD L,000H + INC H + LD A,H + CP ROW - 1 ; End of line? + JR Z,CR3 + JR NC,CR2 + CALL MGP.I + INC H + JP CURS1 +CR2: DEC H + LD (DSPXY),HL + LD HL,ROLU + PUSH HL + PUSH AF + PUSH BC + PUSH DE + CALL ROLU +CR3: LD (DSPXY),HL + CALL MGP.I + +ROLU: LD HL,PBIAS + LD A,(ROLEND) + CP (HL) + JP Z,SCROL +ROLU1: CALL MGP.I + LD A,(HL) + ADD A,005H + JR ROL2 + +?PONT: LD HL,(DSPXY) +?PNT1: PUSH AF + PUSH BC + PUSH DE + PUSH HL + POP BC + LD DE,COLW + LD HL,SCRN - COLW + LD A,(SPAGE) + OR A + JR NZ,?PNT2 + LD HL,(PAGETP) + SBC HL,DE +?PNT2: ADD HL,DE + DEC B + JP P,?PNT2 + LD B,000H + ADD HL,BC + RES 3,H + POP DE + POP BC + POP AF + RET + +?CLER: XOR A + JR ?DINT +?CLRFF: LD A,0FFH +?DINT: LD (HL),A + INC HL + DJNZ ?DINT + RET + +GAPCK: PUSH BC + PUSH DE + PUSH HL + LD BC,KEYPB + LD DE,KEYPC +GAPCK1: LD H,064H +GAPCK2: CALL EDGE + JR C,GAPCK3 + CALL DLY3 + LD A,(DE) + AND 020H + JR NZ,GAPCK1 + DEC H + JR NZ,GAPCK2 +GAPCK3: JP RET3 + + ; MONITOR WORK AREA + ; (MZ700) + +STACK: EQU 010F0H + + ORG STACK +SPV: +IBUFE: ; TAPE BUFFER (128 BYTES) +ATRB: DS virtual 1 ; ATTRIBUTE +NAME: DS virtual 17 ; FILE NAME +SIZE: DS virtual 2 ; BYTESIZE +DTADR: DS virtual 2 ; DATA ADDRESS +EXADR: DS virtual 2 ; EXECUTION ADDRESS +COMNT: DS virtual 92 ; COMMENT +SWPW: DS virtual 10 ; SWEEP WORK +KDATW: DS virtual 2 ; KEY WORK +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 6 ; COLUMN MANAGEMENT +MANGE: DS virtual 1 ; COLUMN MANAGEMENT END +PBIAS: DS virtual 1 ; PAGE BIAS +ROLTOP: DS virtual 1 ; ROLL TOP BIAS +MGPNT: DS virtual 1 ; COLUMN MANAG. POINTER +PAGETP: DS virtual 2 ; PAGE TOP +ROLEND: DS virtual 1 ; ROLL END + DS virtual 14 ; BIAS +FLASH: DS virtual 1 ; FLASHING DATA +SFTLK: DS virtual 1 ; SHIFT LOCK +REVFLG: DS virtual 1 ; REVERSE FLAG +SPAGE: DS virtual 1 ; PAGE CHANGE +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER + + ; EQU TABLE I/O REPORT + +SCRN: EQU 0D000H +ARAM: EQU 0D800H +KEYPA: EQU 0E000H +KEYPB: EQU 0E001H +KEYPC: EQU 0E002H +KEYPF: EQU 0E003H +CSTR: EQU 0E002H +CSTPT: EQU 0E003H +CONT0: EQU 0E004H +CONT1: EQU 0E005H +CONT2: EQU 0E006H +CONTF: EQU 0E007H +SUNDG: EQU 0E008H +TEMP: EQU 0E008H +MEMSW: EQU 0E00CH +MEMSWR: EQU 0E010H +INVDSP: EQU 0E014H +NRMDSP: EQU 0E015H +SCLDSP: EQU 0E200H diff --git a/asm/tapecheck.asm b/asm/tapecheck.asm new file mode 100644 index 0000000..d04115c --- /dev/null +++ b/asm/tapecheck.asm @@ -0,0 +1,1114 @@ + +KEYPA: EQU 0E000h +KEYPB: EQU 0E001h +KEYPC: EQU 0E002h +KEYPF: EQU 0E003h +CSTR: EQU 0E002h +CSTPT: EQU 0E003h +CONT0: EQU 0E004h +CONT1: EQU 0E005h +CONT2: EQU 0E006h +CONTF: EQU 0E007h +SUNDG: EQU 0E008h +TEMP: EQU 0E008h +LETNL: EQU 0006h +NL: EQU 0009h +PRNTS: EQU 000Ch +PRNT: EQU 0012h +MSG: EQU 0015h +MSGX: EQU 0018h +MONIT: EQU 0086h +ST1: EQU 0095h +PRTHL: EQU 03BAh +PRTHX: EQU 03C3h +DPCT: EQU 0DDCh +?BRK: EQU 0D11h +?RSTR1: EQU 0EE6h +TPSTART: EQU 10F0h +MSTART: EQU 0C000h + + + ORG TPSTART + +SPV: +IBUFE: ; TAPE BUFFER (128 BYTES) +;ATRB: DS virtual 1 ; ATTRIBUTE +ATRB: DB 01h ; Code Type, 01 = Machine Code. +;NAME: DS virtual 17 ; FILE NAME +NAME: DB "TAPE CHECK V1.0", 0Dh, 00h ; Title/Name (17 bytes). +;SIZE: DS virtual 2 ; BYTESIZE +SIZE: DW MEND - MSTART ; Size of program. +;DTADR: DS virtual 2 ; DATA ADDRESS +DTADR: DW MSTART ; Load address of program. +;EXADR: DS virtual 2 ; EXECUTION ADDRESS +EXADR: DW MSTART ; Exec address of program. +COMNT: DS 104 ; COMMENT +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 27 ; COLUMN MANAGEMENT +FLASH: DS virtual 1 ; FLASHING DATA +FLPST: DS virtual 2 ; FLASHING POSITION +FLSST: DS virtual 1 ; FLASHING STATUS +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER + + + + ORG MSTART + +ENTRYLOAD: JP START +ENTRYSAVE: JP SAVE + +START: LD DE,TITLE + CALL MSG + CALL LETNL + CALL NL + CALL NL + LD HL,1200h + LD BC,0A000h +CLEAR1: LD A,00h + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JP NZ,CLEAR1 + CALL LOAD + JP ST1 + + ; + ; LOAD COMMAND + ; +LOAD: CALL ?RDI + JP C,?ER +LOA0: CALL NL + LD DE,MSG_LOADFROM + CALL MSG + LD HL,(DTADR) + CALL PRTHL + CALL NL + LD DE,MSG_LOADEXEC + CALL MSG + LD HL,(EXADR) + CALL PRTHL + CALL NL + LD DE,MSG_LOADSIZE + CALL MSG + LD HL,(SIZE) + CALL PRTHL + CALL NL + LD DE,MSG_LOADFILE + CALL MSGX + LD DE,NAME + CALL MSGX + CALL NL + CALL ?RDD + JP C,?ER + LD HL,(EXADR) + LD A,H + CP 12h + JP C,ST1 + JP (HL) + + + ; SAVE COMMAND + +SAVE: CALL NL + LD DE,MSG_SAVEFROM + CALL MSG + LD HL,(DTADR) + CALL PRTHL + CALL NL + LD DE,MSG_SAVEEXEC + CALL MSG + LD HL,(EXADR) + CALL PRTHL + CALL NL + LD DE,MSG_SAVESIZE + CALL MSG + LD HL,(SIZE) + CALL PRTHL + CALL NL + LD DE,MSG_SAVEFILE + CALL MSGX + LD DE,NAME + CALL MSGX + CALL NL + LD A,01H ; ATTRIBUTE: OBJECT CODE + LD (ATRB),A + CALL QWRI + JP C,QER ; WRITE ERROR + CALL QWRD ; DATA + JP C,QER + CALL NL + LD DE,MSGOK ; OK MESSAGE + CALL MSGX ; CALL MSGX + JP ST1 + + ; + ; ERROR (LOADING) + ; +QER: CP 02h + JP Z,ST1 + LD DE,MSG_ERRWRITE + CALL MSG + JP ST1 + ; + ; ERROR (LOADING) + ; +?ER: CP 02h + JP Z,ST1 + LD DE,MSG_ERRCHKSUM + CALL MSG + JP ST1 + ; + ; READ INFORMATION + ; + ; EXIT ACC = 0 : OK CF=0 + ; = 1 : ER CF=1 + ; = 2 : BREAK CF=1 + ; +?RDI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2h + LD E,0CCh + LD BC,80h + LD HL,IBUFE +RD1: CALL MOTOR + JP C,RTP6 + CALL TMARK + JP C,RTP6 +; CALL PRTHL + CALL RTAPE + POP HL + POP BC + POP DE + ;CALL MSTOP + PUSH AF + LD A,(TIMFG) + CP 0F0h + JR NZ,RD2 + EI +RD2: POP AF + RET + + ; + ; READ DATA + ; +?RDD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D2h + LD E,53h + LD BC,(SIZE) + LD HL,(DTADR) + LD A,B + OR C + JP Z,RDD1 + JR RD1 +RDD1: POP HL + POP BC + POP DE + ;CALL MSTOP + PUSH AF + LD A,(TIMFG) + CP 0F0h + JR NZ,RDD2 + EI +RDD2: POP AF + RET + + ; + ; READ TAPE + ; +RTAPE: ;PUSH BC + ;PUSH DE + ;LD DE,MSG_READTAPE + ;CALL MSG + ;CALL NL + ;POP DE + ;POP BC + PUSH DE + PUSH BC + PUSH HL + LD H,2 +RTP1: LD BC,KEYPB + LD DE,CSTR +RTP2: CALL EDGE + JP C,RTP6 + CALL DLY3 + LD A,(DE) + AND 20h + JP Z,RTP2 + LD D,H + LD HL,0 + LD (SUMDT),HL + POP HL + POP BC + PUSH BC + PUSH HL +RTP3: CALL RBYTE + JP C,RTP6 + LD (HL),A + INC HL + DEC BC + LD A,B + OR C + JP NZ,RTP3 + LD HL,(SUMDT) + CALL RBYTE ; Checksum MSB + JP C,RTP6 + LD D,A + CALL RBYTE ; Checksum LSB + JP C,RTP6 + LD E,A + CP L + JP NZ,RTP5 + LD A,D + CP H + JP NZ,RTP5 +RTP0: XOR A + ; + PUSH HL + PUSH DE + PUSH DE + LD DE,MSG_CHKSUM_MZ1 + CALL MSGX + CALL PRTHL + CALL NL + LD DE,MSG_CHKSUM_TP1 + CALL MSGX + POP DE + EX DE,HL + CALL PRTHL + CALL NL + POP DE + POP HL + ; +RTP4: +RET2: POP HL + POP BC + POP DE + CALL MSTOP + PUSH AF + LD A,(TIMFG) + CP 0F0h + JR NZ,RTP8 + EI +RTP8: POP AF + RET + +RTP5: PUSH HL + PUSH DE + PUSH DE + LD DE,MSG_CHKSUM_MZ2 + CALL MSGX + CALL PRTHL + CALL NL + LD DE,MSG_CHKSUM_TP2 + CALL MSGX + POP DE + EX DE,HL + CALL PRTHL + CALL NL + POP DE + POP HL + ; + LD D,1 + DEC D + JR Z,RTP7 + LD H,D + CALL GAPCK + JP RTP1 +RTP7: LD A,1 + JR RTP9 +RTP6: LD A,2 +RTP9: SCF + JR RTP4 + + + ; + ; EDGE + ; BC = KEYPB + ; DE = CSTR + ; EXIT CF = 0 : EDGE + ; = 1 : BREAK + ; +EDGE: LD A,0F0h + LD (KEYPA),A + NOP +EDG1: LD A,(BC) + AND 81h ; SHIFT & BREAK + JP NZ,EDG0 + SCF + RET +EDG0: LD A,(DE) + AND 20h + JP NZ,EDG1 +EDG2: LD A,(BC) + AND 81h + JP NZ,EDG3 + SCF + RET +EDG3: LD A,(DE) + AND 20h + JP Z,EDG2 + RET + + + ; + ; 1 BYTE READ + ; + ; EXIT SUMDT=STORE + ; CF = 1 : BREAK + ; = 0 : DATA=ACC + ; +RBYTE: PUSH BC + PUSH DE + PUSH HL + LD HL,0800h + LD BC,KEYPB + LD DE,CSTR +RBY1: CALL EDGE + JP C,RBY3 + CALL DLY3 + LD A,(DE) + AND 20h + JP Z,RBY2 + PUSH HL + LD HL,(SUMDT) + INC HL + LD (SUMDT),HL + POP HL + SCF +RBY2: LD A,L + RLA + LD L,A + DEC H + JP NZ,RBY1 + CALL EDGE + LD A,L +RBY3: POP HL + POP DE + POP BC + RET + + ; + ; TAPE MARK DETECT + ; + ; E=@L@ : INFORMATION + ; =@S@ : DATA + ; EXIT CF = 0 : OK + ; = 1 : BREAK + ; +TMARK: CALL GAPCK + PUSH BC + PUSH DE + PUSH HL + PUSH BC + PUSH DE + LD DE,MSG_TAPEMARK + CALL MSG + CALL NL + POP DE + POP BC + LD HL,2828h + LD A,E + CP 0CCh + JP Z,TM0 + LD HL,1414h +TM0: LD (TMCNT),HL + LD BC,KEYPB + LD DE,CSTR +TM1: LD HL,(TMCNT) +TM2: CALL EDGE + JP C,TM4 + CALL DLY3 + LD A,(DE) + AND 20h + JP Z,TM1 + DEC H + JP NZ,TM2 +; CALL PRTHL +TM3: CALL EDGE + JP C,TM4 + CALL DLY3 + LD A,(DE) + AND 20h + JP NZ,TM1 + DEC L + JP NZ,TM3 + CALL EDGE +RET3: +TM4: POP HL + POP DE + POP BC + RET + +TM4A: CALL NL + CALL PRTHL ; Print HL as 4digit hex. + LD A,0C4h ; Move cursor left. +TM4B: CALL DPCT + CALL DPCT + CALL DPCT + CALL DPCT + CALL NL + JP ST1 + + ; + ; MOTOR ON + ; + ; D=@W@ : WRITE + ; =@R@ : READ + ; EXIT CF=0 : OK + ; =1 : BREAK +MOTOR: PUSH BC + PUSH DE + PUSH HL + PUSH BC + PUSH DE + LD DE,MSG_MOTORTG + CALL MSG + CALL NL + POP DE + POP BC + LD B,10 +MOT1: LD A,(CSTR) + AND 10h + JR Z,MOT4 +MOT2: LD B,0A6h +MOT3: CALL DLY12 + DJNZ MOT3 + XOR A +MOT7: JR RET3 +MOT4: LD A,06h + LD HL,CSTPT + LD (HL),A + INC A + LD (HL),A + DJNZ MOT1 + CALL NL + LD A,D + CP 0D7h + JR Z,MOT8 + LD DE,MSG1 + JR MOT9 +MOT8: LD DE,MSG3 + CALL MSGX + LD DE,MSG2 +MOT9: CALL MSGX +MOT5: LD A,(CSTR) + AND 10h + JR NZ,MOT2 + CALL ?BRK + JR NZ,MOT5 + SCF + JR MOT7 + + ; + ; MOTOR STOP + ; +MSTOP: PUSH AF + PUSH BC + PUSH DE + PUSH BC + PUSH DE + LD DE,MSG_MOTORSTP + CALL MSG + CALL NL + POP DE + POP BC + LD B,10 +MST1: LD A,(CSTR) + AND 10H + JR Z,MST3 +MST2: LD A,06h + LD (CSTPT),A + INC A + LD (CSTPT),A + DJNZ MST1 +MST3: JP ?RSTR1 + + ; + ; CHECK SUM + ; + ; BC = SIZE + ; HL = DATA ADR + ; EXIT SUMDT=STORE + ; CSMDT=STORE + ; +CKSUM: PUSH BC + PUSH DE + PUSH HL + LD DE,0 +CKS1: LD A,B + OR C + JR NZ,CKS2 + EX DE,HL + LD (SUMDT),HL + LD (CSMDT),HL + POP HL + POP DE + POP BC + RET +CKS2: LD A,(HL) + PUSH BC + LD B,+8 +CKS3: RLCA + JR NC,CKS4 + INC DE +CKS4: DJNZ CKS3 + POP BC + INC HL + DEC BC + JR CKS1 + + + ; + ; 107 uS DELAY + ; +DLY1: LD A,14 +DLY1A: DEC A + JP NZ,DLY1A + RET + + ; + ; 240 uS DELAY + ; +DLY2: LD A,13 +DLY2A: DEC A + JP NZ,DLY2A + RET + + ; + ; 240 uS x 3 DELAY + ; +DLY3: NEG + NEG + LD A,42 + JP DLY2A + + ; + ; 12mS DELAY +DLY12: PUSH BC + LD B,35 +DLY12A: CALL DLY3 + DJNZ DLY12A + POP BC + RET + + + ; + ; GAP * TAPEMARK + ; + ; E = @L@ : LONG GAP + ; = @S@ : SHORT GAP + ; +GAP: PUSH BC + PUSH DE + LD A,E + LD BC,55F0h + LD DE,2028h + CP 0CCh + JP Z,GAP1 + LD BC,2AF8h + LD DE,1414h +GAP1: CALL SHORT +GAP1A: DEC BC + LD A,B + OR C + JR NZ,GAP1A +GAP2: CALL LONG + DEC D + JR NZ,GAP2 +GAP3: CALL SHORT + DEC E + JR NZ,GAP3 + CALL LONG + POP DE + POP BC + RET + + ; + ; GAP CHECK + ; +GAPCK: PUSH BC + PUSH DE + PUSH HL + LD DE,MSG_GAPCK + CALL MSG + CALL NL + LD BC,KEYPB + LD DE,CSTR +GAPCK1: LD H,100 +GAPCK2: CALL EDGE + JR C,GAPCK3 + CALL DLY3 + LD A,(DE) + AND 20h + JR NZ,GAPCK1 + DEC H + JR NZ,GAPCK2 +GAPCK3: JP RET3 + + ; + ; 1 bit write + ; Short Pulse + ; +SHORT: PUSH AF + LD A,03h + LD (CSTPT),A + CALL DLY1 + CALL DLY1 + LD A,02h + LD (CSTPT),A + CALL DLY1 + CALL DLY1 + POP AF + RET + + ; + ; 1 bit write + ; Long Pulse + ; +LONG: PUSH AF + LD A,03h + LD (CSTPT),A + CALL DLY1 + CALL DLY1 + CALL DLY1 + CALL DLY1 + LD A,02h + LD (CSTPT),A + CALL DLY1 + CALL DLY1 + CALL DLY1 + CALL DLY1 + POP AF + RET + + + ; WRITE INFORMATION + +QWRI: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,0CCH ; "L" + LD HL,IBUFE ; 10F0H + LD BC,80H ; WRITE BYTE SIZE +WRI1: CALL CKSUM ; CHECK SUM + CALL MOTOR ; MOTOR ON + JR C,WRI3 + LD A,E + CP 0CCH ; "L" + JR NZ,WRI2 + CALL NL + PUSH DE + LD DE,MSGN7 ; WRITING + RST 18H ; CALL MSGX + LD DE,NAME ; FILE NAME + RST 18H ; CALL MSGX + POP DE +WRI2: CALL GAP + CALL WTAPE +WRI3: JP RET2 + + + ; WRITE DATA + ; EXIT CF=0 : OK + ; =1 : BREAK + +QWRD: DI + PUSH DE + PUSH BC + PUSH HL + LD D,0D7H ; "W" + LD E,53H ; "S" +L047D: LD BC,(SIZE) ; WRITE DATA BYTE SIZE + LD HL,(DTADR) ; WRITE DATA ADDRESS + LD A,B + OR C + JR Z,RET1 + JR WRI1 + + ; TAPE WRITE + ; BC=BYTE SIZE + ; HL=DATA LOW ADDRESS + ; EXIT CF=0 : OK + ; =1 : BREAK + +WTAPE: PUSH DE + PUSH BC + PUSH HL + LD D,02H + LD A,0F8H ; 88H WOULD BE BETTER!! + LD (KEYPA),A ; E000H +WTAP1: LD A,(HL) + CALL WBYTE ; 1 BYTE WRITE + LD A,(KEYPB) ; E001H + AND 81H ; SHIFT & BREAK + JP NZ,WTAP2 + LD A,02H ; BREAK IN CODE + SCF + JR WTAP3 + +WTAP2: INC HL + DEC BC + LD A,B + OR C + JP NZ,WTAP1 + LD HL,(SUMDT) ; SUM DATA SET + LD A,H + CALL WBYTE + LD A,L + CALL WBYTE + CALL LONG + DEC D + JP NZ,L04C2 + OR A + JP WTAP3 + +L04C2: LD B,0 +L04C4: CALL SHORT + DEC B + JP NZ,L04C4 + POP HL + POP BC + PUSH BC + PUSH HL + JP WTAP1 + +WTAP3: +RET1: POP HL + POP BC + POP DE + RET + + DB 2FH + DB 4EH + + ; VERIFY (FROM $CMT) + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER CF=1 + ; =2 : BREAK CF=1 + +QVRFY: DI + PUSH DE + PUSH BC + PUSH HL + LD BC,(SIZE) + LD HL,(DTADR) + LD D,0D2H ; "R" + LD E,53H ; "S" + LD A,B + OR C + JP Z,RTP4 ; END + CALL CKSUM + CALL MOTOR + JP C,RTP6 ; BRK + CALL TMARK ; TAPE MARK DETECT + JP C,RTP6 ; BRK + CALL TVRFY + JP RTP4 + + ; DATA VERIFY + ; BC=SIZE + ; HL=DATA LOW ADDRESS + ; CSMDT=CHECK SUM + ; EXIT ACC=0 : OK CF=0 + ; =1 : ER =1 + ; =2 : BREAK =1 + +TVRFY: PUSH DE + PUSH BC + PUSH HL + LD H,02H ; COMPARE TWICE +TVF1: LD BC,KEYPB + LD DE,CSTR +TVF2: CALL EDGE + JP C,RTP6 ; BRK + CALL DLY3 ; CALL DLY2*3 + LD A,(DE) + AND 20H + JP Z,TVF2 + LD D,H + POP HL + POP BC + PUSH BC + PUSH HL + ; COMPARE TAPE DATA AND STORAGE +TVF3: CALL RBYTE + JP C,RTP6 ; BRK + CP (HL) + JP NZ,RTP7 ; ERROR, NOT EQUAL + INC HL ; STORAGE ADDRESS + 1 + DEC BC ; SIZE - 1 + LD A,B + OR C + JR NZ,TVF3 + ; COMPARE CHECK SUM (1199H/CSMDT) AND TAPE + LD HL,(CSMDT) + CALL RBYTE + CP H + JP NZ,RTP7 ; ERROR, NOT EQUAL + CALL RBYTE + CP L + JP NZ,RTP7 ; ERROR, NOT EQUAL + DEC D ; NUMBER OF COMPARES (2) - 1 + JP Z,RTP8 ; OK, 2 COMPARES + LD H,D ; (-->05C7H), SAVE NUMBER OF COMPARES + JR TVF1 ; NEXT COMPARE + + ; 1 BYTE WRITE + +WBYTE: PUSH BC + LD B,8 + CALL LONG +WBY1: RLCA + CALL C,LONG + CALL NC,SHORT + DEC B + JP NZ,WBY1 + POP BC + RET + + + + +MSG1: DW 207Fh +MSG2: DB "PLAY", 0Dh, 00h +MSG3: DW 207Fh ; PRESS RECORD + DB "RECORD.", 0Dh, 00h +MSGN7: DB "WRITING", 0Dh, 00h +MSGOK: DB "OK", 0Dh, 00h +MSG_ERRCHKSUM: + DB "CHECKSUM ERROR", 0Dh +MSG_ERRWRITE: + DB "WRITE ERROR", 0Dh + +MSG_READTAPE: + DB "READ TAPE", 0Dh, 00h +MSG_TAPEMARK: + DB "TAPEMARK", 0Dh, 00h +MSG_MOTORTG: + DB "MOTOR TOGGLE", 0Dh, 00h +MSG_MOTORSTP: + DB "MOTOR STOP", 0Dh, 00h +MSG_TPMARK: + DB "TAPE MARK START", 0Dh, 00h +MSG_GAPCK: + DB "GAP CHECK", 0Dh, 00h +MSG_LOADFILE: + DB "LOAD FILE = ",0Dh, 00h +MSG_LOADFROM: + DB "LOAD ADDRESS = ", 0Dh, 00h +MSG_LOADEXEC: + DB "EXEC ADDRESS = ", 0Dh, 00h +MSG_LOADSIZE: + DB "LOAD SIZE = ", 0Dh, 00h +MSG_SAVEFILE: + DB "SAVE FILE = ",0Dh, 00h +MSG_SAVEFROM: + DB "SAVE ADDRESS = ", 0Dh, 00h +MSG_SAVEEXEC: + DB "SAVE ADDRESS = ", 0Dh, 00h +MSG_SAVESIZE: + DB "SAVE SIZE = ", 0Dh, 00h +MSG_CHKSUM_MZ1: + DB " MZ CHECKSUM (OK) = ", 0Dh, 00h +MSG_CHKSUM_TP1: + DB "TAPE CHECKSUM (OK) = ", 0Dh, 00h +MSG_CHKSUM_MZ2: + DB " MZ CHECKSUM (ER) = ", 0Dh, 00h +MSG_CHKSUM_TP2: + DB "TAPE CHECKSUM (ER) = ", 0Dh, 00h +TITLE: DB "SHARPMZ TAPE TESTER (C) P. SMART 2018", 0Dh, 00h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +; LD B, 20 ; Number of loops +;LOOP: LD HL,MSTART ; Start of checked memory, +; LD D,0CEh ; End memory check CE00 +;LOOP1: LD A,000h +; CP L +; JR NZ,LOOP1b +; CALL PRTHL ; Print HL as 4digit hex. +; LD A,0C4h ; Move cursor left. +; LD E,004h ; 4 times. +;LOOP1a: CALL DPCT +; DEC E +; JR NZ,LOOP1a +;LOOP1b: INC HL +; LD A,H +; CP D ; Have we reached end of memory. +; JR Z,LOOP3 ; Yes, exit. +; LD A,(HL) ; Read memory location under test, ie. 0. +; CPL ; Subtract, ie. FF - A, ie FF - 0 = FF. +; LD (HL),A ; Write it back, ie. FF. +; SUB (HL) ; Subtract written memory value from A, ie. should be 0. +; JR NZ,LOOP2 ; Not zero, we have an error. +; LD A,(HL) ; Reread memory location, ie. FF +; CPL ; Subtract FF - FF +; LD (HL),A ; Write 0 +; SUB (HL) ; Subtract 0 +; JR Z,LOOP1 ; Loop if the same, ie. 0 +;LOOP2: LD A,16h +; CALL PRNT ; Print A +; CALL PRTHX ; Print HL as 4 digit hex. +; CALL PRNTS ; Print space. +; XOR A +; LD (HL),A +; LD A,(HL) ; Get into A the failing bits. +; CALL PRTHX ; Print A as 2 digit hex. +; CALL PRNTS ; Print space. +; LD A,0FFh ; Repeat but first load FF into memory +; LD (HL),A +; LD A,(HL) +; CALL PRTHX ; Print A as 2 digit hex. +; NOP +; JR LOOP4 +; +;LOOP3: LD DE,OKCHECK +; CALL MSG ; Print check message in DE +; LD A,B ; Print loop count. +; CALL PRTHX +; LD DE,OKMSG +; CALL MSG ; Print ok message in DE +; DEC B +; JR NZ,LOOP +; LD DE,DONEMSG +; CALL MSG ; Print check message in DE +; JP MONIT +; +;OKCHECK: DB 11h +; DB "CHECK: ", 0Dh +;OKMSG: DB "OK.", 0Dh +;DONEMSG: DB 11h +; DB "RAM TEST COMPLETE.", 0Dh +; +;LOOP4: LD B,09h +; CALL PRNTS ; Print space. +; XOR A ; Zero A +; SCF ; Set Carry +;LOOP5: PUSH AF ; Store A and Flags +; LD (HL),A ; Store 0 to bad location. +; LD A,(HL) ; Read back +; CALL PRTHX ; Print A as 2 digit hex. +; CALL PRNTS ; Print space +; POP AF ; Get back A (ie. 0 + C) +; RLA ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB +; DJNZ LOOP5 ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit. +; XOR A ; Zero A, clears flags. +; LD A,80h +; LD B,08h +;LOOP6: PUSH AF ; Repeat above but AND memory location with original A (ie. 80) +; LD C,A ; Basically walk through all the bits to find which one is stuck. +; LD (HL),A +; LD A,(HL) +; AND C +; NOP +; JR Z,LOOP8 ; If zero then print out the bit number +; NOP +; NOP +; LD A,C +; CPL +; LD (HL),A +; LD A,(HL) +; AND C +; JR NZ,LOOP8 ; As above, if the compliment doesnt yield zero, print out the bit number. +;LOOP7: POP AF +; RRCA +; NOP +; DJNZ LOOP6 +; JP MONIT +; +;LOOP8: CALL LETNL ; New line. +; LD DE,BITMSG ; BIT message +; CALL MSG ; Print message in DE +; LD A,B +; DEC A +; CALL PRTHX ; Print A as 2 digit hex, ie. BIT number. +; CALL LETNL ; New line +; LD DE,BANKMSG ; BANK message +; CALL MSG ; Print message in DE +; LD A,H +; CP 50h ; 'P' +; JR NC,LOOP9 ; Work out bank number, 1, 2 or 3. +; LD A,01h +; JR LOOP11 +; +;LOOP9: CP 90h +; JR NC,LOOP10 +; LD A,02h +; JR LOOP11 +; +;LOOP10: LD A,03h +;LOOP11: CALL PRTHX ; Print A as 2 digit hex, ie. BANK number. +; JR LOOP7 +; +;BITMSG: DB " BIT: ", 0Dh +;BANKMSG: DB " BANK: ", 0Dh + +MEND: diff --git a/build_id.v b/build_id.v new file mode 100644 index 0000000..44beff5 --- /dev/null +++ b/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180928" +`define BUILD_TIME "165433" diff --git a/clean.bat b/clean.bat new file mode 100644 index 0000000..7ac8e34 --- /dev/null +++ b/clean.bat @@ -0,0 +1,38 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del *.cdf +del *.rpt +del /s new_rtl_netlist +del /s old_rtl_netlist +pause diff --git a/clean.sh b/clean.sh new file mode 100755 index 0000000..8ebda37 --- /dev/null +++ b/clean.sh @@ -0,0 +1,37 @@ +#!/bin/bash -x + +rm -f *.bak +rm -f *.orig +rm -f *.rej +rm -f *~ +rm -fr db +rm -fr incremental_db +rm -fr output_files +rm -fr simulation +rm -fr greybox_tmp +rm -fr hc_output +rm -fr .qsys_edit +rm -fr hps_isw_handoff +rm -fr sys\.qsys_edit +rm -fr sys\vip +#rm build_id.v +rm -f c5_pin_model_dump.txt +rm -f PLLJ_PLLSPE_INFO.txt +rm -f *.qws +rm -f *.ppf +rm -f *.ddb +rm -f *.csv +rm -f *.cmp +rm -f *.sip +rm -f *.spd +rm -f *.bsf +rm -f *.f +rm -f *.sopcinfo +rm -f *.xml +rm -f *.cdf +rm -f *.rpt +rm -f new_rtl_netlist +rm -f old_rtl_netlist +rm -f asm/*.obj +rm -f asm/*.sym +(cd ../Main_MiSTer; make clean) diff --git a/common/T80/T80.vhd b/common/T80/T80.vhd new file mode 100644 index 0000000..0912e3d --- /dev/null +++ b/common/T80/T80.vhd @@ -0,0 +1,1094 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/common/T80/T8080se.vhd b/common/T80/T8080se.vhd new file mode 100644 index 0000000..b18b47a --- /dev/null +++ b/common/T80/T8080se.vhd @@ -0,0 +1,194 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/common/T80/T80_ALU.vhd b/common/T80/T80_ALU.vhd new file mode 100644 index 0000000..95c98da --- /dev/null +++ b/common/T80/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/common/T80/T80_MCode.vhd b/common/T80/T80_MCode.vhd new file mode 100644 index 0000000..1d40210 --- /dev/null +++ b/common/T80/T80_MCode.vhd @@ -0,0 +1,2029 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + +-- process (IR, ISet, MCycle, F, NMICycle, IntCycle) + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_state) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/common/T80/T80_Pack.vhd b/common/T80/T80_Pack.vhd new file mode 100644 index 0000000..6904b66 --- /dev/null +++ b/common/T80/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/common/T80/T80_Reg.vhd b/common/T80/T80_Reg.vhd new file mode 100644 index 0000000..1c0f263 --- /dev/null +++ b/common/T80/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/common/T80/T80_RegX.vhd b/common/T80/T80_RegX.vhd new file mode 100644 index 0000000..ebeee09 --- /dev/null +++ b/common/T80/T80_RegX.vhd @@ -0,0 +1,176 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers for Xilinx Select RAM +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Removed UNISIM library and added componet declaration +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + component RAM16X1D + port( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic); + end component; + + signal ENH : std_logic; + signal ENL : std_logic; + +begin + + ENH <= CEN and WEH; + ENL <= CEN and WEL; + + bG1: for I in 0 to 7 generate + begin + Reg1H : RAM16X1D + port map( + DPO => DOBH(i), + SPO => DOAH(i), + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIH(i), + DPRA0 => AddrB(0), + DPRA1 => AddrB(1), + DPRA2 => AddrB(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENH); + Reg1L : RAM16X1D + port map( + DPO => DOBL(i), + SPO => DOAL(i), + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIL(i), + DPRA0 => AddrB(0), + DPRA1 => AddrB(1), + DPRA2 => AddrB(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENL); + Reg2H : RAM16X1D + port map( + DPO => DOCH(i), + SPO => open, + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIH(i), + DPRA0 => AddrC(0), + DPRA1 => AddrC(1), + DPRA2 => AddrC(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENH); + Reg2L : RAM16X1D + port map( + DPO => DOCL(i), + SPO => open, + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIL(i), + DPRA0 => AddrC(0), + DPRA1 => AddrC(1), + DPRA2 => AddrC(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENL); + end generate; + +end; diff --git a/common/T80/T80a.vhd b/common/T80/T80a.vhd new file mode 100644 index 0000000..75636aa --- /dev/null +++ b/common/T80/T80a.vhd @@ -0,0 +1,262 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80a is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + D : inout std_logic_vector(7 downto 0) + ); +end T80a; + +architecture rtl of T80a is + + signal CEN : std_logic; + signal Reset_s : std_logic; + signal IntCycle_n : std_logic; + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal MREQ : std_logic; + signal MReq_Inhibit : std_logic; + signal Req_Inhibit : std_logic; + signal RD : std_logic; + signal MREQ_n_i : std_logic; + signal IORQ_n_i : std_logic; + signal RD_n_i : std_logic; + signal WR_n_i : std_logic; + signal RFSH_n_i : std_logic; + signal BUSAK_n_i : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal DO : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal Wait_s : std_logic; + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + BUSAK_n <= BUSAK_n_i; + MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); + RD_n_i <= not RD or Req_Inhibit; + + MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; + IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; + RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; + WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; + RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; + A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); + D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + Reset_s <= '0'; + elsif CLK_n'event and CLK_n = '1' then + Reset_s <= '1'; + end if; + end process; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, + DInst => D, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then + DI_Reg <= to_x01(D); + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + WR_n_i <= '1'; + elsif CLK_n'event and CLK_n = '1' then + WR_n_i <= '1'; + if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! + WR_n_i <= not Write; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + Req_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '1' then + if MCycle = "001" and TState = "010" then + Req_Inhibit <= '1'; + else + Req_Inhibit <= '0'; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + MReq_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if MCycle = "001" and TState = "010" then + MReq_Inhibit <= '1'; + else + MReq_Inhibit <= '0'; + end if; + end if; + end process; + + process(Reset_s,CLK_n) + begin + if Reset_s = '0' then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + elsif CLK_n'event and CLK_n = '0' then + + if MCycle = "001" then + if TState = "001" then + RD <= IntCycle_n; + MREQ <= IntCycle_n; + IORQ_n_i <= IntCycle_n; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '1'; + end if; + if TState = "100" then + MREQ <= '0'; + end if; + else + if TState = "001" and NoRead = '0' then + RD <= not Write; + IORQ_n_i <= not IORQ; + MREQ <= not IORQ; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + end if; + end if; + end if; + end process; + +end; diff --git a/common/T80/T80se.vhd b/common/T80/T80se.vhd new file mode 100644 index 0000000..1b0cb9b --- /dev/null +++ b/common/T80/T80se.vhd @@ -0,0 +1,192 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0240 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/common/T80/T80sed.vhd b/common/T80/T80sed.vhd new file mode 100644 index 0000000..0c28ec2 --- /dev/null +++ b/common/T80/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/common/clk_div.vhd b/common/clk_div.vhd new file mode 100644 index 0000000..ee039ba --- /dev/null +++ b/common/clk_div.vhd @@ -0,0 +1,61 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: clk_div.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: A basic frequency divider module. +-- This module takes an input frequency and divides it based on a provided divider. +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_div is + GENERIC ( + divider : natural + ); + PORT ( + clk_in : in std_logic; + reset : in std_logic; + clk_out : out std_logic + ); +end clk_div; + +architecture Behavioral of clk_div is + signal temporal: std_logic; + signal counter : integer range 0 to divider-1 := 0; +begin + process (reset, clk_in) begin + if (reset = '1') then + temporal <= '0'; + counter <= 0; + + elsif rising_edge(clk_in) then + if (counter = divider-1) then + temporal <= NOT(temporal); + counter <= 0; + else + counter <= counter + 1; + end if; + end if; + end process; + + clk_out <= temporal; +end Behavioral; diff --git a/common/clkgen.vhd b/common/clkgen.vhd new file mode 100644 index 0000000..3e15aca --- /dev/null +++ b/common/clkgen.vhd @@ -0,0 +1,875 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: clkgen.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: A programmable Clock Generate module. +-- This module is the heart of the emulator, providing all required frequencies +-- from a given input clock (ie. DE10 Nano 50MHz). +-- +-- Based on input control signals from the MCTRL block, it changes the core frequencies +-- according to requirements and adjusts delays (such as memory) accordingly. +-- +-- The module also has debugging logic to create debug frequencies (in the FPGA, static +-- is quite possible). The debug frequencies can range from CPU down to 1/10 Hz. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +package clkgen_pkg is + + -- Clock bus, various clocks on a single bus construct. + -- + subtype CLKBUS_WIDTH is integer range 9 downto 0; + + -- Indexes to the various clocks on the bus. + -- + constant CKSYS : integer := 0; -- Master Clock (Out) + constant CKHPS : integer := 1; -- HPS clock. + constant CKMEM : integer := 2; -- Memory Clock, running 2x the CPU clock. + constant CKVIDEO : integer := 3; -- Video base frequency. + constant CKSOUND : integer := 4; -- Sound base frequency. + constant CKRTC : integer := 5; -- RTC base frequency. + constant CKLEDS : integer := 6; -- Debug leds time base. + constant CKCPU : integer := 7; -- Variable CPU clock + constant CKPERIPH : integer := 8; -- Peripheral clock + constant CKRESET : integer := 9; +end clkgen_pkg; + +library IEEE; +library pkgs; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; + +entity clkgen is + Port ( + RST : in std_logic; -- Reset + + -- Clocks + CKBASE : in std_logic; -- Base system main clock. + CLKBUS : out std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module. + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Debug modes. + DEBUG : in std_logic_vector(DEBUG_WIDTH) + ); +end clkgen; + +architecture RTL of clkgen is + +-- +-- Selectable output Clocks +-- +signal PLLLOCKED : std_logic; +signal SYSFREQLOCKED : std_logic; -- System clock is locked and running. +signal CK448Mi : std_logic; -- 448MHz +signal CK224Mi : std_logic; -- 224MHz +signal CK112Mi : std_logic; -- 112MHz +signal CK64Mi : std_logic; -- 64MHz +signal CK56Mi : std_logic; -- 56MHz +signal CK32Mi : std_logic; -- 32MHz +signal CK28Mi : std_logic; -- 28MHz +signal CK17M7i : std_logic; -- 17.7MHz +signal CK16Mi : std_logic; -- 16MHz +signal CK14Mi : std_logic; -- 14MHz +signal CK8M8i : std_logic; -- 8.8MHz +signal CK8Mi : std_logic; -- 8MHz +signal CK7Mi : std_logic; -- 7MHz +signal CK4Mi : std_logic; -- 4MHz +signal CK3M5i : std_logic; -- 3.5MHz +signal CK2Mi : std_logic; -- 2MHz +signal CK1Mi : std_logic; -- 1MHz +signal CK895Ki : std_logic; -- 895KHz Sound frequency. +signal CK100Ki : std_logic; -- Debug frequency. +signal CK31500i : std_logic; -- Clock base frequency, +signal CK31250i : std_logic; -- Clock base frequency. +signal CK15611i : std_logic; -- Clock base frequency. +signal CK10Ki : std_logic; -- 10KHz debug CPU frequency. +signal CK5Ki : std_logic; -- 5KHz debug CPU frequency. +signal CK1Ki : std_logic; -- 1KHz debug CPU frequency. +signal CK500i : std_logic; -- 500Hz debug CPU frequency. +signal CK100i : std_logic; -- 100Hz debug CPU frequency. +signal CK50i : std_logic; -- 50Hz debug CPU frequency. +signal CK10i : std_logic; -- 10Hz debug CPU frequency. +signal CK5i : std_logic; -- 5Hz debug CPU frequency. +signal CK2i : std_logic; -- 2Hz debug CPU frequency. +signal CK1i : std_logic; -- 1Hz debug CPU frequency. +signal CK0_5i : std_logic; -- 0.5Hz debug CPU frequency. +signal CK0_2i : std_logic; -- 0.2Hz debug CPU frequency. +signal CK0_1i : std_logic; -- 0.1Hz debug CPU frequency. +-- +-- Functional clocks. +-- +signal CKLEDSi : std_logic; -- Debug Leds base clock. +signal CKCPUi : std_logic; +signal CKMEMd : std_logic_vector(64 downto 0); -- Delay line for the CPU clock to create the memory clock. +signal CKSOUNDi : std_logic; +signal CKVIDEOi : std_logic; +signal CKRTCi : std_logic; +signal CKPERIPHi : std_logic; +-- + +-- +-- Components +-- +component pll + Port ( + refclk : in std_logic; -- Reference clock + rst : in std_logic; -- Reset + outclk_0 : out std_logic; -- 895MHz + locked : out std_logic -- PLL locked. + ); +end component; + +begin + PLLMAIN : pll + port map ( + refclk => CKBASE, -- Reference clock + rst => RST, -- Reset + outclk_0 => CK448Mi, -- 448MHz + locked => PLLLOCKED -- PLL locked. + ); + + -- + -- Clock Generator - Basic divide circuit for higher end frequencies. + -- + process (RST, PLLLOCKED, CK448Mi) + -- + variable counter224M : unsigned(1 downto 0); -- Binary divider to create 224MHz clock. + variable counter112M : unsigned(2 downto 0); -- Binary divider to create 112MHz clock. + variable counter64M : unsigned(2 downto 0); -- Binary divider to create 64MHz clock. + variable counter56M : unsigned(3 downto 0); -- Binary divider to create 56MHz clock. + variable counter32M : unsigned(3 downto 0); -- Binary divider to create 32MHz clock. + variable counter28M : unsigned(4 downto 0); -- Binary divider to create 28MHz clock. + variable counter17M7 : unsigned(5 downto 0); -- Binary divider to create 17.734475MHz clock. + variable counter16M : unsigned(4 downto 0); -- Binary divider to create 16MHz clock. + variable counter14M : unsigned(5 downto 0); -- Binary divider to create 16MHz clock. + variable counter8M8 : unsigned(5 downto 0); -- Binary divider to create 8.8672375MHz clock. + variable counter8M : unsigned(5 downto 0); -- Binary divider to create 8MHz clock. + variable counter7M : unsigned(6 downto 0); -- Binary divider to create 7MHz clock. + variable counter4M : unsigned(6 downto 0); -- Binary divider to create 4MHz clock. + variable counter3M5 : unsigned(6 downto 0); -- Binary divider to create 3.5MHz clock. + variable counter2M : unsigned(7 downto 0); -- Binary divider to create 2MHz clock. + variable counter1M : unsigned(8 downto 0); -- Binary divider to create 1MHz clock. + variable counter895K : unsigned(8 downto 0); -- Binary divider to create 895K clock. + variable waittosync : integer range 0 to 5; -- Counter which waits until the main clock stabilizes. + + begin + if RST = '1' or PLLLOCKED = '0' then + counter224M := (others => '0'); + counter112M := (others => '0'); + counter64M := (others => '0'); + counter56M := (others => '0'); + counter32M := (others => '0'); + counter28M := (others => '0'); + counter17M7 := (others => '0'); + counter16M := (others => '0'); + counter14M := (others => '0'); + counter8M8 := (others => '0'); + counter8M := (others => '0'); + counter7M := (others => '0'); + counter4M := (others => '0'); + counter3M5 := (others => '0'); + counter2M := (others => '0'); + counter1M := (others => '0'); + counter895K := (others => '0'); + CK224Mi <= '0'; + CK112Mi <= '0'; + CK64Mi <= '0'; + CK56Mi <= '0'; + CK32Mi <= '0'; + CK28Mi <= '0'; + CK17M7i <= '0'; + CK16Mi <= '0'; + CK14Mi <= '0'; + CK8M8i <= '0'; + CK8Mi <= '0'; + CK7Mi <= '0'; + CK4Mi <= '0'; + CK3M5i <= '0'; + CK2Mi <= '0'; + CK1Mi <= '0'; + CK895Ki <= '0'; + SYSFREQLOCKED <= '0'; + waittosync := 5; + + elsif rising_edge(CK448Mi) then + + -- If the main system frequency has stabilized and locked, commence oscillation of sub-frequencies. + if SYSFREQLOCKED = '1' then + + -- 224MHz + if counter224M = 2 then + counter224M := (others => '0'); + CK224Mi <= not CK224Mi; + else + counter224M := counter224M + 1; + end if; + + -- 112MHz + if counter112M = 2 then + counter112M := (others => '0'); + CK112Mi <= not CK112Mi; + else + counter112M := counter112M + 1; + end if; + + -- 64MHz + if counter64M = 3 or counter64M = 7 then + CK64Mi <= not CK64Mi; + + if counter64M = 7 then + counter64M := (others => '0'); + else + counter64M := counter64M + 1; + end if; + else + counter64M := counter64M + 1; + end if; + + -- 56MHz + if counter56M = 4 then + CK56Mi <= not CK56Mi; + counter56M := (others => '0'); + else + counter56M := counter56M + 1; + end if; + + -- 32MHz + if counter32M = 7 then + counter32M := (others => '0'); + CK32Mi <= not CK32Mi; + else + counter32M := counter32M + 1; + end if; + + -- 28MHz + if counter28M = 8 then + counter28M := (others => '0'); + CK28Mi <= not CK28Mi; + else + counter28M := counter28M + 1; + end if; + + -- 17.734475MHz + if counter17M7 = 13 or counter17M7 = 25 then + CK17M7i <= not CK17M7i; + + if counter17M7 = 25 then + counter17M7 := (others => '0'); + else + counter17M7 := counter17M7 + 1; + end if; + else + counter17M7 := counter17M7 + 1; + end if; + + -- 16MHz + if counter16M = 14 then + counter16M := (others => '0'); + CK16Mi <= not CK16Mi; + else + counter16M := counter16M + 1; + end if; + + -- 14MHz + if counter14M = 16 then + counter14M := (others => '0'); + CK14Mi <= not CK14Mi; + else + counter14M := counter14M + 1; + end if; + + -- 8.8672375MHz + if counter8M8 = 25 then + counter8M8 := (others => '0'); + CK8M8i <= not CK8M8i; + else + counter8M8 := counter8M8 + 1; + end if; + + -- 8MHz + if counter8M = 28 then + counter8M := (others => '0'); + CK8Mi <= not CK8Mi; + else + counter8M := counter8M + 1; + end if; + + -- 7MHz + if counter7M = 32 then + counter7M := (others => '0'); + CK7Mi <= not CK7Mi; + else + counter7M := counter7M + 1; + end if; + + -- 4MHz + if counter4M = 56 then + counter4M := (others => '0'); + CK4Mi <= not CK4Mi; + else + counter4M := counter4M + 1; + end if; + + -- 3.546875MHz + if counter3M5 = 63 then + counter3M5 := (others => '0'); + CK3M5i <= not CK3M5i; + else + counter3M5 := counter3M5 + 1; + end if; + + -- 2MHz + if counter2M = 112 then + counter2M := (others => '0'); + CK2Mi <= not CK2Mi; + else + counter2M := counter2M + 1; + end if; + + -- 1MHz + if counter1M = 224 then + counter1M := (others => '0'); + CK1Mi <= not CK1Mi; + else + counter1M := counter1M + 1; + end if; + + -- 895K + if counter895K = 250 then + counter895K := (others => '0'); + CK895Ki <= not CK895Ki; + else + counter895K := counter895K + 1; + end if; + else + waittosync := waittosync -1; + if waittosync = 0 then + SYSFREQLOCKED <= '1'; + end if; + end if; + end if; + end process; + + -- + -- Clock Generator - Basic divide circuit for middle end frequencies. + -- + process (RST, PLLLOCKED, CK1Mi) + -- + variable counter100K : unsigned(5 downto 0); -- Binary divider to create 100K clock. + variable counter31250: unsigned(6 downto 0); -- Binary divider to create 31.250KHz clock. + variable counter15611: unsigned(7 downto 0); -- Binary divider to create 15.611KHz clock. + + begin + if RST = '1' or PLLLOCKED = '0' then + counter100K := (others => '0'); + counter31250 := (others => '0'); + counter15611 := (others => '0'); + CK100Ki <= '0'; + CK31250i <= '0'; + CK15611i <= '0'; + + elsif rising_edge(CK1Mi) then + + -- 100K + if counter100K = 5 then + counter100K := (others => '0'); + CK100Ki <= not CK100Ki; + else + counter100K := counter100K + 1; + end if; + + -- 31,250KHz + if counter31250 = 16 then + counter31250 := (others => '0'); + CK31250i <= not CK31250i; + else + counter31250 := counter31250 + 1; + end if; + + -- 15.611KHz + if counter15611 = 32 then + counter15611 := (others => '0'); + CK15611i <= not CK15611i; + else + counter15611 := counter15611 + 1; + end if; + end if; + end process; + + -- + -- Clock Generator - Basic divide circuit for middle end frequencies. + -- + process (RST, PLLLOCKED, CK17M7i) + -- + variable counter31500: unsigned(9 downto 0); -- Binary divider to create 31.500KHz clock. + begin + if RST = '1' or PLLLOCKED = '0' then + counter31500 := (others => '0'); + CK31500i <= '0'; + + elsif rising_edge(CK17M7i) then + + -- 31.5KHz + if counter31500 = 281 or counter31500=563 then + CK31500i <= not CK31500i; + counter31500 := (others => '0'); + if counter31500 = 563 then + counter31500 := (others => '0'); + else + counter31500 := counter31500 + 1; + end if; + else + counter31500 := counter31500 + 1; + end if; + + end if; + end process; + + -- + -- Clock Generator - Basic divide circuit for middle end frequencies. + -- + process (RST, PLLLOCKED, CK100Ki) + -- + variable counter10K : unsigned(3 downto 0); -- Binary divider to create 10KHz clock. + variable counter5K : unsigned(4 downto 0); -- Binary divider to create 5KHz clock. + variable counter1K : unsigned(6 downto 0); -- Binary divider to create 1KHz clock. + variable counter500 : unsigned(7 downto 0); -- Binary divider to create 500Hz clock. + begin + if RST = '1' or PLLLOCKED = '0' then + counter10K := (others => '0'); + counter5K := (others => '0'); + counter1K := (others => '0'); + counter500 := (others => '0'); + CK10Ki <= '0'; + CK5Ki <= '0'; + CK1Ki <= '0'; + CK500i <= '0'; + + elsif rising_edge(CK100Ki) then + + -- 10KHz + if counter10K = 5 then + counter10K := (others => '0'); + CK10Ki <= not CK10Ki; + else + counter10K := counter10K + 1; + end if; + + -- 5KHz + if counter5K = 10 then + counter5K := (others => '0'); + CK5Ki <= not CK5Ki; + else + counter5K := counter5K + 1; + end if; + + -- 1KHz + if counter1K = 50 then + counter1K := (others => '0'); + CK1Ki <= not CK1Ki; + else + counter1K := counter1K + 1; + end if; + + -- 500Hz + if counter500 = 100 then + counter500 := (others => '0'); + CK500i <= not CK500i; + else + counter500 := counter500 + 1; + end if; + + end if; + end process; + + -- + -- Clock Generator - Basic divide circuit for middle end frequencies. + -- + process (RST, PLLLOCKED, CK1Ki) + -- + variable counter100 : unsigned(3 downto 0); -- Binary divider to create 100Hz clock. + variable counter50 : unsigned(4 downto 0); -- Binary divider to create 50Hz clock. + variable counter10 : unsigned(6 downto 0); -- Binary divider to create 10Hz clock. + variable counter5 : unsigned(7 downto 0); -- Binary divider to create 5Hz clock. + begin + if RST = '1' or PLLLOCKED = '0' then + counter100 := (others => '0'); + counter50 := (others => '0'); + counter10 := (others => '0'); + counter5 := (others => '0'); + CK100i <= '0'; + CK50i <= '0'; + CK10i <= '0'; + CK5i <= '0'; + + elsif rising_edge(CK1Ki) then + + -- 100Hz + if counter100 = 5 then + counter100 := (others => '0'); + CK100i <= not CK100i; + else + counter100 := counter100 + 1; + end if; + + -- 50Hz + if counter50 = 10 then + counter50 := (others => '0'); + CK50i <= not CK50i; + else + counter50 := counter50 + 1; + end if; + + -- 10Hz + if counter10 = 50 then + counter10 := (others => '0'); + CK10i <= not CK10i; + else + counter10 := counter10 + 1; + end if; + + -- 5Hz + if counter5 = 100 then + counter5 := (others => '0'); + CK5i <= not CK5i; + else + counter5 := counter5 + 1; + end if; + end if; + end process; + + -- + -- Clock Generator - Basic divide circuit for low end frequencies. + -- + process (RST, PLLLOCKED, CK100i) + -- + variable counter2 : unsigned(5 downto 0); -- Binary divider to create 2Hz clock. + variable counter1 : unsigned(6 downto 0); -- Binary divider to create 1Hz clock. + variable counter0_5 : unsigned(7 downto 0); -- Binary divider to create 0.5Hz clock. + variable counter0_2 : unsigned(8 downto 0); -- Binary divider to create 0.2Hz clock. + variable counter0_1 : unsigned(9 downto 0); -- Binary divider to create 0.1Hz clock. + begin + if RST = '1' or PLLLOCKED = '0' then + counter2 := (others => '0'); + counter1 := (others => '0'); + counter0_5 := (others => '0'); + counter0_2 := (others => '0'); + counter0_1 := (others => '0'); + CK2i <= '0'; + CK1i <= '0'; + CK0_5i <= '0'; + CK0_2i <= '0'; + CK0_1i <= '0'; + + elsif rising_edge(CK100i) then + + -- 2Hz + if counter2 = 25 then + counter2 := (others => '0'); + CK2i <= not CK2i; + else + counter2 := counter2 + 1; + end if; + + -- 1Hz + if counter1 = 50 then + counter1 := (others => '0'); + CK1i <= not CK1i; + else + counter1 := counter1 + 1; + end if; + + -- 0.5Hz + if counter0_5 = 100 then + counter0_5 := (others => '0'); + CK0_5i <= not CK0_5i; + else + counter0_5 := counter0_5 + 1; + end if; + + -- 0.2Hz + if counter0_2 = 250 then + counter0_2 := (others => '0'); + CK0_2i <= not CK0_5i; + else + counter0_2 := counter0_2 + 1; + end if; + + -- 0.1Hz + if counter0_1 = 500 then + counter0_1 := (others => '0'); + CK0_1i <= not CK0_5i; + else + counter0_1 := counter0_1 + 1; + end if; + end if; + end process; + + -- + -- Clock Generator - Basic divide circuit based on a 18 bit counter. + -- + process (RST, PLLLOCKED, CK448Mi, CK224Mi, CK112Mi, CK64Mi, CK56Mi, CK32Mi, CK28Mi, CK17M7i, CK16Mi, CK14Mi, CK8M8i, CK8Mi, CK7Mi, CK4Mi, CK3M5i, CK2Mi, + CK1Mi, CK895Ki, CK100Ki, CK31500i, CK31250i, CK15611i, CK10Ki, CK5Ki, CK1Ki, CK500i, CK100i, CK50i, CK10i, CK5i, CK2i, CK1i, CK0_5i, CK0_2i, CK0_1i, + SYSFREQLOCKED, CKCPUi, CKMEMd, CKSOUNDi, CKVIDEOi, CKRTCi, CKPERIPHi, CKLEDSi) + -- + variable mdelay : integer range 0 to 64; -- Memory clock delay line index. + + begin + if RST = '1' or PLLLOCKED = '0' then + mdelay := 32; + CKCPUi <= '0'; + CKMEMd <= (others => '0'); + CKSOUNDi <= '0'; + CKVIDEOi <= '0'; + CKRTCi <= '0'; + CKPERIPHi <= '0'; + CKLEDSi <= '0'; + + elsif rising_edge(CK448Mi) then + + -- Only start meaningful assignment once the main clock frequency is locked. + -- + if SYSFREQLOCKED = '1' then + -- Delay line, different CPU frequencies require different memory delays. + CKMEMd(64 downto 1) <= CKMEMd(63 downto 0); + CKMEMd(0) <= CKCPUi; + + -- If debugging has been enabled and the debug cpu frequency set to a valid value, change cpu clock accordingly. + if DEBUG(ENABLED) = '0' or DEBUG(CPUFREQ) = "0000" then + + -- The CPU speed is configured by the CMT register and CMT state or the CPU register. Select the right + -- frequency and form the clock by flipping on the right flip flag. + -- + case CONFIG(CPUSPEED) is + when "0001" => -- 3.5MHz + mdelay := 20; + CKCPUi <= CK3M5i; + when "0010" => -- 4MHz + mdelay := 16; + CKCPUi <= CK4Mi; + when "0011" => -- 7MHz + mdelay := 10; + CKCPUi <= CK7Mi; + when "0100" => -- 8MHz + mdelay := 8; + CKCPUi <= CK8Mi; + when "0101" => -- 14MHz + mdelay := 4; + CKCPUi <= CK14Mi; + when "0110" => -- 16MHz + mdelay := 4; + CKCPUi <= CK16Mi; + when "0111" => -- 28MHz + mdelay := 2; + CKCPUi <= CK28Mi; + when "1000" => -- 32MHz + mdelay := 4; -- was 2 + CKCPUi <= CK32Mi; + when "1001" => -- 56MHz + mdelay := 4; -- was 3; + CKCPUi <= CK56Mi; + when "1010" => -- 64MHz + mdelay := 2; -- was 2; + CKCPUi <= CK64Mi; + when "1011" => -- 112MHz + mdelay := 1; -- was2; + CKCPUi <= CK112Mi; + + -- Unallocated frequencies, use default. + when "0000"| "1100" | "1101" | "1110" | "1111" => -- 2MHz + mdelay := 32; + CKCPUi <= CK2Mi; + end case; + else + case DEBUG(CPUFREQ) is + when "0000" => -- Use normal cpu frequency, so this choice shouldnt be selected. + mdelay := 32; + CKCPUi <= CK2Mi; + when "0001" => -- 1MHz + mdelay := 64; + CKCPUi <= CK1Mi; + when "0010" => -- 100KHz + mdelay := 12; + CKCPUi <= CK100Ki; + when "0011" => -- 10KHz + mdelay := 24; + CKCPUi <= CK10Ki; + when "0100" => -- 5KHz + mdelay := 32; + CKCPUi <= CK5Ki; + when "0101" => -- 1KHz + mdelay := 36; + CKCPUi <= CK1Ki; + when "0110" => -- 500Hz + mdelay := 40; + CKCPUi <= CK500i; + when "0111" => -- 100Hz + mdelay := 44; + CKCPUi <= CK100i; + when "1000" => -- 50Hz + mdelay := 48; + CKCPUi <= CK50i; + when "1001" => -- 10Hz + mdelay := 52; + CKCPUi <= CK10i; + when "1010" => -- 5Hz + mdelay := 56; + CKCPUi <= CK5i; + when "1011" => -- 2Hz + mdelay := 58; + CKCPUi <= CK2i; + when "1100" => -- 1Hz + mdelay := 60; + CKCPUi <= CK1i; + when "1101" => -- 0.5Hz + mdelay := 60; + CKCPUi <= CK0_5i; + when "1110" => -- 0.2Hz + mdelay := 60; + CKCPUi <= CK0_2i; + when "1111" => -- 0.1Hz + mdelay := 60; + CKCPUi <= CK0_1i; + end case; + end if; + + -- Form the video frequency according to the user selection. + -- + case CONFIG(VIDSPEED) is + when "000" => -- 8MHz + CKVIDEOi <= CK8Mi; + + when "001" => -- 16MHz + CKVIDEOi <= CK16Mi; + + when "010" => -- 8.8672375MHz + CKVIDEOi <= CK8M8i; + + when "011" => -- 17.734475MHz + CKVIDEOi <= CK17M7i; + + when "100" | "101" | "110" | "111" => -- Unassigned default to 8MHz + CKVIDEOi <= CK8Mi; + end case; + + -- Form the RTC frequency according to the user selection. + -- + case CONFIG(RTCSPEED) is + when "01" => -- 31,250KHz + CKRTCi <= CK31250i; + when "10" => -- 15.611KHz + CKRTCi <= CK15611i; + when "00" | "11" => -- 31.5KHz + CKRTCi <= CK31500i; + end case; + + -- Form the peripheral frequency according to the user selection. + -- + case CONFIG(PERSPEED) is + when "00" | "01" | "10" | "11" => + CKPERIPHi <= CK2Mi; + end case; + + -- Form the sound frequency according to the user selection. + -- + case CONFIG(SNDSPEED) is + when "01" => -- 895K + CKSOUNDi <= CK895Ki; + + when "00" | "10" | "11" => + CKSOUNDi <= CK2Mi; + end case; + + -- Sampling frequency of signals, typically used to drive LED outputs but could easily be read by an oscilloscope. + -- + case DEBUG(SMPFREQ) is + when "0000" => -- Use normal cpu frequency. + CKLEDSi <= CKCPUi; + when "0001" => -- 1MHz + CKLEDSi <= CK1Mi; + when "0010" => -- 100KHz + CKLEDSi <= CK100Ki; + when "0011" => -- 10KHz + CKLEDSi <= CK10Ki; + when "0100" => -- 5KHz + CKLEDSi <= CK5Ki; + when "0101" => -- 1KHz + CKLEDSi <= CK1Ki; + when "0110" => -- 500Hz + CKLEDSi <= CK500i; + when "0111" => -- 100Hz + CKLEDSi <= CK100i; + when "1000" => -- 50Hz + CKLEDSi <= CK50i; + when "1001" => -- 10Hz + CKLEDSi <= CK10i; + when "1010" => -- 5Hz + CKLEDSi <= CK5i; + when "1011" => -- 2Hz + CKLEDSi <= CK2i; + when "1100" => -- 1Hz + CKLEDSi <= CK1i; + when "1101" => -- 0.5Hz + CKLEDSi <= CK0_5i; + when "1110" => -- 0.2Hz + CKLEDSi <= CK0_2i; + when "1111" => -- 0.1Hz + CKLEDSi <= CK0_1i; + end case; + end if; + end if; + + -- Until the clock generator is programmed and locked to the initial + -- frequency as determined by mctrl, default to a fixed speed set. + -- + if SYSFREQLOCKED = '0' then + CLKBUS(CKCPU) <= CK2Mi; + CLKBUS(CKMEM) <= CKMEMd(32); + CLKBUS(pkgs.clkgen_pkg.CKSYS) <= CK224Mi; + CLKBUS(CKHPS) <= CK32Mi; + CLKBUS(CKSOUND) <= CK2Mi; + CLKBUS(CKRTC) <= CK31500i; + CLKBUS(CKVIDEO) <= CK8Mi; + CLKBUS(CKPERIPH) <= CK2Mi; + CLKBUS(CKLEDS) <= CK100Ki; + CLKBUS(CKRESET) <= CK224Mi; + else + CLKBUS(CKCPU) <= CKCPUi; -- CPU clock. + CLKBUS(CKMEM) <= CKMEMd(mdelay); -- Synchronous Memory clock. + CLKBUS(pkgs.clkgen_pkg.CKSYS) <= CK224Mi; -- System clock. + CLKBUS(CKHPS) <= CK32Mi; -- HPS Sysyem clock. + CLKBUS(CKSOUND) <= CKSOUNDi; -- Clock for the sound generator, + CLKBUS(CKRTC) <= CKRTCi; -- Clock for the RTC generator, + CLKBUS(CKVIDEO) <= CKVIDEOi; -- Video base clock. + CLKBUS(CKPERIPH) <= CKPERIPHi; -- Peripheral base clock. + CLKBUS(CKLEDS) <= CKLEDSi; -- Output sampling base frequency. + CLKBUS(CKRESET) <= CK224Mi; + -- + end if; + end process; + +end RTL; diff --git a/common/dpram.vhd b/common/dpram.vhd new file mode 100644 index 0000000..e61f2ac --- /dev/null +++ b/common/dpram.vhd @@ -0,0 +1,169 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: dpram.vhd +-- Created: July 2018 +-- Author(s): Altera/Intel - refactored by Philip Smart +-- Description: Dual Port RAM as provided by Altera in the Megafunctions suite. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + widthad_b : natural; + width_b : natural := 8; +-- clock_en_a : string := "NORMAL"; +-- clock_en_b : string := "NORMAL"; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + clock_a : IN STD_LOGIC; + clocken_a : IN STD_LOGIC := '1'; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + clock_b : IN STD_LOGIC; + clocken_b : IN STD_LOGIC := '1'; + address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); + wren_b : IN STD_LOGIC := '1'; + q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + clock0 : IN STD_LOGIC ; + clocken0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + clock1 : IN STD_LOGIC ; + clocken1 : IN STD_LOGIC ; + address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); + wren_b : IN STD_LOGIC ; + q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_b-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_b, + operation_mode => "BIDIR_DUAL_PORT", + --operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + widthad_b => widthad_b, + width_a => width_a, + width_b => width_b, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + clock0 => clock_a, + clocken0 => clocken_a, + address_a => address_a, + data_a => data_a, + wren_a => wren_a, + q_a => sub_wire0, + + clock1 => clock_b, + clocken1 => clocken_b, + address_b => address_b, + wren_b => wren_b, + data_b => data_b, + q_b => sub_wire1 + ); + + + +END SYN; diff --git a/common/dprom.vhd b/common/dprom.vhd new file mode 100644 index 0000000..8591047 --- /dev/null +++ b/common/dprom.vhd @@ -0,0 +1,160 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: dprom.vhd +-- Created: July 2018 +-- Author(s): Altera/Intel - refactored by Philip Smart +-- Description: Dual Port ROM as provided by Altera in the Megafunctions suite. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dprom IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_b : IN STD_LOGIC ; + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_b : IN STD_LOGIC; + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dprom; + + +ARCHITECTURE SYN OF dprom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock0 : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock1 : IN STD_LOGIC ; + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_b : IN STD_LOGIC ; + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + --operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + clock0 => clock_a, + data_a => data_a, + wren_a => wren_a, + q_a => sub_wire0, + + address_b => address_b, + clock1 => clock_b, + data_b => data_b, + wren_b => wren_b, + q_b => sub_wire1 + ); + + + +END SYN; diff --git a/common/i8253/counter0.vhd b/common/i8253/counter0.vhd new file mode 100644 index 0000000..4ab1751 --- /dev/null +++ b/common/i8253/counter0.vhd @@ -0,0 +1,145 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: counter0.vhd +-- Created: July 2018 +-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart +-- Description: Sharp MZ series i8253 PIT - Counter 0 +-- This module emulates Counter 0 of the Intel i8253 Programmable Interval Timer. +-- +-- Credits: +-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart +-- +-- History: July 2018 - Initial module refactored and updated for this emulation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter0 is + Port ( + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WRM : in std_logic; + WRD : in std_logic; + KCLK : in std_logic; + CLK : in std_logic; + GATE : in std_logic; + POUT : out std_logic + ); +end counter0; + +architecture Behavioral of counter0 is + +-- +-- counter +-- +signal CREG : std_logic_vector(15 downto 0); +-- +-- initialize +-- +signal INIV : std_logic_vector(15 downto 0); +signal RL : std_logic_vector(1 downto 0); +signal PO : std_logic; +signal UL : std_logic; +signal NEWM : std_logic; +-- +-- count control +-- +signal CEN : std_logic; +signal GT : std_logic; + +begin + + -- Default for unused bus. + DO <= "00000000"; + + -- + -- Counter access mode + -- + process( KCLK, WRM ) begin + if( KCLK'event and KCLK='1' and WRM='0' ) then + RL<=DI(5 downto 4); + end if; + end process; + + -- + -- Counter initialize + -- + process( KCLK, WRD, WRM ) begin + if( KCLK'event and KCLK='1' ) then + if( WRM='0' ) then + NEWM<='1'; + UL<='0'; + elsif( WRD='0' ) then + if( RL="01" ) then + INIV(7 downto 0)<=DI; + NEWM<='0'; + elsif( RL="10" ) then + INIV(15 downto 8)<=DI; + NEWM<='0'; + elsif( RL="11" ) then + if( UL='0' ) then + INIV(7 downto 0)<=DI; + UL<='1'; + else + INIV(15 downto 8)<=DI; + UL<='0'; + NEWM<='0'; + end if; + end if; + end if; + end if; + end process; + + -- + -- Count enable + -- + CEN<='1' when NEWM='0' and GATE='1' else '0'; + + -- + -- Count (mode 3) + -- + process( CLK, WRM, DI(3 downto 1) ) begin + if( CLK'event and CLK='1' ) then + GT<=GATE; + if( WRM='0' ) then + case DI(3 downto 1) is + when "000" => PO<='0'; + when others => PO<='1'; + end case; + elsif( (GT='0' and GATE='1') or CREG=2 ) then + CREG<=INIV; + PO<=not PO; + elsif( CEN='1' ) then + if( CREG(0)='1' ) then + if( PO='1' ) then + CREG<=CREG-3; + else + CREG<=CREG-1; + end if; + else + CREG<=CREG-2; + end if; + end if; + end if; + end process; + + POUT<=PO; + +end Behavioral; diff --git a/common/i8253/counter1.vhd b/common/i8253/counter1.vhd new file mode 100644 index 0000000..3a1423e --- /dev/null +++ b/common/i8253/counter1.vhd @@ -0,0 +1,136 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: counter1.vhd +-- Created: July 2018 +-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart +-- Description: Sharp MZ series i8253 PIT - Counter 1 +-- This module emulates Counter 1 of the Intel i8253 Programmable Interval Timer. +-- +-- Credits: +-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart +-- +-- History: July 2018 - Initial module refactored and updated for this emulation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter1 is + Port ( + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WRM : in std_logic; + WRD : in std_logic; + KCLK : in std_logic; + CLK : in std_logic; + GATE : in std_logic; + POUT : out std_logic + ); +end counter1; + +architecture Behavioral of counter1 is + +-- counter +-- +signal CREG : std_logic_vector(15 downto 0); +-- +-- initialize +-- +signal INIV : std_logic_vector(15 downto 0); +signal RL : std_logic_vector(1 downto 0); +signal PO : std_logic; +signal UL : std_logic; +signal NEWM : std_logic; +-- +-- count control +-- +signal CEN : std_logic; +signal GT : std_logic; + +begin + + -- Default for unused bus. + DO <= "00000000"; + + -- + -- Counter access mode + -- + process( KCLK, WRM ) begin + if( KCLK'event and KCLK='1' and WRM='0' ) then + RL<=DI(5 downto 4); + end if; + end process; + + -- + -- Counter initialize + -- + process( KCLK ) begin + if( KCLK'event and KCLK='1' ) then + if( WRM='0' ) then + NEWM<='1'; + UL<='0'; + elsif( WRD='0' ) then + if( RL="01" ) then + INIV(7 downto 0)<=DI; + NEWM<='0'; + elsif( RL="10" ) then + INIV(15 downto 8)<=DI; + NEWM<='0'; + elsif( RL="11" ) then + if( UL='0' ) then + INIV(7 downto 0)<=DI; + UL<='1'; + else + INIV(15 downto 8)<=DI; + UL<='0'; + NEWM<='0'; + end if; + end if; + end if; + end if; + end process; + + -- + -- Count enable + -- + CEN<='1' when NEWM='0' and GATE='1' else '0'; + + -- + -- Count (mode 2) + -- + process( CLK ) begin + if( CLK'event and CLK='0' ) then + GT<=GATE; + if( WRM='0' ) then + PO<='1'; + elsif( (GT='0' and GATE='1') or CREG=1 ) then + CREG<=INIV; + PO<='1'; + elsif( CREG=2 ) then + PO<='0'; + CREG<=CREG-1; + elsif( CEN='1' ) then + CREG<=CREG-1; + end if; + end if; + end process; + + POUT<=PO when GATE='1' else '1'; + +end Behavioral; diff --git a/common/i8253/counter2.vhd b/common/i8253/counter2.vhd new file mode 100644 index 0000000..9a96814 --- /dev/null +++ b/common/i8253/counter2.vhd @@ -0,0 +1,182 @@ + +-- +-- counter2.vhd +--------------------------------------------------------------------------------------------------------- +-- +-- Name: counter2.vhd +-- Created: July 2018 +-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart +-- Description: Sharp MZ series i8253 PIT - Counter 2 +-- This module emulates Counter 2 of the Intel i8253 Programmable Interval Timer. +-- +-- Credits: +-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart +-- +-- History: July 2018 - Initial module refactored and updated for this emulation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +----------------------------------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity counter2 is + Port ( + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WRD : in std_logic; + WRM : in std_logic; + KCLK : in std_logic; + RD : in std_logic; + CLK : in std_logic; + GATE : in std_logic; + POUT : out std_logic + ); +end counter2; + +architecture Behavioral of counter2 is + +-- +-- counter +-- +signal CREG : std_logic_vector(15 downto 0); +-- +-- initialize and read out +-- +signal INIV : std_logic_vector(15 downto 0); +signal RL : std_logic_vector(1 downto 0); +signal WUL : std_logic; +signal RUL : std_logic; +-- +-- count control +-- +signal PO : std_logic; +signal CD : std_logic_vector(15 downto 0); +signal DTEN : std_logic; +signal CEN : std_logic; +signal LEN : std_logic; +signal LEN_S : std_logic; + +begin + + -- + -- Counter latch + -- + process( KCLK, WRM ) begin + if( KCLK'event and KCLK='1' and WRM='0' ) then + if( DI(5 downto 4)="00" ) then + CD<=CREG; + else + RL<=DI(5 downto 4); + end if; + end if; + end process; + + -- + -- Initialize + -- + process( KCLK, WRD, WRM, DI(5 downto 4) ) begin + if( KCLK'event and KCLK='1' ) then + if( WRM='0' ) then + if( DI(5 downto 4)/="00" ) then + WUL<='0'; + end if; + elsif( WRD='0' ) then + if( RL="01" ) then + INIV(7 downto 0)<=DI; + LEN<='1'; + CEN<='1'; + elsif( RL="10" ) then + INIV(15 downto 8)<=DI; + LEN<='1'; + CEN<='1'; + elsif( RL="11" ) then + if( WUL='0' ) then + INIV(7 downto 0)<=DI; + WUL<='1'; + LEN<='0'; + CEN<='0'; + else + INIV(15 downto 8)<=DI; + WUL<='0'; + LEN<='1'; + CEN<='1'; + end if; + end if; + else + LEN<='0'; + end if; + end if; + end process; + + -- + -- Read control + -- + process( RD, WRM, DI(5 downto 4) ) begin + if( WRM='0' ) then + if( DI(5 downto 4)="00" ) then + DTEN<='1'; + else + RUL<='0'; + end if; + elsif( RD'event and RD='1' ) then + RUL<=not RUL; + if( DTEN='1' and RUL='1' ) then + DTEN<='0'; + end if; + end if; + end process; + + DO<=CD(7 downto 0) when RUL='0' and DTEN='1' else + CD(15 downto 8) when RUL='1' and DTEN='1' else + CREG(7 downto 0) when RUL='0' and DTEN='0' else + CREG(15 downto 8) when RUL='1' and DTEN='0' else (others=>'1'); + + -- + -- Count (mode 0) + -- + process( CLK, WRM, WRD, DI(5 downto 4), RL, LEN, WUL ) begin + if LEN='1' then + LEN_S<='1'; + PO<='0'; + elsif CLK'event and CLK='0' then + if WRM='0' then + if DI(5 downto 4)/="00" then + PO<='0'; + end if; + elsif GATE='1' and CEN='1' then + if CREG=1 then + PO<='1'; + end if; + if LEN_S='1' then + CREG<=INIV; + LEN_S<='0'; + else + CREG<=CREG-1; + end if; + end if; + end if; + end process; + + POUT<=PO; + +end Behavioral; diff --git a/common/i8253/i8253.vhd b/common/i8253/i8253.vhd new file mode 100644 index 0000000..dbb9be8 --- /dev/null +++ b/common/i8253/i8253.vhd @@ -0,0 +1,161 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: i8253.vhd +-- Created: July 2018 +-- Author(s): Nibbles Lab (C) 2005 - 2012, Refactored and ported for this emulation by Philip Smart +-- Description: Sharp MZ series i8253 PIT +-- This module emulates the Intel i8253 Programmable Interval Timer. +-- +-- Credits: +-- Copyright: (c) 2005-2012 Nibbles Lab, 2018 Philip Smart +-- +-- History: July 2018 - Initial module refactored and updated for this emulation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity i8253 is + Port ( + RST : in std_logic; + CLK : in std_logic; + A : in std_logic_vector(1 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CS_n : in std_logic; + WR_n : in std_logic; + RD_n : in std_logic; + CLK0 : in std_logic; + GATE0 : in std_logic; + OUT0 : out std_logic; + CLK1 : in std_logic; + GATE1 : in std_logic; + OUT1 : out std_logic; + CLK2 : in std_logic; + GATE2 : in std_logic; + OUT2 : out std_logic + ); +end i8253; + +architecture Behavioral of i8253 is + +signal WRD0 : std_logic; +signal WRD1 : std_logic; +signal WRD2 : std_logic; +signal WRM0 : std_logic; +signal WRM1 : std_logic; +signal WRM2 : std_logic; +--signal RD0 : std_logic; +signal RD1 : std_logic; +signal RD2 : std_logic; +signal DO0 : std_logic_vector(7 downto 0); +signal DO1 : std_logic_vector(7 downto 0); +signal DO2 : std_logic_vector(7 downto 0); + +component counter0 + Port ( + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WRD : in std_logic; + WRM : in std_logic; + KCLK : in std_logic; + CLK : in std_logic; + GATE : in std_logic; + POUT : out std_logic + ); +end component; + +component counter1 + Port ( + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WRD : in std_logic; + WRM : in std_logic; + KCLK : in std_logic; + CLK : in std_logic; + GATE : in std_logic; + POUT : out std_logic + ); +end component; + +component counter2 + Port ( + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + WRD : in std_logic; + WRM : in std_logic; + KCLK : in std_logic; + RD : in std_logic; + CLK : in std_logic; + GATE : in std_logic; + POUT : out std_logic + ); +end component; + +begin + + WRD0 <= WR_n when CS_n='0' and A="00" else '1'; + WRD1 <= WR_n when CS_n='0' and A="01" else '1'; + WRD2 <= WR_n when CS_n='0' and A="10" else '1'; + WRM0 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="00" else '1'; + WRM1 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="01" else '1'; + WRM2 <= WR_n when CS_n='0' and A="11" and DI(7 downto 6)="10" else '1'; +-- RD0 <= RD_n when CS_n='0' and A="00" else '1'; + RD1 <= RD_n when CS_n='0' and A="01" else '1'; + RD2 <= RD_n when CS_n='0' and A="10" else '1'; + + DO <= DO0 when CS_n='0' and A="00" else + DO1 when CS_n='0' and A="01" else + DO2 when CS_n='0' and A="10" else (others=>'1'); + + CTR0 : counter0 port map ( + DI => DI, + DO => DO0, + WRD => WRD0, + WRM => WRM0, + KCLK => CLK, + CLK => CLK0, + GATE => GATE0, + POUT => OUT0 + ); + + CTR1 : counter1 port map ( + DI => DI, + DO => DO1, + WRD => WRD1, + WRM => WRM1, + KCLK => CLK, + CLK => CLK1, + GATE => GATE1, + POUT => OUT1 + ); + + CTR2 : counter2 port map ( + DI => DI, + DO => DO2, + WRD => WRD2, + WRM => WRM2, + KCLK => CLK, + RD => RD2, + CLK => CLK2, + GATE => GATE2, + POUT => OUT2 + ); + +end Behavioral; diff --git a/common/i8255/i8255.vhd b/common/i8255/i8255.vhd new file mode 100644 index 0000000..7af5db5 --- /dev/null +++ b/common/i8255/i8255.vhd @@ -0,0 +1,700 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: i8255.vhd +-- Created: Feb 2007 +-- Author(s): MikeJ, Refactored and ported for this emulation by Philip Smart +-- Description: Sharp MZ series i8255 PPI +-- This module emulates the Intel i8255 Programmable Peripheral Interface chip. +-- +-- Credits: +-- Copyright: (c) MikeJ - Feb 2007 +-- +-- History: July 2018 - Initial module refactored and updated for this emulation. +-- +--------------------------------------------------------------------------------------------------------- +-- +-- Original copyright notice below:- +-- +-- A simulation model of i8255 PIA +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +--------------------------------------------------------------------------------------------------------- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity i8255 is + port ( + RESET : in std_logic; + CLK : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + DI : in std_logic_vector(7 downto 0); -- D7-D0 + DO : out std_logic_vector(7 downto 0); +-- DO_OE_n : out std_logic; + CS_n : in std_logic; + RD_n : in std_logic; + WR_n : in std_logic; + + PA_I : in std_logic_vector(7 downto 0); + PA_O : out std_logic_vector(7 downto 0); + PA_O_OE_n : out std_logic_vector(7 downto 0); + + PB_I : in std_logic_vector(7 downto 0); + PB_O : out std_logic_vector(7 downto 0); + PB_O_OE_n : out std_logic_vector(7 downto 0); + + PC_I : in std_logic_vector(7 downto 0); + PC_O : out std_logic_vector(7 downto 0); + PC_O_OE_n : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of i8255 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(DI) + begin + bit_mask <= x"01"; + case DI(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and DI(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (CS_n = '0') and (WR_n = '0') then + case ADDR is + when "00" => r_porta <= DI; + when "01" => r_portb <= DI; + when "10" => r_portc <= DI; + + when "11" => if (DI(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= DI; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + --p_oe : process(CS_n, RD_n) + --begin + -- DO_OE_n <= '1'; + -- if (CS_n = '0') and (RD_n = '0') then + -- DO_OE_n <= '0'; + -- end if; + --end process; + + p_read : process(ADDR , porta_read, portb_read, portc_read, control_read) + begin + DO <= x"00"; -- default + --if (CS_n = '0') and (RD_n = '0') then -- not required + case ADDR is + when "00" => DO <= porta_read; + when "01" => DO <= portb_read; + when "10" => DO <= portc_read; + when "11" => DO <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(CS_n, RD_n, WR_n, ADDR ) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (CS_n = '0') and (ADDR = "00") then + porta_we <= not WR_n; + porta_re <= not RD_n; + end if; + + if (CS_n = '0') and (ADDR = "01") then + portb_we <= not WR_n; + portb_re <= not RD_n; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (CS_n = '0') and (WR_n = '0') and (ADDR = "11") and (DI(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= DI(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= DI(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= DI(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= DI(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= DI(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= DI(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= DI(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= DI(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_porta, r_control, groupa_mode, PA_I, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + PA_O <= x"FF"; -- if not driven, float high + PA_O_OE_n <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + PA_O <= r_porta; + PA_O_OE_n <= x"00"; + end if; + porta_read <= PA_I; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + PA_O <= r_porta; + PA_O_OE_n <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + PA_O <= r_porta; + PA_O_OE_n <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_portb, r_control, groupb_mode, PB_I, portb_ipreg) + begin + PB_O <= x"FF"; -- if not driven, float high + PB_O_OE_n <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + PB_O <= r_portb; + PB_O_OE_n <= x"00"; + end if; + portb_read <= PB_I; + else -- strobed mode + if (r_control(1) = '0') then -- output + PB_O <= r_portb; + PB_O_OE_n <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + PC_O <= x"FF"; -- if not driven, float high + PC_O_OE_n <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + PC_O (7 downto 4) <= r_portc(7 downto 4); + PC_O_OE_n(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + PC_O (7) <= a_obf_l; + PC_O_OE_n(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + PC_O (5 downto 4) <= r_portc(5 downto 4); + PC_O_OE_n(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + PC_O (7 downto 6) <= r_portc(7 downto 6); + PC_O_OE_n(7 downto 6) <= "00"; + end if; + PC_O (5) <= a_ibf; + PC_O_OE_n(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + PC_O (7) <= a_obf_l; + PC_O_OE_n(7) <= '0'; + -- 6 is ack_l input + PC_O (5) <= a_ibf; + PC_O_OE_n(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + PC_O (3) <= r_portc(3); + PC_O_OE_n(3) <= '0'; + end if; + -- + else -- stolen + PC_O (3) <= a_intr; + PC_O_OE_n(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + PC_O (2 downto 0) <= r_portc(2 downto 0); + PC_O_OE_n(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + PC_O (1) <= b_obf_l; + PC_O_OE_n(1) <= '0'; + else -- input + PC_O (1) <= b_ibf; + PC_O_OE_n(1) <= '0'; + end if; + PC_O (0) <= b_intr; + PC_O_OE_n(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, PC_I, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= PC_I(6); + else -- port a input + a_stb_l <= PC_I(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= PC_I(6); + a_stb_l <= PC_I(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= PC_I(2); + else -- input + b_stb_l <= PC_I(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= PC_I(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & PC_I(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= PC_I(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= PC_I(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= PA_I; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= PB_I; + end if; + end if; + end process; + +end architecture RTL; diff --git a/common/keymatrix.vhd b/common/keymatrix.vhd new file mode 100644 index 0000000..eabda1b --- /dev/null +++ b/common/keymatrix.vhd @@ -0,0 +1,289 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: keymatrix.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: Keyboard module to convert PS2 key codes into Sharp scan matrix key connections. +-- For each scan output (10 lines) sent by the Sharp, an 8bit response is read in +-- and the bits set indicate keys pressed. This allows for multiple keys to be pressed +-- at the same time. The PS2 scan code is mapped via a rom and the output is used to drive +-- the data in lines of the 8255. +-- +-- Credits: Nibbles Lab (c) 2005-2012 +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written, originally based on the Nibbles Lab code but +-- rewritten to match the overall design of this emulation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library IEEE; +library pkgs; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; + +entity keymatrix is + Port ( + RST_n : in std_logic; + + -- i8255 + PA : in std_logic_vector(3 downto 0); + PB : out std_logic_vector(7 downto 0); + STALL : in std_logic; + + -- PS/2 Keyboard Data + PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data. + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Clock signals used by this module. + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. + ); +end keymatrix; + +architecture Behavioral of keymatrix is + +-- +-- prefix flag +-- +signal FLGF0 : std_logic; +signal FLGE0 : std_logic; +-- +-- MZ-series matrix registers +-- +signal SCAN00 : std_logic_vector(7 downto 0); +signal SCAN01 : std_logic_vector(7 downto 0); +signal SCAN02 : std_logic_vector(7 downto 0); +signal SCAN03 : std_logic_vector(7 downto 0); +signal SCAN04 : std_logic_vector(7 downto 0); +signal SCAN05 : std_logic_vector(7 downto 0); +signal SCAN06 : std_logic_vector(7 downto 0); +signal SCAN07 : std_logic_vector(7 downto 0); +signal SCAN08 : std_logic_vector(7 downto 0); +signal SCAN09 : std_logic_vector(7 downto 0); +signal SCAN10 : std_logic_vector(7 downto 0); +signal SCAN11 : std_logic_vector(7 downto 0); +signal SCAN12 : std_logic_vector(7 downto 0); +signal SCAN13 : std_logic_vector(7 downto 0); +signal SCAN14 : std_logic_vector(7 downto 0); +signal SCANLL : std_logic_vector(7 downto 0); +-- +-- Key code exchange table +-- +signal MTEN : std_logic_vector(3 downto 0); +signal F_KBDT : std_logic_vector(7 downto 0); +signal MAP_DATA : std_logic_vector(7 downto 0); +signal MAP_ADDR : std_logic_vector(7 downto 0); +signal KEY_BANK : std_logic_vector(2 downto 0); + +-- +-- HPS access +-- +signal IOCTL_KEYMAP_WEN : std_logic; +signal IOCTL_DIN_KEYMAP : std_logic_vector(7 downto 0); -- HPS Data to be read into HPS. + +signal KEY_EXTENDED : std_logic; +signal KEY_FLAG : std_logic; +signal KEY_PRESS : std_logic; +signal KEY_VALID : std_logic; +-- +-- Components +-- +component dprom + GENERIC ( + init_file : string; + widthad_a : natural; + width_a : natural + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; +-- data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); +-- wren_a : IN STD_LOGIC; + wren_b : IN STD_LOGIC; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +end component; + +begin + -- + -- Instantiation + -- + -- 0 = MZ80K KEYMAP = 256Bytes -> 0000:00ff 0000 bytes padding + -- 1 = MZ80C KEYMAP = 256Bytes -> 0100:01ff 0000 bytes padding + -- 2 = MZ1200 KEYMAP = 256Bytes -> 0200:02ff 0000 bytes padding + -- 3 = MZ80A KEYMAP = 256Bytes -> 0300:03ff 0000 bytes padding + -- 4 = MZ700 KEYMAP = 256Bytes -> 0400:04ff 0000 bytes padding + -- 5 = MZ80B KEYMAP = 256Bytes -> 0500:05ff 0000 bytes padding + + MAP0 : dprom + GENERIC MAP ( + --init_file => "./mif/key_80k_80b.mif", + init_file => "./mif/combined_keymap.mif", + widthad_a => 11, + width_a => 8 + ) + PORT MAP ( + clock_a => CLKBUS(CKCPU), + address_a => KEY_BANK & F_KBDT, +-- data_a => IOCTL_DOUT(7 DOWNTO 0), +-- wren_a => + q_a => MAP_DATA, + + clock_b => IOCTL_CLK, + address_b => IOCTL_ADDR(10 DOWNTO 0), + data_b => IOCTL_DOUT(7 DOWNTO 0), + wren_b => IOCTL_KEYMAP_WEN, + q_b => IOCTL_DIN_KEYMAP + ); + + -- Store changes to the key valid flag in a flip flop. + process( CLKBUS(CKCPU) ) begin + if rising_edge(CLKBUS(CKCPU)) then + KEY_FLAG <= PS2_KEY(10); + end if; + end process; + + KEY_PRESS <= PS2_KEY(9); + KEY_EXTENDED <= PS2_KEY(8); + KEY_VALID <= '1' when KEY_FLAG /= PS2_KEY(10) else '0'; + KEY_BANK <= "000" when CONFIG(MZ80K) = '1' else -- Key map for MZ80K + "001" when CONFIG(MZ80C) = '1' else -- Key map for MZ80C + "010" when CONFIG(MZ1200) = '1' else -- Key map for MZ1200 + "011" when CONFIG(MZ80A) = '1' else -- Key map for MZ80A + "100" when CONFIG(MZ700) = '1' else -- Key map for MZ700 + "101" when CONFIG(MZ800) = '1' else -- Key map for MZ800 + "110" when CONFIG(MZ80B) = '1' else -- Key map for MZ80B + "111" when CONFIG(MZ2000) = '1'; -- Key map for MZ2000 + + -- + -- Convert + -- + process( RST_n, CLKBUS(CKCPU) ) begin + if RST_n = '0' then + SCAN00 <= (others=>'0'); + SCAN01 <= (others=>'0'); + SCAN02 <= (others=>'0'); + SCAN03 <= (others=>'0'); + SCAN04 <= (others=>'0'); + SCAN05 <= (others=>'0'); + SCAN06 <= (others=>'0'); + SCAN07 <= (others=>'0'); + SCAN08 <= (others=>'0'); + SCAN09 <= (others=>'0'); + SCAN10 <= (others=>'0'); + SCAN11 <= (others=>'0'); + SCAN12 <= (others=>'0'); + SCAN13 <= (others=>'0'); + SCAN14 <= (others=>'0'); + FLGF0 <= '0'; + FLGE0 <= '0'; + MTEN <= (others=>'0'); + MAP_ADDR <= (others=>'1'); + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then + MTEN <= MTEN(2 downto 0) & KEY_VALID; + if KEY_VALID='1' then + if(KEY_EXTENDED='1') then + FLGE0 <= '1'; + end if; + if(KEY_PRESS='0') then + FLGF0 <= '1'; + end if; + if(PS2_KEY(7 downto 0) = X"AA" ) then + F_KBDT <= X"EF"; + else + F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0'; + end if; + end if; + + if MTEN(3)='1' then + case MAP_DATA(7 downto 4) is + when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; + when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0'; + end case; + end if; + end if; + end process; + + PA_L : for I in 0 to 7 generate + SCANLL(I) <= SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I) or + SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I) or + SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I); + end generate PA_L; + + -- + -- response from key access + -- + PB <= (not SCANLL) when STALL='0' and CONFIG(MZ_B)='1' else + (not SCAN00) when PA="0000" else + (not SCAN01) when PA="0001" else + (not SCAN02) when PA="0010" else + (not SCAN03) when PA="0011" else + (not SCAN04) when PA="0100" else + (not SCAN05) when PA="0101" else + (not SCAN06) when PA="0110" else + (not SCAN07) when PA="0111" else + (not SCAN08) when PA="1000" else + (not SCAN09) when PA="1001" else + (not SCAN10) when PA="1010" else + (not SCAN11) when PA="1011" else + (not SCAN12) when PA="1100" else + (not SCAN13) when PA="1101" else (others=>'1'); + + -- + -- HPS access to reload keymap. + -- + IOCTL_KEYMAP_WEN <= '1' when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_WR = '1' + else '0'; + IOCTL_DIN <= X"00" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_RD = '1' + else + (others=>'0'); + +end Behavioral; diff --git a/common/mctrl.vhd b/common/mctrl.vhd new file mode 100644 index 0000000..9e9d08a --- /dev/null +++ b/common/mctrl.vhd @@ -0,0 +1,578 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: mctrl.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: Sharp MZ series Programmable Machine Control logic. +-- This module forms the Programmable control of the emulation along with sync reset +-- management. +-- A set of 16 addressable registers is presented on the external IOCTL interface. +-- Each register controls an aspect of the emulation, such as video mode or cpu speed. +-- +-- Reset to all components is managed by this module, taking cold, warm and internally +-- generated reset signals and creating a unified system reset output. +-- +-- Please see the docs/SharpMZ_Notes.xlsx spreadsheet for details on these registers +-- and the values they take. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +package mctrl_pkg is + + -- Config Bus + -- + subtype CONFIG_WIDTH is integer range 58 downto 0; + + + -- Mode signals indicating type of machine we are emulating. + -- + constant MZ80K : integer := 0; -- Machine is an MZ80K + constant MZ80C : integer := 1; -- Machine is an MZ80C + constant MZ1200 : integer := 2; -- Machine is an MZ1200 + constant MZ80A : integer := 3; -- Machine is an MZ80A + constant MZ700 : integer := 4; -- Machine is an MZ700 + constant MZ800 : integer := 5; -- Machine is an MZ800 + constant MZ80B : integer := 6; -- Machine is an MZ80B + constant MZ2000 : integer := 7; -- Machine is an MZ2000 + subtype CURRENTMACHINE is integer range 7 downto 0; -- Range of bits to indicate current machine, only 1 bit is set at a time. + constant MZ_KC : integer := 8; -- Machine is an MZ80K/MZ80C + constant MZ_A : integer := 9; -- Machine is an MZ1200/MZ80A + constant MZ_B : integer := 10; -- Machine is an MZ2000/MZ80B + constant MZ_80B : integer := 11; -- Machine is an MZ2000/MZ80B + constant MZ_80C : integer := 12; -- Machine is an MZ80K/MZ80C/MZ1200/MZ80A + + -- Type of display to emulate. + -- + constant NORMAL : integer := 13; -- Normal 40 x 25 character monochrome display. + constant NORMAL80 : integer := 14; -- Normal 80 x 25 character monochrome display. + constant COLOUR : integer := 15; -- Colour 40 x 25 character display. + constant COLOUR80 : integer := 16; -- Colour 80 x 25 character display. + + -- Option Roms Enable (some machines by design dont have them, but this emulation allows them to be enabled if needed). + -- + subtype USERROM is integer range 24 downto 17; -- User ROM E800 - EFFF enable per machine. + subtype FDCROM is integer range 32 downto 25; -- FDC ROM F000 - FFFF enable per machine. + + -- Various configurable settings. + -- + constant AUDIOSRC : integer := 33; -- Audio source, 0 = sound generator, 1 = tape audio. + subtype TURBO is integer range 36 downto 34; -- 2MHz/4MHz/8MHz/16MHz/32MHz switch (various). + subtype FASTTAPE is integer range 39 downto 37; -- Speed of tape read/write. + subtype BUTTONS is integer range 41 downto 40; -- Various external buttons, such as CMT play/record. + constant PCGRAM : integer := 42; -- PCG ROM(0) or RAM(1) based. + constant VRAMWAIT : integer := 43; -- Insert video wait states on CPU access as per original design. + constant VRAMDISABLE : integer := 44; -- Disable the Video RAM from display output. + constant GRAMDISABLE : integer := 45; -- Disable the graphics RAM from display output. + + -- Derivative settings to program the clock generator. + -- + subtype CPUSPEED is integer range 49 downto 46; -- Active CPU Speed. + subtype VIDSPEED is integer range 52 downto 50; -- Active Video Speed. + subtype PERSPEED is integer range 54 downto 53; -- Active Peripheral Speed. + subtype RTCSPEED is integer range 56 downto 55; -- Active RTC Speed. + subtype SNDSPEED is integer range 58 downto 57; -- Active Sound Speed. + + -- CMT Bus + -- + subtype CMTBUS_WIDTH is integer range 8 downto 0; + + -- CMT Signals. + -- + constant PLAY_READY : integer := 0; -- Tape play back buffer, 0 = empty, 1 = full. + constant PLAYING : integer := 1; -- Tape playback, 0 = stopped, 1 = in progress. + constant RECORD_READY : integer := 2; -- Tape record buffer full. + constant RECORDING : integer := 3; -- Tape recording, 0 = stopped, 1 = in progress. + constant ACTIVE : integer := 4; -- Tape transfer in progress, 0 = no activity, 1 = activity. + constant SENSE : integer := 5; -- Tape state Sense out. + constant WRITEBIT : integer := 6; -- Write bit to MZ. + constant READBIT : integer := 7; -- Receive bit from MZ. + constant MOTOR : integer := 8; -- Motor on/off. + + -- Debug Bus + -- + subtype DEBUG_WIDTH is integer range 15 downto 0; + + -- Debugging signals. + -- + subtype LEDS_BANK is integer range 2 downto 0; + subtype LEDS_SUBBANK is integer range 5 downto 3; + constant LEDS_ON : integer := 6; + constant ENABLED : integer := 7; + subtype SMPFREQ is integer range 11 downto 8; + subtype CPUFREQ is integer range 15 downto 12; +end mctrl_pkg; + + +library IEEE; +library pkgs; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use pkgs.mctrl_pkg.all; +use pkgs.clkgen_pkg.all; + +entity mctrl is + Port ( + -- Clock signals used by this module. + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); + + -- Reset's + COLD_RESET : in std_logic; + WARM_RESET : in std_logic; + SYSTEM_RESET : out std_logic; + + -- HPS Interface + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Different operations modes. + CONFIG : out std_logic_vector(CONFIG_WIDTH); + + -- Cassette magnetic tape signals. + CMTBUS : in std_logic_vector(CMTBUS_WIDTH); + + -- Debug modes. + DEBUG : out std_logic_vector(DEBUG_WIDTH) + ); +end mctrl; + +architecture rtl of mctrl is + +signal REGISTER_MODEL : std_logic_vector(7 downto 0) := "00000011"; +signal REGISTER_DISPLAY : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_CPU : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_AUDIO : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_CMT : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_CMT2 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_USERROM : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_FDCROM : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_8 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_9 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_10 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_11 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_12 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_13 : std_logic_vector(7 downto 0) := "00000000"; +signal REGISTER_DEBUG : std_logic_vector(7 downto 0) := "00001000"; +signal REGISTER_DEBUG2 : std_logic_vector(7 downto 0) := "00000000"; +signal delay : integer range 0 to 31; +signal REGISTER_RESET : std_logic; + +begin + -- Synchronise the register update with the configuration signals according to the CPU clock. + -- + process (COLD_RESET, CLKBUS(CKCPU)) + begin + if COLD_RESET = '1' then + CONFIG(CONFIG_WIDTH) <= "00000000000000000000000000000000000000000000011001000001000"; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='0' then + + if REGISTER_MODEL(2 downto 0) = "000" then + CONFIG(MZ80K) <= '1'; + else + CONFIG(MZ80K) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "001" then + CONFIG(MZ80C) <= '1'; + else + CONFIG(MZ80C) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "010" then + CONFIG(MZ1200) <= '1'; + else + CONFIG(MZ1200) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "011" then + CONFIG(MZ80A) <= '1'; + else + CONFIG(MZ80A) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "100" then + CONFIG(MZ700) <= '1'; + else + CONFIG(MZ700) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "101" then + CONFIG(MZ800) <= '1'; + else + CONFIG(MZ800) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "110" then + CONFIG(MZ80B) <= '1'; + else + CONFIG(MZ80B) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "111" then + CONFIG(MZ2000) <= '1'; + else + CONFIG(MZ2000) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "000" or REGISTER_MODEL(2 downto 0) = "001" then + CONFIG(MZ_KC) <= '1'; + else + CONFIG(MZ_KC) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "010" or REGISTER_MODEL(2 downto 0) = "011" then + CONFIG(MZ_A) <= '1'; + else + CONFIG(MZ_A) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then + CONFIG(MZ_B) <= '1'; + else + CONFIG(MZ_B) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + CONFIG(MZ_80C) <= '1'; + else + CONFIG(MZ_80C) <= '0'; + end if; + + if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then + CONFIG(MZ_80B) <= '1'; + else + CONFIG(MZ_80B) <= '0'; + end if; + + if REGISTER_DISPLAY(2 downto 0) = "000" then + CONFIG(NORMAL) <= '1'; + else + CONFIG(NORMAL) <= '0'; + end if; + + if REGISTER_DISPLAY(2 downto 0) = "001" then + CONFIG(NORMAL80) <= '1'; + else + CONFIG(NORMAL80) <= '0'; + end if; + + if REGISTER_DISPLAY(2 downto 0) = "010" then + CONFIG(COLOUR) <= '1'; + else + CONFIG(COLOUR) <= '0'; + end if; + + if REGISTER_DISPLAY(2 downto 0) = "011" then + CONFIG(COLOUR80) <= '1'; + else + CONFIG(COLOUR80) <= '0'; + end if; + + -- Convert CPU/CMT and Debug speed selections to actual CPU speed. + -- If debugging enabled and Debug freq not 0, select otherwise CMT if CMT is active, otherwise CPU speed as required. + -- + -- Mapping could be made in software or 1-1 with the register, but setting restrictions and mapping in hw preferred, it + -- limits frequencies belonging to a given machine and makes it easier to change the frequency by NIOS or other controller if + -- MiSTer not used. + + if CMTBUS(ACTIVE) = '1' then + if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + case REGISTER_CMT(2 downto 0) is + when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz + when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz + when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz + when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz + when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz + when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz + when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz + end case; + elsif REGISTER_MODEL(2 downto 0) = "100" then + case REGISTER_CMT(2 downto 0) is + when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz + when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz + when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz + when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz + when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz + when "101" => CONFIG(CPUSPEED) <= "1011"; -- 112MHz + when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz + when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz + end case; + elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then + case REGISTER_CMT(2 downto 0) is + when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz + when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz + when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz + when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz + when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + end case; + else + CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz + end if; + else + if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + case REGISTER_CPU(2 downto 0) is + when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz + when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz + when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz + when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz + when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz + when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz + when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz + end case; + elsif REGISTER_MODEL(2 downto 0) = "100" then + case REGISTER_CPU(2 downto 0) is + when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz + when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz + when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz + when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz + when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz + when "101" => CONFIG(CPUSPEED) <= "1011"; -- 112MHz + when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz + when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz + end case; + elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then + case REGISTER_CPU(2 downto 0) is + when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz + when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz + when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz + when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz + when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz + end case; + else + CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz + end if; + end if; + + -- Setup the video speed dependent upon model and graphics option. + -- + -- MZ700/MZ800 Models. + if REGISTER_MODEL(2 downto 0) = "100" or REGISTER_MODEL(2 downto 0) = "101" then + -- Currently all modes default to one speed! + case REGISTER_DISPLAY(2 downto 0) is + -- 40x25 mode requires 8.8MHz clock, Mono and Colour. + when "000" | "010" | "100" | "101" | "110" | "111" => + CONFIG(VIDSPEED) <= "010"; + + -- 80x25 mode requires 17.7MHz clock, Mono and Colour. + when "001" | "011" => + CONFIG(VIDSPEED) <= "011"; + end case; + -- MZ80K/C/1200/A + elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + case REGISTER_DISPLAY(2 downto 0) is + -- 40x25 mode requires 8MHz clock, Mono and Colour. + when "000" | "010" | "100" | "101" | "110" | "111" => + CONFIG(VIDSPEED) <= "000"; + -- 80x25 mode requires 16MHz clock, Mono and Colour. + when "001" | "011" => + CONFIG(VIDSPEED) <= "001"; + end case; + -- MZ80B or MZ2200 + elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then + case REGISTER_DISPLAY(2 downto 0) is + -- 40x25 mode requires 16MHz clock + when "000" | "001" | "010" | "011" | "100" | "101" | "110" | "111" => + CONFIG(VIDSPEED) <= "001"; + end case; + else + CONFIG(VIDSPEED) <= "000"; + end if; + + -- Setup RTC clock frequency dependent upon model. + if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + CONFIG(RTCSPEED) <= "00"; + elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then + CONFIG(RTCSPEED) <= "01"; + elsif REGISTER_MODEL(2 downto 0) = "100" then + CONFIG(RTCSPEED) <= "10"; + else + CONFIG(RTCSPEED) <= "00"; + end if; + + if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + CONFIG(SNDSPEED) <= "00"; + elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then + CONFIG(SNDSPEED) <= "00"; + elsif REGISTER_MODEL(2 downto 0) = "100" then + CONFIG(SNDSPEED) <= "01"; + else + CONFIG(SNDSPEED) <= "00"; + end if; + + -- Setup the peripheral speed. + if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then + CONFIG(PERSPEED) <= "00"; + elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then + CONFIG(PERSPEED) <= "00"; + elsif REGISTER_MODEL(2 downto 0) = "100" then + CONFIG(PERSPEED) <= "00"; + else + CONFIG(PERSPEED) <= "00"; + end if; + + CONFIG(VRAMDISABLE)<= REGISTER_DISPLAY(4); + CONFIG(GRAMDISABLE)<= REGISTER_DISPLAY(5); + CONFIG(VRAMWAIT) <= REGISTER_DISPLAY(6); + CONFIG(PCGRAM) <= REGISTER_DISPLAY(7); + CONFIG(TURBO) <= REGISTER_CPU(2 downto 0); + CONFIG(FASTTAPE) <= REGISTER_CMT(2 downto 0); + CONFIG(BUTTONS) <= REGISTER_CMT(4 downto 3); + CONFIG(AUDIOSRC) <= REGISTER_AUDIO(0); + DEBUG(LEDS_BANK) <= REGISTER_DEBUG(2 downto 0); + DEBUG(LEDS_SUBBANK)<= REGISTER_DEBUG(5 downto 3); + DEBUG(LEDS_ON) <= REGISTER_DEBUG(6); + DEBUG(ENABLED) <= REGISTER_DEBUG(7); + DEBUG(SMPFREQ) <= REGISTER_DEBUG2(3 downto 0); + DEBUG(CPUFREQ) <= REGISTER_DEBUG2(7 downto 4); + end if; + end process; + + -- Machine control is just a set of registers holding latched signals to configure machine components. + -- A write is made on address 100000000000000000000AAAA to read/write the registers, direction is via the + -- RD/WR signals. + -- AAAA specifies which register to read/write. + -- + process (COLD_RESET, IOCTL_CLK) + begin + if COLD_RESET = '1' then + REGISTER_MODEL <= "00000011"; + REGISTER_DISPLAY <= "00000000"; + REGISTER_CPU <= "00000000"; + REGISTER_AUDIO <= "00000000"; + REGISTER_CMT <= "00000000"; + REGISTER_CMT2 <= "00000000"; + REGISTER_USERROM <= "00000000"; + REGISTER_FDCROM <= "00000000"; + REGISTER_8 <= "00000000"; + REGISTER_9 <= "00000000"; + REGISTER_10 <= "00000000"; + REGISTER_11 <= "00000000"; + REGISTER_12 <= "00000000"; + REGISTER_13 <= "00000000"; + REGISTER_DEBUG <= "00000000"; + REGISTER_DEBUG2 <= "00000000"; + REGISTER_RESET <= '1'; + elsif IOCTL_CLK'event and IOCTL_CLK='1' then + -- For reading of registers, if no specific signal is required, just read back the output latch. + -- + if IOCTL_ADDR(24) = '1' and IOCTL_RD = '1' then + case IOCTL_ADDR(3 downto 0) is + when "0000" => IOCTL_DIN <= X"00" & REGISTER_MODEL; + when "0001" => IOCTL_DIN <= X"00" & REGISTER_DISPLAY; + when "0010" => IOCTL_DIN <= X"00" & REGISTER_CPU; + when "0011" => IOCTL_DIN <= X"00" & REGISTER_AUDIO; + when "0100" => IOCTL_DIN <= X"00" & CMTBUS(7 downto 0); + when "0101" => IOCTL_DIN <= X"00" & REGISTER_CMT2(7 downto 1) & CMTBUS(8 downto 8); + when "0110" => IOCTL_DIN <= X"00" & REGISTER_USERROM; + when "0111" => IOCTL_DIN <= X"00" & REGISTER_FDCROM; + when "1000" => IOCTL_DIN <= X"00" & REGISTER_8; + when "1001" => IOCTL_DIN <= X"00" & REGISTER_9; + when "1010" => IOCTL_DIN <= X"00" & REGISTER_10; + when "1011" => IOCTL_DIN <= X"00" & REGISTER_11; + when "1100" => IOCTL_DIN <= X"00" & REGISTER_12; + when "1101" => IOCTL_DIN <= X"00" & REGISTER_13; + when "1110" => IOCTL_DIN <= X"00" & REGISTER_DEBUG; + when "1111" => IOCTL_DIN <= X"00" & REGISTER_DEBUG2; + end case; + end if; + -- For writing of registers, just assign the input bus to the register. + if IOCTL_ADDR(24) = '1' and IOCTL_WR = '1' then + case IOCTL_ADDR(3 downto 0) is + when "0000" => + -- Assign the model data to the register and preset the default display hardware. + REGISTER_MODEL <= IOCTL_DOUT(7 downto 0); + case IOCTL_DOUT(2 downto 0) is + when "000" | "001" | "010" | "011" => + REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "000"; + when "100" | "101" => + REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "010"; + when "110" | "111" => + REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "000"; + end case; + REGISTER_RESET <= '1'; + when "0001" => + REGISTER_DISPLAY <= IOCTL_DOUT(7 downto 0); + + -- Reset display if the mode changes. + if REGISTER_DISPLAY(2 downto 0) /= IOCTL_DOUT(2 downto 0) then + REGISTER_RESET <= '1'; + end if; + when "0010" => REGISTER_CPU <= IOCTL_DOUT(7 downto 0); + when "0011" => REGISTER_AUDIO <= IOCTL_DOUT(7 downto 0); + when "0100" => REGISTER_CMT <= IOCTL_DOUT(7 downto 0); + when "0101" => REGISTER_CMT2 <= IOCTL_DOUT(7 downto 0); + when "0110" => REGISTER_USERROM <= IOCTL_DOUT(7 downto 0); + when "0111" => REGISTER_FDCROM <= IOCTL_DOUT(7 downto 0); + when "1000" => REGISTER_8 <= IOCTL_DOUT(7 downto 0); + when "1001" => REGISTER_9 <= IOCTL_DOUT(7 downto 0); + when "1010" => REGISTER_10 <= IOCTL_DOUT(7 downto 0); + when "1011" => REGISTER_11 <= IOCTL_DOUT(7 downto 0); + when "1100" => REGISTER_12 <= IOCTL_DOUT(7 downto 0); + when "1101" => REGISTER_13 <= IOCTL_DOUT(7 downto 0); + when "1110" => REGISTER_DEBUG <= IOCTL_DOUT(7 downto 0); + when "1111" => REGISTER_DEBUG2 <= IOCTL_DOUT(7 downto 0); + end case; + end if; + + -- Only allow reset signal to be active for 1 clock cycle, just enough to trigger a system reset. + -- + if REGISTER_RESET = '1' then + REGISTER_RESET <= '0'; + end if; + end if; + end process; + + -- System reset oneshot, triggered on COLD/WARM reset or a status change. + process (CLKBUS(CKRESET), COLD_RESET, WARM_RESET, REGISTER_RESET) + begin + if COLD_RESET = '1' or WARM_RESET = '1' or REGISTER_RESET = '1' then + if COLD_RESET = '1' then + delay <= 1; + elsif WARM_RESET = '1' then + delay <= 16; + else + delay <= 16; + end if; + + elsif CLKBUS(CKRESET)'event and CLKBUS(CKRESET) = '1' then + if delay /= 0 then + delay <= delay + 1; + elsif delay >= 31 then + delay <= 0; + end if; + end if; + end process; + SYSTEM_RESET <= '1' when delay > 0 + else '0'; +end rtl; diff --git a/common/pll.qip b/common/pll.qip new file mode 100644 index 0000000..715f490 --- /dev/null +++ b/common/pll.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTEy::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTEy::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQzNTA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::NTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTIgcHM=::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] +set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"] + +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" diff --git a/common/pll.v b/common/pll.v new file mode 100644 index 0000000..9789b94 --- /dev/null +++ b/common/pll.v @@ -0,0 +1,265 @@ +// megafunction wizard: %Altera PLL v17.0% +// GENERATION: XML +// pll.v + +// Generated using ACDS version 17.0 598 +// +// Customized by Philip Smart, July 2018 as it is not auto-generated. +// Set the module to have 1 output on which all frequencies used in the +// emulation are derived. + +`timescale 1 ps / 1 ps +module pll ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + //output wire outclk_1, // outclk1.clk + //output wire outclk_2, // outclk2.clk + //output wire outclk_3, // outclk3.clk + //output wire outclk_4, // outclk4.clk + output wire locked // locked.export + ); + + pll_0002 pll_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + //.outclk_1 (outclk_1), // outclk1.clk + //.outclk_2 (outclk_2), // outclk2.clk + //.outclk_3 (outclk_3), // outclk3.clk + //.outclk_4 (outclk_4), // outclk4.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll.vo +// RELATED_FILES: pll.v, pll_0002.v diff --git a/common/pll/pll_0002.qip b/common/pll/pll_0002.qip new file mode 100644 index 0000000..aec45eb --- /dev/null +++ b/common/pll/pll_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" + +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" diff --git a/common/pll/pll_0002.v b/common/pll/pll_0002.v new file mode 100644 index 0000000..b066d39 --- /dev/null +++ b/common/pll/pll_0002.v @@ -0,0 +1,107 @@ +// Customised by Philip Smart, July 2018. +// Set the input frequency to that of the Terasic DE10 Nano = 50MHz. +// Set the output frequency to 448MHz, all clocks used within the emulation are derived from this clock. +// +`timescale 1ns/10ps +module pll_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + //output wire outclk_1, + + // interface 'outclk2' + //output wire outclk_2, + + // interface 'outclk3' + //output wire outclk_3, + + // interface 'outclk4' + //output wire outclk_4, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(1), + //.number_of_clocks(5), + .output_clock_frequency0("448 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + //.phase_shift1("0 ps"), + .phase_shift1("0 ps"), + //.phase_shift1("-0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + //.outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .outclk ({outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/emu.sv b/emu.sv new file mode 100644 index 0000000..2329390 --- /dev/null +++ b/emu.sv @@ -0,0 +1,339 @@ +//======================================================================================================= +// +// Name: emu.sv +// Created: June 2018 +// Author(s): Philip Smart +// Description: Sharp MZ series compatible logic. +// +// This module is the main bridge between the emulator (sharpmz.vhd) and the MiSTer +// framework (hps_io.v/sys_top.v). +// +// Copyright: (C) 2018 Sorgelig +// (C) 2018 Philip Smart +// +// History: June 2018 - Initial creation. +// +//======================================================================================================= +// This source file is free software: you can redistribute it and-or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +//======================================================================================================= + +module emu +( + //Master input clock + input CLK_50M, + + //Async reset from top-level module. + //Can be used as initial reset. + input RESET, + + //Must be passed to hps_io module + inout [44:0] HPS_BUS, + + //Base video clock. Usually equals to CLK_SYS. + output CLK_VIDEO, + + //Multiple resolutions are supported using different CE_PIXEL rates. + //Must be based on CLK_VIDEO + output CE_PIXEL, + + //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. + output [7:0] VIDEO_ARX, + output [7:0] VIDEO_ARY, + + // These video signals are defined in sys_top.v, via the video_mixer we output the video from the emulator onto these + // signals, which then get passed as follows: + // emu -> video_mixer -> vga_osd -> vga_out + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, // = ~(VBlank | HBlank) + + output LED_USER, // 1 - ON, 0 - OFF. + + // b[1]: 0 - LED status is system status OR'd with b[0] + // 1 - LED status is controled solely by b[0] + // hint: supply 2'b00 to let the system control the LED. + output [1:0] LED_POWER, + output [1:0] LED_DISK, + output [7:0] LED_MB, + + output [15:0] AUDIO_L, + output [15:0] AUDIO_R, + output AUDIO_S, // 1 - signed audio samples, 0 - unsigned + output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) +// input TAPE_IN, + + // SD-SPI +// output SD_SCK, +// output SD_MOSI, +// input SD_MISO, +// output SD_CS, +// input SD_CD, + + //High latency DDR3 RAM interface + //Use for non-critical time purposes + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE + + //SDRAM interface with lower latency +// ,output SDRAM_CLK, +// output SDRAM_CKE, +// output [12:0] SDRAM_A, +// output [1:0] SDRAM_BA, +// inout [15:0] SDRAM_DQ, +// output SDRAM_DQML, +// output SDRAM_DQMH, +// output SDRAM_nCS, +// output SDRAM_nCAS, +// output SDRAM_nRAS, +// output SDRAM_nWE +); + +//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; +//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; +assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0; + +assign LED_USER = ioctl_download; +assign LED_DISK = 0; +assign LED_POWER = 0; + +assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; +assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; + +wire [2:0] scale = status[4:2]; + +// Menu is handled in the MiSTer c++ program. +// +`include "build_id.v" +localparam CONF_STR = +{ + "SHARP MZ SERIES;;", + "J,Fire;", + "V,v1.01.",`BUILD_DATE +}; + +///////////////// CLOCKS //////////////////////// + +wire clk_sys; + +///////////////// HPS /////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; + +wire [10:0] ps2_key; +wire [24:0] ps2_mouse; + +wire ioctl_download; +wire ioctl_upload; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire ioctl_rd; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; +wire [7:0] ioctl_din; +wire forced_scandoubler; + +hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io +( + .clk_sys(clk_sys), + .HPS_BUS(HPS_BUS), + + .conf_str(CONF_STR), + + .buttons(buttons), + .status(status), + .forced_scandoubler(forced_scandoubler), + + .ioctl_download(ioctl_download), + .ioctl_upload(ioctl_upload), + .ioctl_index(ioctl_index), + .ioctl_wr(ioctl_wr), + .ioctl_rd(ioctl_rd), + .ioctl_addr(ioctl_addr), + .ioctl_dout(ioctl_dout), + .ioctl_din(ioctl_din), + .ioctl_wait(0), + + .sd_conf(0), + .sd_ack_conf(), + + //.ps2_kbd_led_use(0), + //.ps2_kbd_led_status(0), + + .ps2_key(ps2_key), + .ps2_mouse(ps2_mouse) + + // unused + //.joystick_0(), + //.joystick_1(), + //.new_vmode(), + //.img_mounted(), + //.img_readonly(), + //.img_size(), + //.sd_lba(), + //.sd_rd(), + //.sd_wr(), + //.sd_ack(), + //.sd_buff_addr(), + //.sd_buff_dout(), + //.sd_buff_din(), + //.sd_buff_wr(), + //.ps2_kbd_clk_out(), + //.ps2_kbd_data_out(), + //.ps2_kbd_clk_in(), + //.ps2_kbd_data_in(), + //.ps2_mouse_clk_out(), + //.ps2_mouse_data_out(), + //.ps2_mouse_data_in(), + //.ps2_mouse_clk_in(), + //.joystick_analog_0(), + //.joystick_analog_1(), + //.RTC(), + //.TIMESTAMP() +); + +///////////////// RESET ///////////////////////// + +//wire reset = RESET | status[0] | buttons[1] | status[6] | ioctl_download; +wire reset = RESET; +wire warm_reset = status[0] | buttons[1]; //| ioctl_download; + +//////////////// Machine //////////////////////// + +wire [7:0] audio_l_emu; +wire [7:0] audio_r_emu; +assign AUDIO_L = {audio_l_emu,8'd0}; +assign AUDIO_R = {audio_r_emu,8'd0}; +assign AUDIO_S = 1; +assign AUDIO_MIX = 0; + + +wire clk_video_in; +wire [7:0] R_emu; +wire [7:0] G_emu; +wire [7:0] B_emu; +wire hblank_emu; +wire vblank_emu; +wire hsync_emu; +wire vsync_emu; + +sharpmz sharp_mz +( + // Clocks Input to Emulator. + .clkmaster(CLK_50M), + + // System clock. + .clksys(clk_sys), + + // Clocks output by the emulator. + .clkvid(clk_video_in), + + // Reset + .cold_reset(reset), + .warm_reset(warm_reset), + + // LED on MB + .main_leds(LED_MB), + + // PS2 via USB. + .ps2_key(ps2_key), + + // VGA on IO daughter card. + .vga_hb_o(hblank_emu), + .vga_vb_o(vblank_emu), + .vga_hs_o(hsync_emu), + .vga_vs_o(vsync_emu), + .vga_r_o(R_emu), + .vga_g_o(G_emu), + .vga_b_o(B_emu), + + // AUDIO on IO daughter card. + .audio_l_o(audio_l_emu), + .audio_r_o(audio_r_emu), + + // HPS Interface + .ioctl_download(ioctl_download), // HPS Downloading to FPGA. + .ioctl_upload(ioctl_upload), // HPS Uploading from FPGA. + .ioctl_clk(clk_sys), // HPS I/O Clock. + .ioctl_wr(ioctl_wr), // HPS Write Enable to FPGA. + .ioctl_rd(ioctl_rd), // HPS Read Enable from FPGA. + .ioctl_addr(ioctl_addr), // HPS Address in FPGA to write into. + .ioctl_dout(ioctl_dout), // HPS Data to be written into FPGA. + .ioctl_din(ioctl_din) // HPS Data to be read into HPS. +); + +// If ce_pix is same as pixel clock, uncomment below and remove CE_PIXEL from .ce_pix_out below. +// +//assign CE_PIXEL=1; +//assign CLK_VIDEO = clk_sys; +assign CLK_VIDEO = clk_video_in; +assign CE_PIXEL = clk_video_in; + +//video_mixer #(.HALF_DEPTH(0)) video_mixer +video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(clk_video_in), // Video pixel clock from core. + //.ce_pix_out(CE_PIXEL), + + .scanlines({scale == 4, scale == 3, scale == 2}), + .scandoubler(scale || forced_scandoubler), + .hq2x(scale==1), + + .mono(0), + + // Input signals into the mixer, originating from the emulator. + .R(R_emu), + .G(G_emu), + .B(B_emu), + + // Positive pulses. + .HSync(hsync_emu), + .VSync(vsync_emu), + .HBlank(hblank_emu), + .VBlank(vblank_emu), + + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .VGA_DE(VGA_DE) + + // Outputs of the mixer are bound to the VGA_x signals defined in the sys_top module and passed into this module as parameters. + // These signals then feed the vga_osd -> vga_out modules in systop.v +); + +// Uncomment below and comment out video_mixer to pass original signal to sys_top.v. +// To output original signal, edit sys_top.v and comment out vga_osd and vga_out, uncomment the assign statements. +// +//assign VGA_R = R_emu; +//assign VGA_G = G_emu; +//assign VGA_B = B_emu; +//assign VGA_HS = hsync_emu; +//assign VGA_VS = vsync_emu; +//assign VGA_DE = ~(vblank_emu | hblank_emu); + +endmodule diff --git a/jtag.cdf b/jtag.cdf new file mode 100644 index 0000000..f94d545 --- /dev/null +++ b/jtag.cdf @@ -0,0 +1,13 @@ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(SOCVHPS) MfrSpec(OpMask(0)); + P ActionCode(Cfg) + Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz-lite.sof") MfrSpec(OpMask(1)); +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/jtag_uart_0.vhd b/jtag_uart_0.vhd new file mode 100644 index 0000000..512fd36 --- /dev/null +++ b/jtag_uart_0.vhd @@ -0,0 +1,1392 @@ +--Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your +--use of Altera Corporation's design tools, logic functions and other +--software and tools, and its AMPP partner logic functions, and any +--output files any of the foregoing (including device programming or +--simulation files), and any associated documentation or information are +--expressly subject to the terms and conditions of the Altera Program +--License Subscription Agreement or other applicable license agreement, +--including, without limitation, that your use is for the sole purpose +--of programming logic devices manufactured by Altera and sold by Altera +--or its authorized distributors. Please refer to the applicable +--agreement for further details. + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library std; +use std.textio.all; + +entity jtag_uart_0_log_module is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal strobe : IN STD_LOGIC; + signal valid : IN STD_LOGIC + ); +end entity jtag_uart_0_log_module; + + +architecture europa of jtag_uart_0_log_module is + + file text_handle : TEXT ; + + -- synthesis translate_off + -- purpose: convert 8 bit signal data to 8 bit string + FUNCTION bin_to_char(vec_to_convert : STD_LOGIC_VECTOR (7 downto 0)) + RETURN CHARACTER IS + VARIABLE result: CHARACTER; + BEGIN + CASE vec_to_convert IS -- cover basic ascii printable characters... + when X"0a" => result := lf; -- \n, linefeed + when X"0d" => result := nul; -- \r, Ctrl-M + when X"09" => result := ht; -- \t, Ctrl-I, TAB + when X"20" => result := ' ' ; + when X"21" => result := '!' ; + when X"22" => result := '"' ; + when X"23" => result := '#' ; + when X"24" => result := '$' ; + when X"25" => result := '%' ; + when X"26" => result := '&' ; + when X"27" => result := ''' ; -- sync ' char for hilighting txt editors + when X"28" => result := '(' ; + when X"29" => result := ')' ; + when X"2a" => result := '*' ; + when X"2b" => result := '+' ; + when X"2c" => result := ',' ; + when X"2d" => result := '-' ; + when X"2e" => result := '.' ; + when X"2f" => result := '/' ; + when X"30" => result := '0' ; + when X"31" => result := '1' ; + when X"32" => result := '2' ; + when X"33" => result := '3' ; + when X"34" => result := '4' ; + when X"35" => result := '5' ; + when X"36" => result := '6' ; + when X"37" => result := '7' ; + when X"38" => result := '8' ; + when X"39" => result := '9' ; + when X"3a" => result := ':' ; + when X"3b" => result := ';' ; + when X"3c" => result := '<' ; + when X"3d" => result := '=' ; + when X"3e" => result := '>' ; + when X"3f" => result := '?' ; + when X"40" => result := '@' ; + when X"41" => result := 'A' ; + when X"42" => result := 'B' ; + when X"43" => result := 'C' ; + when X"44" => result := 'D' ; + when X"45" => result := 'E' ; + when X"46" => result := 'F' ; + when X"47" => result := 'G' ; + when X"48" => result := 'H' ; + when X"49" => result := 'I' ; + when X"4a" => result := 'J' ; + when X"4b" => result := 'K' ; + when X"4c" => result := 'L' ; + when X"4d" => result := 'M' ; + when X"4e" => result := 'N' ; + when X"4f" => result := 'O' ; + when X"50" => result := 'P' ; + when X"51" => result := 'Q' ; + when X"52" => result := 'R' ; + when X"53" => result := 'S' ; + when X"54" => result := 'T' ; + when X"55" => result := 'U' ; + when X"56" => result := 'V' ; + when X"57" => result := 'W' ; + when X"58" => result := 'X' ; + when X"59" => result := 'Y' ; + when X"5a" => result := 'Z' ; + when X"5b" => result := '[' ; + when X"5c" => result := '\' ; + when X"5d" => result := ']' ; + when X"5e" => result := '^' ; + when X"5f" => result := '_' ; + when X"60" => result := '`' ; + when X"61" => result := 'a' ; + when X"62" => result := 'b' ; + when X"63" => result := 'c' ; + when X"64" => result := 'd' ; + when X"65" => result := 'e' ; + when X"66" => result := 'f' ; + when X"67" => result := 'g' ; + when X"68" => result := 'h' ; + when X"69" => result := 'i' ; + when X"6a" => result := 'j' ; + when X"6b" => result := 'k' ; + when X"6c" => result := 'l' ; + when X"6d" => result := 'm' ; + when X"6e" => result := 'n' ; + when X"6f" => result := 'o' ; + when X"70" => result := 'p' ; + when X"71" => result := 'q' ; + when X"72" => result := 'r' ; + when X"73" => result := 's' ; + when X"74" => result := 't' ; + when X"75" => result := 'u' ; + when X"76" => result := 'v' ; + when X"77" => result := 'w' ; + when X"78" => result := 'x' ; + when X"79" => result := 'y' ; + when X"7a" => result := 'z' ; + when X"7b" => result := '{' ; + when X"7c" => result := '|' ; + when X"7d" => result := '}' ; + when X"7e" => result := '~' ; + when X"7f" => result := '_' ; + WHEN others => + ASSERT False REPORT "data contains a non-printable character" SEVERITY Warning; + result := nul; + END case; + RETURN result; + end bin_to_char; + -- synthesis translate_on + + +begin + +--synthesis translate_off + + + -- purpose: simulate verilog initial function to open file in write mode + -- type : combinational + -- inputs : initial + -- outputs: + process is + variable initial : boolean := true; -- not initialized yet + variable status : file_open_status; -- status for fopen + begin -- process + if initial = true then + file_open (status, text_handle, "jtag_uart_0_output_stream.dat", WRITE_MODE); + initial := false; -- done! + end if; + wait; -- wait forever + end process; + + process (clk) + variable data_string : LINE; -- for line buffer to file + variable status : file_open_status; -- status for fopen + + variable echo_string : LINE; -- for line buffer to screen (stdout) + + begin -- process clk + if clk'event and clk = '1' then -- sync ' chars for hilighting txt editors + if (valid and strobe) = '1' then + + write (data_string,To_bitvector(data)); -- every char flushes line + writeline (text_handle,data_string); + file_close (text_handle); -- flush buffer + file_open (status, text_handle, "jtag_uart_0_output_stream.dat", APPEND_MODE); + + -- save up characters into a line to send to the screen + write (echo_string,bin_to_char(data)); + if data = X"0a" or data = X"0d" then -- \n or \r will flush line + writeline (output,echo_string); + end if; + + end if; + end if; + end process; + --synthesis translate_on + +end europa; + + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity jtag_uart_0_sim_scfifo_w is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal fifo_wr : IN STD_LOGIC; + + -- outputs: + signal fifo_FF : OUT STD_LOGIC; + signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal wfifo_empty : OUT STD_LOGIC; + signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end entity jtag_uart_0_sim_scfifo_w; + + +architecture europa of jtag_uart_0_sim_scfifo_w is +--synthesis translate_off +component jtag_uart_0_log_module is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal strobe : IN STD_LOGIC; + signal valid : IN STD_LOGIC + ); +end component jtag_uart_0_log_module; + +--synthesis translate_on + +begin + +--synthesis translate_off + --jtag_uart_0_log, which is an e_log + jtag_uart_0_log : jtag_uart_0_log_module + port map( + clk => clk, + data => fifo_wdata, + strobe => fifo_wr, + valid => fifo_wr + ); + + + wfifo_used <= A_REP(std_logic'('0'), 6); + r_dat <= A_REP(std_logic'('0'), 8); + fifo_FF <= std_logic'('0'); + wfifo_empty <= std_logic'('1'); +--synthesis translate_on + +end europa; + + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library lpm; +use lpm.all; + +entity jtag_uart_0_scfifo_w is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_clear : IN STD_LOGIC; + signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal fifo_wr : IN STD_LOGIC; + signal rd_wfifo : IN STD_LOGIC; + + -- outputs: + signal fifo_FF : OUT STD_LOGIC; + signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal wfifo_empty : OUT STD_LOGIC; + signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end entity jtag_uart_0_scfifo_w; + + +architecture europa of jtag_uart_0_scfifo_w is +--synthesis translate_off +component jtag_uart_0_sim_scfifo_w is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal fifo_wr : IN STD_LOGIC; + + -- outputs: + signal fifo_FF : OUT STD_LOGIC; + signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal wfifo_empty : OUT STD_LOGIC; + signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component jtag_uart_0_sim_scfifo_w; + +--synthesis translate_on +--synthesis read_comments_as_HDL on +-- component scfifo is +--GENERIC ( +-- lpm_hint : STRING; +-- lpm_numwords : NATURAL; +-- lpm_showahead : STRING; +-- lpm_type : STRING; +-- lpm_width : NATURAL; +-- lpm_widthu : NATURAL; +-- overflow_checking : STRING; +-- underflow_checking : STRING; +-- use_eab : STRING +-- ); +-- PORT ( +-- signal full : OUT STD_LOGIC; +-- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); +-- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); +-- signal empty : OUT STD_LOGIC; +-- signal rdreq : IN STD_LOGIC; +-- signal aclr : IN STD_LOGIC; +-- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); +-- signal clock : IN STD_LOGIC; +-- signal wrreq : IN STD_LOGIC +-- ); +-- end component scfifo; +--synthesis read_comments_as_HDL off + signal internal_fifo_FF : STD_LOGIC; + signal internal_r_dat : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal internal_wfifo_empty : STD_LOGIC; + signal internal_wfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0); + +begin + + --vhdl renameroo for output signals + fifo_FF <= internal_fifo_FF; + --vhdl renameroo for output signals + r_dat <= internal_r_dat; + --vhdl renameroo for output signals + wfifo_empty <= internal_wfifo_empty; + --vhdl renameroo for output signals + wfifo_used <= internal_wfifo_used; +--synthesis translate_off + --the_jtag_uart_0_sim_scfifo_w, which is an e_instance + the_jtag_uart_0_sim_scfifo_w : jtag_uart_0_sim_scfifo_w + port map( + fifo_FF => internal_fifo_FF, + r_dat => internal_r_dat, + wfifo_empty => internal_wfifo_empty, + wfifo_used => internal_wfifo_used, + clk => clk, + fifo_wdata => fifo_wdata, + fifo_wr => fifo_wr + ); + + +--synthesis translate_on +--synthesis read_comments_as_HDL on +-- wfifo : scfifo +-- generic map( +-- lpm_hint => "RAM_BLOCK_TYPE=AUTO", +-- lpm_numwords => 64, +-- lpm_showahead => "OFF", +-- lpm_type => "scfifo", +-- lpm_width => 8, +-- lpm_widthu => 6, +-- overflow_checking => "OFF", +-- underflow_checking => "OFF", +-- use_eab => "ON" +-- ) +-- port map( +-- aclr => fifo_clear, +-- clock => clk, +-- data => fifo_wdata, +-- empty => internal_wfifo_empty, +-- full => internal_fifo_FF, +-- q => internal_r_dat, +-- rdreq => rd_wfifo, +-- usedw => internal_wfifo_used, +-- wrreq => fifo_wr +-- ); +-- +--synthesis read_comments_as_HDL off + +end europa; + + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library std; +use std.textio.all; + +entity jtag_uart_0_drom_module is + generic ( + POLL_RATE : integer := 100 + ); + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal incr_addr : IN STD_LOGIC; + signal reset_n : IN STD_LOGIC; + + -- outputs: + signal new_rom : OUT STD_LOGIC; + signal num_bytes : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal safe : OUT STD_LOGIC + ); +end entity jtag_uart_0_drom_module; + + +architecture europa of jtag_uart_0_drom_module is + signal address : STD_LOGIC_VECTOR (11 DOWNTO 0); + signal d1_pre : STD_LOGIC; + signal d2_pre : STD_LOGIC; + signal d3_pre : STD_LOGIC; + signal d4_pre : STD_LOGIC; + signal d5_pre : STD_LOGIC; + signal d6_pre : STD_LOGIC; + signal d7_pre : STD_LOGIC; + signal d8_pre : STD_LOGIC; + signal d9_pre : STD_LOGIC; + TYPE mem_type is ARRAY( 2047 DOWNTO 0) of STD_LOGIC_VECTOR(7 DOWNTO 0); + signal mem_array : mem_type; + TYPE mem_type1 is ARRAY( 1 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0); + signal mutex : mem_type1; + signal pre : STD_LOGIC; + + signal safe_wire : STD_LOGIC; -- deal with bogus VHDL type casting + signal safe_delay : STD_LOGIC; + FILE mutex_handle : TEXT ; -- open this for read and write manually. + -- stream can be opened simply for read... + FILE stream_handle : TEXT open READ_MODE is "jtag_uart_0_input_stream.dat"; + +-- synthesis translate_off +-- convert functions deadlifted from e_rom.pm + +FUNCTION convert_string_to_number(string_to_convert : STRING; + final_char_index : NATURAL := 0) + RETURN NATURAL IS + VARIABLE result: NATURAL := 0; + VARIABLE current_index : NATURAL := 1; + VARIABLE the_char : CHARACTER; + +BEGIN + IF final_char_index = 0 THEN + result := 0; + ELSE + WHILE current_index <= final_char_index LOOP + the_char := string_to_convert(current_index); + IF '0' <= the_char AND the_char <= '9' THEN + result := result * 16 + character'pos(the_char) - character'pos('0'); + ELSIF 'A' <= the_char AND the_char <= 'F' THEN + result := result * 16 + character'pos(the_char) - character'pos('A') + 10; + ELSIF 'a' <= the_char AND the_char <= 'f' THEN + result := result * 16 + character'pos(the_char) - character'pos('a') + 10; + ELSE + report "convert_string_to_number: Ack, a formatting error!"; + END IF; + current_index := current_index + 1; + END LOOP; + END IF; + RETURN result; +END convert_string_to_number; + + +FUNCTION convert_string_to_std_logic(value : STRING; num_chars : INTEGER; mem_width_chars : INTEGER) + RETURN STD_LOGIC_VECTOR is + VARIABLE num_bits: integer := mem_width_chars * 4; + VARIABLE result: std_logic_vector(num_bits-1 downto 0); + VARIABLE curr_char : integer; + VARIABLE min_width : integer := mem_width_chars; + VARIABLE num_nibbles : integer := 0; + +BEGIN + result := (others => '0'); + num_nibbles := mem_width_chars; + IF (mem_width_chars > num_chars) THEN + num_nibbles := num_chars; + END IF; + + FOR I IN 1 TO num_nibbles LOOP + curr_char := num_nibbles - (I-1); + + CASE value(I) IS + WHEN '0' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0000"; + WHEN '1' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0001"; + WHEN '2' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0010"; + WHEN '3' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0011"; + WHEN '4' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0100"; + WHEN '5' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0101"; + WHEN '6' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0110"; + WHEN '7' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0111"; + WHEN '8' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1000"; + WHEN '9' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1001"; + WHEN 'A' | 'a' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1010"; + WHEN 'B' | 'b' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1011"; + WHEN 'C' | 'c' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1100"; + WHEN 'D' | 'd' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1101"; + WHEN 'E' | 'e' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1110"; + WHEN 'F' | 'f' => result((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1111"; + WHEN ' ' => EXIT; + WHEN HT => exit; + WHEN others => + ASSERT False + REPORT "function From_Hex: string """ & value & """ contains non-hex character" + severity Error; + EXIT; + END case; + END loop; + RETURN result; +END convert_string_to_std_logic; + +-- purpose: open mutex/discard @address/convert value to std_logic_vector +function get_mutex_val (file_name : string) + return STD_LOGIC_VECTOR is + VARIABLE result : STD_LOGIC_VECTOR (31 downto 0) := X"00000000"; + FILE handle : TEXT ; + VARIABLE status : file_open_status; -- status for fopen + VARIABLE data_line : LINE; + VARIABLE the_character_from_data_line : CHARACTER; + VARIABLE converted_number : NATURAL := 0; + VARIABLE found_string_array : STRING(1 TO 128); + VARIABLE string_index : NATURAL := 0; + VARIABLE line_length : NATURAL := 0; + +begin -- get_mutex_val + + file_open (status, handle, file_name, READ_MODE); + IF (status=OPEN_OK) THEN + + WHILE NOT(endfile(handle)) LOOP + readline(handle, data_line); + line_length := data_line'LENGTH; -- match ' for emacs font-lock + + WHILE line_length > 0 LOOP + read(data_line, the_character_from_data_line); + -- check for the @ character indicating a new address wad + -- if found, ignore the line! This is just protection + IF '@' = the_character_from_data_line THEN + exit; -- bail out of this line + end if; + -- process the hex address, character by character ... + IF NOT(' ' = the_character_from_data_line) THEN + string_index := string_index + 1; + found_string_array(string_index) := the_character_from_data_line; + END IF; + line_length := line_length - 1; + end loop; -- read characters + + end loop; -- read lines + END IF; + file_close (handle); + + if string_index /= 0 then + result := convert_string_to_std_logic(found_string_array, string_index, 8); + end if; + + return result; + +end get_mutex_val; + +-- purpose: emulate verilogs readmemh function (mostly) +-- in verilog you say: $readmemh ("file", array); +-- in VHDL, we say: array <= readmemh("file"); -- which makes more sense. +function readmemh (file_name : string) + return mem_type is + VARIABLE result : mem_type; + FILE handle : TEXT ; + VARIABLE status : file_open_status; -- status for fopen + VARIABLE data_line : LINE; + VARIABLE b_address : BOOLEAN := FALSE; -- distinguish between addrs and data + VARIABLE the_character_from_data_line : CHARACTER; + VARIABLE converted_number : NATURAL := 0; + VARIABLE found_string_array : STRING(1 TO 128); + VARIABLE string_index : NATURAL := 0; + VARIABLE line_length : NATURAL := 0; + VARIABLE load_address : NATURAL := 0; + VARIABLE mem_index : NATURAL := 0; +begin -- readmemh + + file_open (status, handle, file_name, READ_MODE); + + WHILE NOT(endfile(handle)) LOOP + readline(handle, data_line); + line_length := data_line'LENGTH; -- match ' for emacs font-lock + b_address := false; + + WHILE line_length > 0 LOOP + read(data_line, the_character_from_data_line); + -- check for the @ character indicating a new address wad + -- if found, ignore the line! This is just protection + IF '@' = the_character_from_data_line and not b_address then -- is addr + b_address := true; + end if; + -- process the hex address, character by character ... + IF NOT((' ' = the_character_from_data_line) or + ('@' = the_character_from_data_line) or + (lf = the_character_from_data_line) or + (cr = the_character_from_data_line)) THEN + string_index := string_index + 1; + found_string_array(string_index) := the_character_from_data_line; + END IF; + line_length := line_length - 1; + end loop; -- read characters + + if b_address then + mem_index := convert_string_to_number(found_string_array, string_index); + b_address := FALSE; + else + result(mem_index) := convert_string_to_std_logic(found_string_array, string_index, 2); + end if; + + string_index := 0; + + end loop; -- read lines + + file_close (handle); + + return result; + +end readmemh; + + +-- purpose: emulate verilogs readmemb function (mostly) +-- in verilog you say: $readmemb ("file", array); +-- in VHDL, we say: array <= readmemb("file"); -- which makes more sense. +function readmemb (file_name : string) + return mem_type is + VARIABLE result : mem_type; + FILE handle : TEXT ; + VARIABLE status : file_open_status; -- status for fopen + VARIABLE data_line : LINE; + VARIABLE the_character_from_data_line : BIT_VECTOR(7 DOWNTO 0); -- '0' & '1's + VARIABLE line_length : NATURAL := 0; + VARIABLE mem_index : NATURAL := 0; +begin -- readmemb + + file_open (status, handle, file_name, READ_MODE); + + WHILE NOT(endfile(handle)) LOOP + readline(handle, data_line); + line_length := data_line'LENGTH; -- match ' for emacs font-lock + + WHILE line_length > 7 LOOP + read(data_line, the_character_from_data_line); + -- No @ characters allowed in binary/bit_vector mode + result(mem_index) := To_stdlogicvector(the_character_from_data_line); + mem_index := mem_index + 1; + line_length := line_length - 8; + end loop; -- read characters + + end loop; -- read lines + + file_close (handle); + + return result; + +end readmemb; + +-- synthesis translate_on + + +begin + +--synthesis translate_off + q <= mem_array(CONV_INTEGER(UNSIGNED((address)))); + process (clk, reset_n) + begin + if reset_n = '0' then + d1_pre <= std_logic'('0'); + d2_pre <= std_logic'('0'); + d3_pre <= std_logic'('0'); + d4_pre <= std_logic'('0'); + d5_pre <= std_logic'('0'); + d6_pre <= std_logic'('0'); + d7_pre <= std_logic'('0'); + d8_pre <= std_logic'('0'); + d9_pre <= std_logic'('0'); + new_rom <= std_logic'('0'); + elsif clk'event and clk = '1' then + d1_pre <= pre; + d2_pre <= d1_pre; + d3_pre <= d2_pre; + d4_pre <= d3_pre; + d5_pre <= d4_pre; + d6_pre <= d5_pre; + d7_pre <= d6_pre; + d8_pre <= d7_pre; + d9_pre <= d8_pre; + new_rom <= d9_pre; + end if; + + end process; + + + num_bytes <= mutex(1); + + safe <= safe_wire; + safe_wire <= to_std_logic( address < mutex(1) ); + + process (clk, reset_n) + begin + if reset_n = '0' then + safe_delay <= '0'; + elsif clk'event and clk = '1' then -- balance ' for emacs quoting + safe_delay <= safe_wire; + end if; + end process; + + process (clk, reset_n) + variable poll_count : integer := POLL_RATE; -- STD_LOGIC_VECTOR (31:0); + variable status : file_open_status; -- status for fopen + variable mutex_string : LINE; -- temp space for read/write data + variable stream_string : LINE; -- temp space for read data + variable init_done : BOOLEAN; -- only used if non-interactive + variable interactive : BOOLEAN := FALSE; + begin + if reset_n /= '1' then + address <= "000000000000"; + mem_array(0) <= X"00"; + mutex(0) <= X"00000000"; + mutex(1) <= X"00000000"; + pre <= '0'; + init_done := FALSE; + elsif clk'event and clk = '1' then -- balance ' for emacs quoting + pre <= '0'; + if incr_addr = '1' and safe_wire = '1' then + address <= address + "000000000001"; + end if; + -- blast mutex via textio after falling edge of safe + if mutex(0) /= X"00000000" and safe_wire = '0' and safe_delay = '1' then + if interactive then -- bash mutex + file_open (status, mutex_handle, "jtag_uart_0_input_mutex.dat", WRITE_MODE); + write (mutex_string, string'("0")); -- balance ' for emacs quoting + writeline (mutex_handle, mutex_string); + file_close (mutex_handle); + mutex(0) <= X"00000000"; + else -- non-nteractive does not bash mutex: it stops poll counter + init_done := TRUE; + end if; + end if; + if poll_count < POLL_RATE then -- wait + if not init_done then -- stop counting if init_done is TRUE + poll_count := poll_count + 1; + end if; + else -- do the real work + poll_count := 0; + -- get mutex via textio ... + mutex(0) <= get_mutex_val ("jtag_uart_0_input_mutex.dat"); + if mutex(0) /= X"00000000" and safe_wire = '0' then + -- read stream into array after previous stream is complete + mutex (1) <= mutex (0); -- save mutex value for address compare + -- get mem_array via textio ... + mem_array <= readmemb("jtag_uart_0_input_stream.dat"); + -- prep address and pre-pulse to alert world to new contents + address <= "000000000000"; + pre <= '1'; + end if; -- poll_count + end if; -- clock + end if; -- reset + end process; + --synthesis translate_on + +end europa; + + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity jtag_uart_0_sim_scfifo_r is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_rd : IN STD_LOGIC; + signal rst_n : IN STD_LOGIC; + + -- outputs: + signal fifo_EF : OUT STD_LOGIC; + signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal rfifo_full : OUT STD_LOGIC; + signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end entity jtag_uart_0_sim_scfifo_r; + + +architecture europa of jtag_uart_0_sim_scfifo_r is +--synthesis translate_off +component jtag_uart_0_drom_module is + generic ( + POLL_RATE : integer := 100 + ); + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal incr_addr : IN STD_LOGIC; + signal reset_n : IN STD_LOGIC; + + -- outputs: + signal new_rom : OUT STD_LOGIC; + signal num_bytes : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal safe : OUT STD_LOGIC + ); +end component jtag_uart_0_drom_module; + +--synthesis translate_on + signal bytes_left : STD_LOGIC_VECTOR (31 DOWNTO 0); + signal fifo_rd_d : STD_LOGIC; + signal internal_fifo_rdata1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal internal_rfifo_full1 : STD_LOGIC; + signal new_rom : STD_LOGIC; + signal num_bytes : STD_LOGIC_VECTOR (31 DOWNTO 0); + signal rfifo_entries : STD_LOGIC_VECTOR (6 DOWNTO 0); + signal safe : STD_LOGIC; + +begin + + --vhdl renameroo for output signals + fifo_rdata <= internal_fifo_rdata1; + --vhdl renameroo for output signals + rfifo_full <= internal_rfifo_full1; +--synthesis translate_off + --jtag_uart_0_drom, which is an e_drom + jtag_uart_0_drom : jtag_uart_0_drom_module + port map( + new_rom => new_rom, + num_bytes => num_bytes, + q => internal_fifo_rdata1, + safe => safe, + clk => clk, + incr_addr => fifo_rd_d, + reset_n => rst_n + ); + + + -- Generate rfifo_entries for simulation + process (clk, rst_n) + begin + if rst_n = '0' then + bytes_left <= std_logic_vector'("00000000000000000000000000000000"); + fifo_rd_d <= std_logic'('0'); + elsif clk'event and clk = '1' then + fifo_rd_d <= fifo_rd; + -- decrement on read + if std_logic'(fifo_rd_d) = '1' then + bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32); + end if; + -- catch new contents + if std_logic'(new_rom) = '1' then + bytes_left <= num_bytes; + end if; + end if; + + end process; + + fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000"))); + internal_rfifo_full1 <= to_std_logic((bytes_left>std_logic_vector'("00000000000000000000000001000000"))); + rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7); + rfifo_used <= rfifo_entries(5 DOWNTO 0); +--synthesis translate_on + +end europa; + + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library lpm; +use lpm.all; + +entity jtag_uart_0_scfifo_r is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_clear : IN STD_LOGIC; + signal fifo_rd : IN STD_LOGIC; + signal rst_n : IN STD_LOGIC; + signal t_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal wr_rfifo : IN STD_LOGIC; + + -- outputs: + signal fifo_EF : OUT STD_LOGIC; + signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal rfifo_full : OUT STD_LOGIC; + signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end entity jtag_uart_0_scfifo_r; + + +architecture europa of jtag_uart_0_scfifo_r is +--synthesis translate_off +component jtag_uart_0_sim_scfifo_r is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_rd : IN STD_LOGIC; + signal rst_n : IN STD_LOGIC; + + -- outputs: + signal fifo_EF : OUT STD_LOGIC; + signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal rfifo_full : OUT STD_LOGIC; + signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component jtag_uart_0_sim_scfifo_r; + +--synthesis translate_on +--synthesis read_comments_as_HDL on +-- component scfifo is +--GENERIC ( +-- lpm_hint : STRING; +-- lpm_numwords : NATURAL; +-- lpm_showahead : STRING; +-- lpm_type : STRING; +-- lpm_width : NATURAL; +-- lpm_widthu : NATURAL; +-- overflow_checking : STRING; +-- underflow_checking : STRING; +-- use_eab : STRING +-- ); +-- PORT ( +-- signal full : OUT STD_LOGIC; +-- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); +-- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); +-- signal empty : OUT STD_LOGIC; +-- signal rdreq : IN STD_LOGIC; +-- signal aclr : IN STD_LOGIC; +-- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); +-- signal clock : IN STD_LOGIC; +-- signal wrreq : IN STD_LOGIC +-- ); +-- end component scfifo; +--synthesis read_comments_as_HDL off + signal internal_fifo_EF : STD_LOGIC; + signal internal_fifo_rdata : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal internal_rfifo_full : STD_LOGIC; + signal internal_rfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0); + +begin + + --vhdl renameroo for output signals + fifo_EF <= internal_fifo_EF; + --vhdl renameroo for output signals + fifo_rdata <= internal_fifo_rdata; + --vhdl renameroo for output signals + rfifo_full <= internal_rfifo_full; + --vhdl renameroo for output signals + rfifo_used <= internal_rfifo_used; +--synthesis translate_off + --the_jtag_uart_0_sim_scfifo_r, which is an e_instance + the_jtag_uart_0_sim_scfifo_r : jtag_uart_0_sim_scfifo_r + port map( + fifo_EF => internal_fifo_EF, + fifo_rdata => internal_fifo_rdata, + rfifo_full => internal_rfifo_full, + rfifo_used => internal_rfifo_used, + clk => clk, + fifo_rd => fifo_rd, + rst_n => rst_n + ); + + +--synthesis translate_on +--synthesis read_comments_as_HDL on +-- rfifo : scfifo +-- generic map( +-- lpm_hint => "RAM_BLOCK_TYPE=AUTO", +-- lpm_numwords => 64, +-- lpm_showahead => "OFF", +-- lpm_type => "scfifo", +-- lpm_width => 8, +-- lpm_widthu => 6, +-- overflow_checking => "OFF", +-- underflow_checking => "OFF", +-- use_eab => "ON" +-- ) +-- port map( +-- aclr => fifo_clear, +-- clock => clk, +-- data => t_dat, +-- empty => internal_fifo_EF, +-- full => internal_rfifo_full, +-- q => internal_fifo_rdata, +-- rdreq => fifo_rd, +-- usedw => internal_rfifo_used, +-- wrreq => wr_rfifo +-- ); +-- +--synthesis read_comments_as_HDL off + +end europa; + + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library lpm; +use lpm.all; + +entity jtag_uart_0 is + port ( + -- inputs: + signal av_address : IN STD_LOGIC; + signal av_chipselect : IN STD_LOGIC; + signal av_read_n : IN STD_LOGIC; + signal av_write_n : IN STD_LOGIC; + signal av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + signal clk : IN STD_LOGIC; + signal rst_n : IN STD_LOGIC; + + -- outputs: + signal av_irq : OUT STD_LOGIC; + signal av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal av_waitrequest : OUT STD_LOGIC; + signal dataavailable : OUT STD_LOGIC; + signal readyfordata : OUT STD_LOGIC + ); +attribute ALTERA_ATTRIBUTE : string; +attribute ALTERA_ATTRIBUTE of jtag_uart_0 : entity is "SUPPRESS_DA_RULE_INTERNAL=""R101,C106,D101,D103"""; +end entity jtag_uart_0; + + +architecture europa of jtag_uart_0 is +component jtag_uart_0_scfifo_w is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_clear : IN STD_LOGIC; + signal fifo_wdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal fifo_wr : IN STD_LOGIC; + signal rd_wfifo : IN STD_LOGIC; + + -- outputs: + signal fifo_FF : OUT STD_LOGIC; + signal r_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal wfifo_empty : OUT STD_LOGIC; + signal wfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component jtag_uart_0_scfifo_w; + +component jtag_uart_0_scfifo_r is + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal fifo_clear : IN STD_LOGIC; + signal fifo_rd : IN STD_LOGIC; + signal rst_n : IN STD_LOGIC; + signal t_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + signal wr_rfifo : IN STD_LOGIC; + + -- outputs: + signal fifo_EF : OUT STD_LOGIC; + signal fifo_rdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + signal rfifo_full : OUT STD_LOGIC; + signal rfifo_used : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component jtag_uart_0_scfifo_r; + +--synthesis read_comments_as_HDL on +-- component alt_jtag_atlantic is +--GENERIC ( +-- INSTANCE_ID : NATURAL; +-- LOG2_RXFIFO_DEPTH : NATURAL; +-- LOG2_TXFIFO_DEPTH : NATURAL; +-- SLD_AUTO_INSTANCE_INDEX : STRING +-- ); +-- PORT ( +-- signal t_pause : OUT STD_LOGIC; +-- signal r_ena : OUT STD_LOGIC; +-- signal t_ena : OUT STD_LOGIC; +-- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); +-- signal t_dav : IN STD_LOGIC; +-- signal rst_n : IN STD_LOGIC; +-- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0); +-- signal r_val : IN STD_LOGIC; +-- signal clk : IN STD_LOGIC +-- ); +-- end component alt_jtag_atlantic; +--synthesis read_comments_as_HDL off + signal ac : STD_LOGIC; + signal activity : STD_LOGIC; + signal fifo_AE : STD_LOGIC; + signal fifo_AF : STD_LOGIC; + signal fifo_EF : STD_LOGIC; + signal fifo_FF : STD_LOGIC; + signal fifo_clear : STD_LOGIC; + signal fifo_rd : STD_LOGIC; + signal fifo_rdata : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal fifo_wdata : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal fifo_wr : STD_LOGIC; + signal ien_AE : STD_LOGIC; + signal ien_AF : STD_LOGIC; + signal internal_av_waitrequest : STD_LOGIC; + signal ipen_AE : STD_LOGIC; + signal ipen_AF : STD_LOGIC; + signal pause_irq : STD_LOGIC; + signal r_dat : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal r_ena : STD_LOGIC; + signal r_val : STD_LOGIC; + signal rd_wfifo : STD_LOGIC; + signal read_0 : STD_LOGIC; + signal rfifo_full : STD_LOGIC; + signal rfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0); + signal rvalid : STD_LOGIC; + signal sim_r_ena : STD_LOGIC; + signal sim_t_dat : STD_LOGIC; + signal sim_t_ena : STD_LOGIC; + signal sim_t_pause : STD_LOGIC; + signal t_dat : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal t_dav : STD_LOGIC; + signal t_ena : STD_LOGIC; + signal t_pause : STD_LOGIC; + signal wfifo_empty : STD_LOGIC; + signal wfifo_used : STD_LOGIC_VECTOR (5 DOWNTO 0); + signal woverflow : STD_LOGIC; + signal wr_rfifo : STD_LOGIC; + +begin + + --avalon_jtag_slave, which is an e_avalon_slave + rd_wfifo <= r_ena AND NOT wfifo_empty; + wr_rfifo <= t_ena AND NOT rfifo_full; + fifo_clear <= NOT rst_n; + --the_jtag_uart_0_scfifo_w, which is an e_instance + the_jtag_uart_0_scfifo_w : jtag_uart_0_scfifo_w + port map( + fifo_FF => fifo_FF, + r_dat => r_dat, + wfifo_empty => wfifo_empty, + wfifo_used => wfifo_used, + clk => clk, + fifo_clear => fifo_clear, + fifo_wdata => fifo_wdata, + fifo_wr => fifo_wr, + rd_wfifo => rd_wfifo + ); + + + --the_jtag_uart_0_scfifo_r, which is an e_instance + the_jtag_uart_0_scfifo_r : jtag_uart_0_scfifo_r + port map( + fifo_EF => fifo_EF, + fifo_rdata => fifo_rdata, + rfifo_full => rfifo_full, + rfifo_used => rfifo_used, + clk => clk, + fifo_clear => fifo_clear, + fifo_rd => fifo_rd, + rst_n => rst_n, + t_dat => t_dat, + wr_rfifo => wr_rfifo + ); + + + ipen_AE <= ien_AE AND fifo_AE; + ipen_AF <= ien_AF AND ((pause_irq OR fifo_AF)); + av_irq <= ipen_AE OR ipen_AF; + activity <= t_pause OR t_ena; + process (clk, rst_n) + begin + if rst_n = '0' then + pause_irq <= std_logic'('0'); + elsif clk'event and clk = '1' then + -- only if fifo is not empty... + if std_logic'((t_pause AND NOT fifo_EF)) = '1' then + pause_irq <= std_logic'('1'); + elsif std_logic'(read_0) = '1' then + pause_irq <= std_logic'('0'); + end if; + end if; + + end process; + + process (clk, rst_n) + begin + if rst_n = '0' then + r_val <= std_logic'('0'); + t_dav <= std_logic'('1'); + elsif clk'event and clk = '1' then + r_val <= r_ena AND NOT wfifo_empty; + t_dav <= NOT rfifo_full; + end if; + + end process; + + process (clk, rst_n) + begin + if rst_n = '0' then + fifo_AE <= std_logic'('0'); + fifo_AF <= std_logic'('0'); + fifo_wr <= std_logic'('0'); + rvalid <= std_logic'('0'); + read_0 <= std_logic'('0'); + ien_AE <= std_logic'('0'); + ien_AF <= std_logic'('0'); + ac <= std_logic'('0'); + woverflow <= std_logic'('0'); + internal_av_waitrequest <= std_logic'('1'); + elsif clk'event and clk = '1' then + fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used)))<=std_logic_vector'("00000000000000000000000000001000"))); + fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (Std_Logic_Vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used)))))))<=std_logic_vector'("00000000000000000000000000001000"))); + fifo_wr <= std_logic'('0'); + read_0 <= std_logic'('0'); + internal_av_waitrequest <= NOT (((av_chipselect AND ((NOT av_write_n OR NOT av_read_n))) AND internal_av_waitrequest)); + if std_logic'(activity) = '1' then + ac <= std_logic'('1'); + end if; + -- write + if std_logic'(((av_chipselect AND NOT av_write_n) AND internal_av_waitrequest)) = '1' then + -- addr 1 is control; addr 0 is data + if std_logic'(av_address) = '1' then + ien_AF <= av_writedata(0); + ien_AE <= av_writedata(1); + if std_logic'((av_writedata(10) AND NOT activity)) = '1' then + ac <= std_logic'('0'); + end if; + else + fifo_wr <= NOT fifo_FF; + woverflow <= fifo_FF; + end if; + end if; + -- read + if std_logic'(((av_chipselect AND NOT av_read_n) AND internal_av_waitrequest)) = '1' then + -- addr 1 is interrupt; addr 0 is data + if std_logic'(NOT av_address) = '1' then + rvalid <= NOT fifo_EF; + end if; + read_0 <= NOT av_address; + end if; + end if; + + end process; + + fifo_wdata <= av_writedata(7 DOWNTO 0); + fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect AND NOT av_read_n) AND internal_av_waitrequest) AND NOT av_address))) = '1'), NOT fifo_EF, std_logic'('0')); + av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(NOT fifo_FF) & A_ToStdLogicVector(NOT fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (Std_Logic_Vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(NOT fifo_FF) & A_ToStdLogicVector(NOT fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32); + process (clk, rst_n) + begin + if rst_n = '0' then + readyfordata <= std_logic'('0'); + elsif clk'event and clk = '1' then + readyfordata <= NOT fifo_FF; + end if; + + end process; + + --vhdl renameroo for output signals + av_waitrequest <= internal_av_waitrequest; +--synthesis translate_off + -- Tie off Atlantic Interface signals not used for simulation + process (clk) + begin + if clk'event and clk = '1' then + sim_t_pause <= std_logic'('0'); + sim_t_ena <= std_logic'('0'); + sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8))); + sim_r_ena <= std_logic'('0'); + end if; + + end process; + + r_ena <= sim_r_ena; + t_ena <= sim_t_ena; + t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat)); + t_pause <= sim_t_pause; + process (fifo_EF) + begin + dataavailable <= NOT fifo_EF; + + end process; + +--synthesis translate_on +--synthesis read_comments_as_HDL on +-- jtag_uart_0_alt_jtag_atlantic : alt_jtag_atlantic +-- generic map( +-- INSTANCE_ID => 0, +-- LOG2_RXFIFO_DEPTH => 6, +-- LOG2_TXFIFO_DEPTH => 6, +-- SLD_AUTO_INSTANCE_INDEX => "YES" +-- ) +-- port map( +-- clk => clk, +-- r_dat => r_dat, +-- r_ena => r_ena, +-- r_val => r_val, +-- rst_n => rst_n, +-- t_dat => t_dat, +-- t_dav => t_dav, +-- t_ena => t_ena, +-- t_pause => t_pause +-- ); +-- +-- process (clk, rst_n) +-- begin +-- if rst_n = '0' then +-- dataavailable <= std_logic'('0'); +-- elsif clk'event and clk = '1' then +-- dataavailable <= NOT fifo_EF; +-- end if; +-- +-- end process; +-- +--synthesis read_comments_as_HDL off + +end europa; + diff --git a/memory_hw.tcl b/memory_hw.tcl new file mode 100644 index 0000000..510aa16 --- /dev/null +++ b/memory_hw.tcl @@ -0,0 +1,47 @@ +# TCL File Generated by Component Editor 17.0 +# Mon Jun 11 22:55:14 BST 2018 +# DO NOT MODIFY + + +# +# memory "memory" v1.0 +# 2018.06.11.22:55:14 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module memory +# +set_module_property DESCRIPTION "" +set_module_property NAME memory +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME memory +set_module_property INSTANTIATE_IN_SYSTEM_MODULE false +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# + +# +# parameters +# + + +# +# display items +# + diff --git a/mif/combined_cgrom.mif b/mif/combined_cgrom.mif new file mode 100644 index 0000000..7c62850 --- /dev/null +++ b/mif/combined_cgrom.mif @@ -0,0 +1,774 @@ +DEPTH = 12288; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00; +0010: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00; +0020: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00; +0030: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00; +0040: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00; +0050: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00; +0070: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00; +0080: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00; +0090: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00; +00a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00; +00b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00; +00c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00; +00d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00; +00e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00; +00f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00; +0100: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00; 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+2870: ee 9a 8a a2 b2 aa aa ee 7c c6 ba aa aa ba c6 7c; +2880: fc 86 ba ba 86 bc a0 e0 7c c6 ba ba aa b2 c2 7c; +2890: fc 86 ba ba 84 b4 aa e6 7e c2 be c4 7a fa 86 fc; +28a0: fe 82 ee 28 28 28 28 38 ee aa aa aa aa ba c6 7c; +28b0: ee aa aa aa aa 54 28 10 ee aa aa ba aa aa 82 fe; +28c0: c6 aa 54 28 28 54 aa c6 ee aa 92 44 28 28 28 38; +28d0: fe 82 fa 14 28 5e 82 fe 00 40 a0 90 ff 7e 00 00; +28e0: 00 02 05 09 ff 7e 00 00 00 7c d6 7c 38 54 92 00; +28f0: 92 54 38 fe 38 54 92 00 00 00 38 54 fe 00 00 00; +2900: 7c 82 b2 aa aa 9a 82 7c 38 48 68 28 28 6c 44 7c; +2910: 7c 82 ba ca 14 2e 42 fe fc 82 fa 22 22 fa 82 fc; +2920: 0c 14 24 54 b6 82 f6 1c fe 82 be 84 7a fa 86 fc; +2930: 7e 82 be bc 82 ba 82 7c fe 82 fa 14 28 50 50 70; +2940: 7c 82 ba 7c 82 ba 82 7c 7c 82 ba 82 7a fa 82 fc; +2950: f8 88 be aa fa 22 3e 00 1f 11 7d 55 5f 44 7c 00; +2960: 3c 5a ff e7 7e 24 42 81 3c 5a ff e7 7e 24 24 66; +2970: 08 1c 2a 7f 77 3e 36 63 08 1c 2a 7f 77 3e 36 14; +2980: 41 a2 3c 5a 7e ff 42 63 82 45 3c 5a 7e ff 42 c6; +2990: 00 5a bd 99 24 42 24 00 81 a5 5a 18 18 24 c3 00; +29a0: 00 24 7e bd 7e 24 24 e7 24 7e bd 7e 24 42 42 c3; +29b0: 3c 5a ff ab d5 ff dd 89 3c 5a ff ab d5 ff 77 22; +29c0: 3c 42 a5 81 99 81 d5 aa 3c 42 a5 81 99 81 ab 55; +29d0: 42 42 66 e7 ff ff 7e 3c 1c fe 3f 0f 0f 3f fe 1c; +29e0: 3c 7e ff ff e7 66 42 42 38 7f fc f0 f0 fc 7f 38; +29f0: 3c 7e ff ff ff ff 7e 3c 10 38 28 28 28 7c fe d6; +2a00: 00 03 07 7e c7 7e 07 03 6b 7f 3e 14 14 14 1c 08; +2a10: 00 c0 e0 7e e3 7e e0 c0 3c 0c 3c 18 3c 76 76 46; +2a20: 3c 24 3c 18 3c 5a 5a 7e 3c 30 3c 18 3c 6e 6e 62; +2a30: 7e 7e 24 24 24 24 24 6c 7e 7e 24 24 24 24 24 66; +2a40: 7e 7e 24 24 24 24 24 36 22 63 f7 b7 ff 7e 3c 3c; +2a50: 38 6c ff 3f 0f 3f fc 38 3c 3c 7e ff ed ef c6 44; +2a60: 1c 36 ff fc f0 fc 3f 1e 3c 7e ff bf ff 7e 3c 3c; +2a70: 3c 3c 7e ff fd ff 7e 3c 1c 36 ff ff ff ff 3e 1c; +2a80: 38 6c ff ff ff ff 7c 38 18 3c 3c 3c 3c 18 3c 3c; +2a90: 00 00 7b ff ff 7b 00 00 3c 3c 18 3c 3c 3c 3c 18; +2aa0: 00 00 de ff ff de 00 00 20 60 20 20 30 28 3c 3c; +2ab0: 00 40 ff 0b 07 03 00 00 3c 3c 14 0c 04 04 06 04; +2ac0: 00 02 ff d0 e0 c0 00 00 10 10 38 7c 92 10 10 38; +2ad0: 00 08 10 31 ff 31 10 08 38 10 10 92 7c 38 10 10; +2ae0: 00 10 08 8c ff 8c 08 10 00 78 60 50 48 04 02 00; +2af0: 00 02 04 48 50 60 78 00 00 40 20 12 0a 06 1e 00; +2b00: 00 1e 06 0a 12 20 40 00 18 7e 7e ff c3 81 81 81; +2b10: 1f 78 70 f0 f0 70 78 1f 81 81 81 c3 ff 7e 7e 18; +2b20: f8 1e 0e 0f 0f 0e 1e f8 bf a1 ad a5 a5 bd 81 ff; +2b30: ff 81 bd a5 85 fd 01 ff ff 81 bd a5 a5 b5 85 fd; +2b40: ff 80 bf a1 a5 bd 81 ff 00 18 00 3c 00 7e 00 ff; +2b50: 01 05 15 55 55 15 05 01 ff 00 7e 00 3c 00 18 00; +2b60: 80 a0 a8 aa aa a8 a0 80 00 08 1c 3e 00 08 1c 3e; +2b70: 00 00 11 33 77 33 11 00 00 3e 1c 08 00 3e 1c 08; +2b80: 00 00 44 66 77 66 44 00 00 00 e7 a5 e7 00 00 00; +2b90: 10 38 54 10 10 54 38 10 00 00 24 42 ff 42 24 00; +2ba0: 7f 41 22 1c 08 08 08 7f 55 55 55 55 55 55 55 55; +2bb0: ff 00 ff 00 ff 00 ff 00 a5 42 a5 00 00 a5 42 a5; +2bc0: 24 42 81 00 00 81 42 24 ff 80 9f a0 a0 a0 a0 a0; +2bd0: ff 01 e5 11 15 11 15 11 00 00 00 ff a0 af a0 ff; +2be0: 00 00 00 ff 41 41 55 ff a0 9f 80 ff 30 30 30 78; +2bf0: 11 e1 01 ff 0c 0c 0c 1e 80 aa 80 95 80 8f 80 ff; +2c00: 01 a9 01 51 01 e1 01 ff 3c 42 ab d5 10 10 14 08; +2c10: 00 00 18 24 24 18 00 00 00 18 24 42 42 24 18 00; +2c20: 3c 42 81 81 81 81 42 3c 00 00 00 18 18 00 00 00; +2c30: 00 00 3c 3c 3c 3c 00 00 00 7e 7e 7e 7e 7e 7e 00; +2c40: 3c 42 9d a1 a1 9d 42 3c ff ff ff e7 e7 ff ff ff; +2c50: ff ff c3 c3 c3 c3 ff ff ff 81 81 81 81 81 81 ff; +2c60: 20 30 20 20 ff 7e 3c 00 3c 42 81 ff ff 81 42 3c; +2c70: 3c 5a 99 99 99 99 5a 3c 3c 5a 99 ff ff 99 5a 3c; +2c80: 00 28 fe aa fe 54 38 10 0f 30 40 4e 8a 8e 80 81; +2c90: f0 0c 02 72 51 71 01 81 0f 30 40 40 8e 80 80 81; +2ca0: f0 0c 02 02 71 01 01 81 81 80 88 84 43 40 30 0f; +2cb0: 81 01 11 21 c2 02 0c f0 81 80 80 87 40 40 30 0f; +2cc0: 81 01 01 e1 02 02 0c f0 81 80 83 84 43 40 30 0f; +2cd0: 81 01 c1 21 c2 02 0c f0 81 80 87 88 48 40 30 0f; +2ce0: 81 01 e1 11 12 02 0c f0 08 10 54 fe fe fe fe 7c; +2cf0: 00 06 08 10 30 78 78 30 00 52 34 06 60 2c 4a 00; +2d00: 91 52 00 03 c0 00 4a 89 80 c0 e0 f0 ff ff ff ff; +2d10: 00 00 01 02 ff c3 c3 ff 00 00 80 40 ff c3 c3 ff; +2d20: 00 c0 20 10 fc fe ff fc 01 03 07 0f ff ff ff ff; +2d30: 02 14 28 08 14 14 08 00 00 fe 42 20 10 20 42 fe; +2d40: 00 03 04 08 3f 7f ff 3f 00 20 10 10 10 28 48 86; +2d50: 00 3c 42 42 42 24 a5 e7 00 44 82 82 92 6c 00 00; +2d60: 00 00 6c 92 92 6c 00 00 00 02 6c 90 90 6e 00 00; +2d70: 00 1e 10 50 50 b0 10 00 00 00 10 00 7c 00 10 00; +2d80: 00 f1 5b 55 55 51 51 00 ff 89 91 c5 a3 89 91 ff; +2d90: ff c3 a5 99 99 a5 c3 ff 00 92 54 38 ee 38 54 92; +2da0: ff 99 99 ff ff 99 99 ff 92 54 38 10 10 10 10 10; +2db0: 38 10 38 10 38 10 38 10 00 00 00 aa ff aa 00 00; +2dc0: 00 10 10 7c 10 10 00 7c 7e 42 7e 42 7e 42 7e 42; +2dd0: 00 ff 55 55 55 55 ff 00 00 00 00 c0 b0 8c 83 ff; +2de0: 00 00 00 03 0d 31 c1 ff 00 00 00 00 3c 7e ff ff; +2df0: ff ff 7e 3c 00 00 00 00 c0 e0 f0 f0 f0 f0 e0 c0; +2e00: 03 07 0f 0f 0f 0f 07 03 03 0c 3f 3f ff 7f 37 1f; +2e10: c0 30 b8 dc ee f6 fb fb 0e 0e 0a 04 01 01 03 0f; +2e20: 7a 74 f4 f4 f4 fa fd fd 04 4e e4 46 6f 7f 60 3f; +2e30: 20 72 27 62 f6 fe 06 fc 3b 31 1b 1f 10 1f 0f 07; +2e40: dc 8c d8 f8 08 f8 f0 e0 01 03 07 06 0e 3e 70 30; +2e50: 80 c0 e0 60 70 7c 0e 0c 1e 0e 06 07 03 37 7f 8b; +2e60: 78 70 60 e0 c0 ec fe d1 01 33 7b 59 8c df 7f 3f; +2e70: 80 cc de 9a 31 fb fe fc 3f 1f 1f 0f 0f 7f 00 ff; +2e80: fc f8 f8 f0 f0 fe 00 ff 00 01 02 04 02 01 1f 1f; +2e90: 00 80 40 20 40 80 f8 f8 02 02 02 02 1f 20 7f 00; +2ea0: 40 40 40 40 f8 04 fe 00 73 73 73 7f 3f 1f 0f 0f; +2eb0: ce ce ce fe fc f8 f0 f0 0f 0f 0f 18 7f 40 7f ff; +2ec0: f0 f0 f0 18 fe 02 fe ff f8 44 42 21 21 42 44 f8; +2ed0: ff 05 07 00 00 07 05 ff fc 86 82 81 81 82 86 fc; +2ee0: 00 00 80 40 7f 80 00 00 00 00 00 00 ff 01 01 01; +2ef0: 01 01 01 01 ff 00 00 00 ff 80 80 80 80 00 00 00; +2f00: 00 00 00 00 80 80 80 ff 00 08 0c 0a f9 0a 0c 08; +2f10: 00 08 0c 3a e9 3a 0c 08 1f 28 48 fe 88 88 8f 00; +2f20: 40 c0 40 e6 09 02 04 0f 40 c0 40 e2 06 0a 1f 02; +2f30: 40 c0 40 ef 01 07 01 0f 40 a0 20 4f e1 07 01 0f; +2f40: c0 60 18 06 18 60 80 fe 01 06 18 60 18 06 01 7f; +2f50: 00 01 06 1d 2a 2a 2a 1f 1b 8f 65 11 c9 a9 b1 f3; +2f60: 4c f7 f0 18 07 02 3e fe 7f 9f 31 41 81 81 f9 fd; +2f70: 88 02 40 00 88 41 00 91 40 01 88 00 40 04 80 11; +2f80: 00 30 58 fd ff 79 30 00 00 0c 1a bf ff 9e 0c 00; +2f90: 00 30 58 fd 3f f9 30 00 00 0c 1a bf fc 9f 0c 00; +2fa0: 10 28 68 bc fc 78 10 38 ba ee aa 38 38 ba fe ba; +2fb0: ba fe ba 38 38 aa ee ba 00 e7 42 ff 9f ff 42 e7; +2fc0: 00 e7 42 ff f9 ff 42 e7 00 00 fc 1c 7f 63 3e 00; +2fd0: 00 00 3f 38 fe c6 7c 00 ff 81 a5 81 81 a5 81 ff; +2fe0: e7 81 81 00 00 81 81 e7 00 04 08 fe 10 fe 20 40; +2ff0: 18 24 24 20 10 10 10 10 08 08 08 08 04 24 24 18; +END; diff --git a/mif/combined_keymap.mif b/mif/combined_keymap.mif new file mode 100644 index 0000000..955a6b5 --- /dev/null +++ b/mif/combined_keymap.mif @@ -0,0 +1,102 @@ +DEPTH = 1536; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: ff ff ff ff ff ff ff 86 ff 37 ff ff ff 90 93 ff; +0010: ff ff 80 ff ff 20 00 ff ff ff 60 50 40 30 10 ff; +0020: ff 61 70 41 21 11 01 ff ff 91 71 51 22 31 02 ff; +0030: ff 72 62 52 42 32 12 ff ff ff 63 43 23 03 13 ff; +0040: ff 73 53 33 24 14 04 ff ff 64 74 44 54 34 05 ff; +0050: ff 95 45 ff 25 15 ff ff 81 85 84 55 ff 75 ff ff; +0060: ff ff ff ff ff ff 65 ff ff 66 35 46 26 ff ff ff; +0070: 96 87 76 56 47 36 ff 06 77 57 67 17 07 27 ff ff; +0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +00c0: ff ff ff ff ff ff ff ff ff ff 16 ff ff ff ff ff; +00d0: ff ff ff ff ff ff ff ff ff ff 97 ff ff ff ff ff; +00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ef; +00f0: ff 81 92 ff 83 ff ff ff ff ff ff ff ff ff ff ff; +0100: ff ff ff ff ff ff ff 86 ff 37 ff ff ff 90 93 ff; +0110: ff ff 80 ff ff 20 00 ff ff ff 60 50 40 30 10 ff; +0120: ff 61 70 41 21 11 01 ff ff 91 71 51 22 31 02 ff; +0130: ff 72 62 52 42 32 12 ff ff ff 63 43 23 03 13 ff; +0140: ff 73 53 33 24 14 04 ff ff 64 74 44 54 34 05 ff; +0150: ff 95 45 ff 25 15 ff ff 81 85 84 55 ff 75 ff ff; +0160: ff ff ff ff ff ff 65 ff ff 66 35 46 26 ff ff ff; +0170: 96 87 76 56 47 36 ff 06 77 57 67 17 07 27 ff ff; +0180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +01a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +01b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +01c0: ff ff ff ff ff ff ff ff ff ff 16 ff ff ff ff ff; +01d0: ff ff ff ff ff ff ff ff ff ff 97 ff ff ff ff ff; +01e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ef; +01f0: ff 81 92 ff 83 ff ff ff ff ff ff ff ff ff ff ff; +0200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0210: ff ff 00 ff 27 14 16 ff ff ff 10 22 13 15 17 ff; +0220: ff 20 21 23 24 27 26 ff ff 40 31 32 34 25 36 ff; +0230: ff 41 30 42 33 35 37 ff ff ff 50 43 44 46 47 ff; +0240: ff 51 52 45 54 57 56 ff ff 60 70 53 63 55 67 ff; +0250: ff ff 62 ff 65 66 ff ff 11 07 73 72 64 76 ff ff; +0260: ff ff ff ff ff ff 61 ff ff 8a ff 84 77 ff ff ff; +0270: 12 ff 74 85 75 a7 ff ff ff 97 92 95 90 96 ff ff; +0280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +02a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +02b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +02c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +02d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +02e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +02f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0310: ff ff 00 ff 27 14 16 ff ff ff 10 22 13 15 17 ff; +0320: ff 20 21 23 24 27 26 ff ff 40 31 32 34 25 36 ff; +0330: ff 41 30 42 33 35 37 ff ff ff 50 43 44 46 47 ff; +0340: ff 51 52 45 54 57 56 ff ff 60 70 53 63 55 67 ff; +0350: ff ff 62 ff 65 66 ff ff 11 07 73 72 64 76 ff ff; +0360: ff ff ff ff ff ff 61 ff ff 8a ff 84 77 ff ff ff; +0370: 12 ff 74 85 75 a7 ff ff ff 97 92 95 90 96 ff ff; +0380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +03a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +03b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +03c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +03d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +03e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +03f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0400: ff ff ff 93 95 97 96 ff ff ff ff ff 94 ff ff ff; +0410: ff 06 80 ff a6 27 57 ff ff ff 16 25 47 21 56 ff; +0420: ff 45 20 44 43 45 55 ff ff 64 22 42 24 26 53 ff; +0430: ff 32 46 40 41 17 52 ff ff ff 33 36 23 51 50 ff; +0440: ff 61 35 37 31 63 62 ff ff 60 70 34 0a 30 75 ff; +0450: ff ff ff ff 14 65 ff ff 04 ff 00 13 ff 67 ff ff; +0460: ff ff ff ff ff ff ff ff ff ff ff 72 ff ff ff ff; +0470: 77 76 74 ff 73 75 87 ff ff ff ff ff ff ff ff ff; +0480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +04a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +04b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +04c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +04d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +04e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +04f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +0500: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff; +0510: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff; +0520: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff; +0530: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff; +0540: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff; +0550: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff; +0560: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff; +0570: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff; +0580: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff; +0590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +05a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +05b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +05c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff; +05d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff; +05e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef; +05f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff; +END; diff --git a/mif/combined_mainmemory.mif b/mif/combined_mainmemory.mif new file mode 100644 index 0000000..f531da3 --- /dev/null +++ b/mif/combined_mainmemory.mif @@ -0,0 +1,3718 @@ +DEPTH = 59392; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: c3 4a 00 c3 a8 07 c3 80 09 c3 7b 09 c3 93 09 c3; +0010: 84 09 c3 95 09 c3 93 08 c3 a1 08 c3 b3 08 c3 11; +0020: 0d c3 36 04 c3 70 04 c3 cf 04 c3 ef 04 c3 75 05; +0030: c3 88 01 c3 fa 02 00 00 c3 38 10 c3 44 03 c3 e5; +0040: 02 c3 ec 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd; +0050: 4d 07 06 ff 21 f1 10 cd d8 0f 3e 16 cd 12 00 3e; +0060: 71 21 00 d8 18 03 c3 35 10 cd e3 09 21 79 03 3e; +0070: c3 32 38 10 22 39 10 3e 04 32 9e 11 cd be 02 cd; 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+DATA_RADIX = HEX; +CONTENT BEGIN +0000: c3 4a 00 c3 e6 07 c3 0e 09 c3 18 09 c3 20 09 c3; +0010: 26 09 c3 35 09 c3 81 09 c3 99 09 c3 bd 08 c3 32; +0020: 0a c3 36 04 c3 75 04 c3 d8 04 c3 f8 04 c3 88 05; +0030: c3 c7 01 c3 08 03 00 00 c3 38 10 c3 58 03 c3 e5; +0040: 02 c3 fa 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd; +0050: c9 0f 3e 16 cd 12 00 06 3c 21 70 11 cd d8 0f 21; +0060: 92 03 3e c3 32 38 10 22 39 10 3e 04 32 9e 11 3c; +0070: 32 9f 11 cd be 02 cd 09 00 11 41 01 cd 15 00 c3; +0080: 6b 01 cd 09 00 3e 2a cd 12 00 11 a3 11 cd 03 00; +0090: 1a fe 1b ca 82 00 fe 2a 20 01 13 21 96 01 06 04; +00a0: cd 80 01 ca cf 00 21 9a 01 cd 80 01 ca 59 01 21; +00b0: 9e 01 06 02 cd 80 01 ca 6b 01 21 a0 01 cd 80 01; +00c0: ca 73 01 21 a2 01 cd 80 01 ca 77 01 c3 82 00 13; +00d0: 13 13 13 1a fe 0d c2 04 01 cd d8 04 da a4 01 cd; +00e0: 09 00 11 38 01 cd 15 00 11 f1 10 21 10 00 19 36; +00f0: 0d cd 15 00 cd f8 04 da a4 01 2a 06 11 7c fe 12; +0100: da 82 00 e9 d5 cd d8 04 da a4 01 cd 09 00 11 31; +0110: 01 cd 15 00 11 f1 10 21 10 00 19 36 0d cd 15 00; +0120: d1 d5 21 f1 10 06 10 cd 80 01 c2 05 01 d1 c3 df; +0130: 00 46 4f 55 4e 44 20 0d 4c 4f 41 44 49 4e 47 20; +0140: 0d 2a 2a 20 20 4d 4f 4e 49 54 4f 52 20 53 50 2d; +0150: 31 30 30 32 20 20 2a 2a 0d 13 13 13 13 1a fe 24; +0160: c2 82 00 13 cd 10 04 da 82 00 e9 3e ff 32 9d 11; +0170: c3 82 00 af c3 6d 01 21 00 f0 7e b7 c2 82 00 e9; +0180: c5 d5 e5 1a be 20 0b 05 28 08 fe 0d 28 04 13 23; +0190: 18 f1 e1 d1 c1 c9 4c 4f 41 44 47 4f 54 4f 53 53; +01a0: 53 47 46 44 fe 02 ca 82 00 cd 09 00 11 b5 01 cd; +01b0: 15 00 c3 82 00 22 43 48 45 43 4b 20 53 55 4d 20; +01c0: 45 52 52 4f 52 22 0d c5 d5 e5 3e 02 32 a0 11 06; +01d0: 01 1a fe 0d 28 02 fe c8 ca 10 02 fe cf ca 03 02; +01e0: fe d7 ca 0c 02 fe 23 21 71 02 20 04 21 89 02 13; +01f0: cd 1c 02 da d1 01 cd c8 02 da 13 02 cd ab 02 41; +0200: c3 d1 01 3e 03 32 a0 11 13 c3 d1 01 3e 01 18 f5; +0210: cd c8 02 f5 cd be 02 f1 e1 d1 c1 c9 c5 06 08 1a; +0220: be 28 09 23 23 23 10 f8 37 13 c1 c9 23 d5 5e 23; +0230: 56 eb 7c b7 28 09 3a a0 11 3d 28 03 29 18 fa 22; +0240: a1 11 3e 02 32 a0 11 d1 13 1a 47 e6 f0 fe 30 28; +0250: 05 3a 9f 11 18 07 13 78 e6 0f 32 9f 11 4f 06 00; +0260: 21 a1 02 09 4e 3a 9e 11 47 af 81 10 fd c1 4f af; +0270: c9 43 77 07 44 a7 06 45 ed 05 46 98 05 47 fc 04; +0280: 41 71 04 42 f5 03 52 00 00 43 0c 07 44 47 06 45; +0290: 98 05 46 48 05 47 b4 04 41 31 04 42 bb 03 52 00; +02a0: 00 01 02 03 04 06 08 0c 10 18 20 2a a1 11 7c b7; +02b0: 28 0c d5 eb 21 04 e0 73 72 3e 01 d1 18 06 3e 34; +02c0: 32 07 e0 af 32 08 e0 c9 21 00 e0 36 f9 23 7e e6; +02d0: 08 20 02 37 c9 3a 08 e0 0f 38 fa 3a 08 e0 0f 30; +02e0: fa 10 f2 af c9 c5 e5 21 71 04 cd ae 02 06 32 af; +02f0: cd 5b 07 10 fa e1 c1 c3 be 02 f5 c5 e6 0f 47 3e; +0300: 08 90 32 9e 11 c1 f1 c9 f3 c5 d5 e5 32 9b 11 3e; +0310: f0 32 9c 11 21 c0 a8 af ed 52 e5 23 eb 3e 74 32; +0320: 07 e0 3e b0 32 07 e0 21 06 e0 73 72 2b 36 0a 36; +0330: 00 3e 80 32 07 e0 23 4e 7e ba 20 fb 79 bb 20 f7; +0340: 2b 00 00 00 36 12 36 7a 23 d1 4e 7e ba 20 fb 79; +0350: bb 20 f7 e1 d1 c1 fb c9 e5 3e 80 32 07 e0 21 06; +0360: e0 f3 5e 56 fb 7b b2 ca 79 03 af 21 c0 a8 ed 52; +0370: da 83 03 eb 3a 9b 11 e1 c9 11 c0 a8 3a 9b 11 ee; +0380: 01 e1 c9 f3 21 06 e0 7e 2f 5f 7e 2f 57 fb 13 c3; +0390: 7c 03 f5 c5 d5 e5 3a 9b 11 ee 01 32 9b 11 3e 80; +03a0: 32 07 e0 21 06 e0 5e 56 21 c0 a8 19 2b 2b eb 21; +03b0: 06 e0 73 72 e1 d1 c1 f1 fb c9 7c cd c3 03 7d cd; +03c0: c3 03 c9 f5 e6 f0 0f 0f 0f 0f cd da 03 cd 12 00; +03d0: f1 e6 0f cd da 03 cd 12 00 c9 d5 e5 21 e9 03 e6; +03e0: 0f 5f 16 00 19 7e e1 d1 c9 30 31 32 33 34 35 36; +03f0: 37 38 39 41 42 43 44 45 46 c5 e5 01 00 10 21 e9; +0400: 03 be 20 03 79 18 06 23 0c 05 20 f5 37 e1 c1 c9; +0410: d5 cd 1f 04 38 07 67 cd 1f 04 38 01 6f d1 c9 c5; +0420: 1a 13 cd f9 03 38 0d 07 07 07 07 4f 1a 13 cd f9; +0430: 03 38 01 b1 c1 c9 f3 d5 c5 e5 16 d7 1e cc 21 f0; +0440: 10 01 80 00 cd 33 07 cd b2 06 da 63 05 7b fe cc; +0450: 20 11 cd 09 00 d5 11 6c 04 cd 15 00 11 f1 10 cd; +0460: 15 00 d1 cd b8 07 cd 8d 04 c3 63 05 57 52 49 54; +0470: 49 4e 47 20 0d f3 d5 c5 e5 16 d7 1e 53 2a 02 11; +0480: e5 c1 2a 04 11 78 b1 ca d4 04 c3 44 04 d5 c5 e5; +0490: 16 02 3e f9 32 00 e0 7e cd a5 07 3a 01 e0 e6 08; +04a0: c2 a7 04 37 c3 d4 04 23 0b 78 b1 c2 97 04 2a 97; +04b0: 11 7c cd a5 07 7d cd a5 07 cd 80 07 15 c2 c4 04; +04c0: b7 c3 d4 04 06 00 cd 67 07 05 c2 c6 04 e1 c1 c5; +04d0: e5 c3 97 04 e1 c1 d1 c9 f3 d5 c5 e5 16 d2 1e cc; +04e0: 01 80 00 21 f0 10 cd b2 06 da 82 05 cd 5e 06 da; +04f0: 82 05 cd 10 05 c3 63 05 f3 d5 c5 e5 16 d2 1e 53; +0500: 2a 02 11 e5 c1 2a 04 11 78 b1 ca 63 05 c3 e6 04; +0510: d5 c5 e5 26 02 01 01 e0 11 02 e0 cd 01 06 da 82; +0520: 05 cd 60 07 cd 60 07 cd 60 07 1a e6 20 ca 1b 05; +0530: 54 21 00 00 22 97 11 e1 c1 c5 e5 cd 24 06 da 82; +0540: 05 77 23 0b 78 b1 c2 3b 05 2a 97 11 cd 24 06 da; +0550: 82 05 5f cd 24 06 da 82 05 bd c2 74 05 7b bc c2; +0560: 74 05 af e1 c1 d1 cd 00 07 f5 3a 9c 11 fe f0 20; +0570: 01 fb f1 c9 15 ca 7c 05 62 c3 15 05 3e 01 37 c3; +0580: 63 05 3e 02 37 c3 63 05 f3 d5 c5 e5 2a 02 11 e5; +0590: c1 2a 04 11 16 d2 1e 53 78 b1 ca 63 05 cd 33 07; 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+20a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +20b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +20c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +20d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +20e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +20f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +21a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +21b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +21c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +21d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +21e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +21f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +22a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +22b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +22c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +22d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +22e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +22f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +23a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +23b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +23c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +23d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +23e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +23f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +24a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +24b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +24c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +24d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +24e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +24f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +25a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +25b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +25c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +25d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +25e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +25f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +26a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +26b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +26c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +26d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +26e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +26f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +27a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +27b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +27c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +27d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +27e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +27f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +28a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +28b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +28c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +28d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +28e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +28f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +29a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +29b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +29c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +29d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +29e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +29f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +2ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +30a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +30b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +30c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +30d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +30e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +30f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +31a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +31b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +31c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +31d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +31e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +31f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +32a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +32b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +32c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +32d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +32e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +32f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +33a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +33b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +33c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +33d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +33e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +33f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +34a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +34b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +34c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +34d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +34e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +34f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +35a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +35b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +35c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +35d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +35e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +35f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +36a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +36b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +36c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +36d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +36e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +36f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +37a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +37b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +37c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +37d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +37e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +37f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +3800: c3 4a 00 c3 e6 07 c3 0e 09 c3 18 09 c3 20 09 c3; +3810: 7f 00 c3 35 09 c3 81 09 c3 99 09 c3 bd 08 c3 32; +3820: 0a c3 36 04 c3 75 04 c3 d8 04 c3 f8 04 c3 88 05; +3830: c3 c7 01 c3 08 03 00 00 c3 38 10 c3 58 03 c3 e5; +3840: 02 c3 fa 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd; +3850: c9 0f 3e 16 d7 06 3c 21 70 11 cd d8 0f 21 92 03; +3860: 3e c3 32 38 10 22 39 10 21 04 05 22 9e 11 cd be; +3870: 02 11 41 01 df cd c0 0a 18 08 11 f1 10 18 96 c3; +3880: 26 09 31 f0 10 11 82 00 d5 cd 09 00 3e 2a d7 11; +3890: a3 11 cd 03 00 1a fe 2a c2 54 0c 13 1a fe 47 ca; +38a0: 59 01 fe 46 ca 00 f6 fe 4d ca 0f 0c fe 53 ca 82; +38b0: 0c fe 40 ca 0e 0e fe 4c 28 1f fe 50 28 36 fe 52; +38c0: ca aa 01 fe 23 ca 12 02 c3 9b 0a cd e8 00 cd 2d; +38d0: 00 38 0a 11 c4 01 cf df c9 cd e8 00 ef da 67 01; +38e0: 2a 06 11 7c fe 12 d8 e9 cd 27 00 38 95 cf 11 38; +38f0: 01 df 18 86 11 00 d0 0e 19 06 28 1a cd ce 0b cd; +3900: 0f 01 13 10 f6 3e 0d cd 0f 01 0d 20 ec c9 d5 f5; +3910: db fe e6 0d b7 28 07 cd 1e 00 28 77 18 f2 f1 d3; +3920: ff 3e 80 d3 fe db fe e6 0d fe 01 20 f8 af d3 fe; +3930: c9 46 4f 55 4e 44 20 0d 4c 4f 41 44 49 4e 47 20; +3940: 0d 2a 2a 20 4d 5a 90 4d 4f 4e 49 54 4f 52 20 56; +3950: 45 52 34 2e 34 20 2a 2a 0d 13 1a fe 4f 20 04 13; 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+58e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +58f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +59a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +59b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +59c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +59d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +59e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +59f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +5ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +60a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +60b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +60c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +60d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +60e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +60f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +61a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +61b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +61c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +61d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +61e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +61f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +62a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +62b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +62c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +62d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +62e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +62f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +63a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +63b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +63c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +63d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +63e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +63f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +64a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +64b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +64c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +64d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +64e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +64f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +65a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +65b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +65c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +65d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +65e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +65f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +66a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +66b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +66c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +66d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +66e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +66f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +67a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +67b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +67c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +67d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +67e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +67f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +68a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +68b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +68c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +68d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +68e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +68f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +69a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +69b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +69c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +69d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +69e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +69f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +6f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; 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+8dc0: 11 7d fe 27 c2 90 0e 5c 16 00 21 73 11 19 7e b7; +8dd0: c2 90 0e 23 36 01 23 36 00 c3 90 0e f5 c5 d5 e5; +8de0: 47 e6 f0 fe c0 c2 de 0f a8 07 07 4f 06 00 21 f3; +8df0: 0d 09 e9 c3 32 0e 00 c3 74 0e 00 c3 84 0e 00 c3; +8e00: 90 0e 00 c3 ae 0e 00 c3 bf 0e 00 c3 c5 0e 00 c3; +8e10: f8 0e 00 c3 49 0f 00 c3 e1 0e 00 c3 ee 0e 00 c3; +8e20: de 0f 00 c3 de 0f 00 c3 8b 0f 00 c3 de 0f 00 c3; +8e30: de 0f cd a6 0d af 32 03 e0 01 c0 03 11 00 d0 21; +8e40: 28 d0 ed b0 eb 06 28 cd d8 0f 01 1a 00 11 73 11; +8e50: 21 73 11 23 ed b0 36 00 3a 73 11 b7 c2 6a 0e cd; +8e60: a6 0d 3e 01 32 03 e0 c3 de 0f 2a 71 11 25 22 71; +8e70: 11 c3 39 0e 2a 71 11 7c fe 18 ca 32 0e 24 22 71; +8e80: 11 c3 de 0f 2a 71 11 7c b7 ca de 0f 25 c3 7e 0e; +8e90: 2a 71 11 7d fe 27 d2 9d 0e 2c c3 7e 0e 2e 00 24; +8ea0: 7c fe 19 da 7e 0e 26 18 22 71 11 c3 32 0e 2a 71; +8eb0: 11 7d b7 28 04 2d c3 7e 0e 2e 27 25 f2 7e 0e 21; +8ec0: 00 00 c3 7e 0e cd a6 0d 0e 19 21 00 d0 06 28 cd; +8ed0: d8 0f 0d c2 cd 0e 21 73 11 06 1b cd d8 0f c3 bf; +8ee0: 0e 3e 05 32 03 e0 3e 00 32 70 11 c3 de 0f 3e 04; +8ef0: 32 03 e0 3e 01 c3 e8 0e 2a 71 11 7c b5 ca de 0f; +8f00: 7d b7 c2 1d 0f 5c 16 00 21 73 11 19 7e b7 c2 1d; +8f10: 0f cd b1 0f cd a6 0d 2b 36 00 c3 ae 0e 2a 71 11; +8f20: 5c 1c 16 00 21 73 11 19 7e 47 b7 3e 28 28 02 3e; +8f30: 50 2a 71 11 95 4f 06 00 cd b1 0f e5 d1 1b cd a6; +8f40: 0d ed b0 2b 36 00 c3 ae 0e 2a 71 11 5c 1c 16 00; +8f50: 21 73 11 19 7e b7 0e 00 2a 71 11 2e 27 28 02 24; +8f60: 0c cd b4 0f 7e b7 c2 de 0f e5 2a 71 11 3e 27 95; +8f70: 47 79 b7 28 04 3e 28 80 47 d1 d5 e1 2b cd a6 0d; +8f80: 7e 12 36 00 2b 1b 10 f8 c3 de 0f 2a 71 11 5c 1c; +8f90: 16 00 21 73 11 19 7e b7 2a 71 11 ca 9d 0e 2e 00; +8fa0: 7c fe 17 28 05 24 24 c3 7e 0e 24 22 71 11 c3 32; +8fb0: 0e 2a 71 11 c5 d5 e5 c1 11 28 00 21 d8 cf 19 05; +8fc0: f2 be 0f 06 00 09 d1 c1 c9 21 03 e0 36 8a 36 07; +8fd0: 36 05 3e 01 32 03 e0 c9 af 77 23 10 fc c9 e1 d1; +8fe0: c1 f1 c9 ae cd ee ff ae fe ac de 4e ff ae df ae; +8ff0: df 2f ff 26 7d fe fd ee fd ac df 7e df ae df ff; +9000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +90a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +90b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +90c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +90d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +90e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +90f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +91a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +91b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +91c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +91d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +91e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +91f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +92a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +92b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +92c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +92d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +92e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +92f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +93a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +93b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +93c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +93d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +93e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +93f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +94a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +94b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +94c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +94d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +94e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +94f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +95a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +95b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +95c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +95d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +95e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +95f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +96a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +96b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +96c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +96d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +96e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +96f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +97a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +97b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +97c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +97d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +97e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +97f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +98a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +98b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +98c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +98d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +98e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +98f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +99a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +99b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +99c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +99d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +99e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +99f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +9ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a0a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a0b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a0c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +a0d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; 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+c3c0: 00 09 7e 18 1b 3e cb b7 c3 ef 08 29 f4 dd c5 e5; +c3d0: d5 21 b5 0a 54 5d 01 00 01 ed b1 28 06 3e f0 d1; +c3e0: e1 c1 c9 b7 2b ed 52 7d 18 f5 22 21 17 11 01 c7; +c3f0: 00 1a 24 23 12 05 04 13 18 03 26 25 19 14 07 06; +c400: 16 02 28 27 09 15 0a 08 0e 00 20 29 10 0f 0c 0b; +c410: 2f 0d be 2a 52 55 4f 2c 2d 2e c5 59 c3 c2 cd 54; +c420: 00 49 28 27 25 24 22 21 e7 20 6a 29 2a 26 00 23; +c430: 00 2e 62 61 97 91 81 c8 00 9a 64 63 92 85 84 93; +c440: 98 83 66 65 99 94 87 86 96 82 68 67 89 95 8a 88; +c450: 8e 00 bf 69 90 8f 8c 8b 51 8d a5 2b bc a4 6b 6a; +c460: 45 57 c6 80 c4 c1 cd 40 00 50 3e 37 38 3c 53 c7; +c470: 00 76 7b 7f 30 34 47 44 6d de 5e 3a 75 71 4b 4a; +c480: da 6f bd 1f 7d 79 5c 72 32 00 9c a1 d6 b0 b4 5b; +c490: 60 1c 9e d2 d8 b2 b6 42 db b8 c5 d4 c3 c2 cd 4e; +c4a0: 00 ba 36 3f 78 7c 46 c8 00 77 3b 7e 70 74 48 41; +c4b0: dd d9 1e 7a 35 31 4c 43 a6 6e a2 5f 3d 39 5d 73; +c4c0: 33 00 9d a3 b1 d5 56 6c d0 1d 9f d1 b3 d7 4d b5; +c4d0: 1b b9 c6 d3 c4 c1 cd b7 00 bb f0 f0 e2 c1 e0 f0; +c4e0: 00 e5 f0 f0 c2 cf ce c3 e3 f3 f0 f0 e4 c4 f7 f6; +c4f0: c6 f2 f0 f0 f9 c5 fa f8 fe f0 f0 f0 e1 ff fc fb; +c500: f0 fd ef f4 e6 cc f0 f0 f0 f0 f0 eb f0 f0 f0 ee; +c510: f0 3e f0 32 00 e0 00 3a 01 e0 b7 17 30 19 1f 1f; +c520: 30 05 1f 30 06 3f c9 3e 40 37 c9 3a 6e 11 3e 01; +c530: 32 6e 11 3e 10 37 c9 e6 02 c8 3e 20 37 c9 f5 3e; +c540: 03 32 03 e0 cd 59 07 cd 59 07 3e 02 32 03 e0 cd; +c550: 59 07 cd 59 07 f1 c9 f5 3e 03 32 03 e0 cd 59 07; +c560: cd 59 07 cd 59 07 cd 59 07 3e 02 32 03 e0 cd 59; +c570: 07 cd 59 07 cd 59 07 cd 60 07 f1 c9 fe 08 28 10; +c580: cb 0e 10 fc cb c6 cb 8e 47 cb 06 10 fc c3 7b 0e; +c590: 23 cb c6 cb 8e 18 f6 cb fe 23 cb 86 18 ef 7f 20; +c5a0: 50 4c 41 59 0d f3 c9 c5 06 23 cd a2 09 10 fb c1; +c5b0: c9 d7 41 30 0d f5 c5 d5 e5 47 cd b1 0f 70 2a 71; +c5c0: 11 7d fe 4f 20 c7 cd 2b 0a 38 c2 3a 91 11 b7 c2; +c5d0: 9d 03 eb 78 fe 07 28 bf 18 a2 24 f3 f5 c5 d5 e5; +c5e0: 47 e6 f0 fe c0 c2 e5 0e a8 07 4f 06 00 21 ff 0d; +c5f0: 3a 91 11 b7 28 03 21 68 01 09 5e 23 56 eb e9 1f; +c600: 0e 5d 0e 6e 0e 7b 0e 95 0e fb 03 b3 0e f2 0e 2d; +c610: 0f e1 0e ee 0e e5 0e 17 0a 73 0f e8 05 59 0f 21; +c620: 7a 11 0e 05 3a 7f 11 81 32 7f 11 3a 7b 11 81 32; +c630: 7b 11 79 86 77 cd c7 09 2a 7d 11 11 d0 07 19 06; +c640: 50 af cb 9c 77 23 10 fa 3a 7a 11 6f 26 e2 7e 21; +c650: 79 11 b7 06 07 cb 1e 2b 10 fb c3 e5 0e 2a 71 11; +c660: 7c fe 18 28 2e 24 cd 83 02 22 71 11 18 77 2a 71; +c670: 11 7c b7 28 35 25 cd 9d 02 18 ee 2a 71 11 7d fe; +c680: 4f 30 03 2c 18 e3 2e 00 24 7c fe 19 38 d8 26 18; +c690: 22 71 11 18 42 2a 71 11 7d b7 28 03 2d 18 ca 2e; +c6a0: 4f 25 f2 76 0e 26 00 22 71 11 3a 91 11 b7 20 35; +c6b0: c3 59 0f 21 73 11 06 1b cd d8 0f 21 00 d0 e5 cd; +c6c0: e2 09 e1 3a 91 11 b7 20 08 22 7d 11 3e 7d 32 7f; +c6d0: 11 3a 00 e2 c3 09 04 3a 91 11 b7 c2 3d 01 c3 9f; +c6e0: 0f af 32 70 11 e1 d1 c1 f1 c9 0d 0d 0d 0d 3e 01; +c6f0: 18 f0 2a 71 11 7c b5 28 ec 7d b7 20 0d cd 2b 0a; +c700: 38 08 cd b1 0f 2b 36 00 18 8b cd 2b 0a 0f 3e 50; +c710: 30 01 07 95 47 cd b1 0f e5 d1 1b cb e2 cb 9c cb; +c720: 9a 7e 12 23 13 10 f6 2b 36 00 c3 95 0e cd 2b 0a; +c730: 0f 2e 4f 7d 30 01 24 cd b4 0f e5 2a 71 11 30 02; +c740: 3e 9f 95 47 d1 1a b7 20 9c cd b1 0f 7e 36 00 23; +c750: cb 9c 5e 77 7b 10 f8 18 8c 21 7a 11 3a 7b 11 be; +c760: 28 83 cd 9d 02 7e d6 05 77 6f 26 e2 7e cd c7 09; +c770: c3 e5 0e cd 2b 0a 0f d2 86 0e 2e 00 24 7c fe 18; +c780: 28 17 30 07 cd 83 02 24 c3 66 0e 25 22 71 11 21; +c790: 9f 0f e5 f5 c5 d5 cd 9f 0f 22 71 11 cd 83 02 21; +c7a0: 7a 11 3a 7f 11 be ca 1f 0e cd 83 02 7e c6 05 18; +c7b0: b7 2a 71 11 f5 c5 d5 e5 c1 11 50 00 21 b0 cf 3a; +c7c0: 91 11 b7 20 05 2a 7d 11 ed 52 19 05 f2 ca 0f 06; +c7d0: 00 09 cb 9c d1 c1 f1 c9 af 18 02 3e ff 77 23 10; +c7e0: fc c9 c5 d5 e5 01 01 e0 11 02 e0 26 64 cd 01 06; +c7f0: 38 0b cd a2 09 1a e6 20 20 f1 25 20 f0 c3 9f 06; +c800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c8a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c8b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c8c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c8d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c8e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c8f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c9a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c9b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c9c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c9d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c9e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +c9f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ca90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +caa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +caf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cb90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cbb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cbc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cbd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cbe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cbf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cc90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ccb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ccc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ccd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ccf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cd90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cda0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cdb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cdc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cdd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cde0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cdf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ce90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ceb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ced0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cf90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cfa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cfb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cfc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cfd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cfe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +cff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d0a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d0b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d0c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d0d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d0e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d0f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d1a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d1b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d1c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d1d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d1e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d1f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d2a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d2b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d2c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d2d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d2e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d2f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d3a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d3b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d3c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d3d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d3e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d3f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d4a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d4b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d4c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d4d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d4e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d4f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d5a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d5b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d5c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d5d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d5e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d5f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d6a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d6b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d6c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d6d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d6e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d6f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d7a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d7b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d7c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d7d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d7e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d7f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d8a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d8b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d8c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d8d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d8e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d8f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d9a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d9b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d9c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d9d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d9e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +d9f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +da90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +daa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +daf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +db90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dbb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dbc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dbd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dbe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dbf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dc90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dcb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dcc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dcd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dcf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dd90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dda0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ddb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ddc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ddd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dde0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ddf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +de90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +deb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +ded0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +def0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +df90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dfa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dfb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dfc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dfd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dfe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +dff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +e000: c3 4a 00 c3 e6 07 c3 0e 09 c3 18 09 c3 20 09 c3; +e010: 24 09 c3 35 09 c3 93 08 c3 a1 08 c3 bd 08 c3 32; +e020: 0a c3 36 04 c3 75 04 c3 d8 04 c3 f8 04 c3 88 05; +e030: c3 c7 01 c3 08 03 00 00 c3 38 10 c3 58 03 c3 77; +e040: 05 c3 e5 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd; +e050: 3e 07 cd 32 0a 30 19 fe 20 20 15 d3 e1 11 f0 ff; +e060: 21 6b 00 01 05 00 ed b0 c3 f0 ff d3 e0 c3 00 00; +e070: 06 ff 21 f1 10 cd d8 0f 3e 16 cd 12 00 3e 71 21; +e080: 00 d8 cd d5 09 21 8d 03 3e c3 32 38 10 22 39 10; +e090: 3e 04 32 9e 11 cd be 02 cd 09 00 11 e7 06 df cd; +e0a0: 77 05 3e 01 32 9d 11 21 00 e8 77 18 55 cd 09 00; +e0b0: 3e 2a cd 12 00 11 a3 11 cd 03 00 1a 13 fe 0d 28; +e0c0: ec fe 4a 28 2e fe 4c 28 48 fe 46 28 32 fe 42 28; +e0d0: 26 fe 23 28 86 fe 50 28 7c fe 4d ca a8 07 fe 53; +e0e0: ca 5e 0f fe 56 ca cb 0f fe 44 ca 29 0d 00 00 00; +e0f0: 00 18 c8 cd 3d 01 e9 3a 9d 11 1f 3f 17 18 a5 21; +e100: 00 f0 7e b7 20 a7 e9 fe 02 28 a2 11 47 01 df 18; +e110: 9c cd d8 04 38 f1 cd 09 00 11 a0 09 df 11 f1 10; +e120: df cd f8 04 38 e1 2a 06 11 7c fe 12 38 e1 e9 e3; +e130: c1 11 a3 11 cd 03 00 1a fe 1b 28 d3 e9 fd e3 f1; +e140: cd 10 04 38 ca fd e9 43 48 45 43 4b 20 53 55 4d; +e150: 20 45 52 2e 0d 1a fe 26 20 16 13 1a fe 4c 28 16; +e160: fe 53 28 17 fe 43 28 23 fe 47 28 18 fe 54 28 10; +e170: cd a5 01 c3 ad 00 11 70 04 18 f5 11 d5 03 18 f0; +e180: 3e 04 18 02 3e 02 cd 8f 01 18 cf 3e 1d 18 f7 0e; +e190: 00 47 cd b6 01 78 d3 ff 3e 80 d3 fe 0e 01 cd b6; +e1a0: 01 af d3 fe c9 d5 c5 f5 1a cd 8f 01 1a 13 fe 0d; +e1b0: 20 f6 f1 c1 d1 c9 db fe e6 0d b9 c8 cd 1e 00 20; +e1c0: f5 31 f0 10 c3 ad 00 c5 d5 e5 3e 02 32 a0 11 06; +e1d0: 01 1a fe 0d 28 3b fe c8 28 37 fe cf 28 27 fe 2d; +e1e0: 28 23 fe 2b 28 27 fe d7 28 23 fe 23 21 6c 02 20; +e1f0: 04 21 84 02 13 cd 1c 02 38 d7 cd c8 02 38 15 cd; +e200: ab 02 41 18 cc 3e 03 32 a0 11 13 18 c4 3e 01 18; +e210: f6 cd c8 02 f5 cd be 02 f1 c3 9b 06 c5 06 08 1a; +e220: be 28 09 23 23 23 10 f8 37 13 c1 c9 23 d5 5e 23; +e230: 56 eb 7c b7 28 09 3a a0 11 3d 28 03 29 18 fa 22; +e240: a1 11 21 a0 11 36 02 2b d1 13 1a 47 e6 f0 fe 30; +e250: 28 03 7e 18 05 13 78 e6 0f 77 21 9c 02 85 6f 4e; +e260: 3a 9e 11 47 af 81 10 fd c1 4f af c9 43 46 08 44; +e270: 5f 07 45 91 06 46 33 06 47 86 05 41 ec 04 42 64; +e280: 04 52 00 00 43 cf 07 44 f5 06 45 33 06 46 da 05; +e290: 47 37 05 41 a5 04 42 23 04 52 00 00 01 02 03 04; +e2a0: 06 08 0c 10 18 20 13 13 13 13 c9 2a a1 11 7c b7; +e2b0: 28 0c d5 eb 21 04 e0 73 72 3e 01 d1 18 06 3e 36; +e2c0: 32 07 e0 af 32 08 e0 c9 21 00 e0 36 f8 23 7e e6; +e2d0: 81 20 02 37 c9 3a 08 e0 0f 38 fa 3a 08 e0 0f 30; +e2e0: fa 10 f2 af c9 f5 c5 e6 0f 47 3e 08 90 32 9e 11; +e2f0: c1 f1 c9 21 73 11 3a 72 11 85 6f 7e 23 cb 16 b6; +e300: cb 1e 0f eb 2a 71 11 c9 f3 c5 d5 e5 32 9b 11 3e; +e310: f0 32 9c 11 21 c0 a8 af ed 52 e5 00 eb 21 07 e0; +e320: 36 74 36 b0 2b 73 72 2b 36 0a 36 00 23 23 36 80; +e330: 2b 4e 7e ba 20 fb 79 bb 20 f7 2b 00 00 00 36 fb; +e340: 36 3c 23 d1 4e 7e ba 20 fb 79 bb 20 f7 e1 d1 c1; +e350: fb c9 d7 41 30 0d 00 00 e5 21 07 e0 36 80 2b f3; +e360: 5e 56 fb 7b b2 28 0e af 21 c0 a8 ed 52 38 10 eb; +e370: 3a 9b 11 e1 c9 11 c0 a8 3a 9b 11 ee 01 e1 c9 f3; +e380: 21 06 e0 7e 2f 5f 7e 2f 57 fb 13 18 eb f5 c5 d5; +e390: e5 21 9b 11 7e ee 01 77 21 07 e0 36 80 2b e5 5e; +e3a0: 56 21 c0 a8 19 2b 2b eb e1 73 72 e1 d1 c1 f1 fb; +e3b0: c9 cd 20 09 7e cd c3 03 7e c9 7c cd c3 03 7d 18; +e3c0: 02 00 00 f5 0f 0f 0f 0f cd da 03 cd 12 00 f1 cd; +e3d0: da 03 c3 12 00 01 09 09 09 0d e6 0f fe 0a 38 02; +e3e0: c6 07 c6 30 c9 d6 30 d8 fe 0a 3f d0 d6 07 fe 10; +e3f0: 3f d8 fe 0a c9 00 00 00 00 18 ea 7f 20 50 4c 41; +e400: 59 0d 7f 20 52 45 43 4f 52 44 2e 0d 00 00 00 00; +e410: d5 cd 1f 04 38 07 67 cd 1f 04 38 01 6f d1 c9 c5; +e420: 1a 13 cd f9 03 38 0d 0f 0f 0f 0f 4f 1a 13 cd f9; +e430: 03 38 01 b1 c1 c9 f3 d5 c5 e5 16 d7 1e cc 21 f0; +e440: 10 01 80 00 cd 1a 07 cd 9f 06 38 18 7b fe cc 20; +e450: 0d cd 09 00 d5 11 67 04 df 11 f1 10 df d1 cd 7a; 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+10080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +100a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +100b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +100c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +100d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +100e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +100f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +101a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +101b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +101c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +101d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +101e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +101f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +102a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +102b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +102c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +102d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +102e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +102f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +103a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +103b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +103c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +103d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +103e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +103f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +104a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +104b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +104c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +104d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +104e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +104f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +105a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +105b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +105c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +105d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +105e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +105f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +106a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +106b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +106c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +106d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +106e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +106f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +107a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +107b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +107c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +107d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +107e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +107f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +108a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +108b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +108c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +108d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +108e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +108f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +109a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +109b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +109c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +109d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +109e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +109f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +10ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +110a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +110b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +110c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +110d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +110e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +110f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +111a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +111b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +111c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +111d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +111e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +111f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +112a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +112b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +112c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +112d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +112e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +112f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +113a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +113b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +113c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +113d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +113e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +113f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +114a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +114b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +114c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +114d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +114e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +114f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +115a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +115b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +115c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +115d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +115e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +115f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +116a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +116b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +116c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +116d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +116e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +116f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +117a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +117b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +117c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +117d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +117e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +117f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +11800: c3 4a 00 c3 e6 07 c3 0e 09 c3 18 09 c3 20 09 c3; +11810: 24 09 c3 35 09 c3 93 08 c3 a1 08 c3 bd 08 c3 32; +11820: 0a c3 36 04 c3 75 04 c3 d8 04 c3 f8 04 c3 88 05; +11830: c3 c7 01 c3 08 03 00 00 c3 38 10 c3 58 03 c3 77; +11840: 05 c3 e5 02 c3 ab 02 c3 be 02 31 f0 10 ed 56 cd; +11850: 3e 07 cd 32 0a 30 19 fe 20 20 15 d3 e1 11 f0 ff; +11860: 21 6b 00 01 05 00 ed b0 c3 f0 ff d3 e0 c3 00 00; +11870: 06 ff 21 f1 10 cd d8 0f 3e 16 cd 12 00 3e 71 21; +11880: 00 d8 cd d5 09 21 8d 03 3e c3 32 38 10 22 39 10; +11890: 3e 04 32 9e 11 cd be 02 cd 09 00 11 e7 06 df cd; +118a0: 77 05 3e 01 32 9d 11 21 00 e8 77 18 55 cd 09 00; +118b0: 3e 2a cd 12 00 11 a3 11 cd 03 00 1a 13 fe 0d 28; +118c0: ec fe 4a 28 2e fe 4c 28 48 fe 46 28 32 fe 42 28; +118d0: 26 fe 23 28 86 fe 50 28 7c fe 4d ca a8 07 fe 53; +118e0: ca 5e 0f fe 56 ca cb 0f fe 44 ca 29 0d 00 00 00; +118f0: 00 18 c8 cd 3d 01 e9 3a 9d 11 1f 3f 17 18 a5 21; +11900: 00 f0 7e b7 20 a7 e9 fe 02 28 a2 11 47 01 df 18; +11910: 9c cd d8 04 38 f1 cd 09 00 11 a0 09 df 11 f1 10; +11920: df cd f8 04 38 e1 2a 06 11 7c fe 12 38 e1 e9 e3; +11930: c1 11 a3 11 cd 03 00 1a fe 1b 28 d3 e9 fd e3 f1; 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+138c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +138d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +138e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +138f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +139a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +139b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +139c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +139d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +139e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +139f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +13ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +140a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +140b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +140c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +140d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +140e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +140f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +141a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +141b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +141c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +141d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +141e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +141f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +142a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +142b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +142c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +142d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +142e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +142f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +143a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +143b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +143c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +143d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +143e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +143f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +144a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +144b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +144c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +144d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +144e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +144f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +145a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +145b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +145c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +145d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +145e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +145f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +146a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +146b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +146c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +146d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +146e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +146f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +147a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +147b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +147c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +147d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +147e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +147f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +148a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +148b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +148c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +148d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +148e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +148f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +149a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +149b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +149c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +149d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +149e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +149f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +14f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; 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+15de0: 00 c3 e8 05 d5 11 2c 1a 1b 7b b2 20 fb d1 c9 21; +15df0: 00 80 dd 21 f8 05 18 1a db f9 fe 00 c2 57 00 dd; +15e00: 21 05 06 18 0d db f9 77 23 7d b4 20 f6 d3 f8 c3; +15e10: 02 00 7c d3 f8 7d d3 f9 16 04 15 20 fd dd e9 00; +15e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +15ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +160a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +160b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +160c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +160d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +160e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +160f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +161a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +161b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +161c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +161d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +161e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +161f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16240: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16250: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16260: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16270: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16280: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16290: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +162a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +162b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +162c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +162d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +162e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +162f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16300: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16310: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16320: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +163a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +163b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +163c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +163d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +163e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +163f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +164a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +164b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +164c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +164d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +164e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +164f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +165a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +165b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +165c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +165d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +165e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +165f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +166a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +166b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +166c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +166d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +166e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +166f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16700: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16710: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16720: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16730: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16740: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16750: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16760: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16770: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16780: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +167a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +167b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +167c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +167d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +167e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +167f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16800: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16810: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16820: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16830: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16840: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16850: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16860: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16870: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16880: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16890: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +168a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +168b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +168c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +168d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +168e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +168f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16900: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16910: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16920: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16930: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16940: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16950: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16960: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +169a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +169b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +169c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +169d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +169e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +169f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +16ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +170a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +170b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +170c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +170d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +170e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +170f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +171a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +171b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +171c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +171d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +171e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +171f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; +17210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff; 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Some components are common +-- by their nature (ie. 8255 PIO) but these are instantiated within the lower +-- tree branch as their design use is less generic. +-- +-- The tree is as follows;- +-- +-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd +-- | -> mz80c_video.vhd +-- | -> pcg.vhd +-- | -> cmt.vhd (this may move to common and be shared with mz80b) +-- | -> keymatrix.vhd (common) +-- | -> pll.v (common) +-- | -> clkgen.vhd (common) +-- | -> T80 (common) +-- | -> i8255 (common) +-- | -> i8253 (common) +-- | -> dpram.vhd (common) +-- | -> dprom.vhd (common) +-- | -> mctrl.vhd (common) +-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv +-- | +-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development) +-- +-- +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: August 2018 - Initial module created. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; + +entity mz80b is + PORT ( + -- Clocks + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module. + + -- Resets. + SYSTEM_RESET : in std_logic; + + -- Z80 CPU + T80_RST_n : in std_logic; + T80_CLK : in std_logic; + T80_CLKEN : out std_logic; + T80_WAIT_n : out std_logic; + T80_INT_n : out std_logic; + T80_NMI_n : out std_logic; + T80_BUSRQ_n : out std_logic; + T80_M1_n : in std_logic; + T80_MREQ_n : in std_logic; + T80_IORQ_n : in std_logic; + T80_RD_n : in std_logic; + T80_WR_n : in std_logic; + T80_RFSH_n : in std_logic; + T80_HALT_n : in std_logic; + T80_BUSAK_n : in std_logic; + T80_A16 : in std_logic_vector(15 downto 0); + T80_DI : out std_logic_vector(7 downto 0); + T80_DO : in std_logic_vector(7 downto 0); + + -- Chip selects to common resources. + CS_ROM_n : out std_logic; + CS_RAM_n : out std_logic; + + -- Audio. + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + + -- Video signals. + R : out std_logic; + G : out std_logic; + B : out std_logic; + HSYNC_n : out std_logic; + VSYNC_n : out std_logic; + HBLANK : out std_logic; + VBLANK : out std_logic; + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- I/O -- I/O down to the core. + PS2_KEY : in std_logic_vector(10 downto 0); + + -- Cassette magnetic tape signals. + CMTBUS : out std_logic_vector(CMTBUS_WIDTH); + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status. + ); +end mz80b; + +architecture rtl of mz80b is +begin + T80_CLKEN <= '1'; + T80_WAIT_n <= '1'; + T80_INT_n <= '1'; + T80_NMI_n <= '1'; + T80_BUSRQ_n <= '1'; + T80_DI <= (others => '0'); + CS_ROM_n <= '1'; + CS_RAM_n <= '1'; + AUDIO_L <= '1'; + AUDIO_R <= '1'; + R <= '0'; + G <= '0'; + B <= '0'; + HSYNC_n <= '0'; + VSYNC_n <= '0'; + HBLANK <= '0'; + VBLANK <= '0'; + CMTBUS <= (others => '0'); + IOCTL_DIN <= (others => '0'); + DEBUG_STATUS_LEDS <= (others => '0'); +end rtl; diff --git a/mz80c/cmt.vhd b/mz80c/cmt.vhd new file mode 100644 index 0000000..10ec217 --- /dev/null +++ b/mz80c/cmt.vhd @@ -0,0 +1,1401 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: cmt.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: Sharp MZ series PWM Tape Interface. +-- This module fully emulates the Sharp PWM tape interface. It uses cache ram +-- to simulate the tape. Data is played out to the Sharp or read from the Sharp +-- and stored in the ram. +-- For reading of data from Tape to the Sharp, the HPS or other controller loads a +-- complete tape into ram and should the Play/Auto function be enabled, playback +-- starts immediately. +-- For writing of data from the Sharp to Taoe, the data is stored in ram and the +-- HPS or other controller, when it gets the completed signal, can read out the ram +-- and store the data onto a local filesystem. +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written and playback mode tested and debugged. +-- August 2018 - Record mode written but not yet debugged/completed. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; +use ieee.numeric_std.all; + +entity cmt is + Port ( + RST : in std_logic; + + -- Clock signals needed by this module. + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Cassette magnetic tape signals. + CMTBUS : out std_logic_vector(CMTBUS_WIDTH); + CMT_READBIT : in std_logic; + CMT_MOTOR : in std_logic; + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS : out std_logic_vector(23 downto 0) -- 8 leds to display cmt internal status. + ); +end cmt; + +architecture RTL of cmt is + +-- +-- Components +-- +component dpram + generic ( + init_file : string; + widthad_a : natural; + width_a : natural; + widthad_b : natural; + width_b : natural; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + Port ( + clock_a : in std_logic := '1'; + clocken_a : in std_logic := '1'; + address_a : in std_logic_vector (widthad_a-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + wren_a : in std_logic := '0'; + q_a : out std_logic_vector (width_a-1 downto 0); + + clock_b : in std_logic; + clocken_b : in std_logic := '1'; + address_b : in std_logic_vector (widthad_b-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0); + wren_b : in std_logic := '0'; + q_b : out std_logic_vector (width_b-1 downto 0) + ); +end component; + +-- HPS Control signals. +signal IOCTL_CS_HDR_n : std_logic; +signal IOCTL_CS_DATA_n : std_logic; +signal IOCTL_TAPEHDR_WEN : std_logic; +signal IOCTL_TAPEDATA_WEN : std_logic; +signal IOCTL_DIN_HDR : std_logic_vector(7 downto 0); +signal IOCTL_DIN_DATA : std_logic_vector(7 downto 0); +-- +signal CMTBUSi : std_logic_vector(CMTBUS_WIDTH); +signal BUTTONS_LAST : std_logic_vector(1 downto 0); +signal PLAY_READY_CNT : integer range 0 to 224000000 := 0; -- 2 second timer. +signal PLAY_READY : std_logic; +signal PLAY_READY_CLR : std_logic; +signal PLAY_READY_SEQ : std_logic_vector(1 downto 0); -- Setup and hold sequencer. +signal PLAY_BUTTON : std_logic; +signal PLAYING : std_logic_vector(2 downto 0); +signal RECORD_READY : std_logic; +signal RECORD_READY_SET : std_logic; +signal RECORD_READY_SEQ : std_logic_vector(1 downto 0); -- Setup and hold sequencer. +signal RECORD_BUTTON : std_logic; +signal RECORDING : std_logic_vector(2 downto 0); +signal MOTOR_CLK : std_logic_vector(1 downto 0); +signal MOTOR_SENSE : std_logic; +signal WRITEBIT : std_logic; +signal READBIT : std_logic; +signal TAPE_MOTOR_ON_n : std_logic; +-- Bit receiver signals. +signal RCV_BIT : std_logic; -- Received bit after PWM demodulation coming from MZ. +signal RCV_AVAIL : std_logic; -- Received bit is available and valid. +signal RCV_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal RCV_COUNT : integer range -3095 to 3095 := 0; +-- Bit transmitter signals. +signal XMIT_DONE : std_logic; -- Transmit of bit complete. +signal XMIT_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal XMIT_LOAD_1 : std_logic; -- Load bit and start transmission selector 1. +signal XMIT_LOAD_2 : std_logic; -- Load bit and start transmission selector 2. +signal XMIT_BIT_1 : std_logic; -- Transmit bit for XMIT_LOAD_2 to be PWM modulated and sent to MZ. +signal XMIT_BIT_2 : std_logic; -- Working bit for active XMIT_BIT. +signal XMIT_COUNT : integer range -7999 to 8000 := 0; +signal XMIT_LIMIT : integer range -7999 to 8000 := 0; +-- Bit padding transmitter signals. +signal XMIT_PADDING_LOAD : std_logic; +signal XMIT_PADDING_BIT : std_logic; +signal XMIT_PADDING_DONE : std_logic; +signal XMIT_PADDING_CNT1 : integer range 0 to 32767 := 0; +signal XMIT_PADDING_CNT2 : integer range 0 to 32767 := 0; +signal XMIT_PADDING_LEVEL1 : std_logic; +signal XMIT_PADDING_LEVEL2 : std_logic; +signal PADDING_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal PADDING_CNT1 : integer range 0 to 32767 := 0; +signal PADDING_CNT2 : integer range 0 to 32767 := 0; +signal PADDING_LEVEL1 : std_logic; +signal PADDING_LEVEL2 : std_logic; +-- Cache RAM header/data transmitter signals. +signal XMIT_RAM_LOAD : std_logic; +signal XMIT_RAM_DONE : std_logic; +signal XMIT_RAM_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal XMIT_RAM_ADDR : std_logic_vector(15 downto 0); +signal XMIT_RAM_COUNT : unsigned(15 downto 0); +signal XMIT_RAM_CHKSUM_CNT : unsigned(1 downto 0); +signal XMIT_RAM_CHECKSUM : std_logic_vector(15 downto 0); +signal XMIT_RAM_TYPE : std_logic; +signal XMIT_RAM_STATE : integer range 0 to 7 := 0; +signal XMIT_RAM_SR : std_logic_vector(8 downto 0); +signal XMIT_RAM_BITCNT : integer range 0 to 8 := 0; +signal XMIT_TAPE_SIZE : unsigned(15 downto 0); +-- RAM control signals. +signal RAM_ADDR : std_logic_vector(15 downto 0); +signal RAM_DATAIN : std_logic_vector(7 downto 0); +signal HDR_RAM_DATAOUT : std_logic_vector(7 downto 0); +signal HDR_RAM_WEN : std_logic; +signal DATA_RAM_DATAOUT : std_logic_vector(7 downto 0); +signal DATA_RAM_WEN : std_logic; +-- +signal RCV_PADDING_LOAD : std_logic; +signal RCV_PADDING_DONE : std_logic; +signal RCV_PADDING_CNT : integer range 0 to 30000 := 0; +signal RCV_PADDING_LEVEL : std_logic; +signal RCV_PADDING_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal PADDING_CNT : integer range 0 to 30000 := 0; +signal PADDING_LEVEL : std_logic; +-- +signal RCV_RAM_LOAD : std_logic; +signal RCV_RAM_DONE : std_logic; +signal RCV_RAM_SUCCESS : std_logic; +signal RCV_RAM_ADDR : std_logic_vector(15 downto 0); +signal RCV_RAM_STATE : integer range 0 to 10 := 0; +signal RCV_RAM_TYPE : std_logic; +signal RCV_RAM_RETRIES : std_logic; +signal RCV_RAM_COUNT : unsigned(15 downto 0); +signal RCV_RAM_CHECKSUM : std_logic_vector(15 downto 0); +signal RCV_RAM_CNT_CKSUM : std_logic; +signal RCV_RAM_CALC_CKSUM : std_logic_vector(15 downto 0); +signal RCV_RAM_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal RCV_RAM_SR : std_logic_vector(8 downto 0); +signal RCV_RAM_BITCNT : integer range 0 to 8 := 0; +signal RCV_TAPE_SIZE : unsigned(15 downto 0); +-- Main process Finite State Machine variables. +signal TAPE_READ_STATE : integer range 0 to 15 := 0; +signal TAPE_READ_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +signal TAPE_WRITE_STATE : integer range 0 to 15 := 0; +signal TAPE_WRITE_SEQ : std_logic_vector(2 downto 0); -- Setup and hold sequencer. +-- +begin + + -- Wired signals between this CMT unit and the MZ/MCtrl bus. + -- + CMTBUSi(pkgs.mctrl_pkg.WRITEBIT) <= WRITEBIT; -- Write a bit to the MZ PIO. + CMTBUSi(pkgs.mctrl_pkg.READBIT) <= CMT_READBIT; -- Read a bit from the MZ PIO. + CMTBUSi(pkgs.mctrl_pkg.SENSE) <= MOTOR_SENSE; -- Indiate current state of Motor, 0 if not running, 1 if running. + CMTBUSi(pkgs.mctrl_pkg.ACTIVE) <= PLAYING(2) or RECORDING(2); + CMTBUSi(pkgs.mctrl_pkg.PLAY_READY) <= PLAY_READY; + CMTBUSi(pkgs.mctrl_pkg.PLAYING) <= PLAYING(2); + CMTBUSi(pkgs.mctrl_pkg.RECORD_READY) <= RECORD_READY; + CMTBUSi(pkgs.mctrl_pkg.RECORDING) <= RECORDING(1); + CMTBUSi(pkgs.mctrl_pkg.MOTOR) <= TAPE_MOTOR_ON_n; + -- + READBIT <= CMT_READBIT; + MOTOR_CLK(1) <= CMT_MOTOR; + CMTBUS <= CMTBUSi; + + -- Mux Signals from different sources. + RAM_ADDR <= RCV_RAM_ADDR when RECORDING(1) = '1' else XMIT_RAM_ADDR; + IOCTL_CS_HDR_n <= '0' when IOCTL_ADDR(24 downto 8) = "00000010100000000" else '1'; + IOCTL_CS_DATA_n <= '0' when IOCTL_ADDR(24 downto 16) = "000000110" else '1'; + IOCTL_TAPEHDR_WEN <= '1' when IOCTL_CS_HDR_n = '0' and IOCTL_WR = '1' else '0'; + IOCTL_TAPEDATA_WEN <= '1' when IOCTL_CS_DATA_n = '0' and IOCTL_WR = '1' else '0'; + IOCTL_DIN <= X"00" & IOCTL_DIN_HDR when IOCTL_CS_HDR_n = '0' + else + X"00" & IOCTL_DIN_DATA when IOCTL_CS_DATA_n = '0' + else + (others => '0'); + + TAPEHDR : dpram + GENERIC MAP ( + init_file => null, + widthad_a => 7, + width_a => 8, + widthad_b => 7, + width_b => 8 + ) + PORT MAP ( + clock_a => CLKBUS(CKMEM), + clocken_a => '1', + address_a => RAM_ADDR(6 downto 0), + data_a => RAM_DATAIN, + wren_a => HDR_RAM_WEN, + q_a => HDR_RAM_DATAOUT, + + clock_b => IOCTL_CLK, + address_b => IOCTL_ADDR(6 downto 0), + data_b => IOCTL_DOUT(7 downto 0), + wren_b => IOCTL_TAPEHDR_WEN, + q_b => IOCTL_DIN_HDR + ); + + TAPEDATA : dpram + GENERIC MAP ( + init_file => null, + widthad_a => 16, + width_a => 8, + widthad_b => 16, + width_b => 8 + ) + PORT MAP ( + clock_a => CLKBUS(CKMEM), + clocken_a => '1', + address_a => RAM_ADDR, + data_a => RAM_DATAIN, + wren_a => DATA_RAM_WEN, + q_a => DATA_RAM_DATAOUT, + + clock_b => IOCTL_CLK, + address_b => IOCTL_ADDR(15 downto 0), + data_b => IOCTL_DOUT(7 downto 0), + wren_b => IOCTL_TAPEDATA_WEN, + q_b => IOCTL_DIN_DATA + ); + + -------------------------------------------------------------------- + -- TAPE HEADER FORMAT + -------------------------------------------------------------------- + -- LGAP | LTM | L | HDR | CHKH | L | 256S | HDRC | CHKH | L + -- SGAP | STM | L | FILE | CHKF | L | 256S | FILEC | CHKF | L + -- LGAP is a long GAP + -- SGAP is a short GAP + -- LTM is a long tapemark - 40 long pulses then 40 short pulses + -- STM is a short tapemark - 20 long pulses then 20 short puses + -- HDR is the tapeheader + -- HDRC is a copy of the tapeheader + -- FILE is the file + -- FILEC is a copy of the file + -- CHKH is a 2 byte checksum of the tape header or its copy + -- CHKF is a 2 byte checksum of the file or its copy + -- L is 1 long pulse + -- 256S contains 256 short pulses + -------------------------------------------------------------------- + + -- Process to determine CMT state according to inputs. ie. If we are STOPPED, PLAYING or RECORDING. + -- This is determined by the input switches in CONFIG(BUTTOS), 00 = Off, 01 = Play, 02 = Record and 03 = Auto. + -- Auto mode indicates the CMT logic has to determine wether it is PLAYING or RECORDING. The default is PLAYING + -- but if a bit is received from the MZ then we switch to RECORDING until a full tape dump has been received. + -- + process( RST, CLKBUS(CKCPU), CONFIG(BUTTONS), MOTOR_CLK ) begin + if RST='1' then + TAPE_MOTOR_ON_n <= '1'; + MOTOR_SENSE <= '0'; + PLAY_BUTTON <= '0'; + RECORD_BUTTON <= '0'; + BUTTONS_LAST <= "00"; + PLAYING <= "000"; + RECORDING <= "000"; + MOTOR_CLK(0) <= '0'; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then + + -- Store last state so we detect change. + BUTTONS_LAST <= CONFIG(BUTTONS); + MOTOR_CLK(0) <= MOTOR_CLK(1); + + -- Store last state so we can detect a switch to recording or play mode. + RECORDING(1 downto 0) <= RECORDING(2 downto 1); + PLAYING(1 downto 0) <= PLAYING(2 downto 1); + + -- Process the buttons and adapt signals accordingly. + -- + if BUTTONS_LAST /= CONFIG(BUTTONS) then + case CONFIG(BUTTONS) is + when "00" => -- Off + PLAY_BUTTON <= '0'; + RECORD_BUTTON <= '0'; + TAPE_MOTOR_ON_n <= '1'; + when "10" => -- Record + PLAY_BUTTON <= '0'; + RECORD_BUTTON <= '1'; + TAPE_MOTOR_ON_n <= '0'; + when "01"|"11" => -- Play/Auto + -- Assume playback mode for Auto unless activity is detected from the MZ, + -- in which case switch to Recording. + PLAY_BUTTON <= '1'; + RECORD_BUTTON <= '0'; + TAPE_MOTOR_ON_n <= '0'; + end case; + end if; + + -- If in auto mode and data starts being received from the MZ, enter record mode. + -- + if CONFIG(BUTTONS) = "11" and RCV_AVAIL = '1' then + PLAY_BUTTON <= '0'; + RECORD_BUTTON <= '1'; + TAPE_MOTOR_ON_n <= '0'; + end if; + + -- If the motor is running then setup the state according to the buttons pressed and the data availability. + -- + if TAPE_MOTOR_ON_n = '0' and PLAY_BUTTON = '1' and PLAY_READY = '1' then + PLAYING(2) <= '1'; + RECORDING(2) <= '0'; + MOTOR_SENSE <= '1'; + elsif TAPE_MOTOR_ON_n = '0' and RECORD_BUTTON = '1' then + PLAYING(2) <= '0'; + RECORDING(2) <= '1'; + MOTOR_SENSE <= '1'; + elsif CONFIG(BUTTONS) /= "11" then + PLAYING(2) <= '0'; + RECORDING(2) <= '0'; + MOTOR_SENSE <= not TAPE_MOTOR_ON_n; + end if; + + -- MZ motor on/off toggle. A high pulse on MOTOR_CLK will toggle the motor state. + -- + if MOTOR_CLK = "10" then + TAPE_MOTOR_ON_n <= not TAPE_MOTOR_ON_n; + end if; + end if; + end process; + + ---------------------------------------------------------------------------------------------------------------------- + -- Write To Tape logic. + -- + -- This block concentrates all the logic required to receive data from the MZ into RAM (virtual tape). + -- Viewed from the CMT, it is the reception of data from computer onto tape. + ---------------------------------------------------------------------------------------------------------------------- + + -- Trigger, when a write occurs to ram, start a counter. Each write resets the counter. After 1 second of + -- no further writes, then the ram data is ready to play. + -- Clear funtionality allows the logic to clear the ready signal to indicate data has been processed. + -- + process( RST, IOCTL_CLK, IOCTL_TAPEHDR_WEN, IOCTL_TAPEDATA_WEN, IOCTL_CS_HDR_n, IOCTL_CS_DATA_n ) + begin + if RST = '1' then + PLAY_READY <= '0'; + PLAY_READY_CNT <= 0; + PLAY_READY_SEQ <= "00"; + RECORD_READY <= '0'; + RECORD_READY_SEQ <= "00"; + + elsif IOCTL_CLK'event and IOCTL_CLK = '1' then + + -- Sample clear signal and hold. Shift right 2 bits, msb = latest value. + PLAY_READY_SEQ(0) <= PLAY_READY_SEQ(1); + PLAY_READY_SEQ(1) <= PLAY_READY_CLR; + + -- Sample record complete signal and hold. Shift righ 2 bits, msb = latest value. + RECORD_READY_SEQ(0) <= RECORD_READY_SEQ(1); + RECORD_READY_SEQ(1) <= RECORD_READY_SET; + + -- If the external clear is triggered, reset ready signal. + if PLAY_READY_SEQ = "10" then + PLAY_READY <= '0'; + PLAY_READY_CNT <= 0; + + -- Every write to ram resets the counter. + elsif IOCTL_TAPEHDR_WEN = '1' or IOCTL_TAPEDATA_WEN = '1' then + PLAY_READY <= '0'; + PLAY_READY_CNT <= 1; + + -- 1 second timer, if no new writes have occurred to RAM, then set the ready flag. + elsif PLAY_READY_CNT >= 112000000 then + PLAY_READY_CNT <= 0; + PLAY_READY <= '1'; + end if; + + -- Set RECORD_READY if fsm determines a full tape message received. + if RECORD_READY_SEQ = "10" then + RECORD_READY <= '1'; + + -- HPS access resets signal. + elsif IOCTL_CS_HDR_n = '0' or IOCTL_CS_DATA_n = '0' then + RECORD_READY <= '0'; + + -- If the fsm resets the signal then clear the flag as it will be receiving a new tape message. + elsif RECORD_READY_SEQ = "00" then + RECORD_READY <= '0'; + end if; + + -- Increment counters if enabled. + if PLAY_READY_CNT >= 1 then + PLAY_READY_CNT <= PLAY_READY_CNT + 1; + end if; + end if; + end process; + + + -- State machine to represent the tape drive WRITE mode (MZ -> RAM) using cache memory as the tape, which is read by the HPS after data is stored. + -- + process( RST, CLKBUS(CKCPU), RECORDING ) begin + -- For reset, hold machine in reset. + if RST = '1' then + RECORD_READY_SET <= '0'; + TAPE_WRITE_STATE <= 15; + TAPE_WRITE_SEQ <= "000"; + RCV_PADDING_LOAD <= '0'; + RCV_PADDING_LEVEL<= '0'; + RCV_PADDING_CNT <= 0; + RCV_RAM_LOAD <= '0'; + RCV_RAM_TYPE <= '0'; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU) = '1' then + + -- If recording is inactive, hold state variables in reset. + if RECORDING = "00" then + RECORD_READY_SET <= '0'; + TAPE_WRITE_STATE <= 15; + TAPE_WRITE_SEQ <= "000"; + RCV_PADDING_LOAD <= '0'; + RCV_PADDING_LEVEL<= '0'; + RCV_PADDING_CNT <= 0; + RCV_RAM_LOAD <= '0'; + RCV_RAM_TYPE <= '0'; + + -- Change in recording state, start fsm to receive data from the MZ and store in the cache RAM ready for HPS upload. + elsif RECORDING = "10" then + if TAPE_WRITE_STATE = 15 then + TAPE_WRITE_STATE <= 0; + RCV_RAM_TYPE <= '0'; + end if; + + elsif RECORDING = "11" then + + -- Sample the done signal, when setup and stable, we can continue. + TAPE_WRITE_SEQ(1 downto 0)<= TAPE_WRITE_SEQ(2 downto 1); + TAPE_WRITE_SEQ(2) <= (RCV_PADDING_LOAD or RCV_RAM_LOAD) and (RCV_PADDING_DONE and RCV_RAM_DONE); + + -- If reception has just been started and acknowledged by the DONE flag being reset, reset the activation strobe. + -- + if TAPE_WRITE_SEQ = "111" then + RCV_PADDING_LOAD <= '0'; + RCV_RAM_LOAD <= '0'; + end if; + + -- If reception is in progress, run the FSM. + -- + if RCV_PADDING_LOAD = '0' and RCV_RAM_LOAD = '0' then + + -- Default is to move onto next state per clock cycle, unless modified by the state action. + TAPE_WRITE_STATE <= TAPE_WRITE_STATE + 1; + + -- Execute current state. + case TAPE_WRITE_STATE is + + -- As the Gap (Short/Long) is a continuous stream of '0' pulses, we can wait for 1000 '0' pulses then move onto the tapemark. + -- + when 0 => + RCV_PADDING_CNT <= 1000; + RCV_PADDING_LEVEL <= '0'; + RCV_PADDING_LOAD <= '1'; -- Wait for 100 '1' pulses from MZ. + when 1 => + if RCV_PADDING_DONE = '0' then + TAPE_WRITE_STATE <= 1; + end if; + -- Wait for Tapemark, 40 long/short pulses for Header, 20 long/short pulses for Data. + when 2 => + -- Header = 0, Data = 1 + if RCV_RAM_TYPE = '0' then + -- Setup to receive a Long Tape Mark. + RCV_PADDING_CNT <= 40; + RCV_PADDING_LEVEL<= '1'; + else + -- Setup to receive a Short Tape Mark. + RCV_PADDING_CNT <= 20; + RCV_PADDING_LEVEL<= '1'; + end if; + RCV_PADDING_LOAD <= '1'; + when 3 => + if RCV_PADDING_DONE = '0' then + TAPE_WRITE_STATE <= 3; + end if; + when 4 => + -- Header = 0, Data = 1 + if RCV_RAM_TYPE = '0' then + -- Setup to receive a Long Tape Mark. + RCV_PADDING_CNT <= 40; + RCV_PADDING_LEVEL<= '0'; + else + -- Setup to receive a Short Tape Mark. + RCV_PADDING_CNT <= 20; + RCV_PADDING_LEVEL<= '0'; + end if; + RCV_PADDING_LOAD <= '1'; + when 5 => + if RCV_PADDING_DONE = '0' then + TAPE_WRITE_STATE <= 5; + end if; + -- Wait for single long pulse. + when 6 => + RCV_PADDING_LEVEL <= '1'; + RCV_PADDING_CNT <= 1; + RCV_PADDING_LOAD <= '1'; + when 7 => + if RCV_PADDING_DONE = '0' then + TAPE_WRITE_STATE <= 7; + end if; + + -- Now read in the header/data (MZ writing to RAM tape). + when 8 => + RECORD_READY_SET <= '0'; + RCV_RAM_RETRIES <= '1'; + when 9 => + RCV_RAM_LOAD <= '1'; + when 10 => + if RCV_RAM_DONE = '0' then + TAPE_WRITE_STATE <= 10; + end if; + when 11 => + if RCV_RAM_SUCCESS = '0' then + -- In the event the data block read checksum fails, perform 1 retry before pausing the FSM. + if RCV_RAM_RETRIES = '1' then + RCV_RAM_RETRIES <= '0'; + TAPE_WRITE_STATE <= 9; + else + -- Nothing can be done, checksum errors shouldnt occur, so just exit. + TAPE_WRITE_STATE <= 15; + end if; + end if; + + -- Wait for single long pulse. + when 12 => + RCV_PADDING_LEVEL <= '1'; + RCV_PADDING_CNT <= 1; + RCV_PADDING_LOAD <= '1'; + when 13 => + if RCV_PADDING_DONE = '0' then + TAPE_WRITE_STATE <= 13; + end if; + + -- If we have received the header, switch to receive the data. + -- On completion, signal hps to read memory by setting status flag and start recording fsm again. + when 14 => + if RCV_RAM_TYPE = '0' then + RCV_RAM_TYPE <= '1'; + TAPE_WRITE_STATE <= 0; + else + RECORD_READY_SET <= '1'; + TAPE_WRITE_STATE <= 15; + end if; + + -- Final state, stay until reset. + when 15 => + TAPE_WRITE_STATE <= 15; + end case; + end if; + end if; + end if; + end process; + + -- Process to recieve the header/data blocks and checksum from the MZ and store it into the cache RAM. ie. MZ -> RAM. + -- The bit stream is assumed to be at the correct point and the data is serialised and loaded into the RAM. + -- + -- RCV_RAM_DONE is high when the tape header and checksum have been received. + -- + -- RCV_RAM_LOAD = = Start receiving the tape data and checksum. + -- RCV_RAM_DONE = = Tape data and checksum recieved + -- RCV_RAM_SUCCESS = = Tape data and checksum recieved, checksums match. + -- CLKBUS(CKCPU) = = Base clock for encoding/decoding of pwm pulse. + -- + process( RST, RCV_RAM_LOAD, CLKBUS(CKCPU) ) begin + if RST = '1' then + RCV_RAM_DONE <= '0'; + RCV_RAM_SUCCESS <= '0'; + RCV_RAM_ADDR <= std_logic_vector(to_unsigned(0, 16)); + RCV_RAM_COUNT <= to_unsigned(0, 16); -- Count of bytes to transmit, excludes checksum. + RCV_RAM_CHECKSUM <= std_logic_vector(to_unsigned(0, 16)); + RCV_RAM_STATE <= 0; + RCV_RAM_SEQ <= "000"; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU) = '1' then + + -- Sample load signal and hold. Shift right 3 bits, msb = latest value. + RCV_RAM_SEQ(1 downto 0) <= RCV_RAM_SEQ(2 downto 1); + RCV_RAM_SEQ(2) <= RCV_RAM_LOAD; + + -- If load is stable, acknowledge by bringing DONE low and start process. + if RCV_RAM_SEQ = "111" then + RCV_RAM_DONE <= '0'; + RCV_RAM_SUCCESS <= '0'; + + -- When RCV_RAM_LOAD is asserted and setled, sample parameters, set address and count for the given ram block and commence de-serialisation. + -- + elsif RCV_RAM_SEQ = "110" then + if RCV_RAM_TYPE = '0' then + RCV_RAM_COUNT <= to_unsigned(128, 16); + else + RCV_RAM_COUNT <= RCV_TAPE_SIZE; + end if; + RCV_RAM_ADDR <= std_logic_vector(to_unsigned(0, 16)); + HDR_RAM_WEN <= '0'; + DATA_RAM_WEN <= '0'; + RCV_RAM_CNT_CKSUM <= '1'; + RCV_RAM_CALC_CKSUM <= std_logic_vector(to_unsigned(0, 16)); + RCV_RAM_STATE <= 0; + + -- If the DONE signal is low, then run the actual process, raising DONE when complete. + elsif RCV_RAM_DONE = '0' then + + -- FSM to implement the receiption of data from MZ and storage in cache RAM> + case(RCV_RAM_STATE) is + when 0 => + when 1 => + RCV_RAM_BITCNT <= 8; + + -- Store 1 bit. + when 2 => + if RCV_AVAIL = '1' then + -- Only store the data bits, 1st bit is just padding. + if RCV_RAM_BITCNT < 8 then + if RCV_BIT = '1' then + RCV_RAM_CALC_CKSUM <= RCV_RAM_CALC_CKSUM + 1; + end if; + RCV_RAM_SR <= RCV_RAM_SR(7 downto 0) & RCV_BIT; + end if; + RCV_RAM_STATE <= 3; + end if; + when 3 => + -- At end of transmission, load the full byte into RAM and make ready for next incoming byte. + if RCV_RAM_BITCNT = 0 then + RCV_RAM_COUNT <= RCV_RAM_COUNT - 1; + RCV_RAM_STATE <= 4; + + -- For the header, extract the size of the tape data block and the load address. + -- + if RCV_RAM_TYPE = '0' then + if RCV_RAM_ADDR = 18 then + RCV_TAPE_SIZE(7 downto 0) <= unsigned(RCV_RAM_SR(7 downto 0)); + elsif RCV_RAM_ADDR = 19 then + RCV_TAPE_SIZE(15 downto 8) <= unsigned(RCV_RAM_SR(7 downto 0)); + end if; + end if; + else + RCV_RAM_BITCNT <= RCV_RAM_BITCNT - 1; + RCV_RAM_STATE <= 2; + end if; + when 4 => + if RCV_RAM_COUNT = 0 and RCV_RAM_CNT_CKSUM = '1' then + RCV_RAM_CHECKSUM(15 downto 8) <= RCV_RAM_SR(7 downto 0); + RCV_RAM_CNT_CKSUM <= '0'; + RCV_RAM_STATE <= 1; + elsif RCV_RAM_COUNT = 0 and RCV_RAM_CNT_CKSUM = '0' then + RCV_RAM_CHECKSUM(7 downto 0) <= RCV_RAM_SR(7 downto 0); + RCV_RAM_STATE <= 8; + else + RAM_DATAIN <= RCV_RAM_SR(7 downto 0); + RCV_RAM_STATE <= 5; + end if; + when 5 => + -- Assert Write to load data into RAM. + if RCV_RAM_TYPE = '0' then + HDR_RAM_WEN <= '1'; + else + DATA_RAM_WEN <= '1'; + end if; + RCV_RAM_STATE <= 6; + when 6 => + -- Deassert write. + if RCV_RAM_TYPE = '0' then + HDR_RAM_WEN <= '0'; + else + DATA_RAM_WEN <= '0'; + end if; + RCV_RAM_STATE <= 7; + when 7 => + -- Once write transaction has completed, update the RAM address. + RCV_RAM_ADDR <= RCV_RAM_ADDR + 1; + -- Receive the next byte which will be Checksum MSB. + RCV_RAM_STATE <= 1; + when 8 => + -- Compare checksums, raise SUCCESS flag if they match. + if RCV_RAM_CHECKSUM = RCV_RAM_CALC_CKSUM then + RCV_RAM_SUCCESS <= '1'; + end if; + RCV_RAM_STATE <= 9; + when 9 => + RCV_RAM_DONE <= '1'; + when others => + end case; + end if; + end if; + end process; + + -- Process to read a sequence of identical bits. This is for GAP, Tape Marks and Pulse Sequences which seperate the + -- meaningful data blocks in the tape stream. + -- + -- RCV_PADDING_LOAD = = Load the counter and level and commence counting required number of bits. + -- RCV_PADDING_LEVEL = = Level of the bit to detect, 0 = 0 (low), 1 = 1 (high). A bit received opposite to what we are detecting resets the count. + -- RCV_PADDING_CNT = = Number of bits of RCV_PADDING_LEVEL to receive. + -- CLKBUS(CKMEM) = = Base clock for encoding/decoding of pwm pulse. + -- RCV_PADDING_DONE = = Status, 0 = counting or idle, 1 = done, number of required bits received. + -- + process( RST, CLKBUS(CKMEM), RCV_PADDING_LOAD ) begin + if RST = '1' then + PADDING_CNT <= 0; + PADDING_LEVEL <= '0'; + RCV_PADDING_DONE <= '0'; + RCV_PADDING_SEQ <= "000"; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU) = '1' then + + -- Sample incoming LOAD and hold. Detect when a sample is required. + RCV_PADDING_SEQ(1 downto 00) <= RCV_PADDING_SEQ(2 downto 1); + RCV_PADDING_SEQ(2) <= RCV_PADDING_LOAD; + + -- If load is stable, acknowldge by bringing DONE low and start the process. + if RCV_PADDING_SEQ = "111" then + RCV_PADDING_DONE <= '0'; + + -- When the load signal goes high, sample the count and level and prepare for counting. + -- + elsif RCV_PADDING_SEQ = "110" then + PADDING_CNT <= RCV_PADDING_CNT; + PADDING_LEVEL <= RCV_PADDING_LEVEL; + + -- If DONE is low, we are processing. + elsif RCV_PADDING_DONE = '0' then + + -- On activation of received data available, sample bit. If sampled bit is same as level, decrement counter otherwise reset counter. + -- + if RCV_AVAIL = '1' then + if RCV_BIT = PADDING_LEVEL then + PADDING_CNT <= PADDING_CNT - 1; + else + PADDING_CNT <= RCV_PADDING_CNT; + end if; + + -- When counter reaches zero, raise the DONE flag as operation is complete. + -- + if PADDING_CNT = 0 then + RCV_PADDING_DONE <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Process to read a bit (PWM decode) from the MZ output. + -- Basically we detect when the bit rises then start counting a fixed period of time. Once the period has + -- elapsed, we sample the data and indicate it is available. + -- + -- RCV_BIT = TO TAPE = Decoded bit received from MZ. + -- RCV_AVAIL = TO TAPE = RCV_BIT = 1 received and valid. + -- READBIT = FROM MZ = Encoded bit transmitted by MZ. + -- CLKBUS(CKMEM) = = Base clock for encoding/decoding of pwm pulse. + -- + -- Machine Time uS Description N + -- MZ80KCA/700 368.00 Reading point 736 + -- Machine Time uS Description N-80K N-700 + -- MZ80KCA/700 464.00 Long Pulse Start 1856 3248 + -- 494.00 Long Pulse End 1976 3458 + -- 240.00 Short Pulse Start 960 1680 + -- 264.00 Short Pulse End 1056 1848 + -- 368.00 Reading point. 1472 2576 + -- MZ80B 333.00 Long Pulse Start 2664 + -- 334.00 Long Pulse End 2672 + -- 166.75 Short Pulse Start 1334 + -- 166.00 Short Pulse End 1328 + -- 255.00 Reading point. 2040 + -- + process( RST, CLKBUS(CKMEM), READBIT) begin + if RST = '1' then + RCV_AVAIL <= '0'; + RCV_COUNT <= 1; + RCV_BIT <= '0'; + RCV_SEQ <= "000"; + + elsif CLKBUS(CKMEM)'event and CLKBUS(CKMEM) = '1' then + + -- Sample incoming bit and hold. Detect when a valid transmission starts. + RCV_SEQ(1 downto 0) <= RCV_SEQ(2 downto 1); + RCV_SEQ(2) <= READBIT; + + -- A rising edge indicates the start of the data. We measure in from this edge the following + -- amount of time, then sample the bit as the 'read' value. + -- + if RCV_SEQ = "100" then + -- Indicate data is being sampled, when = 1 data available. + RCV_AVAIL <= '0'; + + -- Pulse periods for MZ80C type machines + if CONFIG(MZ_80C) = '1' then + RCV_COUNT <= -1472; + elsif CONFIG(MZ700) = '1' then + RCV_COUNT <= -2576; + else + RCV_COUNT <= -2040; + end if; + + elsif RCV_COUNT <= 0 then + + if RCV_AVAIL = '0' and RCV_COUNT = 0 then + RCV_BIT <= READBIT; + RCV_AVAIL <= '1'; + else + RCV_COUNT <= RCV_COUNT + 1; + end if; + + end if; + end if; + end process; + + + ---------------------------------------------------------------------------------------------------------------------- + -- Read From Tape logic (write to MZ). + -- Definitions: Read = Read from virtual tape (RAM). + -- Write = Write into virtual tape (RAM). + -- Xmit = Transmit from CMT to MZ. + -- Rcv = Receive from MZ into CMT. + -- Thus you read Read from tape and transmit to MZ, or Receive from MZ and write onto virtual tape. + -- Playing is when the CMT is reading from tape, Recording is when the CMT is writing to tape. + -- + -- This block concentrates all the logic required to deliver data from RAM (virtual tape) to the MZ. + -- Viewed from the CMT, it is the transmission of data from tape to computer. + ---------------------------------------------------------------------------------------------------------------------- + + -- State machine to represent the tape drive READ mode (RAM -> MZ) using cache memory as the tape, which is populated by the HPS. + -- + process( RST, CLKBUS(CKCPU), PLAYING ) begin + -- For reset, hold machine in reset. + if RST = '1' then + PLAY_READY_CLR <= '0'; + TAPE_READ_STATE <= 0; + TAPE_READ_SEQ <= "000"; + XMIT_PADDING_LOAD <= '0'; + XMIT_RAM_LOAD <= '0'; + XMIT_RAM_TYPE <= '0'; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU) = '1' then + + -- If not in playing mode, clear necessary signals and wait. + if PLAYING = "000" then + PLAY_READY_CLR <= '0'; + + -- If playing has been suspended, on 3rd clock determine the next state, setup and clear necessary signals. + elsif PLAYING = "001" then + XMIT_PADDING_LOAD <= '0'; + XMIT_RAM_LOAD <= '0'; + + -- If the data block was received on first attempt, MZ will stop the motor, so skip the second block. + if XMIT_RAM_TYPE = '0' and TAPE_READ_STATE > 6 and TAPE_READ_STATE < 15 then + TAPE_READ_STATE <= 14; + else + PLAY_READY_CLR <= '1'; + TAPE_READ_STATE <= 15; + end if; + + -- Change in play state, start fsm to play out the ram contents when the HPS upload has completed. + elsif PLAYING = "110" then + if TAPE_READ_STATE = 15 then + TAPE_READ_STATE <= 0; + XMIT_RAM_TYPE <= '0'; + PLAY_READY_CLR <= '0'; + end if; + + -- If playing, run the FSM. + elsif PLAYING = "111" then + + -- Sample the done signal, when setup and stable, we can continue. + TAPE_READ_SEQ(1 downto 0) <= TAPE_READ_SEQ(2 downto 1); + TAPE_READ_SEQ(2) <= (XMIT_PADDING_LOAD or XMIT_RAM_LOAD) and (XMIT_PADDING_DONE and XMIT_RAM_DONE); + + -- If a transmission has just been started and acknowledged by the DONE flag being reset, reset the activation strobe. + -- + if TAPE_READ_SEQ(0) = '1' then + XMIT_PADDING_LOAD <= '0'; + XMIT_RAM_LOAD <= '0'; + end if; + + -- If a transmission is in progress, run the FSM. + -- + if XMIT_PADDING_LOAD = '0' and XMIT_RAM_LOAD = '0' then + + -- Default is to move onto next state per clock cycle, unless modified by the state action. + TAPE_READ_STATE <= TAPE_READ_STATE + 1; + + -- Execute current state. + case TAPE_READ_STATE is + + -- Section 1 - Header + -- + when 0 => + -- Header = 0, Data = 1 + if XMIT_RAM_TYPE = '0' then + -- Setup to send a Long Gap. + if CONFIG(MZ_80C) = '1' or CONFIG(MZ700) = '1' then + XMIT_PADDING_CNT1 <= 22000; + else + XMIT_PADDING_CNT1 <= 10000; + end if; + else + if CONFIG(MZ_80C) = '1' or CONFIG(MZ700) = '1' then + XMIT_PADDING_CNT1 <= 11000; + else + XMIT_PADDING_CNT1 <= 10000; + end if; + end if; + XMIT_PADDING_LEVEL1 <= '0'; -- Short Pulses + XMIT_PADDING_CNT2 <= 0; + XMIT_PADDING_LEVEL2 <= '0'; + XMIT_PADDING_LOAD <= '1'; + + when 1 => + -- Wait for the padding transmission to complete. + if XMIT_PADDING_DONE = '0' then + TAPE_READ_STATE <= 1; + end if; + + when 2 => + -- Header = 0, Data = 1 + if XMIT_RAM_TYPE = '0' then + -- Setup to send a Long Tape Mark. + XMIT_PADDING_CNT1 <= 40; + XMIT_PADDING_CNT2 <= 40; + else + -- Setup to send a Short Tape Mark. + XMIT_PADDING_CNT1 <= 20; + XMIT_PADDING_CNT2 <= 20; + end if; + XMIT_PADDING_LEVEL1 <= '1'; -- Long Pulses + XMIT_PADDING_LEVEL2 <= '0'; -- Short Pulses + XMIT_PADDING_LOAD <= '1'; + + when 3 => + if XMIT_PADDING_DONE = '0' then + TAPE_READ_STATE <= 3; + end if; + + when 4 => + -- Setup to send a Long Pulse. + XMIT_PADDING_CNT1 <= 1; + XMIT_PADDING_LEVEL1 <= '1'; -- Long Pulse + XMIT_PADDING_CNT2 <= 0; + XMIT_PADDING_LEVEL2 <= '0'; + XMIT_PADDING_LOAD <= '1'; + + when 5 => + if XMIT_PADDING_DONE = '0' then + TAPE_READ_STATE <= 5; + end if; + + -- Send the header and checksum for header. + when 6 => + XMIT_RAM_LOAD <= '1'; -- Send First copy of header/data. + + when 7 => + if XMIT_RAM_DONE = '0' then -- If first copy successfully received, MZ will issue a motor stop. + TAPE_READ_STATE <= 7; + end if; + + when 8 => + -- Setup to send 256 short pulse padding. + XMIT_PADDING_CNT1 <= 256; + XMIT_PADDING_LEVEL1 <= '0'; + XMIT_PADDING_CNT2 <= 0; + XMIT_PADDING_LEVEL2 <= '0'; + XMIT_PADDING_LOAD <= '1'; + + when 9 => + if XMIT_PADDING_DONE = '0' then + TAPE_READ_STATE <= 9; + end if; + + -- Resend the header/data as backup copy. + when 10 => + XMIT_RAM_LOAD <= '1'; -- If required, send second copy of header/data. + + when 11 => + if XMIT_RAM_DONE = '0' then + TAPE_READ_STATE <= 11; + end if; + + when 12 => + -- Setup to send a Long Pulse. + XMIT_PADDING_CNT1 <= 1; + XMIT_PADDING_LEVEL1 <= '1'; + XMIT_PADDING_CNT2 <= 0; + XMIT_PADDING_LEVEL2 <= '0'; + XMIT_PADDING_LOAD <= '1'; + + when 13 => + if XMIT_PADDING_DONE = '0' then + TAPE_READ_STATE <= 13; + end if; + + -- Switch to data if we have just transmitted the header, else terminate the process. + when 14 => + if XMIT_RAM_TYPE = '0' then + XMIT_RAM_TYPE <= '1'; + TAPE_READ_STATE <= 0; + else + PLAY_READY_CLR <= '1'; + end if; + + -- Clear the Play Ready strobe and wait at this state until external actions reset the state. + when 15 => + PLAY_READY_CLR <= '0'; + TAPE_READ_STATE <= 15; + end case; + end if; + end if; + end if; +end process; + +-- Process to read the tape data blocks and checksum from RAM and transmit it to the MZ. +-- +-- The ram is serialised and written to the MZ. A checksum (count of 1's) is calculated and transmitted +-- immediately after the data. +-- XMIT_READ_DONE is high when the tape header and checksum transmission are complete. +-- Normally, XMIT_RAM_LOAD is asserted high and then wait until XMIT_DONE goes high, finally deassert XMIT_RAM_LOAD to low. +-- +-- XMIT_LOAD_2 = = Load signal to commence bit transmission. +-- XMIT_BIT_2 = = Input into bit transmitter of bit value to be sent. +-- XMIT_RAM_DONE = = Transmission of RAM block complete (= 1). +-- XMIT_RAM_TYPE = = 0 - Header, 1 = Data +-- XMIT_RAM_ADDR = = Address of the RAM to be transmitted. RAM can be header or data ram block +-- XMIT_RAM_COUNT = = Count of bytes to be sent, 0 = end. +-- XMIT_RAM_CHECKSUM = = Sum of number of 1's transmitted. +-- XMIT_RAM_STATE = = State machine current state. +-- CLKBUS(CKCPU) = = Base clock for encoding/decoding of pwm pulse. +-- +process( RST, CLKBUS(CKCPU), XMIT_RAM_LOAD, XMIT_RAM_TYPE ) begin + if RST = '1' then + XMIT_RAM_DONE <= '1'; -- Default state is DONE, data transmitted. Set to 0 when transmission in progress. + XMIT_LOAD_2 <= '0'; -- LOAD signal to the bit writer. 1 = start bit transmission. + -- + XMIT_BIT_2 <= '0'; -- Level of bit to transmit. + XMIT_RAM_ADDR <= std_logic_vector(to_unsigned(0, 16)); -- Address of cache memory for next byte. + XMIT_RAM_COUNT <= to_unsigned(0, 16); -- Count of bytes to transmit, excludes checksum. + XMIT_RAM_CHKSUM_CNT <= to_unsigned(0, 2); -- Count of checksum bytes to transmit. + XMIT_RAM_CHECKSUM <= std_logic_vector(to_unsigned(0, 16)); -- Calculated checksum, count of all 1's in data bytes. + XMIT_RAM_STATE <= 0; -- FSM state. + XMIT_RAM_SEQ <= "000"; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU) = '1' then + + -- Sample load signal and hold. Shift right 3 bits, msb = latest value. + XMIT_RAM_SEQ(1 downto 0) <= XMIT_RAM_SEQ(2 downto 1); + XMIT_RAM_SEQ(2) <= XMIT_RAM_LOAD; + + -- If load is stable, acknowledge by bringing DONE low and start process. + if XMIT_RAM_SEQ = "111" then + XMIT_RAM_DONE <= '0'; + + -- When XMIT_RAM_LOAD is asserted and setled, sample parameters, set address and count for the given ram block and commence serialisation. + -- + elsif XMIT_RAM_SEQ = "110" then + if XMIT_RAM_TYPE = '0' then + XMIT_RAM_COUNT <= to_unsigned(128, 16); + else + XMIT_RAM_COUNT <= XMIT_TAPE_SIZE; + end if; + XMIT_RAM_CHKSUM_CNT <= to_unsigned(1, 2); + XMIT_RAM_ADDR <= std_logic_vector(to_unsigned(0, 16)); + XMIT_RAM_CHECKSUM <= std_logic_vector(to_unsigned(0, 16)); + XMIT_RAM_STATE <= 1; + XMIT_LOAD_2 <= '0'; + + -- If the DONE signal is low, then run the actual process, raising DONE when complete. + elsif XMIT_RAM_DONE = '0' then + + -- Simple FSM to implement transmission of RAM contents according to MZ Tape Protocol. + case(XMIT_RAM_STATE) is + when 0 => + when 1 => + if XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT = 1 then + XMIT_RAM_SR <= '1' & XMIT_RAM_CHECKSUM(15 downto 8); + elsif XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT = 0 then + XMIT_RAM_SR <= '1' & XMIT_RAM_CHECKSUM(7 downto 0); + else + -- Extract the size of the tape data block and the load address if this is the header. + -- + if XMIT_RAM_TYPE = '0' then + if XMIT_RAM_ADDR = 18 then + XMIT_TAPE_SIZE(7 downto 0) <= unsigned(HDR_RAM_DATAOUT); + elsif XMIT_RAM_ADDR = 19 then + XMIT_TAPE_SIZE(15 downto 8) <= unsigned(HDR_RAM_DATAOUT); + end if; + XMIT_RAM_SR <= '1' & HDR_RAM_DATAOUT; + else + XMIT_RAM_SR <= '1' & DATA_RAM_DATAOUT; + end if; + end if; + XMIT_RAM_BITCNT <= 8; -- 9 bits to transmit, pre 1 + 8 bits of data byte. + XMIT_RAM_STATE <= 2; + when 2 => + XMIT_BIT_2 <= XMIT_RAM_SR(8); + XMIT_LOAD_2 <= '1'; + if XMIT_RAM_SR(8) = '1' and XMIT_RAM_BITCNT < 8 and XMIT_RAM_COUNT > 0 then + XMIT_RAM_CHECKSUM <= XMIT_RAM_CHECKSUM + 1; + end if; + XMIT_RAM_SR <= XMIT_RAM_SR(7 downto 0) & '0'; + XMIT_RAM_STATE <= 3; + when 3 => + -- As we are using the same clock freq, need to wait until XMIT_DONE is set to 0, indicating transmission in progress. + if XMIT_LOAD_2 = '1' and XMIT_DONE = '0' then + XMIT_LOAD_2 <= '0'; + XMIT_RAM_STATE <= 4; + end if; + when 4 => + -- Wait until the DONE signal is asserted before continuing. + if XMIT_DONE = '1' then + XMIT_RAM_STATE <= 5; + end if; + when 5 => + XMIT_BIT_2 <= '0'; -- Reset bit.. + if XMIT_RAM_BITCNT = 0 then + if XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT = 0 then + XMIT_RAM_STATE <= 6; + else + if XMIT_RAM_COUNT > 0 then + XMIT_RAM_COUNT <= XMIT_RAM_COUNT - 1; + XMIT_RAM_ADDR <= XMIT_RAM_ADDR + 1; + elsif XMIT_RAM_COUNT = 0 and XMIT_RAM_CHKSUM_CNT > 0 then + XMIT_RAM_CHKSUM_CNT <= XMIT_RAM_CHKSUM_CNT - 1; + end if; + XMIT_RAM_STATE <= 1; + end if; + else + XMIT_RAM_BITCNT <= XMIT_RAM_BITCNT - 1; + XMIT_RAM_STATE <= 2; + end if; + when others => XMIT_RAM_DONE <= '1'; + end case; + end if; + end if; +end process; + +-- Process to send padding from CMT to MZ. +-- +-- This process transmits a set of pulses to represent the Gap, Tape Mark, Short Seperator or Long pulse of an MZ tape +-- message. XMIT_PADDING_LOAD when high starts the generation, XMIT_PADDING_DONE is set high when generation completes. +-- Normally, the invoker process sets up the number of bits and level in the parameters: + +-- XMIT_PADDING_CNT1 = Internal = If > 0, then transmit this number of bits first. +-- XMIT PADDING_LEVEL1 = Internal = Level of the bit to transmit CNT1 times. +-- XMIT PADDING_CNT2 = Internal = If > 0, then tramsit this number of bits second. +-- XMIT_PADDING_LEVEL2 = Internal = Level of the bit to transmit CNT2 times. +-- +-- After completion of transmission, the Done signal is asserted high: +-- XMIT_PADDING_DONE = Internal = 0 when transmission in progress, 1 when transmission completed. +-- +-- Clocks: +-- CLKBUS(CKCPU) = Internal = Base clock for encoding/decoding of pwm pulse. +-- +process( RST, CLKBUS(CKCPU), XMIT_PADDING_LOAD ) begin + if RST = '1' then + XMIT_PADDING_DONE <= '1'; -- PADDING transmission complete signal, DONE = 1 when complete, 0 during transmit. + XMIT_LOAD_1 <= '0'; -- LOAD signal to bit transmitted, loads required bit when = 1 for 1 cycle. + PADDING_CNT1 <= 0; + PADDING_LEVEL1 <= '0'; + PADDING_CNT2 <= 0; + PADDING_LEVEL2 <= '0'; + PADDING_SEQ <= "000"; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU) = '1' then + + -- Sample load signal and hold. Shift right 3 bits, msb = latest value. + PADDING_SEQ(1 downto 0) <= PADDING_SEQ(2 downto 1); + PADDING_SEQ(2) <= XMIT_PADDING_LOAD; + + -- If LOAD active for 3 periods, bring DONE low to acknowledge LOAD signal and start processing. + -- + if PADDING_SEQ = "111" then + XMIT_PADDING_DONE <= '0'; + end if; + + -- If LOAD active for 2 periods, sample and store the provided parameters. + -- + if PADDING_SEQ = "110" then + -- Sample the parameters XMIT_PADDING_CNT1, XMIT_PADDING_CNT2, XMIT_PADDING_LEVEL1, XMIT_PADDING_LEVEL2 and + -- write out the number of Level1 @ Cnt1, Level2 @ Cnt2 bits. + PADDING_CNT1 <= XMIT_PADDING_CNT1; + PADDING_LEVEL1 <= XMIT_PADDING_LEVEL1; + PADDING_CNT2 <= XMIT_PADDING_CNT2; + PADDING_LEVEL2 <= XMIT_PADDING_LEVEL2; + XMIT_LOAD_1 <= '0'; + end if; + + -- If DONE is low, we are processing. + if XMIT_PADDING_DONE = '0' then + + -- Reset strobe when acknowledged by XMIT_DONE going low. + if XMIT_LOAD_1 = '1' and XMIT_DONE = '0' then + XMIT_LOAD_1 <= '0'; + + -- If we arent loading a padding sequence, then we are either waiting for a Done signal + -- or need to commence a new transmission. + -- + elsif XMIT_LOAD_1 = '0' then + + -- If transmission buffer empty, setup next bit to transmit. + -- + if XMIT_DONE = '1' then + + -- Set the completion flag if the counters expire or PLAYING is disabled. + --. + if PLAYING = "000" or (PADDING_CNT1 = 0 and PADDING_CNT2 = 0) then + -- Final wait for done on the last bit before setting our done flag. + XMIT_PADDING_DONE <= '1'; + + -- First, transmit the nummber of Counter 1 bits defined in Level 1. + elsif PADDING_CNT1 > 0 then + XMIT_BIT_1 <= PADDING_LEVEL1; -- Set the mux input bit according to input level, + XMIT_LOAD_1 <= '1'; -- Set the mux input to commence xmit. + PADDING_CNT1 <= PADDING_CNT1 - 1; -- Decrement counter as this bit is now being transmitted. + + -- Then transmit the number of Counter 2 bits defined in Level 2. + elsif PADDING_CNT2 > 0 then + XMIT_BIT_1 <= PADDING_LEVEL2; + XMIT_LOAD_1 <= '1'; + PADDING_CNT2 <= PADDING_CNT2 - 1; + end if; + end if; + end if; + end if; + end if; +end process; + +-- Process to write a bit (PWM encode) to the MZ input. +-- The timings are as follows with a default SCLK of 2MHz. For faster operation, MZ clock is boosted +-- and the SCLK is also boosted on a 1:1 relationship, thus the dividers are halved per boost. +-- +-- XMIT_LOAD_1 = FROM TAPE = When high, Bit available on XMIT_BIT_1 to encode and transmit to MZ. +-- XMIT_LOAD_2 = FROM TAPE = When high, Bit available on XMIT_BIT_2 to encode and transmit to MZ. +-- XMIT_DONE = TO TAPE = When high, transmission of bit complete. Resets to 0 on active XMIT_LOAD signal. +-- WRITEBIT = FROM MZ = Encoded bit tranmitted to MZ. +-- CLKBUS(CKCPU) = = Base clock for encoding/decoding of pwm pulse. +-- +-- Machine Time uS Description N-80K(CKMEM) N-80K(CKCPU) N-700(CKCPU) N-700(CKMEM) +-- MZ80KCA/700 464.00 Long Pulse Start 1856 928 1624 3248 +-- 494.00 Long Pulse End 1976 988 1729 3458 +-- 240.00 Short Pulse Start 960 480 840 1680 +-- 264.00 Short Pulse End 1056 528 924 1848 +-- 368.00 Read point. 1472 736 1288 2576 +-- MZ80B 333.00 Long Pulse Start 2664 1332 +-- 334.00 Long Pulse End 2672 1336 +-- 166.75 Short Pulse Start 1334 667 +-- 166.00 Short Pulse End 1328 664 +-- 255.00 Read point. 2040 1020 +-- +process( RST, CLKBUS(CKCPU), XMIT_LOAD_1, XMIT_LOAD_2 ) begin + -- When RESET is high, hold in reset mode. + if RST = '1' then + XMIT_DONE <= '1'; -- Completion signal, 0 when transmitting, 1 when done. + WRITEBIT <= '0'; -- Bit facing towards MZ input. + XMIT_LIMIT <= 0; -- End of pulse. + XMIT_COUNT <= 0; -- Pulse start, bit set to 1, reset to 0 on counter = 0 + XMIT_SEQ <= "000"; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then + + -- Sample load signal and hold. Shift right 3 bits, msb = latest value. + XMIT_SEQ(1 downto 0) <= XMIT_SEQ(2 downto 1); + XMIT_SEQ(2) <= XMIT_LOAD_1 or XMIT_LOAD_2; + + -- If load is stable, acknowledge by bringing DONE low and start process. + if XMIT_SEQ = "111" then + XMIT_DONE <= '0'; + WRITEBIT <= '1'; + + -- Store run values on 2nd clock cycle of LOAD being active. + elsif XMIT_SEQ = "110" then + + -- Pulse periods for MZ80C type machines + if CONFIG(MZ_KC) = '1' or CONFIG(MZ_A) = '1' then + if (XMIT_LOAD_1 = '1' and XMIT_BIT_1 = '1') or (XMIT_LOAD_2 = '1' and XMIT_BIT_2 = '1') then + XMIT_LIMIT <= 988; -- 1976; + XMIT_COUNT <= -928; -- -1856; + else + XMIT_LIMIT <= 528; -- 1056; + XMIT_COUNT <= -480; -- -960; + end if; + elsif CONFIG(MZ700) = '1' then + -- Pulse periods for MZ700 type machines + if (XMIT_LOAD_1 = '1' and XMIT_BIT_1 = '1') or (XMIT_LOAD_2 = '1' and XMIT_BIT_2 = '1') then + XMIT_LIMIT <= 1729; -- 3458; + XMIT_COUNT <= -1624; -- -3248; + else + XMIT_LIMIT <= 924; -- 1848; + XMIT_COUNT <= -840; -- -1680; + end if; + else + -- Pulse periods for MZ80B type machines + if (XMIT_LOAD_1 = '1' and XMIT_BIT_1 = '1') or (XMIT_LOAD_2 = '1' and XMIT_BIT_2 = '1') then + XMIT_LIMIT <= 1336; -- 2672; + XMIT_COUNT <= -1332; -- -2664; + else + XMIT_LIMIT <= 664; -- 1328; + XMIT_COUNT <= -667; -- -1334; + end if; + end if; + + -- On expiration of timer, signal completion. + elsif XMIT_COUNT = XMIT_LIMIT then + XMIT_DONE <= '1'; + + -- If the counter is running, format the output pulse. + elsif XMIT_COUNT /= XMIT_LIMIT then + -- At zero, we have elapsed the correct high period for the write bit, now bring it low for the remaining period. + if XMIT_COUNT = 0 then + WRITEBIT <= '0'; + end if; + XMIT_COUNT <= XMIT_COUNT + 1; + end if; + end if; +end process; + +DEBUG_STATUS_LEDS(0) <= WRITEBIT; +DEBUG_STATUS_LEDS(1) <= XMIT_DONE; +DEBUG_STATUS_LEDS(2) <= XMIT_LOAD_1; +DEBUG_STATUS_LEDS(3) <= XMIT_LOAD_2; +DEBUG_STATUS_LEDS(4) <= XMIT_PADDING_LOAD; +DEBUG_STATUS_LEDS(5) <= XMIT_PADDING_DONE; +DEBUG_STATUS_LEDS(6) <= XMIT_RAM_LOAD; +DEBUG_STATUS_LEDS(7) <= XMIT_RAM_DONE; + +DEBUG_STATUS_LEDS(8) <= PLAY_READY; +DEBUG_STATUS_LEDS(9) <= PLAY_READY_CLR; +DEBUG_STATUS_LEDS(10) <= PLAYING(2); +DEBUG_STATUS_LEDS(11) <= PLAYING(1); +DEBUG_STATUS_LEDS(12) <= PLAYING(0); +DEBUG_STATUS_LEDS(13) <= RECORDING(2); +DEBUG_STATUS_LEDS(14) <= RECORDING(1); +DEBUG_STATUS_LEDS(15) <= RECORDING(0); + +DEBUG_STATUS_LEDS(16) <= READBIT; +DEBUG_STATUS_LEDS(17) <= RCV_AVAIL; +DEBUG_STATUS_LEDS(18) <= RECORD_READY; +DEBUG_STATUS_LEDS(19) <= RCV_RAM_TYPE; +DEBUG_STATUS_LEDS(20) <= RCV_PADDING_LOAD; +DEBUG_STATUS_LEDS(21) <= RCV_PADDING_DONE; +DEBUG_STATUS_LEDS(22) <= RCV_RAM_LOAD; +DEBUG_STATUS_LEDS(23) <= RCV_RAM_DONE; +--DEBUG_STATUS_LEDS(19 downto 16) <= std_logic_vector(to_unsigned(TAPE_READ_STATE, 4)); +--DEBUG_STATUS_LEDS(22 downto 20) <= TAPE_READ_SEQ; --PADDING_SEQ; +--DEBUG_STATUS_LEDS(23 downto 19) <= XMIT_RAM_SEQ; + +end RTL; diff --git a/mz80c/mz80c.vhd b/mz80c/mz80c.vhd new file mode 100644 index 0000000..ff4a692 --- /dev/null +++ b/mz80c/mz80c.vhd @@ -0,0 +1,1073 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: mz80c.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: Sharp MZ series Personal Computer: +-- Models MZ-80K, MZ-80C, MZ-1200, MZ-80A, MZ-700, MZ-800 +-- +-- This module is the main (top level) container for the Personal MZ Computer +-- Emulation. +-- +-- The design tries to work from top-down, where components which are common +-- to the Business and Personal MZ series are at the top (ie. main memory, +-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal) +-- to the machine specific modules and components. Some components are common +-- by their nature (ie. 8255 PIO) but these are instantiated within the lower +-- tree branch as their design use is less generic. +-- +-- The tree is as follows;- +-- +-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd +-- | -> mz80c_video.vhd +-- | -> pcg.vhd +-- | -> cmt.vhd (this may move to common and be shared with mz80b) +-- | -> keymatrix.vhd (common) +-- | -> pll.v (common) +-- | -> clkgen.vhd (common) +-- | -> T80 (common) +-- | -> i8255 (common) +-- | -> i8253 (common) +-- | -> dpram.vhd (common) +-- | -> dprom.vhd (common) +-- | -> mctrl.vhd (common) +-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv +-- | +-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development) +-- +-- +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; + +entity mz80c is + PORT ( + -- Clocks + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module. + + -- Resets. + SYSTEM_RESET : in std_logic; + + -- Z80 CPU + T80_RST_n : in std_logic; + T80_CLK : in std_logic; + T80_CLKEN : out std_logic; + T80_WAIT_n : out std_logic; + T80_INT_n : out std_logic; + T80_NMI_n : out std_logic; + T80_BUSRQ_n : out std_logic; + T80_M1_n : in std_logic; + T80_MREQ_n : in std_logic; + T80_IORQ_n : in std_logic; + T80_RD_n : in std_logic; + T80_WR_n : in std_logic; + T80_RFSH_n : in std_logic; + T80_HALT_n : in std_logic; + T80_BUSAK_n : in std_logic; + T80_A16 : in std_logic_vector(15 downto 0); + T80_DI : out std_logic_vector(7 downto 0); + T80_DO : in std_logic_vector(7 downto 0); + + -- Chip selects to common resources. + CS_ROM_n : out std_logic; + CS_RAM_n : out std_logic; + + -- Audio. + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + + -- Video signals. + R : out std_logic; + G : out std_logic; + B : out std_logic; + HSYNC_n : out std_logic; + VSYNC_n : out std_logic; + HBLANK : out std_logic; + VBLANK : out std_logic; + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- I/O -- I/O down to the core. + PS2_KEY : in std_logic_vector(10 downto 0); + + -- Cassette magnetic tape signals. + CMTBUS : out std_logic_vector(CMTBUS_WIDTH); + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status. + ); +end mz80c; + +architecture rtl of mz80c is + +-- +-- Buffered output signals. +-- +signal HBLANKi : std_logic; +signal VBLANKi : std_logic; +signal BLNK_n : std_logic; +signal Ri : std_logic; +signal Gi : std_logic; +signal Bi : std_logic; +signal HSYNC_ni : std_logic; +signal VSYNC_ni : std_logic; + +-- Parent signals. +-- +signal MZ_RESET : std_logic; +signal MZ_MEMORY_SWAP : std_logic; +signal MZ_LOW_RAM_ENABLE : std_logic; +signal MZ_HIGH_RAM_ENABLE : std_logic; +signal MZ_HIGH_RAM_INHIBIT : std_logic; +signal MZ_INHIBIT_RESET : std_logic; +signal MZ_GRAM_ENABLE : std_logic; +signal i8255_PA_I : std_logic_vector(7 downto 0); +signal i8255_PA_O : std_logic_vector(7 downto 0); +signal i8255_PB_I : std_logic_vector(7 downto 0); +signal i8255_PB_O : std_logic_vector(7 downto 0); +signal i8255_PC_I : std_logic_vector(7 downto 0); +signal i8255_PC_O : std_logic_vector(7 downto 0); +-- +-- System Clocks +-- +signal MZ_RTC_CASCADE_CLK : std_logic; -- i8253 subdivision of the 31.250KHz clock creating 1s/1Hz timebase. +-- +-- Decodes, misc +-- +signal CMTBUSi : std_logic_vector(CMTBUS_WIDTH); +signal CMT_READBITi : std_logic; +signal CMT_MOTORi : std_logic; +signal CS_D_n : std_logic; +signal CS_E_n : std_logic; +signal CS_E0_n : std_logic; +signal CS_E1_n : std_logic; +signal CS_E2_n : std_logic; +signal CS_ESWP_n : std_logic; +signal CS_G_n : std_logic; +signal DO367 : std_logic_vector(7 downto 0); +signal CS_BANKSWITCH_n : std_logic; +signal CS_MZ700BS_n : std_logic; +signal CS_IO_E0_n : std_logic; +signal CS_IO_E1_n : std_logic; +signal CS_IO_E2_n : std_logic; +signal CS_IO_E3_n : std_logic; +signal CS_IO_E4_n : std_logic; +signal CS_IO_E5_n : std_logic; +signal CS_IO_E6_n : std_logic; +signal CS_IO_E8_n : std_logic; +signal CS_IO_E9_n : std_logic; +signal CS_IO_GRAM_n : std_logic; +signal CS_ROM_ni : std_logic; +signal CS_RAM_ni : std_logic; +signal VGATE_n : std_logic; -- Video Outpu Enable +signal VRAMDO : std_logic_vector(7 downto 0); +signal IOCTL_DIN_VIDEO : std_logic_vector(15 downto 0); +signal IOCTL_DIN_KEY : std_logic_vector(15 downto 0); +signal IOCTL_DIN_CMT : std_logic_vector(15 downto 0); +signal T80_IWR_n : std_logic; +signal T80_INT_ni : std_logic; +-- +-- PPI +-- +signal DOPPI : std_logic_vector(7 downto 0); +signal INTMSK : std_logic; -- EISUU/KANA LED +-- +-- PIT +-- +signal DOPIT : std_logic_vector(7 downto 0); +signal SOUND_ENABLE : std_logic; +signal SOUND_PULSE_X2 : std_logic; +signal SOUND : std_logic; +signal INTX : std_logic; +-- +-- CURSOR blink +-- +signal CURSOR_RESET : std_logic; +signal CURSOR_CLK : std_logic; +signal CURSOR_BLINK : std_logic; +signal CCOUNT : std_logic_vector(4 downto 0); +-- +-- Remote +-- +signal SNS : std_logic; +signal MTR : std_logic; +signal M_ON : std_logic; +signal SENSE0 : std_logic; +signal SWIN : std_logic_vector(3 downto 0); +-- +-- Debug +-- +signal PULSECPU : std_logic; + +-- +-- Components +-- +component i8255 + port ( + RESET : in std_logic; + CLK : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + DI : in std_logic_vector(7 downto 0); -- D7-D0 + DO : out std_logic_vector(7 downto 0); + CS_n : in std_logic; + RD_n : in std_logic; + WR_n : in std_logic; + + PA_I : in std_logic_vector(7 downto 0); + PA_O : out std_logic_vector(7 downto 0); + PA_O_OE_n : out std_logic_vector(7 downto 0); + + PB_I : in std_logic_vector(7 downto 0); + PB_O : out std_logic_vector(7 downto 0); + PB_O_OE_n : out std_logic_vector(7 downto 0); + + PC_I : in std_logic_vector(7 downto 0); + PC_O : out std_logic_vector(7 downto 0); + PC_O_OE_n : out std_logic_vector(7 downto 0) + ); +end component; + +component i8253 + Port ( + RST : in std_logic; + CLK : in std_logic; + A : in std_logic_vector(1 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CS_n : in std_logic; + WR_n : in std_logic; + RD_n : in std_logic; + CLK0 : in std_logic; + GATE0 : in std_logic; + OUT0 : out std_logic; + CLK1 : in std_logic; + GATE1 : in std_logic; + OUT1 : out std_logic; + CLK2 : in std_logic; + GATE2 : in std_logic; + OUT2 : out std_logic + ); +end component; + +component mz80c_video is + Port ( + RST_n : in std_logic; -- Reset + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Clocks + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module. + + -- CPU Signals + T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus + T80_RD_n : in std_logic; -- CPU Read Signal + T80_WR_n : in std_logic; -- CPU Write Signal + T80_MREQ_n : in std_logic; -- CPU Memory Request + T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge + T80_WAIT_n : out std_logic; -- CPU Wait Request + T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus in + T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus out + + -- Selects. + CS_D_n : in std_logic; -- VRAM Select + CS_E_n : in std_logic; -- Peripherals Select + CS_G_n : in std_logic; -- GRAM Select + CS_IO_GRAM_n : in std_logic; -- GRAM IO Select range E8 - EF + + -- Video Signals + VGATE_n : in std_logic; -- Video Output Control + HBLANK : out std_logic; -- Horizontal Blanking + VBLANK : out std_logic; -- Vertical Blanking + HSYNC_n : out std_logic; -- Horizontal Sync + VSYNC_n : out std_logic; -- Vertical Sync + ROUT : out std_logic; -- Red Output + GOUT : out std_logic; -- Green Output + BOUT : out std_logic; -- Green Output + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable to FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. + ); +end component; + +component keymatrix + Port ( + RST_n : in std_logic; + + -- i8255 + PA : in std_logic_vector(3 downto 0); + PB : out std_logic_vector(7 downto 0); + STALL : in std_logic; + + -- PS/2 Keyboard Data + PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data. + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Clock signals created by this module. + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable to FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. + ); +end component; + +component cmt + Port ( + -- HPS Bus + RST : in std_logic; + + -- Clock signals created by this module. + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Cassette magnetic tape signals. + CMTBUS : out std_logic_vector(CMTBUS_WIDTH); + CMT_READBIT : in std_logic; + CMT_MOTOR : in std_logic; + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS : out std_logic_vector(23 downto 0) -- 24 leds to display cmt internal status. + ); +end component; + +begin + + -- + -- Instantiation + -- + PPI0 : i8255 + port map ( + RESET => MZ_RESET, + CLK => CLKBUS(CKCPU), + ENA => '1', + ADDR => T80_A16(1 downto 0), + DI => T80_DO, + DO => DOPPI, + CS_n => CS_E0_n, + RD_n => T80_RD_n, + WR_n => T80_WR_n, + + PA_I => i8255_PA_O, + PA_O => i8255_PA_O, + PA_O_OE_n => open, + + PB_I => i8255_PB_I, + PB_O => open, + PB_O_OE_n => open, + + PC_I => i8255_PC_I, + PC_O => i8255_PC_O, + PC_O_OE_n => open + ); + + PIT0 : i8253 + port map ( + RST => MZ_RESET, + CLK => CLKBUS(CKCPU), + A => T80_A16(1 downto 0), + DI => T80_DO, + DO => DOPIT, + CS_n => CS_E1_n, + WR_n => T80_WR_n, + RD_n => T80_RD_n, + CLK0 => CLKBUS(CKSOUND), + GATE0 => SOUND_ENABLE, + OUT0 => SOUND_PULSE_X2, + CLK1 => CLKBUS(CKRTC), + GATE1 => '1', + OUT1 => MZ_RTC_CASCADE_CLK, + CLK2 => MZ_RTC_CASCADE_CLK, + GATE2 => '1', + OUT2 => INTX + ); + + VIDEO0 : mz80c_video + port map ( + RST_n => T80_RST_n, -- Reset + + -- Different operations modes. + CONFIG => CONFIG, + + -- Clocks + CLKBUS => CLKBUS, -- Clock signals created by clkgen module. + + -- CPU Signals + T80_A => T80_A16(13 downto 0), -- CPU Address Bus + T80_RD_n => T80_RD_n, -- CPU Read Signal + T80_WR_n => T80_WR_n, -- CPU Write Signal + T80_MREQ_n => T80_MREQ_n, -- CPU Memory Request + T80_BUSACK_n => T80_BUSAK_n, -- CPU Bus Acknowledge + T80_WAIT_n => T80_WAIT_n, -- CPU Wait Request + T80_DI => T80_DO, -- CPU Data Bus(in) + T80_DO => VRAMDO, -- CPU Data Bus(out) + + -- Selects. + CS_D_n => CS_D_n, -- VRAM Select + CS_E_n => CS_E_n, -- Peripherals Select + CS_G_n => CS_G_n, -- GRAM Select + CS_IO_GRAM_n => CS_IO_GRAM_n, -- GRAM IO Select range E8 - EF + + -- Video Signals + VGATE_n => VGATE_n, -- Video Output Control + HBLANK => HBLANKi, -- Horizontal Blanking + VBLANK => VBLANKi, -- Vertical Blanking + HSYNC_n => HSYNC_ni, -- Horizontal Sync + VSYNC_n => VSYNC_ni, -- Vertical Sync + ROUT => Ri, -- Red Output + GOUT => Gi, -- Green Output + BOUT => Bi, -- Blue Output + + -- HPS Interface + IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, + IOCTL_UPLOAD => IOCTL_UPLOAD, + IOCTL_CLK => IOCTL_CLK, -- HPS I/O Clock. + IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA. + IOCTL_RD => IOCTL_RD, -- HPS Read Enable to FPGA. + IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into. + IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA. + IOCTL_DIN => IOCTL_DIN_VIDEO -- HPS Data to be sent to HPS. + ); + + KEYS : keymatrix + port map ( + RST_n => T80_RST_n, + + -- i8255 + PA => i8255_PA_O(3 downto 0), + PB => i8255_PB_I, + STALL => i8255_PA_O(4), + + -- PS/2 Keyboard Data + PS2_KEY => PS2_KEY, -- PS2 Key data. + + -- Different operations modes. + CONFIG => CONFIG, + + -- Clock signals created by this module. + CLKBUS => CLKBUS, + + -- HPS Interface + IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA. + IOCTL_UPLOAD => IOCTL_UPLOAD, -- HPS Uploading from FPGA. + IOCTL_CLK => IOCTL_CLK, -- HPS I/O Clock. + IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA. + IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA. + IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into. + IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA. + IOCTL_DIN => IOCTL_DIN_KEY -- HPS Data to be sent to HPS. + ); + + TAPE0 : cmt + port map ( + RST => MZ_RESET, + + -- Clock signals needed by this module. + CLKBUS => CLKBUS, + + -- Different operations modes. + CONFIG => CONFIG, + + -- Cassette magnetic tape signals. + CMTBUS => CMTBUSi, -- Output is fed from CMT into MCTRL and MZ.. + CMT_READBIT => CMT_READBITi, + CMT_MOTOR => CMT_MOTORi, + + -- HPS Interface + IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA. + IOCTL_UPLOAD => IOCTL_UPLOAD, -- HPS Uploading from FPGA. + IOCTL_CLK => IOCTL_CLK, -- HPS I/O Clock. + IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA. + IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA. + IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into. + IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA. + IOCTL_DIN => IOCTL_DIN_CMT, -- HPS Data to be sent to HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS=> DEBUG_STATUS_LEDS(63 downto 40) -- 24 leds to display cmt internal status. + ); + + -- Parent signals onto local wires. + -- + T80_BUSRQ_n <= '1'; + T80_NMI_n <= '1'; + T80_CLKEN <= '1'; + MZ_RESET <= SYSTEM_RESET; + + -- + -- MZ-80A - Mask interrupt from 8253 if INTMSK low. + -- MZ-80K - Interrupt is from 8253 direct. + T80_INT_ni <= '0' when ((CONFIG(MZ_A)='1' or CONFIG(MZ700) = '1') and INTX='1' and INTMSK='1') or ((CONFIG(MZ_KC)='1' and INTX='1')) + else '1'; + T80_INT_n <= T80_INT_ni; + + -- + -- Control Signals + -- + --T80_IWR_n <= T80_IORQ_n or T80_WR_n; + + -- PIO and PIT signals. + -- + i8255_PC_I(7) <= VBLANKi; -- V-BLANK signal + i8255_PC_I(6) <= CURSOR_BLINK; -- Cursor Blink + i8255_PC_I(5) <= CMTBUSi(WRITEBIT); -- MZ in from CMT out. + i8255_PC_I(4) <= CMTBUSi(SENSE); -- CMT Read/Write status. + i8255_PC_I(3) <= CMT_MOTORi; -- Motor active status. + i8255_PC_I(2) <= INTMSK; -- Red/Green LED MZ80K, Interrupt Mask MZ80A + i8255_PC_I(1) <= CMT_READBITi; -- MZ out to CMT in + i8255_PC_I(0) <= VGATE_n; -- Video Output Enable + CMT_MOTORi <= i8255_PC_O(3); + CMT_READBITi <= i8255_PC_O(1); + CURSOR_RESET <= i8255_PA_O(7); + INTMSK <= i8255_PC_O(2); + VGATE_n <= i8255_PC_O(0); + CMTBUS <= CMTBUSi; + + -- + -- Data Bus Multiplexing, plex all the output devices onto the Z80 Data Input according to the CS. + -- + T80_DI <= DOPPI when CS_E0_n ='0' and T80_RD_n = '0' -- Read from 8255 + else + DOPIT when CS_E1_n ='0' and T80_RD_n = '0' -- Read from 8253 + else + DO367 when CS_E2_n ='0' and T80_RD_n = '0' -- Read from LS367 + else + VRAMDO when CS_D_n ='0' and T80_RD_n = '0' -- Read from VRAM + else + VRAMDO when CS_G_n ='0' and T80_RD_n = '0' -- Read from GRAM + else + (others=>'1'); + + -- HPS Bus Multiplexing for reads. + IOCTL_DIN <= IOCTL_DIN_VIDEO when IOCTL_ADDR(24 downto 16)="000000100" -- Video RAM + else + IOCTL_DIN_VIDEO when IOCTL_ADDR(24 downto 16)="000001000" -- PCG + else + IOCTL_DIN_KEY when IOCTL_ADDR(24 downto 16)="000000011" + else + IOCTL_DIN_CMT when IOCTL_ADDR(24 downto 16)="000000101" or IOCTL_ADDR(24 downto 16)="000000110" + else + "1100110010101010"; -- Test pattern. + + -- + -- Chip Select map. + -- + -- 0000 - 0FFF = CS_ROM_n : MZ80K/A/700 = Monitor ROM or RAM (MZ80A rom swap) + -- 1000 - CFFF = CS_RAM_n : MZ80K/A/700 = RAM + -- C000 - CFFF = CS_ROM_n : MZ80A = Monitor ROM (MZ80A rom swap) + -- D000 - D7FF = CS_D_n : MZ80K/A/700 = VRAM + -- D800 - DFFF = CS_D_n : MZ700 = Colour VRAM (MZ700) + -- E000 - E003 = CS_E0_n : MZ80K/A/700 = 8255 + -- E004 - E007 = CS_E1_n : MZ80K/A/700 = 8253 + -- E008 - E00B = CS_E2_n : MZ80K/A/700 = LS367 + -- E00C - E00F = CS_ESWP_n : MZ80A = Memory Swap (MZ80A) + -- E010 - E013 = CS_ESWP_n : MZ80A = Reset Memory Swap (MZ80A) + -- E014 = CS_E5_n : MZ80A/700 = Normat CRT display + -- E015 = CS_E6_n : MZ80A/700 = Reverse CRT display + -- E200 - E2FF = : MZ80A/700 = VRAM roll up/roll down. + -- E800 - EFFF = : MZ80K/A/700 = User ROM socket or DD Eprom (MZ700) + -- F000 - F7FF = : MZ80K/A/700 = Floppy Disk interface. + -- F800 - FFFF = : MZ80K/A/700 = Floppy Disk interface. + -- + -- C000 - CFFF + --CS_C_n <= '0' when ( (T80_A16(15 downto 12)="1100" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0') + -- ) + -- else '1'; + + -- D000 - DFFF + CS_D_n <= '0' when ( (T80_A16(15 downto 12)="1101" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0') + and + ( (CONFIG(MZ_KC)='1' or CONFIG(MZ_A)='1') + or + (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='0' and MZ_HIGH_RAM_INHIBIT='0') + ) + ) + else '1'; + -- E000 - EFFF + CS_E_n <= '0' when ( (T80_A16(15 downto 12)="1110" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0') + and + ( (CONFIG(MZ_KC)='1' or CONFIG(MZ_A)='1') + or + (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='0' and MZ_HIGH_RAM_INHIBIT='0') + ) + ) + else '1'; + -- Sub division E000 - E200 + CS_E0_n <= '0' when CS_E_n='0' and T80_A16(11 downto 2)="0000000000" -- 8255 + else '1'; + CS_E1_n <= '0' when CS_E_n='0' and T80_A16(11 downto 2)="0000000001" -- 8253 + else '1'; + CS_E2_n <= '0' when CS_E_n='0' and T80_A16(11 downto 2)="0000000010" -- LS367 + else '1'; + CS_ESWP_n <= '0' when CONFIG(MZ_A)='1' and CS_E_n='0' and T80_RD_n='0' and T80_A16(11 downto 5)="0000000" -- ROM/RAM Swap + else '1'; + + -- F000 - FFFF + --CS_F_n <= '0' when ( (T80_A16(15 downto 12)="1111" and T80_MREQ_n = '0' and MZ_GRAM_ENABLE = '0') + -- and + -- ( (CONFIG(MZ_KC)='1' or CONFIG(MZ_A)='1') + -- or + -- (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='0' and MZ_HIGH_RAM_INHIBIT='0') + -- ) + -- ) + -- else '1'; + + -- C000 - FFFF + CS_G_n <= '0' when MZ_GRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11" and T80_MREQ_n='0' + else '1'; + -- + CS_ROM_ni <= '0' when ( ( (T80_A16(15 downto 12)="0000") + and + ( (CONFIG(MZ_A)='1' and MZ_MEMORY_SWAP='0') -- 0000 -> 0FFF MZ80A ROM + or + (CONFIG(MZ_KC)='1') -- 0000 -> 0FFF MZ80K ROM + or + (CONFIG(MZ700)='1' and MZ_LOW_RAM_ENABLE='0') -- 0000 -> 0FFF MZ700 ROM + ) + ) + or + ( (T80_A16(15 downto 12)="1100") + and + ( (CONFIG(MZ_A)='1' and MZ_GRAM_ENABLE='0' and MZ_MEMORY_SWAP='1') -- C000 -> CFFF MZ80A ROM memory swapped. + ) + ) + or + ( T80_A16(15 downto 11) = "11101" -- E800 -> EFFF User ROM memory. + and + (CONFIG(USERROM) and CONFIG(CURRENTMACHINE)) /= "00000000" -- Active machine has the user rom enabled. + and + MZ_GRAM_ENABLE = '0' -- Graphics RAM is not enabled. + and + (MZ_HIGH_RAM_ENABLE = '0' or (MZ_HIGH_RAM_ENABLE = '1' and MZ_HIGH_RAM_INHIBIT = '1')) -- High RAM is not enabled. + ) + or + ( T80_A16(15 downto 12) = "1111" + and + (CONFIG(FDCROM) and CONFIG(CURRENTMACHINE)) /= "00000000" -- Active machine has the fdc rom enabled. + and + MZ_GRAM_ENABLE = '0' -- Graphics RAM is not enabled. + and + (MZ_HIGH_RAM_ENABLE = '0' or (MZ_HIGH_RAM_ENABLE = '1' and MZ_HIGH_RAM_INHIBIT = '1')) -- F000 -> FFFF FDC ROM memory. + ) + ) and T80_MREQ_n='0' + else '1'; + CS_ROM_n <= CS_ROM_ni; + -- + CS_RAM_ni <= '0' when ( ( (T80_A16(15 downto 12)="0000") + and + ( (CONFIG(MZ_A)='1' and MZ_MEMORY_SWAP='1') -- 0000 -> 0FFF MZ80A memory swapped. + or + (CONFIG(MZ700)='1' and MZ_LOW_RAM_ENABLE='1') -- 0000 -> 0FFF MZ700 Low Ram Enabled. + ) + ) + or + + (T80_A16(15 downto 12)="0001" or T80_A16(15 downto 12)="0010" or -- 1000 -> 2FFF + T80_A16(15 downto 12)="0011" or T80_A16(15 downto 12)="0100" or -- 3000 -> 4FFF + T80_A16(15 downto 12)="0101" or T80_A16(15 downto 12)="0110" or -- 5000 -> 6FFF + T80_A16(15 downto 12)="0111" or T80_A16(15 downto 12)="1000" or -- 7000 -> 8FFF + T80_A16(15 downto 12)="1001" or T80_A16(15 downto 12)="1010" or -- 9000 -> AFFF + T80_A16(15 downto 12)="1011") -- B000 -> BFFF + or + + ( (MZ_GRAM_ENABLE = '0') + and -- Higher memory only available when GRAM not active. + ( ( (T80_A16(15 downto 12)="1100") + and + ( (CONFIG(MZ_A)='1' and MZ_MEMORY_SWAP='0') -- C000 -> CFFF MZ80A memory not swapped. + or + (CONFIG(MZ_KC)='1') -- C000 -> CFFF MZ80K + or + (CONFIG(MZ700)='1') -- C000 -> CFFF MZ700 + ) + ) + or + ( (CONFIG(MZ700)='1' and MZ_HIGH_RAM_ENABLE='1' and MZ_HIGH_RAM_INHIBIT='0') -- D000 -> FFFF MZ700 Ram Enabled. + and + ( (T80_A16(15 downto 12)="1101" or T80_A16(15 downto 12)="1110" + or + T80_A16(15 downto 12)="1111") + ) + ) + ) + ) + ) + and T80_MREQ_n='0' + else '1'; + CS_RAM_n <= CS_RAM_ni; + + -- + -- IO Select Map. + -- E0 - E6 are used by the MZ700 to perform memory bank switching. + -- E8 - EF are Graphics enhancements. + -- E8 switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions. + -- E9 switches out the graphics ram and returns to previous state. + -- EA, sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). + -- EB, sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte). + -- EC, sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte). + -- ED, sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte). + -- + CS_BANKSWITCH_n <= '0' when T80_IORQ_n='0' and T80_WR_n = '0' and T80_A16(7 downto 4) = "1110" + else '1'; + CS_MZ700BS_n <= '0' when CONFIG(MZ700)='1' and CS_BANKSWITCH_n = '0' and T80_A16(3) = '0' + else '1'; + CS_IO_GRAM_n <= '0' when CS_BANKSWITCH_n = '0' and T80_A16(3) = '1' -- IO E8-EF Graphics framebuffer. + else '1'; + CS_IO_E0_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "000" -- IO E0 = 0000 -> 0FFF RAM, D000 -> FFFF No Action + else '1'; + CS_IO_E1_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "001" -- IO E1 = 0000 -> 0FFF No Action, D000 -> FFFF RAM + else '1'; + CS_IO_E2_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "010" -- IO E2 = 0000 -> 0FFF ROM, D000 -> FFFF No Action + else '1'; + CS_IO_E3_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "011" -- IO E3 = 0000 -> 0FFF No Action, D000 -> FFFF VRAM + IO Ports + else '1'; + CS_IO_E4_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "100" -- IO E4 = 0000 -> 0FFF ROM, D000 -> FFFF VRAM + IO Ports + else '1'; + CS_IO_E5_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "101" -- IO E5 = 0000 -> 0FFF No Action, D000 -> FFFF Inhibit + else '1'; + CS_IO_E6_n <= '0' when CS_MZ700BS_n = '0' and T80_A16(2 downto 0) = "110" -- IO E6 = 0000 -> 0FFF No Action, D000 -> FFFF Unlock Inhibit + else '1'; + CS_IO_E8_n <= '0' when CS_IO_GRAM_n = '0' and T80_A16(2 downto 0) = "000" -- IO E8 = C000 -> FFFF map to Graphics RAM. + else '1'; + CS_IO_E9_n <= '0' when CS_IO_GRAM_n = '0' and T80_A16(2 downto 0) = "001" -- IO E9 = C000 -> FFFF revert to previous mode. + else '1'; + + -- MZ80A/1200 Memory Swap - swap rom out and ram in. + -- + process( MZ_RESET, CS_ESWP_n ) begin + if(MZ_RESET = '1') then + MZ_MEMORY_SWAP <= '0'; + elsif(CS_ESWP_n'event and CS_ESWP_n='0') then + if(T80_A16(4 downto 2) = "011") then + MZ_MEMORY_SWAP <= '1'; + elsif(T80_A16(4 downto 2) = "100") then + MZ_MEMORY_SWAP <= '0'; + end if; + end if; + end process; + + -- MZ700 - Latch wether to enable RAM or ROM at 0000->0FFF. + -- + process( MZ_RESET, CLKBUS(CKCPU), CS_IO_E0_n, CS_IO_E2_n, CS_IO_E4_n ) begin + if(MZ_RESET = '1') then + MZ_LOW_RAM_ENABLE <= '0'; + + elsif(CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1') then + + if(CS_IO_E0_n = '0') then + MZ_LOW_RAM_ENABLE <= '1'; + + elsif(CS_IO_E2_n = '0') then + MZ_LOW_RAM_ENABLE <= '0'; + + elsif(CS_IO_E4_n = '0') then + MZ_LOW_RAM_ENABLE <= '0'; + end if; + end if; + end process; + + -- MZ700 - Latch wether to enable I/O or RAM at D000->FFFF. + -- + process( MZ_RESET, CLKBUS(CKCPU), CS_IO_E1_n, CS_IO_E3_n, CS_IO_E4_n, MZ_HIGH_RAM_INHIBIT ) begin + if(MZ_RESET = '1') then + MZ_HIGH_RAM_ENABLE <= '0'; + MZ_INHIBIT_RESET <= '0'; + + elsif(CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1') then + + if(CS_IO_E1_n = '0' and MZ_HIGH_RAM_INHIBIT = '0') then + MZ_HIGH_RAM_ENABLE <= '1'; + + elsif(CS_IO_E3_n = '0' and MZ_HIGH_RAM_INHIBIT = '0') then + MZ_HIGH_RAM_ENABLE <= '0'; + + elsif(CS_IO_E4_n = '0') then + MZ_HIGH_RAM_ENABLE <= '0'; + MZ_INHIBIT_RESET <= '1'; + + elsif(MZ_HIGH_RAM_INHIBIT = '0' and MZ_INHIBIT_RESET = '1') then + MZ_INHIBIT_RESET <= '0'; + end if; + end if; + end process; + + -- MZ700 - Latch wether to inhibit all functionality at D000->FFFF. + -- + process( MZ_RESET, CLKBUS(CKCPU), CS_IO_E5_n, CS_IO_E6_n, MZ_INHIBIT_RESET ) begin + if(MZ_RESET = '1') then + MZ_HIGH_RAM_INHIBIT <= '0'; + + elsif(CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1') then + + if(CS_IO_E5_n = '0') then + MZ_HIGH_RAM_INHIBIT <= '1'; + + elsif(CS_IO_E6_n = '0' or MZ_INHIBIT_RESET = '1') then + MZ_HIGH_RAM_INHIBIT <= '0'; + end if; + end if; + end process; + + -- Graphics Ram - Latch wether to enable Graphics RAM page from C000 - FFFF. + -- + process( MZ_RESET, CLKBUS(CKCPU), CS_IO_E8_n, CS_IO_E9_n ) begin + if(MZ_RESET = '1') then + MZ_GRAM_ENABLE <= '0'; + + elsif(CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1') then + + if(CS_IO_E8_n = '0') then + MZ_GRAM_ENABLE <= '1'; + + elsif(CS_IO_E9_n = '0') then + MZ_GRAM_ENABLE <= '0'; + + end if; + end if; + end process; + + -- + -- Cursor Base Clock + -- + process( CLKBUS(CKPERIPH), T80_RST_n ) + variable TCOUNT : std_logic_vector(15 downto 0); + begin + if T80_RST_n = '0' then + TCOUNT := (others=>'0'); + + elsif CLKBUS(CKPERIPH)'event and CLKBUS(CKPERIPH)='1' then + if( TCOUNT = 18371 ) then + TCOUNT := (others=>'0'); + CURSOR_CLK <= not CURSOR_CLK; + else + TCOUNT := TCOUNT + '1'; + end if; + end if; + end process; + + -- + -- Cursor blink Clock + -- + process( CURSOR_CLK, CURSOR_RESET ) begin + if( CURSOR_RESET='0' ) then + CCOUNT <= (others => '0'); + elsif( CURSOR_CLK'event and CURSOR_CLK = '1' ) then + if( CCOUNT = 18 ) then + CCOUNT <=(others=>'0'); + CURSOR_BLINK <= not CURSOR_BLINK; + else + CCOUNT <= CCOUNT+'1'; + end if; + end if; + end process; + + -- + -- Sound gate control + -- + process( CLKBUS(CKPERIPH), T80_WR_n, CS_E2_n, T80_RST_n ) begin + if( T80_RST_n = '0' ) then + SOUND_ENABLE <= '0'; + + elsif( CLKBUS(CKPERIPH)'event and CLKBUS(CKPERIPH) = '1' and T80_WR_n = '0' and CS_E2_n = '0' ) then + SOUND_ENABLE <= T80_DO(0); + end if; + end process; + + -- Audio output. Choose between generated sound and CMT pulse audio. + -- + AUDIO_L <= SOUND when CONFIG(AUDIOSRC) = '0' -- Sound Output Left + else + CMTBUSi(WRITEBIT); + AUDIO_R <= SOUND when CONFIG(AUDIOSRC) = '0' -- Sound Output Right + else + CMTBUSi(READBIT); + + -- The signal coming out of the 8253 is not a square wave and twice the frequency. The addition of a flip-flop to divide the + -- frequency by 2 results in a square wave of the correct audio frequency. + process( SOUND_PULSE_X2 ) begin + if( SOUND_PULSE_X2'event and SOUND_PULSE_X2 = '1' ) then + SOUND <= not SOUND; + end if; + end process; + + -- MZ80 BLNK signal, enabled by VGATE being active and HBLANKi pulsing. If HBLANKi stops pulsing for more + -- than 32ms, then BLNK goes inactive. + -- + process( CLKBUS(CKPERIPH), T80_RST_n ) + variable TCOUNT : std_logic_vector(6 downto 0); + variable HBLANKLAST : std_logic; + begin + if T80_RST_n = '0' then + BLNK_n <= '1'; + TCOUNT := (others=>'0'); + + elsif CLKBUS(CKPERIPH)'event and CLKBUS(CKPERIPH)='1' then + -- If HBLANKi goes active the first time or is retriggered, reset counter and set BLANKING active. + if (HBLANKi = '1' and TCOUNT = 0) or (HBLANKi = '1' and HBLANKLAST = '0') then + TCOUNT := "0000001"; + BLNK_n <= '0'; + + -- If not retriggered and we get to the end of the count (32ms) then turn off the BLANKING signal. + elsif TCOUNT = 63 then + TCOUNT := (others=>'0'); + BLNK_n <= '1'; + else + TCOUNT := TCOUNT + '1'; + end if; + + -- Remember last state so we can retrigger. + HBLANKLAST := HBLANKi; + end if; + end process; + + -- Try state register read, LS124 in MZ80A, LS367 in MZZ700. On MZ700 this register also inputs the + -- Joystick readings, yet to be implemented. + -- + DO367(0) <= CURSOR_CLK; + DO367(7) <= not HBLANKi when CONFIG(MZ700) = '1' + else + '1' when CONFIG(MZ_A) = '1' and (BLNK_n = '0' and VGATE_n = '0') + else '1'; + DO367(6 downto 1) <= (others=>'1'); + + -- Video Output. + -- + HSYNC_n <= HSYNC_ni; + VSYNC_n <= VSYNC_ni; + R <= Ri; + G <= Gi; + B <= Bi; + VBLANK <= VBLANKi; + HBLANK <= HBLANKi; + + -- A simple 1*cpufreq second pulse to indicate accuracy of CPU frequency for debug purposes.. + -- + process (SYSTEM_RESET, CLKBUS(CKCPU)) + variable cnt : integer range 0 to 1999999 := 0; + begin + if SYSTEM_RESET = '1' then + PULSECPU <= '0'; + cnt := 0; + elsif rising_edge(CLKBUS(CKCPU)) then + cnt := cnt + 1; + if cnt = 0 then + PULSECPU <= not PULSECPU; + end if; + end if; + end process; + + -- Debug leds. + -- + DEBUG_STATUS_LEDS(0) <= CS_D_n; + DEBUG_STATUS_LEDS(1) <= CS_E_n; + DEBUG_STATUS_LEDS(2) <= CS_E0_n; + DEBUG_STATUS_LEDS(3) <= CS_E1_n; + DEBUG_STATUS_LEDS(4) <= CS_E2_n; + DEBUG_STATUS_LEDS(5) <= CS_ESWP_n; + DEBUG_STATUS_LEDS(6) <= CS_ROM_ni; + DEBUG_STATUS_LEDS(7) <= CS_RAM_ni; + -- + DEBUG_STATUS_LEDS(8) <= CS_BANKSWITCH_n; + DEBUG_STATUS_LEDS(9) <= CS_IO_E0_n; + DEBUG_STATUS_LEDS(10) <= CS_IO_E1_n; + DEBUG_STATUS_LEDS(11) <= CS_IO_E2_n; + DEBUG_STATUS_LEDS(12) <= CS_IO_E3_n; + DEBUG_STATUS_LEDS(13) <= CS_IO_E4_n; + DEBUG_STATUS_LEDS(14) <= CS_IO_E5_n; + DEBUG_STATUS_LEDS(15) <= CS_IO_E6_n; + -- + DEBUG_STATUS_LEDS(16) <= CS_IO_E8_n; + DEBUG_STATUS_LEDS(17) <= CS_IO_E9_n; + DEBUG_STATUS_LEDS(18) <= CS_IO_GRAM_n; + DEBUG_STATUS_LEDS(19) <= CS_G_n; + DEBUG_STATUS_LEDS(20) <= MZ_GRAM_ENABLE; + DEBUG_STATUS_LEDS(21) <= '0'; + DEBUG_STATUS_LEDS(22) <= '0'; + DEBUG_STATUS_LEDS(23) <= '0'; + -- + DEBUG_STATUS_LEDS(24) <= PULSECPU; + DEBUG_STATUS_LEDS(25) <= T80_INT_ni; + DEBUG_STATUS_LEDS(26) <= INTMSK; + DEBUG_STATUS_LEDS(27) <= MZ_MEMORY_SWAP; + DEBUG_STATUS_LEDS(28) <= MZ_LOW_RAM_ENABLE; + DEBUG_STATUS_LEDS(29) <= MZ_HIGH_RAM_ENABLE; + DEBUG_STATUS_LEDS(30) <= MZ_HIGH_RAM_INHIBIT; + DEBUG_STATUS_LEDS(31) <= MZ_INHIBIT_RESET; + -- + DEBUG_STATUS_LEDS(32) <= '0'; + DEBUG_STATUS_LEDS(33) <= '0'; + DEBUG_STATUS_LEDS(34) <= '0'; + DEBUG_STATUS_LEDS(35) <= '0'; + DEBUG_STATUS_LEDS(36) <= CURSOR_BLINK; + DEBUG_STATUS_LEDS(37) <= SOUND_ENABLE; + DEBUG_STATUS_LEDS(38) <= MZ_RTC_CASCADE_CLK; + DEBUG_STATUS_LEDS(39) <= PULSECPU; + -- + -- LEDS 40 .. 63 are provided by the CMT unit. + -- + -- LEDS 64 .. 112 are available. + DEBUG_STATUS_LEDS(111 downto 64) <= (others => '0'); +end rtl; diff --git a/mz80c/mz80c_video.vhd b/mz80c/mz80c_video.vhd new file mode 100644 index 0000000..e43cc56 --- /dev/null +++ b/mz80c/mz80c_video.vhd @@ -0,0 +1,1459 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: mz80c_video.vhd +-- Created: July 2018 +-- Author(s): Philip Smart +-- Description: Sharp MZ series Video logic. +-- This module fully emulates the Sharp MZ Personal Computer series video display +-- logic plus extensions. +-- The display is capable of performing 40x25, 80x25 Mono/Colour display along with +-- a Programmable Character Generator and a bit mapped 320x200/640x200 framebuffer. +-- The design is slightly different to the original Sharps in that I use a dual +-- buffer technique, ie. the original 1K/2K VRAM + ARAM and a pixel mapped displaybuffer. +-- During Vertical blanking, the VRAM+ARAM is copied and expanded into the display +-- buffer which is then displayed during the next display window. Part of the reasoning +-- was to cut down on snow/tearing on the older K/C models (but still provide the +-- blanking signals so any original software works) and also allow the option of +-- disabling the MZ80A/700 wait states. +-- As an addition, I added a graphics framebuffer (320x200, 640x200 8 colours) +-- the interface to which is, at the moment, non-standard, but as I get more details +-- on add on cards, I can add mapping layers so this graphics framebuffer can be used +-- by customised software. Pixels drawn in the graphics framebuffer can be blended into +-- the main display buffer via programmable logic mode (ie. XOR, OR etc). +-- A lot of timing information can be found in the docs/SharpMZ_Notes.xlsx spreadsheet, +-- but the main info is: +-- MZ80K/C/1200/A (Monochrome) +-- Signal Start End Period Comment +-- 64uS 15.625KHz +-- HDISPEN 0 320 40uS +-- HBLANK 318 510 24uS +-- BLNK 318 486 21uS +-- HSYNC 393 438 5.625uS +-- +-- 16.64mS 60.10Hz +-- VDISPEN 0 200 12.8mS +-- VSYNC 219 223 256uS +-- VBLANK 201 259 3.712mS not VDISPEN +-- +-- MZ700 (Colour) +-- Signal Start End Period Comment +-- 64.056uS 15.611KHz +-- HDISPEN 0 320 36.088uS +-- HBLANK 320 567 27.968uS +-- BLNK 320 548 25.7126uS +-- HSYNC 400 440 4.567375uS +-- +-- 16.654mS 50.0374Hz +-- VDISPEN 0 200 12.8112mS +-- VSYNC 212 215 0.19216ms +-- VBLANK 201 311 7.1738mS not VDISPEN +-- +-- Copyright: (c) 2018 Philip Smart +-- +-- History: July 2018 - Initial module written. +-- August 2018 - Main portions written, including the display buffer. +-- September 2018 - Added the graphics framebuffer. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; + +entity mz80c_video is + Port ( + RST_n : in std_logic; -- Reset + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Clocks + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module. + + -- CPU Signals + T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus + T80_RD_n : in std_logic; -- CPU Read Signal + T80_WR_n : in std_logic; -- CPU Write Signal + T80_MREQ_n : in std_logic; -- CPU Memory Request + T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge + T80_WAIT_n : out std_logic; -- CPU Wait Request + T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus in + T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus out + + -- Selects. + CS_D_n : in std_logic; -- VRAM Select + CS_E_n : in std_logic; -- Peripherals Select + CS_G_n : in std_logic; -- GRAM Select + CS_IO_GRAM_n : in std_logic; -- GRAM IO Select range E8 - EF + + -- Video Signals + VGATE_n : in std_logic; -- Video Output Control + HBLANK : out std_logic; -- Horizontal Blanking + VBLANK : out std_logic; -- Vertical Blanking + HSYNC_n : out std_logic; -- Horizontal Sync + VSYNC_n : out std_logic; -- Vertical Sync + ROUT : out std_logic; -- Red Output + GOUT : out std_logic; -- Green Output + BOUT : out std_logic; -- Green Output + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock.. + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. + ); +end mz80c_video; + +architecture RTL of mz80c_video is + +-- +-- Registers +-- +signal MAX_COLUMN : integer range 0 to 80; +signal MAX_ROW : integer range 0 to 25; +signal MAX_SUBROW : integer range 0 to 8; +signal FB_ADDR : std_logic_vector(13 downto 0); -- Frame buffer actual address +signal OFFSET_ADDR : std_logic_vector(7 downto 0); -- Display Offset - for MZ1200/80A machines with 2K VRAM +signal SR_G_DATA : std_logic_vector(7 downto 0); -- Shift Register to Display Green +signal SR_R_DATA : std_logic_vector(7 downto 0); -- Shift Register to Display Red +signal SR_B_DATA : std_logic_vector(7 downto 0); -- Shift Register to Display Blue +signal DISPLAY_DATA : std_logic_vector(23 downto 0); +signal XFER_ADDR : std_logic_vector(10 downto 0); +signal XFER_SUB_ADDR : std_logic_vector(2 downto 0); +signal XFER_VRAM_DATA : std_logic_vector(15 downto 0); +signal XFER_GRAM_DATA : std_logic_vector(23 downto 0); +signal XFER_MAPPED_DATA : std_logic_vector(23 downto 0); +signal XFER_WEN : std_logic; +signal XFER_VRAM_ADDR : std_logic_vector(10 downto 0); +signal XFER_DST_ADDR : std_logic_vector(13 downto 0); +signal XFER_CGROM_ADDR : std_logic_vector(11 downto 0); +signal CGROM_DATA : std_logic_vector(7 downto 0); -- Font Data To Display +signal DISPLAY_INVERT : std_logic; -- Invert display Mode of MZ80A/1200 + +-- +-- CPU/Video Access +-- +signal VRAM_VIDEO_DATA : std_logic_vector(7 downto 0); -- Display data output to CPU. +signal VRAM_ADDR : std_logic_vector(11 downto 0); -- VRAM Address. +signal VRAM_DATA_IN : std_logic_vector(7 downto 0); -- VRAM Data in. +signal VRAM_DATA_OUT : std_logic_vector(7 downto 0); -- VRAM Data out. +signal VRAM_WEN : std_logic; -- VRAM Write enable signal. +signal VRAM_CLK : std_logic; -- Clock used to access the VRAM (CKMEM or IOCTL_CLK). +signal GRAM_VIDEO_DATA : std_logic_vector(7 downto 0); -- Graphics display data output to CPU. +signal GRAM_ADDR : std_logic_vector(13 downto 0); -- Graphics RAM Address. +signal GRAM_DATA_IN_R : std_logic_vector(7 downto 0); -- Graphics Red RAM Data. +signal GRAM_DATA_IN_G : std_logic_vector(7 downto 0); -- Graphics Green RAM Data. +signal GRAM_DATA_IN_B : std_logic_vector(7 downto 0); -- Graphics Blue RAM Data. +signal GRAM_DATA_OUT_R : std_logic_vector(7 downto 0); -- Graphics Red RAM Data out. +signal GRAM_DATA_OUT_G : std_logic_vector(7 downto 0); -- Graphics Green RAM Data out. +signal GRAM_DATA_OUT_B : std_logic_vector(7 downto 0); -- Graphics Blue RAM Data out. +signal GRAM_WEN_R : std_logic; -- Graphics Red RAM Write enable signal. +signal GRAM_WEN_G : std_logic; -- Graphics Green RAM Write enable signal. +signal GRAM_WEN_B : std_logic; -- Graphics Blue RAM Write enable signal. +signal GRAM_CLK : std_logic; -- Clock used to access the GRAM (CKMEM or IOCTL_CLK). +signal GRAM_MODE : std_logic_vector(7 downto 0); -- Programmable mode register to control GRAM operations. +signal GRAM_RED_WRITER : std_logic_vector(7 downto 0); -- Red pixel writer filter. +signal GRAM_GREEN_WRITER : std_logic_vector(7 downto 0); -- Green pixel writer filter. +signal GRAM_BLUE_WRITER : std_logic_vector(7 downto 0); -- Blue pixel writer filter. +signal T80_MA : std_logic_vector(11 downto 0); -- CPU Address Masked according to machine model. +signal CS_INVERT_n : std_logic; -- Chip Select to enable Inverse mode. +signal CS_SCROLL_n : std_logic; -- Chip Select to perform a hardware scroll. +signal CS_IO_EA_n : std_logic; -- Chip Select to write to the Graphics mode register. +signal CS_IO_EB_n : std_logic; -- Chip Select to write to the Red pixel per byte indirect write register. +signal CS_IO_EC_n : std_logic; -- Chip Select to write to the Green pixel per byte indirect write register. +signal CS_IO_ED_n : std_logic; -- Chip Select to write to the Blue pixel per byte indirect write register. +signal CS_PCG_n : std_logic; +signal WAITi_n : std_logic; -- Wait +signal WAITii_n : std_logic; -- Wait(delayed) +signal VWEN : std_logic; -- Write enable to VRAM. +signal GWEN_R : std_logic; -- Write enable to Red GRAM. +signal GWEN_G : std_logic; -- Write enable to Green GRAM. +signal GWEN_B : std_logic; -- Write enable to Blue GRAM. +-- +-- Internal Signals +-- +signal H_COUNT : unsigned(10 downto 0); -- Horizontal pixel counter +signal H_BLANKi : std_logic; -- Horizontal Blanking +signal H_SYNC_ni : std_logic; -- Horizontal Blanking +signal H_DISPLAY_START : integer range 0 to 2047; +signal H_DISPLAY_END : integer range 0 to 2047; +signal H_BLNK_START : integer range 0 to 2047; +signal H_BLNK_END : integer range 0 to 2047; +signal H_SYNC_START : integer range 0 to 2047; +signal H_SYNC_END : integer range 0 to 2047; +signal H_LINE_END : integer range 0 to 2047; +signal V_COUNT : unsigned(10 downto 0); -- Vertical pixel counter +signal V_BLANKi : std_logic; -- Vertical Blanking +signal V_SYNC_ni : std_logic; -- Horizontal Blanking +signal V_DISPLAY_START : integer range 0 to 2047; +signal V_DISPLAY_END : integer range 0 to 2047; +signal V_SYNC_START : integer range 0 to 2047; +signal V_SYNC_END : integer range 0 to 2047; +signal V_LINE_END : integer range 0 to 2047; +signal BLNK : std_logic; -- Horizontal Blanking CPU Wait interval +signal BLNK_MEMACCESS : std_logic; -- Horizontal Blanking Memory Access +-- +-- CG-ROM +-- +signal CGROM_DO : std_logic_vector(7 downto 0); +signal CGROM_BANK : std_logic_vector(3 downto 0); +-- +-- PCG +-- +signal CGRAM_DO : std_logic_vector(7 downto 0); +signal CG_ADDR : std_logic_vector(11 downto 0); +signal CGRAM_ADDR : std_logic_vector(11 downto 0); +signal PCG_DATA : std_logic_vector(7 downto 0); +signal CGRAM_DI : std_logic_vector(7 downto 0); +signal CGRAM_WE_n : std_logic; +signal CGRAM_WEN : std_logic; +signal CGRAM_SEL : std_logic; +-- +-- HPS Control. +-- +signal IOCTL_CS_VRAM_n : std_logic; -- Chip Select to allow the HPS to access the VRAM. +signal IOCTL_CS_GRAM_n : std_logic; -- Chip Select to allow the HPS to access the GRAM. +signal IOCTL_WEN_VRAM : std_logic; -- Write Enable to allow the HPS to write to VRAM. +signal IOCTL_WEN_GRAM_R : std_logic; -- Write Enable to allow the HPS to write to the Red GRAM. +signal IOCTL_WEN_GRAM_G : std_logic; -- Write Enable to allow the HPS to write to the Green GRAM. +signal IOCTL_WEN_GRAM_B : std_logic; -- Write Enable to allow the HPS to write to the Blue GRAM. +signal IOCTL_DIN_VRAM : std_logic_vector(7 downto 0); +signal IOCTL_DIN_GRAM : std_logic_vector(7 downto 0); +signal IOCTL_DIN_PCG : std_logic_vector(15 downto 0); +signal IOCTL_CS_CGROM_n : std_logic; +signal IOCTL_CS_CGRAM_n : std_logic; +signal IOCTL_WEN_CGROM : std_logic; +signal IOCTL_WEN_CGRAM : std_logic; +signal IOCTL_DIN_CGROM : std_logic_vector(7 downto 0); +signal IOCTL_DIN_CGRAM : std_logic_vector(7 downto 0); + +-- +-- Components +-- +component dpram + generic ( + init_file : string; + widthad_a : natural; + width_a : natural; + widthad_b : natural; + width_b : natural; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + Port ( + clock_a : in std_logic ; + clocken_a : in std_logic := '1'; + address_a : in std_logic_vector (widthad_a-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + wren_a : in std_logic; + q_a : out std_logic_vector (width_a-1 downto 0); + + clock_b : in std_logic ; + clocken_b : in std_logic := '1'; + address_b : in std_logic_vector (widthad_b-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0); + wren_b : in std_logic; + q_b : out std_logic_vector (width_b-1 downto 0) + ); +end component; + +begin + + -- + -- Instantiation + -- + + -- Video memory as seen by the MZ Series. This is a 1K or 2K or 2K + 2K Attribute RAM + -- organised as 4K x 8 on the CPU side and 2K x 16 on the display side, top bits are not used for MZ80K/C/1200/A. + -- + VRAM0 : dpram + GENERIC MAP ( + init_file => null, + widthad_a => 12, + width_a => 8, + widthad_b => 11, + width_b => 16, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => VRAM_CLK, + clocken_a => '1', + address_a => VRAM_ADDR, + data_a => VRAM_DATA_IN, + wren_a => VRAM_WEN, + q_a => VRAM_DATA_OUT, + + -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE). + clock_b => CLKBUS(CKSYS), + clocken_b => '1', + address_b => XFER_VRAM_ADDR, + data_b => (others => '0'), + wren_b => '0', + q_b => XFER_VRAM_DATA + ); + + -- Graphics frame buffer memory. This is an enhancement and allows for 320x200 or 640x200 pixel display in 8 colours. It matches + -- the output frame buffer in size, so the contents are blended by a programmable logical operator (ie. OR) with the expanded Video + -- Ram contents to create the output display. + -- + GRAMG : dpram -- GREEN + GENERIC MAP ( + init_file => null, + widthad_a => 14, + width_a => 8, + widthad_b => 14, + width_b => 8, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => GRAM_CLK, + clocken_a => '1', + address_a => GRAM_ADDR, + data_a => GRAM_DATA_IN_G, + wren_a => GRAM_WEN_G, + q_a => GRAM_DATA_OUT_G, + + -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE). + clock_b => CLKBUS(CKSYS), + clocken_b => '1', + address_b => XFER_DST_ADDR, -- FB Destination address is used as GRAM is on a 1:1 mapping with FB. + data_b => (others => '0'), + wren_b => '0', + q_b => XFER_GRAM_DATA(7 downto 0) + ); + -- + GRAMR : dpram -- RED + GENERIC MAP ( + init_file => null, + widthad_a => 14, + width_a => 8, + widthad_b => 14, + width_b => 8, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => GRAM_CLK, + clocken_a => '1', + address_a => GRAM_ADDR, + data_a => GRAM_DATA_IN_R, + wren_a => GRAM_WEN_R, + q_a => GRAM_DATA_OUT_R, + + -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE). + clock_b => CLKBUS(CKSYS), + clocken_b => '1', + address_b => XFER_DST_ADDR, -- FB Destination address is used as GRAM is on a 1:1 mapping with FB. + data_b => (others => '0'), + wren_b => '0', + q_b => XFER_GRAM_DATA(15 downto 8) + ); + -- + GRAMB : dpram -- BLUE + GENERIC MAP ( + init_file => null, + widthad_a => 14, + width_a => 8, + widthad_b => 14, + width_b => 8, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => GRAM_CLK, + clocken_a => '1', + address_a => GRAM_ADDR, + data_a => GRAM_DATA_IN_B, + wren_a => GRAM_WEN_B, + q_a => GRAM_DATA_OUT_B, + + -- Port B used for VRAM -> DISPLAY BUFFER transfer (SOURCE). + clock_b => CLKBUS(CKSYS), + clocken_b => '1', + address_b => XFER_DST_ADDR, -- FB Destination address is used as GRAM is on a 1:1 mapping with FB. + data_b => (others => '0'), + wren_b => '0', + q_b => XFER_GRAM_DATA(23 downto 16) + ); + + -- Display Buffer Memory, organised in a Row x Col format, where Address = (Row * MAX_COLUMN * 8) + Col, + -- but in real terms it is a 320x200x3 or 640x200x3 frame buffer. + -- + FRAMEBUF0 : dpram + GENERIC MAP ( + init_file => null, + widthad_a => 14, + width_a => 24, + widthad_b => 14, + width_b => 24, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for Display output. + clock_a => CLKBUS(CKVIDEO), + clocken_a => '1', + address_a => FB_ADDR, + data_a => (others => '0'), + wren_a => '0', + q_a => DISPLAY_DATA, + + -- Port B used for VRAM -> DISPLAY BUFFER transfer (DESTINATION). + clock_b => CLKBUS(CKSYS), + clocken_b => '1', + address_b => XFER_DST_ADDR, + data_b => XFER_MAPPED_DATA, + wren_b => XFER_WEN + --q_b => + ); + + -- 0 = MZ80K CGROM = 2Kbytes -> 0000:07ff + -- 1 = MZ80C CGROM = 2Kbytes -> 0800:0fff + -- 2 = MZ1200 CGROM = 2Kbytes -> 1000:17ff + -- 3 = MZ80A CGROM = 2Kbytes -> 1800:1fff + -- 4 = MZ700 CGROM = 4Kbytes -> 2000:2fff + -- + CGROM0 : dpram + GENERIC MAP ( + init_file => "./mif/combined_cgrom.mif", + widthad_a => 15, + width_a => 8, + widthad_b => 15, + width_b => 8 + ) + PORT MAP ( + clock_a => CLKBUS(CKSYS), + clocken_a => '1', + address_a => CGROM_BANK & CG_ADDR(10 downto 0), + data_a => (others => '0'), + wren_a => '0', + q_a => CGROM_DO, + + clock_b => IOCTL_CLK, + clocken_b => '1', + address_b => IOCTL_ADDR(14 downto 0), + data_b => IOCTL_DOUT(7 DOWNTO 0), + wren_b => IOCTL_WEN_CGROM, + q_b => IOCTL_DIN_CGROM + ); + + CGRAM : dpram + GENERIC MAP ( + init_file => "./mif/combined_cgrom.mif", + widthad_a => 15, + width_a => 8, + widthad_b => 15, + width_b => 8 + ) + PORT MAP ( + clock_a => CLKBUS(CKSYS), + clocken_a => '1', + address_a => CGROM_BANK & CG_ADDR(10 downto 0), + data_a => CGRAM_DI, + wren_a => CGRAM_WEN, + q_a => CGRAM_DO, + + clock_b => IOCTL_CLK, + clocken_b => '1', + address_b => IOCTL_ADDR(14 DOWNTO 0), + data_b => IOCTL_DOUT(7 DOWNTO 0), + wren_b => IOCTL_WEN_CGRAM, + q_b => IOCTL_DIN_CGRAM + ); + + -- Clock as maximum system speed to minimise transfer time. + -- + process( RST_n, CLKBUS(CKSYS) ) + variable XFER_CYCLE : integer range 0 to 6; + variable XFER_SRC_COL : integer range 0 to 80; + variable XFER_SRC_ROW : integer range 0 to 25; + variable XFER_DST_COL : integer range 0 to 80; + variable XFER_DST_ROW : integer range 0 to 25; + variable XFER_DST_SUBROW : integer range 0 to 7; + variable MAPPED_DATA : std_logic_vector(23 downto 0); + begin + if RST_n='0' then + XFER_VRAM_ADDR <= (others => '0'); + XFER_DST_ADDR <= (others => '0'); + XFER_CGROM_ADDR <= (others => '0'); + XFER_SRC_COL := 0; + XFER_SRC_ROW := 0; + XFER_DST_COL := 0; + XFER_DST_SUBROW := 0; + XFER_DST_ROW := 0; + XFER_CYCLE := 0; + XFER_WEN <= '0'; + + -- Process on negative edge as the RAM locks a write on positive edge. + -- + elsif CLKBUS(CKSYS)'event and CLKBUS(CKSYS)='0' then + + -- If we are in the active transfer window, start transfer. + if V_COUNT >= V_DISPLAY_END and XFER_DST_ROW < MAX_ROW then + + -- Finite state machine to implement read, map and write. + case (XFER_CYCLE) is + -- Setup the source character address. + when 0 => + if CONFIG(MZ_KC) = '1' then + XFER_VRAM_ADDR <= std_logic_vector(to_unsigned((XFER_SRC_ROW * MAX_COLUMN) + XFER_SRC_COL, 11)); + else + XFER_VRAM_ADDR <= std_logic_vector(to_unsigned((XFER_SRC_ROW * MAX_COLUMN) + XFER_SRC_COL, 11)) + (OFFSET_ADDR & "000"); + end if; + XFER_CYCLE := 1; + + -- Get the source character and map via the PCG to a slice of the displayed character. + -- Recalculate the destination address based on this loops values. + when 1 => + -- Setup the PCG address based on the read character. + XFER_CGROM_ADDR <= XFER_VRAM_DATA(15) & XFER_VRAM_DATA(7 downto 0) & std_logic_vector(to_unsigned(XFER_DST_SUBROW, 3)); + + -- Destination is recalculated each loop due to subrow changing. + -- As the Graphics framebuffer is on a 1-1, we use the same address counter to read out data from GRAM. + XFER_DST_ADDR <= std_logic_vector(to_unsigned((((XFER_DST_ROW * MAX_SUBROW) + XFER_DST_SUBROW) * MAX_COLUMN) + XFER_DST_COL, 14)); + XFER_CYCLE := 2; + + -- An extra clock needed for the CGROM to settle. + when 2 => + XFER_CYCLE := 3; + + -- Expand and store the slice of the character. + when 3 => + -- Graphics mode:- 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), + -- 5 = GRAM Output Enable 0 = active. + -- 4 = VRAM Output Enable, 0 = active. + -- 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), + -- 1/0 = Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). + if CONFIG(VRAMDISABLE) = '0' and GRAM_MODE(4) = '0' then + if CONFIG(COLOUR) = '1' or CONFIG(COLOUR80) = '1' then + if CGROM_DATA(7) = '0' then + MAPPED_DATA(7) := XFER_VRAM_DATA(10); + MAPPED_DATA(15) := XFER_VRAM_DATA(9); + MAPPED_DATA(23) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(7) := XFER_VRAM_DATA(14); + MAPPED_DATA(15) := XFER_VRAM_DATA(13); + MAPPED_DATA(23) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(6) = '0' then + MAPPED_DATA(6) := XFER_VRAM_DATA(10); + MAPPED_DATA(14) := XFER_VRAM_DATA(9); + MAPPED_DATA(22) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(6) := XFER_VRAM_DATA(14); + MAPPED_DATA(14) := XFER_VRAM_DATA(13); + MAPPED_DATA(22) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(5) = '0' then + MAPPED_DATA(5) := XFER_VRAM_DATA(10); + MAPPED_DATA(13) := XFER_VRAM_DATA(9); + MAPPED_DATA(21) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(5) := XFER_VRAM_DATA(14); + MAPPED_DATA(13) := XFER_VRAM_DATA(13); + MAPPED_DATA(21) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(4) = '0' then + MAPPED_DATA(4) := XFER_VRAM_DATA(10); + MAPPED_DATA(12) := XFER_VRAM_DATA(9); + MAPPED_DATA(20) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(4) := XFER_VRAM_DATA(14); + MAPPED_DATA(12) := XFER_VRAM_DATA(13); + MAPPED_DATA(20) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(3) = '0' then + MAPPED_DATA(3) := XFER_VRAM_DATA(10); + MAPPED_DATA(11) := XFER_VRAM_DATA(9); + MAPPED_DATA(19) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(3) := XFER_VRAM_DATA(14); + MAPPED_DATA(11) := XFER_VRAM_DATA(13); + MAPPED_DATA(19) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(2) = '0' then + MAPPED_DATA(2) := XFER_VRAM_DATA(10); + MAPPED_DATA(10) := XFER_VRAM_DATA(9); + MAPPED_DATA(18) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(2) := XFER_VRAM_DATA(14); + MAPPED_DATA(10) := XFER_VRAM_DATA(13); + MAPPED_DATA(18) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(1) = '0' then + MAPPED_DATA(1) := XFER_VRAM_DATA(10); + MAPPED_DATA(9) := XFER_VRAM_DATA(9); + MAPPED_DATA(17) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(1) := XFER_VRAM_DATA(14); + MAPPED_DATA(9) := XFER_VRAM_DATA(13); + MAPPED_DATA(17) := XFER_VRAM_DATA(12); + end if; + if CGROM_DATA(0) = '0' then + MAPPED_DATA(0) := XFER_VRAM_DATA(10); + MAPPED_DATA(8) := XFER_VRAM_DATA(9); + MAPPED_DATA(16) := XFER_VRAM_DATA(8); + else + MAPPED_DATA(0) := XFER_VRAM_DATA(14); + MAPPED_DATA(8) := XFER_VRAM_DATA(13); + MAPPED_DATA(16) := XFER_VRAM_DATA(12); + end if; + end if; + if CONFIG(NORMAL) = '1' or CONFIG(NORMAL80) = '1' then + if CGROM_DATA(7) = '0' then + MAPPED_DATA(7) := '0'; + MAPPED_DATA(15) := '0'; + MAPPED_DATA(23) := '0'; + else + MAPPED_DATA(7) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(15) := '1'; + MAPPED_DATA(23) := '1'; + end if; + end if; + if CGROM_DATA(6) = '0' then + MAPPED_DATA(6) := '0'; + MAPPED_DATA(14) := '0'; + MAPPED_DATA(22) := '0'; + else + MAPPED_DATA(6) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(14) := '1'; + MAPPED_DATA(22) := '1'; + end if; + end if; + if CGROM_DATA(5) = '0' then + MAPPED_DATA(5) := '0'; + MAPPED_DATA(13) := '0'; + MAPPED_DATA(21) := '0'; + else + MAPPED_DATA(5) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(13) := '1'; + MAPPED_DATA(21) := '1'; + end if; + end if; + if CGROM_DATA(4) = '0' then + MAPPED_DATA(4) := '0'; + MAPPED_DATA(12) := '0'; + MAPPED_DATA(20) := '0'; + else + MAPPED_DATA(4) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(12) := '1'; + MAPPED_DATA(20) := '1'; + end if; + end if; + if CGROM_DATA(3) = '0' then + MAPPED_DATA(3) := '0'; + MAPPED_DATA(11) := '0'; + MAPPED_DATA(19) := '0'; + else + MAPPED_DATA(3) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(11) := '1'; + MAPPED_DATA(19) := '1'; + end if; + end if; + if CGROM_DATA(2) = '0' then + MAPPED_DATA(2) := '0'; + MAPPED_DATA(10) := '0'; + MAPPED_DATA(18) := '0'; + else + MAPPED_DATA(2) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(10) := '1'; + MAPPED_DATA(18) := '1'; + end if; + end if; + if CGROM_DATA(1) = '0' then + MAPPED_DATA(1) := '0'; + MAPPED_DATA(9) := '0'; + MAPPED_DATA(17) := '0'; + else + MAPPED_DATA(1) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(9) := '1'; + MAPPED_DATA(17) := '1'; + end if; + end if; + if CGROM_DATA(0) = '0' then + MAPPED_DATA(0) := '0'; + MAPPED_DATA(8) := '0'; + MAPPED_DATA(16) := '0'; + else + MAPPED_DATA(0) := '1'; + if CONFIG(MZ_KC) = '1' then + MAPPED_DATA(8) := '1'; + MAPPED_DATA(16) := '1'; + end if; + end if; + + -- If invert option selected, invert green. + -- + if CONFIG(MZ_A) = '1' and DISPLAY_INVERT = '1' then + MAPPED_DATA(7 downto 0) := not MAPPED_DATA(7 downto 0); + end if; + end if; + else + MAPPED_DATA := (others => '0'); + end if; + + -- Graphics ram enabled? + -- + if CONFIG(GRAMDISABLE) = '0' and GRAM_MODE(5) = '0' then + -- Merge in the graphics data using defined mode. + -- + case GRAM_MODE(7 downto 6) is + when "00" => + MAPPED_DATA := MAPPED_DATA or XFER_GRAM_DATA; + when "01" => + MAPPED_DATA := MAPPED_DATA and XFER_GRAM_DATA; + when "10" => + MAPPED_DATA := MAPPED_DATA nand XFER_GRAM_DATA; + when "11" => + MAPPED_DATA := MAPPED_DATA xor XFER_GRAM_DATA; + end case; + end if; + + -- Assign the video data to the framebuffer input. + XFER_MAPPED_DATA <= MAPPED_DATA; + XFER_CYCLE := 4; + + -- Commence write of mapped data. + when 4 => + XFER_WEN <= '1'; + XFER_CYCLE := 5; + + -- Complete write and update address. + when 5 => + -- Write cycle to framebuffer finished. + XFER_WEN <= '0'; + XFER_CYCLE := 6; + + -- Update the counters. + when 6 => + -- For each source character, we generate 8 lines in the frame buffer. Thus we increment the + -- source character sub-row which addresses a different portion of the Character Generator Rom + -- and store that data into the frame buffer. Once we get to the last sub-row address, + -- increment the source and destination address parameters. + if XFER_DST_SUBROW < MAX_SUBROW-1 then + XFER_DST_SUBROW := XFER_DST_SUBROW + 1; + XFER_CYCLE := 1; + else + -- Increment Source Column/Row + if XFER_SRC_COL < MAX_COLUMN - 1 then + XFER_SRC_COL := XFER_SRC_COL + 1; + else + XFER_SRC_COL := 0; + XFER_SRC_ROW := XFER_SRC_ROW + 1; + end if; + + -- Increment Destination Column/Row - reset subrow to 0 + XFER_DST_SUBROW := 0; + if XFER_DST_COL < MAX_COLUMN - 1 then + XFER_DST_COL := XFER_DST_COL + 1; + else + XFER_DST_COL := 0; + XFER_DST_ROW := XFER_DST_ROW + 1; + end if; + XFER_CYCLE := 0; + end if; + end case; + end if; + + -- On a new cycle, reset the transfer parameters. + -- + if V_COUNT = V_DISPLAY_START then + XFER_VRAM_ADDR <= (others => '0'); + XFER_DST_ADDR <= (others => '0'); + XFER_CGROM_ADDR <= (others => '0'); + XFER_SRC_COL := 0; + XFER_SRC_ROW := 0; + XFER_DST_COL := 0; + XFER_DST_SUBROW := 0; + XFER_DST_ROW := 0; + XFER_CYCLE := 0; + XFER_WEN <= '0'; + end if; + end if; + end process; + + -- + -- Blank & Sync Generation + -- + process( RST_n, CLKBUS(CKVIDEO), H_LINE_END, V_LINE_END ) + variable configured : integer range 0 to 2000000; + variable FB_COL : integer range 0 to 80; + variable FB_LINE : integer range 0 to 200; + begin + -- On reset, initialise parameters then set wait timer running. + -- + if RST_n='0' then + + FB_COL := 0; + FB_LINE := 0; + FB_ADDR <= (others => '0'); + + -- In order to ensure the correct machine configuration has been latched, wait a period of + -- time before loading the display configuration. + -- + configured := 2000000; + + elsif CLKBUS(CKVIDEO)'event and CLKBUS(CKVIDEO)='1' then + + -- When the time period for allowing the machine configuration to be latched has expired, set the + -- display configuration according to machine/display model. + if configured = 1 then + + -- MZ80K/C/1200/A machines have a monochrome 60Hz display, with scan of 512 x 260 for a 320x200 viewable area. + if CONFIG(NORMAL) = '1' then + MAX_COLUMN <= 40; -- 40 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(H_LINE_END, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 320; + H_BLNK_START <= 320; + H_BLNK_END <= 486; + H_SYNC_START <= 320 + 73; + H_SYNC_END <= 320 + 73 + 45; + H_LINE_END <= 511; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 19; + V_SYNC_END <= 200 + 19 + 4; + V_LINE_END <= 259; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + + -- MZ80K/C/1200/A machines with an adapted monochrome 60Hz display, with scan of 1024 x 260 for a 640x200 viewable area. + elsif CONFIG(NORMAL80) = '1' then + MAX_COLUMN <= 80; -- 80 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(H_LINE_END, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 640; + H_BLNK_START <= 640; + H_BLNK_END <= 972; + H_SYNC_START <= 640 + 146; + H_SYNC_END <= 640 + 146 + 90; + H_LINE_END <= 1023; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 19; + V_SYNC_END <= 200 + 19 + 4; + V_LINE_END <= 259; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + + -- MZ700 has a colour 50Hz display, with scan of 568 x 320 for a 320x200 viewable area. + elsif CONFIG(COLOUR) = '1' and CONFIG(MZ700) = '1' then + MAX_COLUMN <= 40; -- 40 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(H_LINE_END, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 320; + H_BLNK_START <= 320; + H_BLNK_END <= 548; + H_SYNC_START <= 320 + 80; + H_SYNC_END <= 320 + 80 + 40; + H_LINE_END <= 567; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 45; + V_SYNC_END <= 200 + 45 + 3; + V_LINE_END <= 311; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + + -- MZ700 has colour 50Hz display, with scan of 1136 x 320 for a 640x200 viewable area. + elsif CONFIG(COLOUR80) = '1' and CONFIG(MZ700) = '1' then + MAX_COLUMN <= 80; -- 80 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(H_LINE_END, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 640; + H_BLNK_START <= 640; + H_BLNK_END <= 1096; + H_SYNC_START <= 640 + 160; + H_SYNC_END <= 640 + 160 + 80; + H_LINE_END <= 1134; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 45; + V_SYNC_END <= 200 + 45 + 3; + V_LINE_END <= 311; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + + -- MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display, with scan of 512 x 260 for a 320x200 viewable area. + elsif CONFIG(COLOUR) = '1' then + MAX_COLUMN <= 40; -- 40 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(H_LINE_END, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 320; + H_BLNK_START <= 320; + H_BLNK_END <= 486; + H_SYNC_START <= 320 + 73; + H_SYNC_END <= 320 + 73 + 45; + H_LINE_END <= 511; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 19; + V_SYNC_END <= 200 + 19 + 4; + V_LINE_END <= 259; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + + -- MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display, with scan of 1024 x 260 for a 640x200 viewable area. + elsif CONFIG(COLOUR80) = '1' then + MAX_COLUMN <= 80; -- 80 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(H_LINE_END, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 640; + H_BLNK_START <= 640; + H_BLNK_END <= 972; + H_SYNC_START <= 640 + 146; + H_SYNC_END <= 640 + 146 + 90; + H_LINE_END <= 1023; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 19; + V_SYNC_END <= 200 + 19 + 4; + V_LINE_END <= 259; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + + -- Default set for unrecognised machine id. + -- + else + MAX_COLUMN <= 40; -- 40 x 25 character display area. + MAX_ROW <= 25; + MAX_SUBROW <= 8; + H_COUNT <= to_unsigned(0, 11); + V_COUNT <= to_unsigned(0, 11); --(others => '0'); + H_BLANKi <= '1'; + V_BLANKi <= '0'; + BLNK <= '0'; + H_SYNC_ni <= '1'; + V_SYNC_ni <= '1'; + H_DISPLAY_START <= 0; + H_DISPLAY_END <= 320; + H_BLNK_START <= 320; + H_BLNK_END <= 486; + H_SYNC_START <= 320 + 73; + H_SYNC_END <= 320 + 73 + 45; + H_LINE_END <= 511; + V_DISPLAY_START <= 0; + V_DISPLAY_END <= 200; + V_SYNC_START <= 200 + 19; + V_SYNC_END <= 200 + 19 + 4; + V_LINE_END <= 259; + FB_ADDR <= (others => '0'); + SR_G_DATA <= (others => '0'); + SR_R_DATA <= (others => '0'); + SR_B_DATA <= (others => '0'); + end if; + + configured := 0; + + elsif configured = 0 then + -- Activate/deactivate signals according to pixel position. + -- + if H_COUNT = H_DISPLAY_START then H_BLANKi <= '0'; end if; + if H_COUNT = H_DISPLAY_END then H_BLANKi <= '1'; end if; + if H_COUNT = H_BLNK_START then BLNK <= '1'; end if; + if H_COUNT = H_BLNK_END then BLNK <= '0'; end if; + if H_COUNT = H_SYNC_END then H_SYNC_ni <= '1'; end if; + if H_COUNT = H_SYNC_START then H_SYNC_ni <= '0'; end if; + if V_COUNT = V_DISPLAY_START then V_BLANKi <= '0'; end if; + if V_COUNT = V_DISPLAY_END then V_BLANKi <= '1'; end if; + if V_COUNT = V_SYNC_START then V_SYNC_ni <= '0'; end if; + if V_COUNT = V_SYNC_END then V_SYNC_ni <= '1'; end if; + + -- During the active display area, clock out from the frame buffer the pixel information. + -- + if H_COUNT < H_DISPLAY_END and V_COUNT < V_DISPLAY_END then + + -- Data is stored in the frame buffer in bytes, 1 bit per pixel x 8 and 3 colors, thus 1 x 8 x 3 or 24 bit. Read + -- out the values into shift registers to be serialised. + -- + if H_COUNT(2 downto 0) = "000" then + SR_G_DATA <= DISPLAY_DATA(7 downto 0); + SR_R_DATA <= DISPLAY_DATA(15 downto 8); + SR_B_DATA <= DISPLAY_DATA(23 downto 16); + end if; + + -- One clock cycle after loading the shift registers, we update the column position so the next memory location + -- address can be calculated and presented to RAM so new data is available for next shift register load. + -- + if H_COUNT(2 downto 0) = "001" then + if FB_COL < MAX_COLUMN - 1 then + FB_COL := FB_COL + 1; + elsif FB_COL = MAX_COLUMN -1 then + FB_COL := 0; + FB_LINE := FB_LINE + 1; + end if; + end if; + + -- Using the horizontal counter in sets of 8, when 0 we load the shift register from memory and bit 7 is immediately + -- available as a pixel, then all other horizontal counter values, ie. 1 - 7, we shift the bits along to be output + -- as a video signal. + -- + if H_COUNT(2 downto 0) /= "000" then + SR_G_DATA <= SR_G_DATA(6 downto 0) & '0'; + SR_R_DATA <= SR_R_DATA(6 downto 0) & '0'; + SR_B_DATA <= SR_B_DATA(6 downto 0) & '0'; + end if; + end if; + + -- The column and row position is reset to home once we reach the end of the active display. + -- + if H_COUNT = H_LINE_END and V_COUNT = V_DISPLAY_END then + FB_COL := 0; + FB_LINE := 0; + end if; + + -- Calculate the new frame buffer address, based on Line x Col format. + -- + FB_ADDR <= std_logic_vector(to_unsigned((FB_LINE * MAX_COLUMN) + FB_COL, 14)); + + -- Horizontal/Vertical counters are updated each clock cycle to accurately track pixel/timing. + -- + if H_COUNT = H_LINE_END then + H_COUNT <= (others => '0'); + + if V_COUNT = V_LINE_END then + V_COUNT <= (others => '0'); + else + V_COUNT <= V_COUNT + 1; + end if; + else + H_COUNT <= H_COUNT + 1; + end if; + else + -- Decrement configured timer to implement Reset -> load config delay. + -- + configured := configured -1; + end if; + end if; + end process; + + -- + -- Control Registers + -- MZ1200/80A: INVERT display, accessed at E014 + -- SCROLL display, accessed at E200 - E2FF, the address determines the offset. + -- EA, sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). + -- EB, sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte). + -- EC, sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte). + -- ED, sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte). + -- + process( RST_n, CLKBUS(CKCPU) ) begin + if RST_n='0' then + DISPLAY_INVERT <= '0'; + OFFSET_ADDR <= (others => '0'); + GRAM_MODE <= "00001100"; + GRAM_RED_WRITER <= (others => '1'); + GRAM_GREEN_WRITER <= (others => '1'); + GRAM_BLUE_WRITER <= (others => '1'); + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then + + if CS_INVERT_n='0' and T80_RD_n='0' then + DISPLAY_INVERT <= T80_MA(0); + end if; + + if CS_SCROLL_n='0' and T80_RD_n='0' then + if CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1' then + OFFSET_ADDR <= (others => '0'); + else + OFFSET_ADDR <= T80_A(7 downto 0); + end if; + end if; + + if CS_IO_EA_n='0' and T80_WR_n='0' then + GRAM_MODE <= T80_DI; + end if; + + if CS_IO_EB_n='0' and T80_WR_n='0' then + GRAM_RED_WRITER <= T80_DI; + end if; + + if CS_IO_EC_n='0' and T80_WR_n='0' then + GRAM_GREEN_WRITER <= T80_DI; + end if; + + if CS_IO_ED_n='0' and T80_WR_n='0' then + GRAM_BLUE_WRITER <= T80_DI; + end if; + end if; + end process; + + -- Enable Video Wait States - Original design has wait states inserted into the cycle if the CPU accesses the VRAM during display. In the updated design, the VRAM + -- is copied into a framebuffer during the Vertical Blanking period so no wait states are needed. To keep consistency with the original design (for programs which depend on it), + -- the wait states can be enabled by configuration. + -- + process( T80_MREQ_n ) begin + if T80_MREQ_n'event and T80_MREQ_n='0' then + BLNK_MEMACCESS <= BLNK; + end if; + end process; + -- + -- Extend wait by 1 cycle + process( CLKBUS(CKCPU) ) begin + if CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then + WAITii_n <= WAITi_n; + end if; + end process; + + -- + -- PCG Access Registers + -- + -- E010: PCG_DATA (byte to describe 8-pixel row of a character) + -- E011: PCG_ADDR (offset in the PCG in 8-pixel row unit) -> up to 256/8 = 32 characters + -- E012: PCG_CTRL + -- bit 0-1: character selector -> (PCG_ADDR + 256*(PCG_CTRL&3)) -> address in the range of the upper 128 characters font + -- bit 2 : font selector -> PCG_CTRL&2 == 0 -> 1st font else 2nd font + -- bit 3 : select which font for display + -- bit 4 : use programmable font for display + -- bit 5 : set programmable upper font -> PCG_CTRL&20 == 0 -> fixed upper 128 characters else programmable upper 128 characters + -- So if you want to change a character pattern (only doable in the upper 128 characters of a font), you need to: + -- - set bit 5 to 1 : PCG_CTRL[5] = 1 + -- - set the font to select : PCG_CTRL[2] = font_number + -- - set the first row address of the character: PCG_ADDR[0..7] = row[0..7] and PCG_CTRL[0..1] = row[8..9] + -- - set the 8 pixels of the row in PCG_DATA + -- + process( RST_n, CLKBUS(CKCPU) ) begin + if RST_n = '0' then + CGRAM_ADDR <= (others=>'0'); + PCG_DATA <= (others=>'0'); + CGRAM_WE_n <= '1'; + + elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then + + if CS_PCG_n = '0' and T80_WR_n = '0' then + -- Set the PCG Data to program to RAM. + if T80_A(1 downto 0) = "00" then + PCG_DATA <= T80_DI; + end if; + + -- Set the PCG Address in RAM. + if T80_A(1 downto 0) = "01" then + CGRAM_ADDR(7 downto 0) <= T80_DI; + end if; + + -- Set the PCG Control register. + if T80_A(1 downto 0) = "10" then + CGRAM_ADDR(11 downto 8) <= (T80_DI(2) and CONFIG(MZ_A)) & '1' & T80_DI(1 downto 0); + CGRAM_WE_n <= not T80_DI(4); + CGRAM_SEL <= T80_DI(5); + end if; + end if; + end if; + end process; + + -- + -- CPU / RAM signals and selects. + -- + WAITi_n <= '0' when CS_D_n = '0' and BLNK_MEMACCESS = '0' and BLNK = '0' and (CONFIG(MZ_A) = '1' or CONFIG(MZ700) = '1') + else '1'; + T80_WAIT_n <= WAITi_n and WAITii_n when CONFIG(VRAMWAIT) = '1' + else '1'; + T80_MA <= "00" & T80_A(9 downto 0) when CONFIG(MZ_KC) = '1' + else + T80_A(11 downto 0); + -- Program Character Generator RAM. E010 - Write cycle (Read cycle = reset memory swap). + CS_PCG_n <= '0' when CS_E_n = '0' and T80_A(10 downto 4) = "0000001" + else '1'; -- D010 -> D01f + -- Invert display register. E014/E015 + CS_INVERT_n <= '0' when CS_E_n = '0' and CONFIG(MZ_A) = '1' and T80_MA(11 downto 9) = "000" and T80_MA(4 downto 2) = "101" + else '1'; + -- Scroll display register. E200 - E2FF + CS_SCROLL_n <= '0' when CS_E_n = '0' and T80_A(11 downto 8)="0010" and CONFIG(MZ_A)='1' + else '1'; + -- EA, sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), + -- 5 = GRAM Output Enable, 4 = VRAM Output Enable, + -- 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), + -- 1/0 = Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). + CS_IO_EA_n <= '0' when CS_IO_GRAM_n = '0' and T80_A(2 downto 0) = "010" + else '1'; + -- EB, sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte). + CS_IO_EB_n <= '0' when CS_IO_GRAM_n = '0' and T80_A(2 downto 0) = "011" + else '1'; + -- EC, sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte). + CS_IO_EC_n <= '0' when CS_IO_GRAM_n = '0' and T80_A(2 downto 0) = "100" + else '1'; + -- ED, sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte). + CS_IO_ED_n <= '0' when CS_IO_GRAM_n = '0' and T80_A(2 downto 0) = "101" + else '1'; + + T80_DO <= VRAM_VIDEO_DATA when T80_RD_n = '0' and CS_D_n = '0' + else + GRAM_VIDEO_DATA when T80_RD_n = '0' and CS_G_n = '0' + else + (others=>'0'); + + VRAM_ADDR <= T80_MA(10 downto 0) & T80_MA(11) when IOCTL_CS_VRAM_n = '1' + else + IOCTL_ADDR(10 downto 0) & IOCTL_ADDR(11); + VRAM_DATA_IN <= T80_DI when IOCTL_CS_VRAM_n = '1' + else + IOCTL_DOUT(7 downto 0); + VWEN <= '1' when T80_WR_n='0' and CS_D_n = '0' + else '0'; + VRAM_WEN <= VWEN when IOCTL_CS_VRAM_n = '1' + else + IOCTL_WEN_VRAM; + VRAM_VIDEO_DATA <= VRAM_DATA_OUT when IOCTL_CS_VRAM_n = '1' + else + (others=>'0'); + IOCTL_DIN_VRAM <= VRAM_DATA_OUT when IOCTL_CS_VRAM_n = '0' + else + (others=>'0'); + VRAM_CLK <= CLKBUS(CKMEM) when IOCTL_CS_VRAM_n = '1' + else + IOCTL_CLK; + + -- CGROM Data to CG RAM, either ROM -> RAM copy or Z80 provides map. + -- + CGRAM_DI <= CGROM_DO when CGRAM_SEL = '1' -- Data from ROM + else + PCG_DATA when CGRAM_SEL = '0' -- Data from PCG + else (others=>'0'); + CGRAM_WEN <= not (CGRAM_WE_n or CS_PCG_n) and not T80_WR_n; + + -- + -- Font select + -- + CGROM_DATA <= CGROM_DO when CONFIG(PCGRAM)='0' + else + PCG_DATA when CS_PCG_n='0' and T80_A(1 downto 0)="10" and T80_WR_n='0' + else + CGRAM_DO when CONFIG(PCGRAM)='1' + else (others => '1'); + CG_ADDR <= CGRAM_ADDR(11 downto 0) when CGRAM_WE_n = '0' + else XFER_CGROM_ADDR; + CGROM_BANK <= "0000" when CONFIG(MZ80K) = '1' + else + "0001" when CONFIG(MZ80C) = '1' + else + "0010" when CONFIG(MZ1200) = '1' + else + "0011" when CONFIG(MZ80A) = '1' + else + "0100" when CONFIG(MZ700) = '1' and XFER_CGROM_ADDR(11) = '0' + else + "0101" when CONFIG(MZ700) = '1' and XFER_CGROM_ADDR(11) = '1' + else + "0110" when CONFIG(MZ800) = '1' and XFER_CGROM_ADDR(11) = '0' + else + "0111" when CONFIG(MZ800) = '1' and XFER_CGROM_ADDR(11) = '1' + else + "1000" when CONFIG(MZ80B) = '1' + else + "1001" when CONFIG(MZ2000) = '1' + else + "1111"; + + + -- As the Graphics RAM is an odd size, 16384 x 3 colour planes, it has to be in 3 seperate 16K blocks to avoid wasting memory (or having it synthesized away), + -- thus there are 3 sets of signals, 1 per colour. + -- + GRAM_ADDR <= T80_A(13 downto 0) when IOCTL_CS_GRAM_n = '1' + else + IOCTL_ADDR(13 downto 0); + -- direct writes when accessing individual pages. + GRAM_DATA_IN_R <= T80_DI when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "00" + else + T80_DI and GRAM_RED_WRITER when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11" + else + IOCTL_DOUT(7 downto 0) when IOCTL_ADDR(15 downto 14) = "00" + else + (others=>'0'); + -- direct writes when accessing individual pages. + GRAM_DATA_IN_G <= T80_DI when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "01" + else + T80_DI and GRAM_GREEN_WRITER when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11" + else + IOCTL_DOUT(7 downto 0) when IOCTL_ADDR(15 downto 14) = "01" + else + (others=>'0'); + -- direct writes when accessing individual pages. + GRAM_DATA_IN_B <= T80_DI when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "10" + else + T80_DI and GRAM_BLUE_WRITER when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(3 downto 2) = "11" + else + IOCTL_DOUT(7 downto 0) when IOCTL_ADDR(15 downto 14) = "10" + else + (others=>'0'); + GWEN_R <= '1' when T80_WR_n = '0' and CS_G_n = '0' and GRAM_MODE(3 downto 2) = "00" + else + '1' when T80_WR_n = '0' and CS_G_n = '0' and GRAM_MODE(3 downto 2) = "11" + else + '0'; + GRAM_WEN_R <= GWEN_R when IOCTL_CS_GRAM_n = '1' + else + IOCTL_WEN_GRAM_R; + GWEN_G <= '1' when T80_WR_n='0' and CS_G_n = '0' and GRAM_MODE(3 downto 2) = "01" + else + '1' when T80_WR_n='0' and CS_G_n = '0' and GRAM_MODE(3 downto 2) = "11" + else + '0'; + GRAM_WEN_G <= GWEN_G when IOCTL_CS_GRAM_n = '1' + else + IOCTL_WEN_GRAM_G; + GWEN_B <= '1' when T80_WR_n='0' and CS_G_n = '0' and GRAM_MODE(3 downto 2) = "10" + else + '1' when T80_WR_n='0' and CS_G_n = '0' and GRAM_MODE(3 downto 2) = "11" + else + '0'; + GRAM_WEN_B <= GWEN_B when IOCTL_CS_GRAM_n = '1' + else + IOCTL_WEN_GRAM_B; + + GRAM_VIDEO_DATA <= GRAM_DATA_OUT_R when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "00" + else + GRAM_DATA_OUT_G when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "01" + else + GRAM_DATA_OUT_B when IOCTL_CS_GRAM_n = '1' and GRAM_MODE(1 downto 0) = "10" + else + (others=>'0'); + IOCTL_DIN_GRAM <= GRAM_DATA_OUT_R when IOCTL_CS_GRAM_n = '0' and GRAM_MODE(1 downto 0) = "00" + else + GRAM_DATA_OUT_G when IOCTL_CS_GRAM_n = '0' and GRAM_MODE(1 downto 0) = "01" + else + GRAM_DATA_OUT_B when IOCTL_CS_GRAM_n = '0' and GRAM_MODE(1 downto 0) = "10" + else + (others=>'0'); + GRAM_CLK <= CLKBUS(CKMEM) when IOCTL_CS_GRAM_n = '1' + else + IOCTL_CLK; + + -- + -- HPS Access - match whole address, additional LE but easier to read. + -- + IOCTL_WEN_VRAM <= '1' when IOCTL_CS_VRAM_n = '0' and IOCTL_WR = '1' + else '0'; + IOCTL_WEN_GRAM_R <= '1' when IOCTL_CS_GRAM_n = '0' and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "00" + else '0'; + IOCTL_WEN_GRAM_G <= '1' when IOCTL_CS_GRAM_n = '0' and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "01" + else '0'; + IOCTL_WEN_GRAM_B <= '1' when IOCTL_CS_GRAM_n = '0' and IOCTL_WR = '1' and IOCTL_ADDR(15 downto 14) = "10" + else '0'; + IOCTL_WEN_CGROM <= '1' when IOCTL_CS_CGROM_n = '0' and IOCTL_WR = '1' + else '0'; + IOCTL_WEN_CGRAM <= '1' when IOCTL_CS_CGRAM_n = '0' and IOCTL_WR = '1' + else '0'; + IOCTL_CS_VRAM_n <= '0' when IOCTL_ADDR(24 downto 16) = "000000100" + else '1'; + IOCTL_CS_GRAM_n <= '0' when IOCTL_ADDR(24 downto 16) = "000000100" + else '1'; + IOCTL_CS_CGROM_n <= '0' when IOCTL_ADDR(24 downto 15) = "0000001110" + else '1'; + IOCTL_CS_CGRAM_n <= '0' when IOCTL_ADDR(24 downto 11) = "00000100000000" + else '1'; + IOCTL_DIN <= X"00" & IOCTL_DIN_VRAM when IOCTL_CS_VRAM_n = '0' and IOCTL_RD = '1' + else + X"00" & IOCTL_DIN_GRAM when IOCTL_CS_GRAM_n = '0' and IOCTL_RD = '1' + else + X"00" & IOCTL_DIN_CGROM when IOCTL_CS_CGROM_n = '0' and IOCTL_RD = '1' + else + X"00" & IOCTL_DIN_CGRAM when IOCTL_CS_CGRAM_n = '0' and IOCTL_RD = '1' + else + (others=>'0'); + + -- + -- Video Output Signals + -- + VBLANK <= V_BLANKi; + HBLANK <= H_BLANKi; + VSYNC_n <= V_SYNC_ni; + HSYNC_n <= H_SYNC_ni; + ROUT <= SR_R_DATA(7) when H_BLANKi='0' or VGATE_n='1' + else + '0'; + GOUT <= SR_G_DATA(7) when H_BLANKi='0' or VGATE_n='1' + else + '0'; + BOUT <= SR_B_DATA(7) when H_BLANKi='0' or VGATE_n='1' + else + '0'; +end RTL; diff --git a/mzf/hi-ramcheck.mzf b/mzf/hi-ramcheck.mzf new file mode 100644 index 0000000..c68c09f Binary files /dev/null and b/mzf/hi-ramcheck.mzf differ diff --git a/mzf/ramtest.mzf b/mzf/ramtest.mzf new file mode 100644 index 0000000..6813dbc Binary files /dev/null and b/mzf/ramtest.mzf differ diff --git a/mzf/tapecheck.mzf b/mzf/tapecheck.mzf new file mode 100644 index 0000000..ac015d0 Binary files /dev/null and b/mzf/tapecheck.mzf differ diff --git a/releases/SharpMZ_20180926.rbf b/releases/SharpMZ_20180926.rbf new file mode 100644 index 0000000..6d750a8 Binary files /dev/null and b/releases/SharpMZ_20180926.rbf differ diff --git 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+ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ \ No newline at end of file diff --git a/sharpmz-lite.qsf b/sharpmz-lite.qsf new file mode 100644 index 0000000..bed0f0c --- /dev/null +++ b/sharpmz-lite.qsf @@ -0,0 +1,433 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name VERILOG_MACRO "LITE=1" + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name TOP_LEVEL_ENTITY sys_top +#set_global_assignment -name TOP_LEVEL_ENTITY emu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name SEED 1 + +#============================================================ +# ADC +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +#set_location_assignment PIN_U9 -to ADC_CONVST +#set_location_assignment PIN_V10 -to ADC_SCK +#set_location_assignment PIN_AC4 -to ADC_SDI +#set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +#set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +#set_location_assignment PIN_U14 -to ARDUINO_IO[4] +#set_location_assignment PIN_U13 -to ARDUINO_IO[5] +#set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +#set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +#set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +#set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +#set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +#set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +#set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +#set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +#set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +#set_location_assignment PIN_AG11 -to ARDUINO_IO[15] + +#============================================================ +# SDIO +#============================================================ +#set_location_assignment PIN_AF25 -to SDIO_DAT[0] +#set_location_assignment PIN_AF23 -to SDIO_DAT[1] +#set_location_assignment PIN_AD26 -to SDIO_DAT[2] +#set_location_assignment PIN_AF28 -to SDIO_DAT[3] +#set_location_assignment PIN_AF27 -to SDIO_CMD +#set_location_assignment PIN_AH26 -to SDIO_CLK +#set_location_assignment PIN_AH7 -to SDIO_CD +# +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* +# +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_AE17 -to VGA_R[0] +set_location_assignment PIN_AE20 -to VGA_R[1] +set_location_assignment PIN_AF20 -to VGA_R[2] +set_location_assignment PIN_AH18 -to VGA_R[3] +set_location_assignment PIN_AH19 -to VGA_R[4] +set_location_assignment PIN_AF21 -to VGA_R[5] + +set_location_assignment PIN_AE19 -to VGA_G[0] +set_location_assignment PIN_AG15 -to VGA_G[1] +set_location_assignment PIN_AF18 -to VGA_G[2] +set_location_assignment PIN_AG18 -to VGA_G[3] +set_location_assignment PIN_AG19 -to VGA_G[4] +set_location_assignment PIN_AG20 -to VGA_G[5] + +set_location_assignment PIN_AG21 -to VGA_B[0] +set_location_assignment PIN_AA20 -to VGA_B[1] +set_location_assignment PIN_AE22 -to VGA_B[2] +set_location_assignment PIN_AF22 -to VGA_B[3] +set_location_assignment PIN_AH23 -to VGA_B[4] +set_location_assignment PIN_AH21 -to VGA_B[5] + +set_location_assignment PIN_AH22 -to VGA_HS +set_location_assignment PIN_AG24 -to VGA_VS + +set_location_assignment PIN_AH27 -to VGA_EN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + +#============================================================ +# AUDIO +#============================================================ +set_location_assignment PIN_AC24 -to AUDIO_L +set_location_assignment PIN_AE25 -to AUDIO_R +set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + +#============================================================ +# SDRAM +#============================================================ +#set_location_assignment PIN_Y11 -to SDRAM_A[0] +#set_location_assignment PIN_AA26 -to SDRAM_A[1] +#set_location_assignment PIN_AA13 -to SDRAM_A[2] +#set_location_assignment PIN_AA11 -to SDRAM_A[3] +#set_location_assignment PIN_W11 -to SDRAM_A[4] +#set_location_assignment PIN_Y19 -to SDRAM_A[5] +#set_location_assignment PIN_AB23 -to SDRAM_A[6] +#set_location_assignment PIN_AC23 -to SDRAM_A[7] +#set_location_assignment PIN_AC22 -to SDRAM_A[8] +#set_location_assignment PIN_C12 -to SDRAM_A[9] +#set_location_assignment PIN_AB26 -to SDRAM_A[10] +#set_location_assignment PIN_AD17 -to SDRAM_A[11] +#set_location_assignment PIN_D12 -to SDRAM_A[12] +#set_location_assignment PIN_Y17 -to SDRAM_BA[0] +#set_location_assignment PIN_AB25 -to SDRAM_BA[1] + +#set_location_assignment PIN_E8 -to SDRAM_DQ[0] +#set_location_assignment PIN_V12 -to SDRAM_DQ[1] +#set_location_assignment PIN_D11 -to SDRAM_DQ[2] +#set_location_assignment PIN_W12 -to SDRAM_DQ[3] +#set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +#set_location_assignment PIN_D8 -to SDRAM_DQ[5] +#set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +#set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +#set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +#set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +#set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +#set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +#set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +#set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +#set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +#set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +#set_location_assignment PIN_AG13 -to SDRAM_DQML +#set_location_assignment PIN_AF13 -to SDRAM_DQMH + +#set_location_assignment PIN_AD20 -to SDRAM_CLK +#set_location_assignment PIN_AG10 -to SDRAM_CKE + +#set_location_assignment PIN_AA19 -to SDRAM_nWE +#set_location_assignment PIN_AA18 -to SDRAM_nCAS +#set_location_assignment PIN_Y18 -to SDRAM_nCS +#set_location_assignment PIN_W14 -to SDRAM_nRAS + +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* +#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* +#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* +#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* +#set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +#set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# I/O +#============================================================ +set_location_assignment PIN_Y15 -to LED_USER +set_location_assignment PIN_AA15 -to LED_HDD +set_location_assignment PIN_AG28 -to LED_POWER + +set_location_assignment PIN_AH24 -to BTN_USER +set_location_assignment PIN_AG25 -to BTN_OSD +set_location_assignment PIN_AG23 -to BTN_RESET + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +#============================================================ +# HDMI +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS +#set_location_assignment PIN_U10 -to HDMI_I2C_SCL +#set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +#set_location_assignment PIN_T13 -to HDMI_I2S +#set_location_assignment PIN_T11 -to HDMI_LRCLK +#set_location_assignment PIN_U11 -to HDMI_MCLK +#set_location_assignment PIN_T12 -to HDMI_SCLK +#set_location_assignment PIN_AG5 -to HDMI_TX_CLK +#set_location_assignment PIN_AD19 -to HDMI_TX_DE +#set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +#set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +#set_location_assignment PIN_W8 -to HDMI_TX_D[2] +#set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +#set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +#set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +#set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +#set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +#set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +#set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +#set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +#set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +#set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +#set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +#set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +#set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +#set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +#set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +#set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +#set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +#set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +#set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +#set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +#set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +#set_location_assignment PIN_T8 -to HDMI_TX_HS +#set_location_assignment PIN_AF11 -to HDMI_TX_INT +#set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# SW +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +#set_location_assignment PIN_Y24 -to SW[0] +#set_location_assignment PIN_W24 -to SW[1] +#set_location_assignment PIN_W21 -to SW[2] +#set_location_assignment PIN_W20 -to SW[3] + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + +set_global_assignment -name CDF_FILE jtag.cdf +set_global_assignment -name QIP_FILE sys/sys.qip +set_global_assignment -name VHDL_FILE jtag_uart_0.vhd +set_global_assignment -name SYSTEMVERILOG_FILE emu.sv +set_global_assignment -name VHDL_FILE sharpmz.vhd + +#============================================================ +# Original MZ80C T80 CPU +#============================================================ +#set_global_assignment -name VHDL_FILE common/T80.orig/T80_Reg.vhd +#set_global_assignment -name VHDL_FILE common/T80.orig/T80_Pack.vhd +#set_global_assignment -name VHDL_FILE common/T80.orig/T80_MCode.vhd +#set_global_assignment -name VHDL_FILE common/T80.orig/T80_ALU.vhd +#set_global_assignment -name VHDL_FILE common/T80.orig/T80.vhd +#set_global_assignment -name VHDL_FILE common/T80.orig/T80s.vhd + +#============================================================ +# Latest T80 CPU +#============================================================ +set_global_assignment -name VHDL_FILE common/T80/T80.vhd +set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE common/T80/T80a.vhd +set_global_assignment -name VHDL_FILE common/T80/T80se.vhd +set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd + +#============================================================ +# i8253 Programmable Interval Timer +#============================================================ +set_global_assignment -name VHDL_FILE common/i8253/i8253.vhd +set_global_assignment -name VHDL_FILE common/i8253/counter0.vhd +set_global_assignment -name VHDL_FILE common/i8253/counter1.vhd +set_global_assignment -name VHDL_FILE common/i8253/counter2.vhd + +#============================================================ +# i8255 Programmable Peripheral Interface +#============================================================ +set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd + +#============================================================ +# MZ80C specific modules. +#============================================================ +set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd +set_global_assignment -name VHDL_FILE mz80c/cmt.vhd +set_global_assignment -name VHDL_FILE mz80c/mz80c_video.vhd + +#============================================================ +# MZ80B specific modules. +#============================================================ +set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd + +#============================================================ +# PLL +#============================================================ +set_global_assignment -name QIP_FILE common/pll.qip +set_global_assignment -name VHDL_FILE common/clkgen.vhd + +#============================================================ +# Common modules +#============================================================ +set_global_assignment -name VHDL_FILE common/dprom.vhd +set_global_assignment -name VHDL_FILE common/clk_div.vhd +set_global_assignment -name VHDL_FILE common/mctrl.vhd +set_global_assignment -name VHDL_FILE common/dpram.vhd +set_global_assignment -name VHDL_FILE common/keymatrix.vhd + +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON +set_global_assignment -name ALLOW_REGISTER_RETIMING ON + + + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/sharpmz-lite.qws b/sharpmz-lite.qws new file mode 100644 index 0000000..185237e Binary files /dev/null and b/sharpmz-lite.qws differ diff --git a/sharpmz-lite.rbf b/sharpmz-lite.rbf new file mode 100644 index 0000000..7f3691a Binary files /dev/null and b/sharpmz-lite.rbf differ diff --git a/sharpmz-lite.srf b/sharpmz-lite.srf new file mode 100644 index 0000000..96a7c6e --- /dev/null +++ b/sharpmz-lite.srf @@ -0,0 +1,17 @@ +{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored filter at sys_top.sdc(15): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(14): Argument is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored filter at sys_top.sdc(32): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|T80s:T80s\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/sharpmz-lite_assignment_defaults.qdf b/sharpmz-lite_assignment_defaults.qdf new file mode 100644 index 0000000..3420a0f --- /dev/null +++ b/sharpmz-lite_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 18:06:35 June 18, 2018 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/sharpmz.qpf b/sharpmz.qpf new file mode 100644 index 0000000..5625625 --- /dev/null +++ b/sharpmz.qpf @@ -0,0 +1,13 @@ +# +# please keep this file read-only! +# Quartus changes this file everytime revision is switched, +# and it will be marked as changed with every commit. +# + +QUARTUS_VERSION = "16.1" +DATE = "23:13:02 April 27, 2017" + +# Revisions + +PROJECT_REVISION = "sharpmz-lite" +PROJECT_REVISION = "sharpmz" diff --git a/sharpmz.qsf b/sharpmz.qsf new file mode 100644 index 0000000..45d75c4 --- /dev/null +++ b/sharpmz.qsf @@ -0,0 +1,357 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name TOP_LEVEL_ENTITY sys_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name SEED 1 + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] + +#============================================================ +# SDIO +#============================================================ +set_location_assignment PIN_AF25 -to SDIO_DAT[0] +set_location_assignment PIN_AF23 -to SDIO_DAT[1] +set_location_assignment PIN_AD26 -to SDIO_DAT[2] +set_location_assignment PIN_AF28 -to SDIO_DAT[3] +set_location_assignment PIN_AF27 -to SDIO_CMD +set_location_assignment PIN_AH26 -to SDIO_CLK +set_location_assignment PIN_AH7 -to SDIO_CD + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_AE17 -to VGA_R[0] +set_location_assignment PIN_AE20 -to VGA_R[1] +set_location_assignment PIN_AF20 -to VGA_R[2] +set_location_assignment PIN_AH18 -to VGA_R[3] +set_location_assignment PIN_AH19 -to VGA_R[4] +set_location_assignment PIN_AF21 -to VGA_R[5] + +set_location_assignment PIN_AE19 -to VGA_G[0] +set_location_assignment PIN_AG15 -to VGA_G[1] +set_location_assignment PIN_AF18 -to VGA_G[2] +set_location_assignment PIN_AG18 -to VGA_G[3] +set_location_assignment PIN_AG19 -to VGA_G[4] +set_location_assignment PIN_AG20 -to VGA_G[5] + +set_location_assignment PIN_AG21 -to VGA_B[0] +set_location_assignment PIN_AA20 -to VGA_B[1] +set_location_assignment PIN_AE22 -to VGA_B[2] +set_location_assignment PIN_AF22 -to VGA_B[3] +set_location_assignment PIN_AH23 -to VGA_B[4] +set_location_assignment PIN_AH21 -to VGA_B[5] + +set_location_assignment PIN_AH22 -to VGA_HS +set_location_assignment PIN_AG24 -to VGA_VS + +set_location_assignment PIN_AH27 -to VGA_EN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + +#============================================================ +# AUDIO +#============================================================ +set_location_assignment PIN_AC24 -to AUDIO_L +set_location_assignment PIN_AE25 -to AUDIO_R +set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_Y11 -to SDRAM_A[0] +set_location_assignment PIN_AA26 -to SDRAM_A[1] +set_location_assignment PIN_AA13 -to SDRAM_A[2] +set_location_assignment PIN_AA11 -to SDRAM_A[3] +set_location_assignment PIN_W11 -to SDRAM_A[4] +set_location_assignment PIN_Y19 -to SDRAM_A[5] +set_location_assignment PIN_AB23 -to SDRAM_A[6] +set_location_assignment PIN_AC23 -to SDRAM_A[7] +set_location_assignment PIN_AC22 -to SDRAM_A[8] +set_location_assignment PIN_C12 -to SDRAM_A[9] +set_location_assignment PIN_AB26 -to SDRAM_A[10] +set_location_assignment PIN_AD17 -to SDRAM_A[11] +set_location_assignment PIN_D12 -to SDRAM_A[12] +set_location_assignment PIN_Y17 -to SDRAM_BA[0] +set_location_assignment PIN_AB25 -to SDRAM_BA[1] + +set_location_assignment PIN_E8 -to SDRAM_DQ[0] +set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_D11 -to SDRAM_DQ[2] +set_location_assignment PIN_W12 -to SDRAM_DQ[3] +set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +set_location_assignment PIN_D8 -to SDRAM_DQ[5] +set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +set_location_assignment PIN_AG13 -to SDRAM_DQML +set_location_assignment PIN_AF13 -to SDRAM_DQMH + +set_location_assignment PIN_AD20 -to SDRAM_CLK +set_location_assignment PIN_AG10 -to SDRAM_CKE + +set_location_assignment PIN_AA19 -to SDRAM_nWE +set_location_assignment PIN_AA18 -to SDRAM_nCAS +set_location_assignment PIN_Y18 -to SDRAM_nCS +set_location_assignment PIN_W14 -to SDRAM_nRAS + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# I/O +#============================================================ +set_location_assignment PIN_Y15 -to LED_USER +set_location_assignment PIN_AA15 -to LED_HDD +set_location_assignment PIN_AG28 -to LED_POWER + +set_location_assignment PIN_AH24 -to BTN_USER +set_location_assignment PIN_AG25 -to BTN_OSD +set_location_assignment PIN_AG23 -to BTN_RESET + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + +set_global_assignment -name CDF_FILE jtag.cdf +set_global_assignment -name QIP_FILE sys/sys.qip +set_global_assignment -name QSYS_FILE sys/vip.qsys +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/sharpmz.sdc b/sharpmz.sdc new file mode 100644 index 0000000..b7bd86e --- /dev/null +++ b/sharpmz.sdc @@ -0,0 +1,213 @@ +## Generated SDC file "sharpmz.sdc" + +## Copyright (C) 1991-2011 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition" + +## DATE "Mon Jul 16 23:49:03 2012" + +## +## DEVICE "EP3C16F484C6" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] +create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}] +create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}] +#create_clock -name {MCLK} -period 10.000 -waveform { 0.000 5.000 } [get_ports {SDRAM_CLK}] +#create_clock -name {SDCLK} -period 100.000 -waveform { 0.000 50.000 } [get_ports {SDIO_CLK}] +#create_clock -name {VMCLK} -period 10.000 -waveform { 0.000 5.000 } + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[0]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[0]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[1]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[1]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[2]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[2]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[3]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[3]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[4]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[4]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[5]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[5]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[6]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[6]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[7]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[7]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[8]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[8]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[9]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[9]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[10]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[10]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[11]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[11]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[12]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[12]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[13]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[13]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[14]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[14]}] +#set_input_delay -add_delay -max -clock [get_clocks {VMCLK}] 6.000 [get_ports {SDRAM_DQ[15]}] +#set_input_delay -add_delay -min -clock [get_clocks {VMCLK}] 0.000 [get_ports {SDRAM_DQ[15]}] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[0]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[1]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[2]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[3]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[4]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[5]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[6]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[7]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[8]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[9]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_A[10]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nCAS}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nCS}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[0]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[1]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[2]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[3]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[4]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[5]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[6]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[7]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[8]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[9]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[10]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[11]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[12]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[13]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[14]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQ[15]}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQML}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nRAS}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_DQMH}] +#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nWE}] +#set_output_delay -add_delay -clock [get_clocks {SDCLK}] 0.000 [get_ports {SDIO_CMD}] +#set_output_delay -add_delay -clock [get_clocks {SDCLK}] 0.000 [get_ports {SDIO_DAT[3]}] +set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 0.000 [get_ports {altera_reserved_tdo}] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] +set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}] +set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] +set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] +set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] +set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] +set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|*resetlatch}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[33]}] +set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[0]}] +set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[34]}] +set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|*MonDReg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] +set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|*jdo*}] +set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|ir*}] +set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go}] +set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_writedata_d1*|*}] -to [get_registers *] +set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_nativeaddress_d1*|*}] -to [get_registers *] +set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_readdata_p1*}] -to [get_registers *] +set_false_path -from [get_keepers -nocase {*the*clock*|slave_readdata_p1*}] -to [get_registers *] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/sharpmz.tl b/sharpmz.tl new file mode 100644 index 0000000..f456e92 --- /dev/null +++ b/sharpmz.tl @@ -0,0 +1,371 @@ +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. + +# Quartus Prime: Generate Tcl File for Project +# File: sharpmz.tcl +# Generated on: Wed Jun 20 13:50:16 2018 + +# Load Quartus Prime Tcl Project package +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "sharpmz"]} { + puts "Project sharpmz is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists sharpmz]} { + project_open -revision sharpmz-lite sharpmz + } else { + project_new -revision sharpmz-lite sharpmz + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name VERILOG_MACRO "LITE=1" + set_global_assignment -name FAMILY "Cyclone V" + set_global_assignment -name DEVICE 5CSEBA6U23I7 + set_global_assignment -name TOP_LEVEL_ENTITY sys_top + set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 + set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition" + set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" + set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA + set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 + set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + set_global_assignment -name GENERATE_RBF_FILE ON + set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + set_global_assignment -name SAVE_DISK_SPACE OFF + set_global_assignment -name SMART_RECOMPILE ON + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" + set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 + set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF + set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS + set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + set_global_assignment -name SEED 1 + set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + set_global_assignment -name CDF_FILE jtag.cdf + set_global_assignment -name QIP_FILE sys/sys.qip + set_global_assignment -name VHDL_FILE jtag_uart_0.vhd + set_global_assignment -name SYSTEMVERILOG_FILE sharpmz.sv + set_global_assignment -name VHDL_FILE mz80c/T80/T80_Reg.vhd + set_global_assignment -name VHDL_FILE mz80c/T80/T80_Pack.vhd + set_global_assignment -name VHDL_FILE mz80c/T80/T80_MCode.vhd + set_global_assignment -name VHDL_FILE mz80c/T80/T80_ALU.vhd + set_global_assignment -name VHDL_FILE mz80c/T80/T80.vhd + set_global_assignment -name VHDL_FILE mz80c/T80/T80s.vhd + set_global_assignment -name VHDL_FILE mz80c/cmt.vhd + set_global_assignment -name VHDL_FILE mz80c/counter0.vhd + set_global_assignment -name VHDL_FILE mz80c/counter1.vhd + set_global_assignment -name VHDL_FILE mz80c/counter2.vhd + set_global_assignment -name VHDL_FILE mz80c/dpram64k.vhd + set_global_assignment -name VHDL_FILE mz80c/dpram.vhd + set_global_assignment -name VHDL_FILE mz80c/i8253.vhd + set_global_assignment -name VHDL_FILE mz80c/i8255.vhd + set_global_assignment -name VHDL_FILE mz80c/keymatrix.vhd + set_global_assignment -name VHDL_FILE mz80c/ls367.vhd + set_global_assignment -name VHDL_FILE mz80c/mctrl.vhd + set_global_assignment -name VHDL_FILE mz80c/sharpmz.vhd + set_global_assignment -name VHDL_FILE mz80c/pcg.vhd + set_global_assignment -name VERILOG_FILE mz80c/pll_mz80c.v + set_global_assignment -name VERILOG_FILE mz80c/pll_mz80c_1.v + set_global_assignment -name VHDL_FILE mz80c/ps2kb.vhd + set_global_assignment -name VHDL_FILE mz80c/ScanConv.vhd + set_global_assignment -name VHDL_FILE mz80c/dprom.vhd + set_global_assignment -name VHDL_FILE mz80c/videoout.vhd + set_global_assignment -name VHDL_FILE mz80c/clk_div.vhd + set_global_assignment -name VHDL_FILE mz80c/clkgen.vhd + set_global_assignment -name VHDL_FILE mz80c/mrom.vhd + set_global_assignment -name VHDL_FILE mz80c/ram1k.vhd + set_global_assignment -name QIP_FILE mz80c/linebuf.qip + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + set_location_assignment PIN_U9 -to ADC_CONVST + set_location_assignment PIN_V10 -to ADC_SCK + set_location_assignment PIN_AC4 -to ADC_SDI + set_location_assignment PIN_AD4 -to ADC_SDO + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] + set_location_assignment PIN_AG9 -to ARDUINO_IO[3] + set_location_assignment PIN_U14 -to ARDUINO_IO[4] + set_location_assignment PIN_U13 -to ARDUINO_IO[5] + set_location_assignment PIN_AG8 -to ARDUINO_IO[6] + set_location_assignment PIN_AH8 -to ARDUINO_IO[7] + set_location_assignment PIN_AF17 -to ARDUINO_IO[8] + set_location_assignment PIN_AE15 -to ARDUINO_IO[9] + set_location_assignment PIN_AF15 -to ARDUINO_IO[10] + set_location_assignment PIN_AG16 -to ARDUINO_IO[11] + set_location_assignment PIN_AH11 -to ARDUINO_IO[12] + set_location_assignment PIN_AH12 -to ARDUINO_IO[13] + set_location_assignment PIN_AH9 -to ARDUINO_IO[14] + set_location_assignment PIN_AG11 -to ARDUINO_IO[15] + set_location_assignment PIN_AF25 -to SDIO_DAT[0] + set_location_assignment PIN_AF23 -to SDIO_DAT[1] + set_location_assignment PIN_AD26 -to SDIO_DAT[2] + set_location_assignment PIN_AF28 -to SDIO_DAT[3] + set_location_assignment PIN_AF27 -to SDIO_CMD + set_location_assignment PIN_AH26 -to SDIO_CLK + set_location_assignment PIN_AH7 -to SDIO_CD + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* + set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] + set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD + set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD + set_location_assignment PIN_AE17 -to VGA_R[0] + set_location_assignment PIN_AE20 -to VGA_R[1] + set_location_assignment PIN_AF20 -to VGA_R[2] + set_location_assignment PIN_AH18 -to VGA_R[3] + set_location_assignment PIN_AH19 -to VGA_R[4] + set_location_assignment PIN_AF21 -to VGA_R[5] + set_location_assignment PIN_AE19 -to VGA_G[0] + set_location_assignment PIN_AG15 -to VGA_G[1] + set_location_assignment PIN_AF18 -to VGA_G[2] + set_location_assignment PIN_AG18 -to VGA_G[3] + set_location_assignment PIN_AG19 -to VGA_G[4] + set_location_assignment PIN_AG20 -to VGA_G[5] + set_location_assignment PIN_AG21 -to VGA_B[0] + set_location_assignment PIN_AA20 -to VGA_B[1] + set_location_assignment PIN_AE22 -to VGA_B[2] + set_location_assignment PIN_AF22 -to VGA_B[3] + set_location_assignment PIN_AH23 -to VGA_B[4] + set_location_assignment PIN_AH21 -to VGA_B[5] + set_location_assignment PIN_AH22 -to VGA_HS + set_location_assignment PIN_AG24 -to VGA_VS + set_location_assignment PIN_AH27 -to VGA_EN + set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* + set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + set_location_assignment PIN_AC24 -to AUDIO_L + set_location_assignment PIN_AE25 -to AUDIO_R + set_location_assignment PIN_AG26 -to AUDIO_SPDIF + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* + set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + set_location_assignment PIN_Y11 -to SDRAM_A[0] + set_location_assignment PIN_AA26 -to SDRAM_A[1] + set_location_assignment PIN_AA13 -to SDRAM_A[2] + set_location_assignment PIN_AA11 -to SDRAM_A[3] + set_location_assignment PIN_W11 -to SDRAM_A[4] + set_location_assignment PIN_Y19 -to SDRAM_A[5] + set_location_assignment PIN_AB23 -to SDRAM_A[6] + set_location_assignment PIN_AC23 -to SDRAM_A[7] + set_location_assignment PIN_AC22 -to SDRAM_A[8] + set_location_assignment PIN_C12 -to SDRAM_A[9] + set_location_assignment PIN_AB26 -to SDRAM_A[10] + set_location_assignment PIN_AD17 -to SDRAM_A[11] + set_location_assignment PIN_D12 -to SDRAM_A[12] + set_location_assignment PIN_Y17 -to SDRAM_BA[0] + set_location_assignment PIN_AB25 -to SDRAM_BA[1] + set_location_assignment PIN_E8 -to SDRAM_DQ[0] + set_location_assignment PIN_V12 -to SDRAM_DQ[1] + set_location_assignment PIN_D11 -to SDRAM_DQ[2] + set_location_assignment PIN_W12 -to SDRAM_DQ[3] + set_location_assignment PIN_AH13 -to SDRAM_DQ[4] + set_location_assignment PIN_D8 -to SDRAM_DQ[5] + set_location_assignment PIN_AH14 -to SDRAM_DQ[6] + set_location_assignment PIN_AF7 -to SDRAM_DQ[7] + set_location_assignment PIN_AE24 -to SDRAM_DQ[8] + set_location_assignment PIN_AD23 -to SDRAM_DQ[9] + set_location_assignment PIN_AE6 -to SDRAM_DQ[10] + set_location_assignment PIN_AE23 -to SDRAM_DQ[11] + set_location_assignment PIN_AG14 -to SDRAM_DQ[12] + set_location_assignment PIN_AD5 -to SDRAM_DQ[13] + set_location_assignment PIN_AF4 -to SDRAM_DQ[14] + set_location_assignment PIN_AH3 -to SDRAM_DQ[15] + set_location_assignment PIN_AG13 -to SDRAM_DQML + set_location_assignment PIN_AF13 -to SDRAM_DQMH + set_location_assignment PIN_AD20 -to SDRAM_CLK + set_location_assignment PIN_AG10 -to SDRAM_CKE + set_location_assignment PIN_AA19 -to SDRAM_nWE + set_location_assignment PIN_AA18 -to SDRAM_nCAS + set_location_assignment PIN_Y18 -to SDRAM_nCS + set_location_assignment PIN_W14 -to SDRAM_nRAS + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* + set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + set_location_assignment PIN_Y15 -to LED_USER + set_location_assignment PIN_AA15 -to LED_HDD + set_location_assignment PIN_AG28 -to LED_POWER + set_location_assignment PIN_AH24 -to BTN_USER + set_location_assignment PIN_AG25 -to BTN_OSD + set_location_assignment PIN_AG23 -to BTN_RESET + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* + set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + set_location_assignment PIN_V11 -to FPGA_CLK1_50 + set_location_assignment PIN_Y13 -to FPGA_CLK2_50 + set_location_assignment PIN_E11 -to FPGA_CLK3_50 + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS + set_location_assignment PIN_U10 -to HDMI_I2C_SCL + set_location_assignment PIN_AA4 -to HDMI_I2C_SDA + set_location_assignment PIN_T13 -to HDMI_I2S + set_location_assignment PIN_T11 -to HDMI_LRCLK + set_location_assignment PIN_U11 -to HDMI_MCLK + set_location_assignment PIN_T12 -to HDMI_SCLK + set_location_assignment PIN_AG5 -to HDMI_TX_CLK + set_location_assignment PIN_AD19 -to HDMI_TX_DE + set_location_assignment PIN_AD12 -to HDMI_TX_D[0] + set_location_assignment PIN_AE12 -to HDMI_TX_D[1] + set_location_assignment PIN_W8 -to HDMI_TX_D[2] + set_location_assignment PIN_Y8 -to HDMI_TX_D[3] + set_location_assignment PIN_AD11 -to HDMI_TX_D[4] + set_location_assignment PIN_AD10 -to HDMI_TX_D[5] + set_location_assignment PIN_AE11 -to HDMI_TX_D[6] + set_location_assignment PIN_Y5 -to HDMI_TX_D[7] + set_location_assignment PIN_AF10 -to HDMI_TX_D[8] + set_location_assignment PIN_Y4 -to HDMI_TX_D[9] + set_location_assignment PIN_AE9 -to HDMI_TX_D[10] + set_location_assignment PIN_AB4 -to HDMI_TX_D[11] + set_location_assignment PIN_AE7 -to HDMI_TX_D[12] + set_location_assignment PIN_AF6 -to HDMI_TX_D[13] + set_location_assignment PIN_AF8 -to HDMI_TX_D[14] + set_location_assignment PIN_AF5 -to HDMI_TX_D[15] + set_location_assignment PIN_AE4 -to HDMI_TX_D[16] + set_location_assignment PIN_AH2 -to HDMI_TX_D[17] + set_location_assignment PIN_AH4 -to HDMI_TX_D[18] + set_location_assignment PIN_AH5 -to HDMI_TX_D[19] + set_location_assignment PIN_AH6 -to HDMI_TX_D[20] + set_location_assignment PIN_AG6 -to HDMI_TX_D[21] + set_location_assignment PIN_AF9 -to HDMI_TX_D[22] + set_location_assignment PIN_AE8 -to HDMI_TX_D[23] + set_location_assignment PIN_T8 -to HDMI_TX_HS + set_location_assignment PIN_AF11 -to HDMI_TX_INT + set_location_assignment PIN_V13 -to HDMI_TX_VS + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + set_location_assignment PIN_AH17 -to KEY[0] + set_location_assignment PIN_AH16 -to KEY[1] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + set_location_assignment PIN_W15 -to LED[0] + set_location_assignment PIN_AA24 -to LED[1] + set_location_assignment PIN_V16 -to LED[2] + set_location_assignment PIN_V15 -to LED[3] + set_location_assignment PIN_AF26 -to LED[4] + set_location_assignment PIN_AE26 -to LED[5] + set_location_assignment PIN_Y16 -to LED[6] + set_location_assignment PIN_AA23 -to LED[7] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + set_location_assignment PIN_Y24 -to SW[0] + set_location_assignment PIN_W24 -to SW[1] + set_location_assignment PIN_W21 -to SW[2] + set_location_assignment PIN_W20 -to SW[3] + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Including default assignments + set_global_assignment -name REVISION_TYPE BASE -family "Cyclone V" + set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS OFF -family "Cyclone V" + set_global_assignment -name TIMEQUEST_CCPP_TRADEOFF_TOLERANCE 0 -family "Cyclone V" + set_global_assignment -name TDC_CCPP_TRADEOFF_TOLERANCE 30 -family "Cyclone V" + set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -family "Cyclone V" + set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" + set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -family "Cyclone V" + set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" + set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ON -family "Cyclone V" + set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" -family "Cyclone V" + set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -family "Cyclone V" + set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -family "Cyclone V" + set_global_assignment -name AUTO_DELAY_CHAINS ON -family "Cyclone V" + set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON -family "Cyclone V" + set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ -family "Cyclone V" + set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION ON -family "Cyclone V" + set_global_assignment -name ENABLE_OCT_DONE OFF -family "Cyclone V" + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/sharpmz.vhd b/sharpmz.vhd new file mode 100644 index 0000000..ef8c2c8 --- /dev/null +++ b/sharpmz.vhd @@ -0,0 +1,1382 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sharpmz.vhd +-- Created: June 2018 +-- Author(s): Philip Smart +-- Description: Sharp MZ series compatible logic. +-- +-- This module is the main (top level) container for the Emulation. +-- +-- The design tries to work from top-down, where components which are common +-- to the Business and Personal MZ series are at the top (ie. main memory, +-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal) +-- to the machine specific modules and components. Some components are common +-- by their nature (ie. 8255 PIO) but these are instantiated within the lower +-- tree branch as their design use is less generic. +-- +-- The tree is as follows;- +-- +-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd +-- | -> mz80c_video.vhd +-- | -> pcg.vhd +-- | -> cmt.vhd (this may move to common and be shared with mz80b) +-- | -> keymatrix.vhd (common) +-- | -> pll.v (common) +-- | -> clkgen.vhd (common) +-- | -> T80 (common) +-- | -> i8255 (common) +-- | -> i8253 (common) +-- | -> dpram.vhd (common) +-- | -> dprom.vhd (common) +-- | -> mctrl.vhd (common) +-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv +-- | +-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development) +-- +-- The idea of the design is to keep the emulation as independent of the HPS +-- as possible (so it works standalone), only needing the HPS to set control registers, +-- load tape ram and overlay the menu system. This in theory should allow easier +-- porting if someone wants to port this emulator to another platform or even +-- target an non-HPS Cyclone chip and instantiate another CPU as the menu control. +-- +-- As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used +-- by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory (or the +-- external SDRAM) depending on wether I decide to cache entire Floppy Disks as per the CMT +-- unit. +-- +-- Credits: Credit to Nibbles Lab. 2012-2016, as I was originally going to port his mz80c_de0 emulator +-- based on a Terasic DE0 board. He used external memory and an instantiated NIOSII CPU +-- to provide a menu/control system. Some snippets of his code, such as the keyboard matrix +-- have been re-used in this emulation. +-- Copyright: (c) 2018 Philip Smart +-- +-- History: June 2018 - Initial creation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use pkgs.clkgen_pkg.all; +use pkgs.mctrl_pkg.all; + +entity sharpmz is + port( + -------------------- Clock Input ---------------------------- + clkmaster : in std_logic; -- Master Clock(50MHz) + clksys : out std_logic; -- System clock. + clkvid : out std_logic; -- Pixel base clock of video. + -------------------- Reset ---------------------------- + cold_reset : in std_logic; + warm_reset : in std_logic; + -------------------- main_leds ---------------------------- + main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0] + -------------------- PS2 ---------------------------- + ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data. + -------------------- VGA ---------------------------- + vga_hb_o : out std_logic; -- VGA Horizontal Blank + vga_vb_o : out std_logic; -- VGA Vertical Blank + vga_hs_o : out std_logic; -- VGA H_SYNC + vga_vs_o : out std_logic; -- VGA V_SYNC + vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0 + vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0] + vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0] + -------------------- AUDIO ------------------------------ + audio_l_o : out std_logic; + audio_r_o : out std_logic; + -------------------- HPS Interface ------------------------------ + ioctl_download : in std_logic; -- HPS Downloading to FPGA. + ioctl_upload : in std_logic; -- HPS Uploading from FPGA. + ioctl_clk : in std_logic; -- HPS I/O Clock. + ioctl_wr : in std_logic; -- HPS Write Enable to FPGA. + ioctl_rd : in std_logic; -- HPS Read Enable from FPGA. + ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. +); +end sharpmz; + +architecture rtl of sharpmz is + +-- Parent signals brought out onto wires. +-- +signal MZ_PS2_KEY : std_logic_vector(10 downto 0); +-- +-- Master Control signals and configuration. +-- +signal MZ_SYSTEM_RESET : std_logic; +signal MZ_MEMWR : std_logic; +-- +-- Signal BUS's +-- +signal CLKBUS : std_logic_vector(CLKBUS_WIDTH); +signal CONFIG : std_logic_vector(CONFIG_WIDTH); +signal DEBUG : std_logic_vector(DEBUG_WIDTH); +signal MZ_CMTBUS : std_logic_vector(CMTBUS_WIDTH); +-- +-- HPS Control. +-- +signal MZ_IOCTL_DOWNLOAD : std_logic; +signal MZ_IOCTL_UPLOAD : std_logic; +signal MZ_IOCTL_CLK : std_logic; +signal MZ_IOCTL_WR : std_logic; +signal MZ_IOCTL_RD : std_logic; +signal MZ_IOCTL_ADDR : std_logic_vector(24 downto 0); +signal MZ_IOCTL_DOUT : std_logic_vector(15 downto 0); +signal MZ_IOCTL_DIN_SYSROM : std_logic_vector(7 downto 0); +signal MZ_IOCTL_DIN_SYSRAM : std_logic_vector(7 downto 0); +signal MZ_IOCTL_DIN_MZ80C : std_logic_vector(15 downto 0); +signal MZ_IOCTL_DIN_MZ80B : std_logic_vector(15 downto 0); +signal MZ_IOCTL_DIN_MCTRL : std_logic_vector(15 downto 0); +signal MZ_IOCTL_WENROM : std_logic; +signal MZ_IOCTL_WENRAM : std_logic; +signal MZ_IOCTL_RENROM : std_logic; +signal MZ_IOCTL_RENRAM : std_logic; +-- +-- T80 for MZ80C +-- +signal MZ80C_RST_n : std_logic; +signal MZ80C_MREQ_n : std_logic; +signal MZ80C_BUSRQ_n : std_logic; +signal MZ80C_IORQ_n : std_logic; +signal MZ80C_WR_n : std_logic; +signal MZ80C_RD_n : std_logic; +signal MZ80C_MWR_n : std_logic; +signal MZ80C_MRD_n : std_logic; +signal MZ80C_IWR_n : std_logic; +signal MZ80C_WAIT_n : std_logic; +signal MZ80C_M1_n : std_logic; +signal MZ80C_RFSH_n : std_logic; +signal MZ80C_A16 : std_logic_vector(15 downto 0); +signal MZ80C_INT_n : std_logic; +signal MZ80C_DO : std_logic_vector(7 downto 0); +signal MZ80C_DI : std_logic_vector(7 downto 0); +signal MZ80C_BUSAK_n : std_logic; +signal MZ80C_CLK : std_logic; +signal MZ80C_CLKEN : std_logic; +signal MZ80C_NMI_n : std_logic; +signal MZ80C_HALT_n : std_logic; +-- +-- Tape Control +-- +signal MZ80C_CMTBUS : std_logic_vector(CMTBUS_WIDTH); +-- +-- Video +-- +signal MZ_R : std_logic; +signal MZ_B : std_logic; +signal MZ_G : std_logic; +signal MZ_HSYNC_n : std_logic; +signal MZ_VSYNC_n : std_logic; +signal MZ_HBLANK : std_logic; +signal MZ_VBLANK : std_logic; +-- +-- Selects for MZ80C. +-- +signal MZ80C_CS_ROM_n : std_logic; +signal MZ80C_CS_RAM_n : std_logic; +-- +-- Audio for MZ80C +-- +signal MZ80C_AUDIO_L : std_logic; +signal MZ80C_AUDIO_R : std_logic; +-- +-- Video for MZ80C +-- +signal MZ80C_R : std_logic; +signal MZ80C_G : std_logic; +signal MZ80C_B : std_logic; +signal MZ80C_HSYNC_n : std_logic; +signal MZ80C_VSYNC_n : std_logic; +signal MZ80C_HBLANK : std_logic; +signal MZ80C_VBLANK : std_logic; +-- +-- Debug for MZ80C +-- +signal MZ80C_DEBUG_LEDS : std_logic_vector(111 downto 0); +-- +-- T80 for MZ80B +-- +signal MZ80B_RST_n : std_logic; +signal MZ80B_MREQ_n : std_logic; +signal MZ80B_BUSRQ_n : std_logic; +signal MZ80B_IORQ_n : std_logic; +signal MZ80B_WR_n : std_logic; +signal MZ80B_RD_n : std_logic; +signal MZ80B_MWR_n : std_logic; +signal MZ80B_MRD_n : std_logic; +signal MZ80B_IWR_n : std_logic; +signal MZ80B_WAIT_n : std_logic; +signal MZ80B_M1_n : std_logic; +signal MZ80B_RFSH_n : std_logic; +signal MZ80B_A16 : std_logic_vector(15 downto 0); +signal MZ80B_INT_n : std_logic; +signal MZ80B_DO : std_logic_vector(7 downto 0); +signal MZ80B_DI : std_logic_vector(7 downto 0); +signal MZ80B_BUSAK_n : std_logic; +signal MZ80B_CLK : std_logic; +signal MZ80B_CLKEN : std_logic; +signal MZ80B_NMI_n : std_logic; +signal MZ80B_HALT_n : std_logic; +-- +-- Selects for MZ80B. +-- +signal MZ80B_CS_ROM_n : std_logic; +signal MZ80B_CS_RAM_n : std_logic; +-- +-- Audio for MZ80B +-- +signal MZ80B_AUDIO_L : std_logic; +signal MZ80B_AUDIO_R : std_logic; +-- +-- Tape Control +-- +signal MZ80B_CMTBUS : std_logic_vector(CMTBUS_WIDTH); +-- +-- Video for MZ80B +-- +signal MZ80B_R : std_logic; +signal MZ80B_G : std_logic; +signal MZ80B_B : std_logic; +signal MZ80B_HSYNC_n : std_logic; +signal MZ80B_VSYNC_n : std_logic; +signal MZ80B_HBLANK : std_logic; +signal MZ80B_VBLANK : std_logic; +--signal MZ80B_CLKVIDEO : std_logic; +-- +-- Debug for MZ80B +-- +signal MZ80B_DEBUG_LEDS : std_logic_vector(111 downto 0); +-- +-- T80 +-- +signal T80_RST_n : std_logic; +signal T80_MREQ_n : std_logic; +signal T80_BUSRQ_n : std_logic; +signal T80_IORQ_n : std_logic; +signal T80_WR_n : std_logic; +signal T80_RD_n : std_logic; +signal T80_MWR_n : std_logic; +signal T80_MRD_n : std_logic; +signal T80_WAIT_n : std_logic; +signal T80_M1_n : std_logic; +signal T80_RFSH_n : std_logic; +signal T80_A16 : std_logic_vector(15 downto 0); +signal T80_INT_n : std_logic; +signal T80_DO : std_logic_vector(7 downto 0); +signal T80_DI : std_logic_vector(7 downto 0); +signal T80_BUSAK_n : std_logic; +signal T80_CLKEN : std_logic; +signal T80_NMI_n : std_logic; +signal T80_HALT_n : std_logic; +-- +-- Decodes, control, misc +-- +signal WENSYSRAM : std_logic; +signal CSBANKSWITCH_n : std_logic; +-- +-- Monitor ROM +-- +signal DOSYSROM : std_logic_vector(7 downto 0); +signal CS_ROM_n : std_logic; +signal MROM_BANK : std_logic_vector(5 downto 0); +-- +-- Static RAM +-- +signal DOSYSRAM : std_logic_vector(7 downto 0); +signal CS_RAM_n : std_logic; +-- +-- Debug and internal process signals. +-- +signal Q0 : std_logic; +signal Q1 : std_logic; +signal Q2 : std_logic; +signal Q3 : std_logic; +signal debug_counter : integer range 0 to 13 := 0; +signal flip_counter : integer range 0 to 10000000 := 0; +signal block_flip : integer range 0 to 800000 := 0; +signal bank_flip : integer range 0 to 10000000 := 0; + +-- +-- Components +-- +component clkgen + Port ( + RST : in std_logic; -- Reset + + -- Clocks + CKBASE : in std_logic; -- Base system main clock. + CLKBUS : out std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module. + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Debug modes. + DEBUG : in std_logic_vector(DEBUG_WIDTH) + ); +end component; + +component T80se + generic ( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + Port ( + RESET_n : in std_logic; + CLK_n : in std_logic; -- NB. Clock is high active. + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end component; + +component dpram + generic ( + init_file : string; + widthad_a : natural; + width_a : natural; + widthad_b : natural; + width_b : natural; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + Port ( + clock_a : in std_logic := '1'; + clocken_a : in std_logic := '1'; + address_a : in std_logic_vector (widthad_a-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + wren_a : in std_logic := '0'; + q_a : out std_logic_vector (width_a-1 downto 0); + + clock_b : in std_logic; + clocken_b : in std_logic := '1'; + address_b : in std_logic_vector (widthad_b-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0); + wren_b : in std_logic := '0'; + q_b : out std_logic_vector (width_b-1 downto 0) + ); +end component; + +component mctrl + Port ( + -- Clock signals used by this module. + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); + + -- Reset's + COLD_RESET : in std_logic; + WARM_RESET : in std_logic; + SYSTEM_RESET : out std_logic; + + -- HPS Interface + IOCTL_CLK : in std_logic; -- HPS I/O Clock + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Different operations modes. + CONFIG : out std_logic_vector(CONFIG_WIDTH); + + -- Cassette magnetic tape signals. + CMTBUS : in std_logic_vector(CMTBUS_WIDTH); + + -- Debug modes. + DEBUG : out std_logic_vector(DEBUG_WIDTH) + ); +end component; + +component mz80c + PORT ( + -- Clocks + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module. + + -- Resets. + SYSTEM_RESET : in std_logic; + + -- Z80 CPU + T80_RST_n : in std_logic; + T80_CLK : in std_logic; + T80_CLKEN : out std_logic; + T80_WAIT_n : out std_logic; + T80_INT_n : out std_logic; + T80_NMI_n : out std_logic; + T80_BUSRQ_n : out std_logic; + T80_M1_n : in std_logic; + T80_MREQ_n : in std_logic; + T80_IORQ_n : in std_logic; + T80_RD_n : in std_logic; + T80_WR_n : in std_logic; + T80_RFSH_n : in std_logic; + T80_HALT_n : in std_logic; + T80_BUSAK_n : in std_logic; + T80_A16 : in std_logic_vector(15 downto 0); + T80_DI : out std_logic_vector(7 downto 0); + T80_DO : in std_logic_vector(7 downto 0); + + -- Chip selects to common resources. + CS_ROM_n : out std_logic; + CS_RAM_n : out std_logic; + + -- Audio. + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + + -- Video signals. + R : out std_logic; + G : out std_logic; + B : out std_logic; + HSYNC_n : out std_logic; + VSYNC_n : out std_logic; + HBLANK : out std_logic; + VBLANK : out std_logic; + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Cassette magnetic tape signals. + CMTBUS : out std_logic_vector(CMTBUS_WIDTH); + + -- I/O -- I/O down to the core. + PS2_KEY : in std_logic_vector(10 downto 0); + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status. + ); +end component; + +component mz80b + PORT ( + -- Clocks + CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by this module. + + -- Resets. + SYSTEM_RESET : in std_logic; + + -- Z80 CPU + T80_RST_n : in std_logic; + T80_CLK : in std_logic; + T80_CLKEN : out std_logic; + T80_WAIT_n : out std_logic; + T80_INT_n : out std_logic; + T80_NMI_n : out std_logic; + T80_BUSRQ_n : out std_logic; + T80_M1_n : in std_logic; + T80_MREQ_n : in std_logic; + T80_IORQ_n : in std_logic; + T80_RD_n : in std_logic; + T80_WR_n : in std_logic; + T80_RFSH_n : in std_logic; + T80_HALT_n : in std_logic; + T80_BUSAK_n : in std_logic; + T80_A16 : in std_logic_vector(15 downto 0); + T80_DI : out std_logic_vector(7 downto 0); + T80_DO : in std_logic_vector(7 downto 0); + + -- Chip selects to common resources. + CS_ROM_n : out std_logic; + CS_RAM_n : out std_logic; + + -- Audio. + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + + -- Video signals. + R : out std_logic; + G : out std_logic; + B : out std_logic; + HSYNC_n : out std_logic; + VSYNC_n : out std_logic; + HBLANK : out std_logic; + VBLANK : out std_logic; + + -- Different operations modes. + CONFIG : in std_logic_vector(CONFIG_WIDTH); + + -- Cassette magnetic tape signals. + CMTBUS : out std_logic_vector(CMTBUS_WIDTH); + + -- I/O -- I/O down to the core. + PS2_KEY : in std_logic_vector(10 downto 0); + + -- HPS Interface + IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA. + IOCTL_CLK : in std_logic; -- HPS I/O Clock + IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA. + IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS. + + -- Debug Status Leds + DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status. + ); +end component; + +begin + + -- + -- Instantiation + -- + CLKGEN0 : clkgen port map ( + RST => cold_reset, -- Reset + + -- Clocks + CKBASE => clkmaster, -- Input clocks from top level. + CLKBUS => CLKBUS, -- Clock signals created by this module. + + -- Different operations modes. + CONFIG => CONFIG, + + -- Debug modes. + DEBUG => DEBUG + ); + + CPU0 : T80se + generic map ( + Mode => 0, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write => 1, -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait => 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ) + port map ( + RESET_n => T80_RST_n, + CLK_n => CLKBUS(CKCPU), -- T80se uses positive level clock. + CLKEN => T80_CLKEN, + WAIT_n => T80_WAIT_n, + INT_n => T80_INT_n, + NMI_n => T80_NMI_n, + BUSRQ_n => T80_BUSRQ_n, + M1_n => T80_M1_n, + MREQ_n => T80_MREQ_n, + IORQ_n => T80_IORQ_n, + RD_n => T80_RD_n, + WR_n => T80_WR_n, + RFSH_n => T80_RFSH_n, --RFSH_n + HALT_n => T80_HALT_n, + BUSAK_n => T80_BUSAK_n, + A => T80_A16, + DI => T80_DI, + DO => T80_DO + ); + + -- MZ80 System RAM + -- + SYSRAM : dpram + generic map ( + init_file => "./mif/combined_mainmemory.mif", + widthad_a => 16, + width_a => 8, + widthad_b => 16, + width_b => 8, + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED" + ) + port map ( + clock_a => CLKBUS(CKMEM), + clocken_a => '1', + address_a => T80_A16, + data_a => T80_DO, + wren_a => WENSYSRAM, -- Pulse width controlled according to Master Clock. + q_a => DOSYSRAM, + + clock_b => MZ_IOCTL_CLK, + clocken_b => '1', + address_b => MZ_IOCTL_ADDR(15 downto 0), + data_b => MZ_IOCTL_DOUT(7 downto 0), + wren_b => MZ_IOCTL_WENRAM, + q_b => MZ_IOCTL_DIN_SYSRAM + ); + + -- MZ Monitor ROM + -- 0 = 80K MROM 4KBytes -> 0000:0fff 0000 bytes padding + -- 1 = 80x25 80K MROM 4KBytes -> 1000:1fff 0000 bytes padding + -- 2 = 80C MROM 4KBytes -> 2000:2fff 0000 bytes padding + -- 3 = 80x25 80C MROM 4KBytes -> 3000:3fff 0000 bytes padding + -- 4 = 1200 MROM 4KBytes -> 4000:4fff 0000 bytes padding + -- 5 = 80x25 1200 MROM 4KBytes -> 5000:5fff 0000 bytes padding + -- 6 = 80A MROM 4KBytes -> 6000:6fff 0000 bytes padding + -- 7 = 80x25 80A MROM 4KBytes -> 7000:7fff 0000 bytes padding + -- 8 = 700 MROM 4KBytes -> 8000:8fff 0000 bytes padding + -- 9 = 80x25 700 MROM 4KBytes -> 9000:9fff 0000 bytes padding + -- 10 = 80B MROM 2KBytes -> a000:afff 0800 bytes padding + -- 11 = 80x25 80B MROM 2KBytes -> b000:bfff 0800 bytes padding + -- + --SYSROM : dprom + SYSROM : dpram + generic map ( + init_file => "./mif/combined_mrom.mif", + widthad_a => 17, + width_a => 8, + widthad_b => 17, + width_b => 8, + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED" + ) + port map ( + clock_a => CLKBUS(CKMEM), + clocken_a => '1', + address_a => MROM_BANK & T80_A16(10 downto 0), + data_a => T80_DO, + wren_a => '0', -- Block writes from Z80 to ROM. + q_a => DOSYSROM, + + clock_b => MZ_IOCTL_CLK, + clocken_b => '1', + address_b => MZ_IOCTL_ADDR(16 downto 0), + data_b => MZ_IOCTL_DOUT(7 downto 0), + wren_b => MZ_IOCTL_WENROM, + q_b => MZ_IOCTL_DIN_SYSROM + ); + + CTRL0 : mctrl + port map ( + -- Clock + CLKBUS => CLKBUS, + + -- Reset's + COLD_RESET => cold_reset, + WARM_RESET => warm_reset, + SYSTEM_RESET => MZ_SYSTEM_RESET, + + -- HPS Interface + IOCTL_CLK => MZ_IOCTL_CLK, -- HPS I/O Clock + IOCTL_WR => MZ_IOCTL_WR, + IOCTL_RD => MZ_IOCTL_RD, + IOCTL_ADDR => MZ_IOCTL_ADDR, + IOCTL_DOUT => MZ_IOCTL_DOUT, + IOCTL_DIN => MZ_IOCTL_DIN_MCTRL, + + -- Different operations modes. + CONFIG => CONFIG, + + -- Cassette magnetic tape signals. + CMTBUS => MZ_CMTBUS, + + -- Debug modes. + DEBUG => DEBUG + ); + + MZ80HW : mz80c + port map ( + -- Clocks + CLKBUS => CLKBUS, -- Clock signals created by this module. + + -- Resets. + SYSTEM_RESET => MZ_SYSTEM_RESET, -- Reset generated by system based on Cold/Warm or trigger. + + -- Z80 CPU + T80_RST_n => MZ80C_RST_n, + T80_CLK => MZ80C_CLK, + T80_CLKEN => MZ80C_CLKEN, + T80_WAIT_n => MZ80C_WAIT_n, + T80_INT_n => MZ80C_INT_n, + T80_NMI_n => MZ80C_NMI_n, + T80_BUSRQ_n => MZ80C_BUSRQ_n, + T80_M1_n => MZ80C_M1_n, + T80_MREQ_n => MZ80C_MREQ_n, + T80_IORQ_n => MZ80C_IORQ_n, + T80_RD_n => MZ80C_RD_n, + T80_WR_n => MZ80C_WR_n, + T80_RFSH_n => MZ80C_RFSH_n, --RFSH_n + T80_HALT_n => MZ80C_HALT_n, + T80_BUSAK_n => MZ80C_BUSAK_n, + T80_A16 => MZ80C_A16, + T80_DI => MZ80C_DI, + T80_DO => MZ80C_DO, + + -- Chip selects to common resources. + CS_ROM_n => MZ80C_CS_ROM_n, + CS_RAM_n => MZ80C_CS_RAM_n, + + -- Audio. + AUDIO_L => MZ80C_AUDIO_L, + AUDIO_R => MZ80C_AUDIO_R, + + -- Video signals. + R => MZ80C_R, + G => MZ80C_G, + B => MZ80C_B, + HSYNC_n => MZ80C_HSYNC_n, + VSYNC_n => MZ80C_VSYNC_n, + HBLANK => MZ80C_HBLANK, + VBLANK => MZ80C_VBLANK, + + -- Different operations modes. + CONFIG => CONFIG, + + -- CMT status signals. + CMTBUS => MZ80C_CMTBUS, + + -- I/O -- I/O down to the core. + PS2_KEY => MZ_PS2_KEY, + + -- HPS Interface + IOCTL_DOWNLOAD => MZ_IOCTL_DOWNLOAD, + IOCTL_UPLOAD => MZ_IOCTL_UPLOAD, + IOCTL_CLK => MZ_IOCTL_CLK, -- HPS I/O Clock + IOCTL_WR => MZ_IOCTL_WR, + IOCTL_RD => MZ_IOCTL_RD, + IOCTL_ADDR => MZ_IOCTL_ADDR, + IOCTL_DOUT => MZ_IOCTL_DOUT, + IOCTL_DIN => MZ_IOCTL_DIN_MZ80C, + + -- Debug Status Leds + DEBUG_STATUS_LEDS=> MZ80C_DEBUG_LEDS + ); + + MZ80BHW : mz80b + port map ( + -- Clocks + CLKBUS => CLKBUS, -- Clock signals created by this module. + + -- Resets. + SYSTEM_RESET => MZ_SYSTEM_RESET, -- Reset generated by system based on Cold/Warm or trigger. + + -- Z80 CPU + T80_RST_n => MZ80B_RST_n, + T80_CLK => MZ80B_CLK, + T80_CLKEN => MZ80B_CLKEN, + T80_WAIT_n => MZ80B_WAIT_n, + T80_INT_n => MZ80B_INT_n, + T80_NMI_n => MZ80B_NMI_n, + T80_BUSRQ_n => MZ80B_BUSRQ_n, + T80_M1_n => MZ80B_M1_n, + T80_MREQ_n => MZ80B_MREQ_n, + T80_IORQ_n => MZ80B_IORQ_n, + T80_RD_n => MZ80B_RD_n, + T80_WR_n => MZ80B_WR_n, + T80_RFSH_n => MZ80B_RFSH_n, --RFSH_n + T80_HALT_n => MZ80B_HALT_n, + T80_BUSAK_n => MZ80B_BUSAK_n, + T80_A16 => MZ80B_A16, + T80_DI => MZ80B_DI, + T80_DO => MZ80B_DO, + + -- Chip selects to common resources. + CS_ROM_n => MZ80B_CS_ROM_n, + CS_RAM_n => MZ80B_CS_RAM_n, + + -- Audio. + AUDIO_L => MZ80B_AUDIO_L, + AUDIO_R => MZ80B_AUDIO_R, + + -- Video signals. + R => MZ80B_R, + G => MZ80B_G, + B => MZ80B_B, + HSYNC_n => MZ80B_HSYNC_n, + VSYNC_n => MZ80B_VSYNC_n, + HBLANK => MZ80B_HBLANK, + VBLANK => MZ80B_VBLANK, + + -- Different operations modes. + CONFIG => CONFIG, + + -- CMT status signals. + CMTBUS => MZ80B_CMTBUS, + + -- I/O -- I/O down to the core. + PS2_KEY => MZ_PS2_KEY, + + -- HPS Interface + IOCTL_DOWNLOAD => MZ_IOCTL_DOWNLOAD, + IOCTL_UPLOAD => MZ_IOCTL_UPLOAD, + IOCTL_CLK => MZ_IOCTL_CLK, -- HPS I/O Clock + IOCTL_WR => MZ_IOCTL_WR, + IOCTL_RD => MZ_IOCTL_RD, + IOCTL_ADDR => MZ_IOCTL_ADDR, + IOCTL_DOUT => MZ_IOCTL_DOUT, + IOCTL_DIN => MZ_IOCTL_DIN_MZ80B, + + -- Debug Status Leds + DEBUG_STATUS_LEDS=> MZ80B_DEBUG_LEDS + ); + + -- Clocks. + -- + --clksys <= CLKBUS(CKMEM); -- System clock. + clksys <= CLKBUS(CKHPS); -- HPS clock. + clkvid <= CLKBUS(CKVIDEO); -- Video pixel clock output. + + -- Multiplexer -> Signals to enabled hardware. + -- + MZ80C_RST_n <= T80_RST_n when CONFIG(MZ_80C) = '1' else '1'; -- If not selected, hold in reset. + MZ80B_RST_n <= T80_RST_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_CLK <= CLKBUS(CKCPU) when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_CLK <= CLKBUS(CKCPU) when CONFIG(MZ_80B) = '1' else '1'; + T80_CLKEN <= MZ80C_CLKEN when CONFIG(MZ_80C) = '1' else MZ80B_CLKEN; + T80_WAIT_n <= MZ80C_WAIT_n when CONFIG(MZ_80C) = '1' else MZ80B_WAIT_n; + T80_INT_n <= MZ80C_INT_n when CONFIG(MZ_80C) = '1' else MZ80B_INT_n; + T80_NMI_n <= MZ80C_NMI_n when CONFIG(MZ_80C) = '1' else MZ80B_NMI_n; + T80_BUSRQ_n <= MZ80C_BUSRQ_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80C_M1_n <= T80_M1_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_M1_n <= T80_M1_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_MREQ_n <= T80_MREQ_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_MREQ_n <= T80_MREQ_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_IORQ_n <= T80_IORQ_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_IORQ_n <= T80_IORQ_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_RD_n <= T80_RD_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_RD_n <= T80_RD_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_WR_n <= T80_WR_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_WR_n <= T80_WR_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_RFSH_n <= T80_RFSH_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_RFSH_n <= T80_RFSH_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_HALT_n <= T80_HALT_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_HALT_n <= T80_HALT_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_BUSAK_n <= T80_BUSAK_n when CONFIG(MZ_80C) = '1' else '1'; + MZ80B_BUSAK_n <= T80_BUSAK_n when CONFIG(MZ_80B) = '1' else '1'; + MZ80C_A16 <= T80_A16 when CONFIG(MZ_80C) = '1' else (others=>'1'); + MZ80B_A16 <= T80_A16 when CONFIG(MZ_80B) = '1' else (others=>'1'); + MZ_CMTBUS <= MZ80C_CMTBUS when CONFIG(MZ_80C) = '1' else MZ80B_CMTBUS; + T80_DI <= DOSYSRAM when CS_RAM_n ='0' and T80_RD_n = '0' -- Read from System RAM + else + DOSYSROM when CS_ROM_n ='0' and T80_RD_n = '0' -- Read from System ROM + else + MZ80C_DI when CONFIG(MZ_80C) = '1' + else + MZ80B_DI when CONFIG(MZ_80B) = '1' + else + (others=>'1'); -- Float the bus as high when not driven. + MZ80C_DO <= T80_DO when CONFIG(MZ_80C) = '1' else (others=>'1'); + MZ80B_DO <= T80_DO when CONFIG(MZ_80B) = '1' else (others=>'1'); + CS_ROM_n <= MZ80C_CS_ROM_n when CONFIG(MZ_80C) = '1' else MZ80B_CS_ROM_n; + CS_RAM_n <= MZ80C_CS_RAM_n when CONFIG(MZ_80C) = '1' else MZ80B_CS_RAM_n; + audio_l_o <= MZ80C_AUDIO_L when CONFIG(MZ_80C) = '1' else MZ80B_AUDIO_L; + audio_r_o <= MZ80C_AUDIO_R when CONFIG(MZ_80C) = '1' else MZ80B_AUDIO_R; + MZ_R <= MZ80C_R when CONFIG(MZ_80C) = '1' else MZ80B_R; + MZ_G <= MZ80C_G when CONFIG(MZ_80C) = '1' else MZ80B_G; + MZ_B <= MZ80C_B when CONFIG(MZ_80C) = '1' else MZ80B_B; + MZ_HSYNC_n <= MZ80C_HSYNC_n when CONFIG(MZ_80C) = '1' else MZ80B_HSYNC_n; + MZ_VSYNC_n <= MZ80C_VSYNC_n when CONFIG(MZ_80C) = '1' else MZ80B_VSYNC_n; + MZ_HBLANK <= MZ80C_HBLANK when CONFIG(MZ_80C) = '1' else MZ80B_HBLANK; + MZ_VBLANK <= MZ80C_VBLANK when CONFIG(MZ_80C) = '1' else MZ80B_VBLANK; + + -- VGA can be output in original format or via the Scan converter to increase line width. + -- + vga_hs_o <= not MZ_HSYNC_n; + vga_vs_o <= not MZ_VSYNC_n; + vga_r_o <= ('0', '0', MZ_R, MZ_R, MZ_R, MZ_R, MZ_R, MZ_R); + vga_g_o <= ('0', '0', MZ_G, MZ_G, MZ_G, MZ_G, MZ_G, MZ_G); + vga_b_o <= ('0', '0', MZ_B, MZ_B, MZ_B, MZ_B, MZ_B, MZ_B); + vga_vb_o <= MZ_VBLANK; + vga_hb_o <= MZ_HBLANK; + + -- Parent signals onto local wires. + -- + MZ_PS2_KEY <= ps2_key; + MZ_IOCTL_DOWNLOAD <= ioctl_download; + MZ_IOCTL_UPLOAD <= ioctl_upload; + MZ_IOCTL_CLK <= ioctl_clk; + MZ_IOCTL_WR <= ioctl_wr; + MZ_IOCTL_RD <= ioctl_rd; + MZ_IOCTL_ADDR <= ioctl_addr; + MZ_IOCTL_DOUT <= ioctl_dout; + ioctl_din <= X"00" & MZ_IOCTL_DIN_SYSROM when MZ_IOCTL_RENROM = '1' + else + X"00" & MZ_IOCTL_DIN_SYSRAM when MZ_IOCTL_RENRAM = '1' + else + MZ_IOCTL_DIN_MCTRL when IOCTL_ADDR(24 downto 4) = "100000000000000000000" + else + MZ_IOCTL_DIN_MZ80C when CONFIG(MZ_80C) = '1' + else + MZ_IOCTL_DIN_MZ80B when CONFIG(MZ_80B) = '1' + else + (others=>'0'); + + -- + -- Control Signals + -- + T80_MRD_n <= T80_MREQ_n or T80_RD_n; + T80_MWR_n <= T80_MREQ_n or T80_WR_n; + T80_RST_n <= not MZ_SYSTEM_RESET; + -- + MZ_MEMWR <= not T80_WR_n; + WENSYSRAM <= MZ_MEMWR when CS_RAM_n = '0' -- Write enable to System RAM + else '0'; + MZ_IOCTL_WENROM <= '1' when MZ_IOCTL_ADDR(24 downto 17)="00000000" and MZ_IOCTL_WR = '1' -- Write enable from HPS to ROM. + else '0'; + MZ_IOCTL_WENRAM <= '1' when MZ_IOCTL_ADDR(24 downto 16)="000000010" and MZ_IOCTL_WR = '1' -- Write enable from HPS to RAM. + else '0'; + MZ_IOCTL_RENROM <= '1' when MZ_IOCTL_ADDR(24 downto 17)="00000000" and MZ_IOCTL_RD = '1' -- Read enable from ROM to HPS. + else '0'; + MZ_IOCTL_RENRAM <= '1' when MZ_IOCTL_ADDR(24 downto 16)="000000010" and MZ_IOCTL_RD = '1' -- Read enable from RAM to HPS. + else '0'; + + -- System ROM. 128K split up into chunks which are enabled according to the running machine. The ROM can be accessed by the + -- HPS via the IOCTL bus and updated as necessary. + -- + -- 16 15 14 13 12 11 16 15 14 13 12 11 + -- K 4096 0 4095 0000000 0 0 0 0 0 0 0000FFF 0 0 0 0 0 1 + -- 4096 4096 8191 0001000 0 0 0 0 1 0 0001FFF 0 0 0 0 1 1 + -- 2048 8192 10239 0002000 0 0 0 1 0 0 00027FF 0 0 0 1 0 0 + -- 2048 10240 12287 0002800 0 0 0 1 0 1 0002FFF 0 0 0 1 0 1 + -- 2048 12288 14335 0003000 0 0 0 1 1 0 00037FF 0 0 0 1 1 0 + -- C 4096 14336 18431 0003800 0 0 0 1 1 1 00047FF 0 0 1 0 0 0 + -- 4096 18432 22527 0004800 0 0 1 0 0 1 00057FF 0 0 1 0 1 0 + -- 2048 22528 22527 0005800 0 0 1 0 1 1 0005FFF 0 0 1 0 1 1 + -- 2048 22528 24575 0006000 0 0 1 1 0 0 00067FF 0 0 1 1 0 0 + -- 2048 24576 26623 0006800 0 0 1 1 0 1 0006FFF 0 0 1 1 0 1 + -- 12 4096 18432 22527 0007000 0 0 1 1 1 0 0007FFF 0 0 1 1 1 1 + -- 4096 22528 26623 0008000 0 1 0 0 0 0 0008FFF 0 1 0 0 0 1 + -- 2048 26624 28671 0009000 0 1 0 0 1 0 00097FF 0 1 0 0 1 0 + -- 2048 28672 30719 0009800 0 1 0 0 1 1 0009FFF 0 1 0 0 1 1 + -- 2048 30720 32767 000A000 0 1 0 1 0 0 000A7FF 0 1 0 1 0 0 + -- A 4096 22528 26623 000A800 0 1 0 1 0 1 000B7FF 0 1 0 1 1 0 + -- 4096 26624 30719 000B800 0 1 0 1 1 1 000C7FF 0 1 1 0 0 0 + -- 2048 30720 32767 000C800 0 1 1 0 0 1 000CFFF 0 1 1 0 0 1 + -- 2048 32768 34815 000D000 0 1 1 0 1 0 000D7FF 0 1 1 0 1 0 + -- 2048 34816 36863 000D800 0 1 1 0 1 1 000DFFF 0 1 1 0 1 1 + -- 7 4096 26624 30719 000E000 0 1 1 1 0 0 000EFFF 0 1 1 1 0 1 + -- 4096 30720 34815 000F000 0 1 1 1 1 0 000FFFF 0 1 1 1 1 1 + -- 2048 34816 36863 0010000 1 0 0 0 0 0 00107FF 1 0 0 0 0 0 + -- 2048 36864 38911 0010800 1 0 0 0 0 1 0010FFF 1 0 0 0 0 1 + -- 2048 38912 40959 0011000 1 0 0 0 1 0 00117FF 1 0 0 0 1 0 + -- 8 4096 30720 34815 0011800 1 0 0 0 1 1 00127FF 1 0 0 1 0 0 + -- 4096 34816 38911 0012800 1 0 0 1 0 1 00137FF 1 0 0 1 1 0 + -- 2048 38912 40959 0013800 1 0 0 1 1 1 0013FFF 1 0 0 1 1 1 + -- 2048 40960 43007 0014000 1 0 1 0 0 0 00147FF 1 0 1 0 0 0 + -- 2048 43008 45055 0014800 1 0 1 0 0 1 0014FFF 1 0 1 0 0 1 + -- B 2048 34816 36863 0015000 1 0 1 0 1 0 00157FF 1 0 1 0 1 0 + -- 2048 36864 38911 0015800 1 0 1 0 1 1 0015FFF 1 0 1 0 1 1 + -- 2048 38912 40959 0016000 1 0 1 1 0 0 00167FF 1 0 1 1 0 0 + -- 2048 40960 43007 0016800 1 0 1 1 0 1 0016FFF 1 0 1 1 0 1 + -- 2048 43008 45055 0017000 1 0 1 1 1 0 00177FF 1 0 1 1 1 0 + -- 20 2048 36864 38911 0017800 1 0 1 1 1 1 0017FFF 1 0 1 1 1 1 + -- 2048 38912 40959 0018000 1 1 0 0 0 0 00187FF 1 1 0 0 0 0 + -- 2048 40960 43007 0018800 1 1 0 0 0 1 0018FFF 1 1 0 0 0 1 + -- 2048 43008 45055 0019000 1 1 0 0 1 0 00197FF 1 1 0 0 1 0 + -- 2048 45056 47103 0019800 1 1 0 0 1 1 0019FFF 1 1 0 0 1 1 + -- + MROM_BANK <= "00000" & T80_A16(11) when CONFIG(MZ80K) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "00001" & T80_A16(11) when CONFIG(MZ80K) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "000100" when CONFIG(MZ80K) = '1' and T80_A16(15 downto 11) = "11101" + else + "000101" when CONFIG(MZ80K) = '1' and T80_A16(15 downto 11) = "11110" + else + "000110" when CONFIG(MZ80K) = '1' and T80_A16(15 downto 11) = "11111" + else + "000111" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(11) = '0' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "001000" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(11) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "001001" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(11) = '0' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "001010" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(11) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "001011" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(15 downto 11) = "11101" + else + "001100" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(15 downto 11) = "11110" + else + "001101" when CONFIG(pkgs.mctrl_pkg.MZ80C) = '1' and T80_A16(15 downto 11) = "11111" + else + "00111" & T80_A16(11) when CONFIG(MZ1200) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "01000" & T80_A16(11) when CONFIG(MZ1200) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "010010" when CONFIG(MZ1200) = '1' and T80_A16(15 downto 11) = "11101" + else + "010011" when CONFIG(MZ1200) = '1' and T80_A16(15 downto 11) = "11110" + else + "010100" when CONFIG(MZ1200) = '1' and T80_A16(15 downto 11) = "11111" + else + "010101" when CONFIG(MZ80A) = '1' and T80_A16(11) = '0' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "010110" when CONFIG(MZ80A) = '1' and T80_A16(11) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "010111" when CONFIG(MZ80A) = '1' and T80_A16(11) = '0' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "011000" when CONFIG(MZ80A) = '1' and T80_A16(11) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "011001" when CONFIG(MZ80A) = '1' and T80_A16(15 downto 11) = "11101" + else + "011010" when CONFIG(MZ80A) = '1' and T80_A16(15 downto 11) = "11110" + else + "011011" when CONFIG(MZ80A) = '1' and T80_A16(15 downto 11) = "11111" + else + "01110" & T80_A16(11) when CONFIG(MZ700) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "01111" & T80_A16(11) when CONFIG(MZ700) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "100000" when CONFIG(MZ700) = '1' and T80_A16(15 downto 11) = "11101" + else + "100001" when CONFIG(MZ700) = '1' and T80_A16(15 downto 11) = "11110" + else + "100010" when CONFIG(MZ700) = '1' and T80_A16(15 downto 11) = "11111" + else + "100011" when CONFIG(MZ800) = '1' and T80_A16(11) = '0' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "100100" when CONFIG(MZ800) = '1' and T80_A16(11) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "100101" when CONFIG(MZ800) = '1' and T80_A16(11) = '0' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "100110" when CONFIG(MZ800) = '1' and T80_A16(11) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "100111" when CONFIG(MZ800) = '1' and T80_A16(15 downto 11) = "11101" + else + "101000" when CONFIG(MZ800) = '1' and T80_A16(15 downto 11) = "11110" + else + "101001" when CONFIG(MZ800) = '1' and T80_A16(15 downto 11) = "11111" + else + -- MZ80/2000 Series have different rom requirements. + "101010" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "101011" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "101100" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and T80_A16(15 downto 11) = "11101" + else + "101101" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and T80_A16(15 downto 11) = "11110" + else + "101110" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and T80_A16(15 downto 11) = "11111" + else + "101111" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and (CONFIG(NORMAL80) = '0' and CONFIG(COLOUR80) = '0') + else + "110000" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and (CONFIG(NORMAL80) = '1' or CONFIG(COLOUR80) = '1') + else + "110001" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and T80_A16(15 downto 11) = "11101" + else + "110010" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and T80_A16(15 downto 11) = "11110" + else + "110011" when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and T80_A16(15 downto 11) = "11111" + else + "000000"; -- Default to K ROM. + + -- Debug: Every 5 seconds, change the mb led bank to show a set of values (0 -> 7), bank indicated by 1 second of a bank number. + -- + --process( cold_reset, CLKBUS(CKLEDS), DEBUG) begin + process( MZ_SYSTEM_RESET, CLKBUS(CKLEDS), DEBUG) begin + if MZ_SYSTEM_RESET = '1' then + debug_counter <= 0; + flip_counter <= 0; + + elsif rising_edge(CLKBUS(CKLEDS)) then + + -- If debug mode is enabled, enable use of sequencer. + -- + if DEBUG(ENABLED) = '1' then + + -- If LEDS are switched on, run the sample sequencer. + -- + if DEBUG(LEDS_ON) = '1' then + + -- The changing of the values displayed depends on the sample frequency as this drives the process. + case DEBUG(SMPFREQ) is + when "0000" => -- CMT/CPU frequency - default to 1s/5s @ 2MHz. + block_flip <= 250000; + bank_flip <= 10000000; + when "0001" => -- 1MHz + block_flip <= 800000; + bank_flip <= 5000000; + when "0010" => -- 100KHz + block_flip <= 80000; + bank_flip <= 500000; + when "0011" => -- 10KHz + block_flip <= 8000; + bank_flip <= 50000; + when "0100" => -- 5KHz + block_flip <= 4000; + bank_flip <= 25000; + when "0101" => -- 1KHz + block_flip <= 800; + bank_flip <= 5000; + when "0110" => -- 500Hz + block_flip <= 400; + bank_flip <= 2500; + when "0111" => -- 100Hz + block_flip <= 80; + bank_flip <= 500; + when "1000" => -- 50Hz + block_flip <= 40; + bank_flip <= 250; + when "1001" => -- 10Hz + block_flip <= 8; + bank_flip <= 50; + when "1010" => -- 5Hz + block_flip <= 4; + bank_flip <= 25; + when "1011" => -- 2Hz + block_flip <= 1; + bank_flip <= 10; + when "1100" => -- 1Hz + block_flip <= 1; + bank_flip <= 5; + when "1101" => -- 0.5Hz + block_flip <= 1; + bank_flip <= 5; + when "1110" => -- 0.2Hz + block_flip <= 1; + bank_flip <= 2; + when "1111" => -- 0.1Hz + block_flip <= 1; + bank_flip <= 1; + end case; + + -- If a subbank has been provided, we dont cycle through the blocks in the bank, + -- just fix on the given subbank. + -- + case DEBUG(LEDS_SUBBANK) is + when "001" => debug_counter <= 1; + when "010" => debug_counter <= 3; + when "011" => debug_counter <= 5; + when "100" => debug_counter <= 7; + when "101" => debug_counter <= 9; + when "110" => debug_counter <= 11; + when "111" => debug_counter <= 13; + when "000" => + flip_counter <= flip_counter + 1; + if(flip_counter = block_flip-1 and (debug_counter mod 2) = 0) then + flip_counter <= 0; + debug_counter <= debug_counter + 1; + elsif(flip_counter = bank_flip-1) then + flip_counter <= 0; + debug_counter <= debug_counter + 1; + end if; + end case; + + -- Bank 0 : T80 Signals + if( DEBUG(LEDS_BANK) = "000") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "00010000"; + when 1 => main_leds(7 downto 0) <= T80_A16(7 downto 0); -- Address Bus A0->A7 + when 2 => main_leds(7 downto 0) <= "00010001"; + when 3 => main_leds(7 downto 0) <= T80_A16(15 downto 8); -- Address Bus A8->A15 + when 4 => main_leds(7 downto 0) <= "00010010"; + when 5 => main_leds(7 downto 0) <= T80_DI(7 downto 0); -- Data Bus D0->D7 + when 6 => main_leds(7 downto 0) <= "00010011"; + when 7 => main_leds(0) <= T80_RST_n; -- T80 signals + main_leds(1) <= T80_WAIT_n; + main_leds(2) <= T80_INT_n; + main_leds(3) <= T80_BUSRQ_n; + main_leds(4) <= T80_M1_n; + main_leds(5) <= T80_IORQ_n; + main_leds(6) <= T80_MRD_n; + main_leds(7) <= T80_MWR_n; + when 8 => main_leds(7 downto 0) <= "00010100"; + when 10=> main_leds(7 downto 0) <= "00010101"; + when 12=> main_leds(7 downto 0) <= "00010110"; + when others => main_leds <= "00010111"; + end case; + + -- Bank 1 : Video and Keyboard. + elsif( DEBUG(LEDS_BANK) = "001") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "00110000"; + when 1 => main_leds(0) <= MZ_VBLANK; -- Video signals + main_leds(1) <= MZ_HBLANK; -- Video signals + main_leds(2) <= '0'; + main_leds(3) <= MZ_HSYNC_n; + main_leds(4) <= MZ_VSYNC_n; + main_leds(5) <= MZ_R; + main_leds(6) <= MZ_G; + main_leds(7) <= MZ_B; + when 2 => main_leds(7 downto 0) <= "00110001"; + when 3 => main_leds(0) <= MZ_PS2_KEY(0); -- PS2 Keyboard Data + main_leds(1) <= MZ_PS2_KEY(1); + main_leds(2) <= MZ_PS2_KEY(2); + main_leds(3) <= MZ_PS2_KEY(3); + main_leds(4) <= MZ_PS2_KEY(4); + main_leds(5) <= MZ_PS2_KEY(5); + main_leds(6) <= MZ_PS2_KEY(6); + main_leds(7) <= MZ_PS2_KEY(7); + when 4 => main_leds(7 downto 0) <= "00110010"; + when 5 => main_leds(0) <= MZ_PS2_KEY(9); + main_leds(1) <= MZ_PS2_KEY(10); + main_leds(2) <= CS_ROM_n; + main_leds(3) <= CS_RAM_n; + main_leds(4) <= WENSYSRAM; + main_leds(7 downto 5) <= CONFIG(TURBO); + when 6 => main_leds(7 downto 0) <= "00111011"; + when 8 => main_leds(7 downto 0) <= "00111100"; + when 10=> main_leds(7 downto 0) <= "00111101"; + when 12=> main_leds(7 downto 0) <= "00111110"; + when others => main_leds <= "00110111"; + end case; + + -- Bank 2: IOCTL + elsif( DEBUG(LEDS_BANK) = "010") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "01010000"; + when 1 => main_leds <= MZ_IOCTL_ADDR(23 downto 16); + when 2 => main_leds(7 downto 0) <= "01010001"; + when 3 => main_leds <= MZ_IOCTL_ADDR(15 downto 8); + when 4 => main_leds(7 downto 0) <= "01010010"; + when 5 => main_leds <= MZ_IOCTL_ADDR(7 downto 0); + when 6 => main_leds(7 downto 0) <= "01010011"; + when 7 => main_leds(0) <= MZ_IOCTL_RD; + main_leds(1) <= MZ_IOCTL_WR; + main_leds(2) <= MZ_IOCTL_DOWNLOAD; + main_leds(3) <= MZ_IOCTL_UPLOAD; + main_leds(4) <= MZ_IOCTL_WENROM; + main_leds(5) <= MZ_IOCTL_WENRAM; + main_leds(6) <= MZ_IOCTL_RENROM; + main_leds(7) <= MZ_IOCTL_RENRAM; + when 8 => main_leds(7 downto 0) <= "01010100"; + when 10=> main_leds(7 downto 0) <= "01010101"; + when 12=> main_leds(7 downto 0) <= "01010110"; + when others => main_leds <= "01010111"; + end case; + + -- Bank 3 : Config + elsif( DEBUG(LEDS_BANK) = "011") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "01110000"; + when 1 => main_leds(0) <= CONFIG(MZ80K); -- Mode of operation. + main_leds(1) <= CONFIG(pkgs.mctrl_pkg.MZ80C); + main_leds(2) <= CONFIG(MZ1200); + main_leds(3) <= CONFIG(MZ80A); + main_leds(4) <= CONFIG(pkgs.mctrl_pkg.MZ80B); + main_leds(5) <= CONFIG(MZ2000); + main_leds(6) <= CONFIG(MZ700); + main_leds(7) <= CONFIG(MZ800); + when 2 => main_leds(7 downto 0) <= "01110001"; + when 3 => main_leds(0) <= CONFIG(MZ_KC); + main_leds(1) <= CONFIG(MZ_A); + main_leds(2) <= CONFIG(pkgs.mctrl_pkg.MZ_B); + main_leds(3) <= CONFIG(MZ_80B); + main_leds(4) <= CONFIG(MZ_80C); + main_leds(5) <= CONFIG(NORMAL); + main_leds(6) <= CONFIG(NORMAL80); + main_leds(7) <= CONFIG(COLOUR); + when 4 => main_leds(7 downto 0) <= "01110010"; + when 5 => main_leds(0) <= CONFIG(AUDIOSRC); + main_leds(3 downto 1) <= CONFIG(TURBO); + main_leds(6 downto 4) <= CONFIG(FASTTAPE); + main_leds(7) <= CONFIG(PCGRAM); + when 6 => main_leds(7 downto 0) <= "01110011"; + when 7 => main_leds(3 downto 0) <= CONFIG(CPUSPEED); + main_leds(6 downto 4) <= CONFIG(VIDSPEED); + main_leds(7) <= '0'; + when 8 => main_leds(7 downto 0) <= "01110100"; + when 9 => main_leds(1 downto 0) <= CONFIG(PERSPEED); + main_leds(3 downto 2) <= CONFIG(RTCSPEED); + main_leds(5 downto 4) <= CONFIG(SNDSPEED); + main_leds(7 downto 6) <= CONFIG(BUTTONS); + when 10=> main_leds(7 downto 0) <= "01110101"; + when 11=> main_leds <= "00000000"; + when 12=> main_leds(7 downto 0) <= "01110110"; + when 13=> main_leds <= "00000000"; + when others => main_leds <= "01110111"; + end case; + + + -- Bank 4 & 5: MZ80C Debug Leds + elsif( DEBUG(LEDS_BANK) = "100") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "10010000"; + when 1 => main_leds <= MZ80C_DEBUG_LEDS(7 downto 0); + when 2 => main_leds(7 downto 0) <= "10010001"; + when 3 => main_leds <= MZ80C_DEBUG_LEDS(15 downto 8); + when 4 => main_leds(7 downto 0) <= "10010010"; + when 5 => main_leds <= MZ80C_DEBUG_LEDS(23 downto 16); + when 6 => main_leds(7 downto 0) <= "10010011"; + when 7 => main_leds <= MZ80C_DEBUG_LEDS(31 downto 24); + when 8 => main_leds(7 downto 0) <= "10010100"; + when 9 => main_leds <= MZ80C_DEBUG_LEDS(39 downto 32); + when 10=> main_leds(7 downto 0) <= "10010101"; + when 11=> main_leds <= MZ80C_DEBUG_LEDS(47 downto 40); + when 12=> main_leds(7 downto 0) <= "10010110"; + when 13=> main_leds <= MZ80C_DEBUG_LEDS(55 downto 48); + when others => main_leds <= "10010111"; + end case; + elsif( DEBUG(LEDS_BANK) = "101") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "10110000"; + when 1 => main_leds <= MZ80C_DEBUG_LEDS(63 downto 56); + when 2 => main_leds(7 downto 0) <= "10110001"; + when 3 => main_leds <= MZ80C_DEBUG_LEDS(71 downto 64); + when 4 => main_leds(7 downto 0) <= "10110010"; + when 5 => main_leds <= MZ80C_DEBUG_LEDS(79 downto 72); + when 6 => main_leds(7 downto 0) <= "10110011"; + when 7 => main_leds <= MZ80C_DEBUG_LEDS(87 downto 80); + when 8 => main_leds(7 downto 0) <= "10110100"; + when 9 => main_leds <= MZ80C_DEBUG_LEDS(95 downto 88); + when 10=> main_leds(7 downto 0) <= "10110101"; + when 11=> main_leds <= MZ80C_DEBUG_LEDS(103 downto 96); + when 12=> main_leds(7 downto 0) <= "10110110"; + when 13=> main_leds <= MZ80C_DEBUG_LEDS(111 downto 104); + when others => main_leds <= "10110111"; + end case; + + -- Bank 6 & 7 : MZ80B Debug Leds + elsif( DEBUG(LEDS_BANK) = "110") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "11010000"; + when 1 => main_leds <= MZ80B_DEBUG_LEDS(7 downto 0); + when 2 => main_leds(7 downto 0) <= "11010001"; + when 3 => main_leds <= MZ80B_DEBUG_LEDS(15 downto 8); + when 4 => main_leds(7 downto 0) <= "11010010"; + when 5 => main_leds <= MZ80B_DEBUG_LEDS(23 downto 16); + when 6 => main_leds(7 downto 0) <= "11010011"; + when 7 => main_leds <= MZ80B_DEBUG_LEDS(31 downto 24); + when 8 => main_leds(7 downto 0) <= "11010100"; + when 9 => main_leds <= MZ80B_DEBUG_LEDS(39 downto 32); + when 10=> main_leds(7 downto 0) <= "11010101"; + when 11=> main_leds <= MZ80B_DEBUG_LEDS(47 downto 40); + when 12=> main_leds(7 downto 0) <= "11010110"; + when 13=> main_leds <= MZ80B_DEBUG_LEDS(55 downto 48); + when others => main_leds <= "11010111"; + end case; + elsif( DEBUG(LEDS_BANK) = "111") then + case debug_counter is + when 0 => main_leds(7 downto 0) <= "11110000"; + when 1 => main_leds <= MZ80B_DEBUG_LEDS(63 downto 56); + when 2 => main_leds(7 downto 0) <= "11110001"; + when 3 => main_leds <= MZ80B_DEBUG_LEDS(71 downto 64); + when 4 => main_leds(7 downto 0) <= "11110010"; + when 5 => main_leds <= MZ80B_DEBUG_LEDS(79 downto 72); + when 6 => main_leds(7 downto 0) <= "11110011"; + when 7 => main_leds <= MZ80B_DEBUG_LEDS(87 downto 80); + when 8 => main_leds(7 downto 0) <= "11110100"; + when 9 => main_leds <= MZ80B_DEBUG_LEDS(95 downto 88); + when 10=> main_leds(7 downto 0) <= "11110101"; + when 11=> main_leds <= MZ80B_DEBUG_LEDS(103 downto 96); + when 12=> main_leds(7 downto 0) <= "11110110"; + when 13=> main_leds <= MZ80B_DEBUG_LEDS(111 downto 104); + when others => main_leds <= "11110111"; + end case; + end if; + end if; + end if; + end if; + end process; +end rtl; diff --git a/sharpmz_assignment_defaults.qdf b/sharpmz_assignment_defaults.qdf new file mode 100644 index 0000000..c9c4c19 --- /dev/null +++ b/sharpmz_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition +# Date created = 18:26:55 June 18, 2018 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. 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NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/sys/build_id.tcl b/sys/build_id.tcl new file mode 100644 index 0000000..8777a14 --- /dev/null +++ b/sys/build_id.tcl @@ -0,0 +1,69 @@ + +# Build TimeStamp Verilog Module +# Jeff Wiencrot - 8/1/2011 +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Build CDF file +# Sorgelig - 17/2/2018 +proc generateCDF {revision device outpath} { + + set outputFileName "jtag.cdf" + set outputFile [open $outputFileName "w"] + + puts $outputFile "JedecChain;" + puts $outputFile " FileRevision(JESD32A);" + puts $outputFile " DefaultMfr(6E);" + puts $outputFile "" + puts $outputFile " P ActionCode(Ign)" + puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));" + puts $outputFile " P ActionCode(Cfg)" + puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" + puts $outputFile "ChainEnd;" + puts $outputFile "" + puts $outputFile "AlteraBegin;" + puts $outputFile " ChainType(JTAG);" + puts $outputFile "AlteraEnd;" +} + +set project_name [lindex $quartus(args) 1] +set revision [lindex $quartus(args) 2] + +if {[project_exists $project_name]} { + if {[string equal "" $revision]} { + project_open $project_name -revision [get_current_revision $project_name] + } else { + project_open $project_name -revision $revision + } +} else { + post_message -type error "Project $project_name does not exist" + exit +} + +set device [get_global_assignment -name DEVICE] +set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] + +if [is_project_open] { + project_close +} + +generateBuildID_Verilog +generateCDF $revision $device $outpath diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv new file mode 100644 index 0000000..0265c5c --- /dev/null +++ b/sys/hdmi_config.sv @@ -0,0 +1,202 @@ + +module hdmi_config +( + // Host Side + input iCLK, + input iRST_N, + + input dvi_mode, + input audio_96k, + + // I2C Side + output I2C_SCL, + inout I2C_SDA +); + +// Internal Registers/Wires +reg mI2C_GO = 0; +wire mI2C_END; +wire mI2C_ACK; +reg [15:0] LUT_DATA; +reg [7:0] LUT_INDEX = 0; + +i2c #(50_000_000, 20_000) i2c_av +( + .CLK(iCLK), + + .I2C_SCL(I2C_SCL), // I2C CLOCK + .I2C_SDA(I2C_SDA), // I2C DATA + + .I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip! + .START(mI2C_GO), // START transfer + .END(mI2C_END), // END transfer + .ACK(mI2C_ACK) // ACK +); + +////////////////////// Config Control //////////////////////////// +always@(posedge iCLK or negedge iRST_N) begin + reg [1:0] mSetup_ST = 0; + + if(!iRST_N) begin + LUT_INDEX <= 0; + mSetup_ST <= 0; + mI2C_GO <= 0; + end else begin + if(init_data[LUT_INDEX] != 16'hFFFF) begin + case(mSetup_ST) + 0: begin + mI2C_GO <= 1; + mSetup_ST <= 1; + end + 1: if(~mI2C_END) mSetup_ST <= 2; + 2: begin + mI2C_GO <= 0; + if(mI2C_END) begin + mSetup_ST <= 0; + if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1; + end + end + endcase + end + end +end + +//////////////////////////////////////////////////////////////////// +///////////////////// Config Data LUT ////////////////////////// + +wire [15:0] init_data[58] = +'{ + 16'h9803, // ADI required Write. + + {8'hD6, 8'b1100_0000}, // [7:6] HPD Control... + // 00 = HPD is from both HPD pin or CDC HPD + // 01 = HPD is from CDC HPD + // 10 = HPD is from HPD pin + // 11 = HPD is always high + + 16'h4110, // Power Down control + 16'h9A70, // ADI required Write. + 16'h9C30, // ADI required Write. + {8'h9D, 8'b0110_0001}, // [7:4] must be b0110!. + // [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid! + // [1:0] must be b01! + 16'hA2A4, // ADI required Write. + 16'hA3A4, // ADI required Write. + 16'hE0D0, // ADI required Write. + + + 16'h35_40, + 16'h36_D9, + 16'h37_0A, + 16'h38_00, + 16'h39_2D, + 16'h3A_00, + + {8'h16, 8'b0011_1000}, // Output Format 444 [7]=0. + // [6] must be 0! + // Colour Depth for Input Video data [5:4] b11 = 8-bit. + // Input Style [3:2] b10 = Style 1 (ignored when using 444 input). + // DDR Input Edge falling [1]=0 (not using DDR atm). + // Output Colour Space RGB [0]=0. + + {8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0 + + {8'h18, 8'b0100_0110}, // CSC disabled [7]=0. + // CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380. + // CSC Equation 3 [4:0] b00110. + + + {8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx. + + 16'h4000, // General Control Packet Enable + + {8'h48, 8'b0000_1000}, // [6]=0 Normal bus order! + // [5] DDR Alignment. + // [4:3] b01 Data right justified (for YCbCr 422 input modes). + + 16'h49A8, // ADI required Write. + 16'h4C00, // ADI required Write. + + {8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4]. + // AVI InfoFrame Valid [4]. + // Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both. + // Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None. + + 16'h7301, + + {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled. + + 16'h9902, // ADI required Write. + 16'h9B18, // ADI required Write. + + 16'h9F00, // ADI required Write. + + {8'hA1, 8'b0000_0000}, // [6]=1 Monitor Sense Power Down DISabled. + + 16'hA408, // ADI required Write. + 16'hA504, // ADI required Write. + 16'hA600, // ADI required Write. + 16'hA700, // ADI required Write. + 16'hA800, // ADI required Write. + 16'hA900, // ADI required Write. + 16'hAA00, // ADI required Write. + 16'hAB40, // ADI required Write. + + {8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled. + // [6:5] must be b00! + // [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?) + // [3:2] must be b01! + // [1]=1 HDMI Mode. + // [0] must be b0! + + 16'hB900, // ADI required Write. + + {8'hBA, 8'b0110_0000}, // [7:5] Input Clock delay... + // b000 = -1.2ns. + // b001 = -0.8ns. + // b010 = -0.4ns. + // b011 = No delay. + // b100 = 0.4ns. + // b101 = 0.8ns. + // b110 = 1.2ns. + // b111 = 1.6ns. + + 16'hBB00, // ADI required Write. + + 16'hDE9C, // ADI required Write. + 16'hE460, // ADI required Write. + 16'hFA7D, // Nbr of times to search for good phase + + + // (Audio stuff on Programming Guide, Page 66)... + + {8'h0A, 8'b0000_0000}, // [6:4] Audio Select. b000 = I2S. + // [3:2] Audio Mode. (HBR stuff, leave at 00!). + + {8'h0B, 8'b0000_1110}, // + + {8'h0C, 8'b0000_0100}, // [7] 0 = Use sampling rate from I2S stream. 1 = Use samp rate from I2C Register. + // [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register. + // [2] 1 = I2S0 Enable. + // [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES. + + {8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified. + {8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits. + {8'h15, audio_96k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz. + // Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs. + + // Audio Clock Config + 16'h0100, // + audio_96k ? 16'h0230 : 16'h0218, // Set N Value 12288/6144 + 16'h0300, // + + 16'h0701, // + 16'h0822, // Set CTS Value 74250 + 16'h090A, // + + 16'hFFFF // END +}; + +//////////////////////////////////////////////////////////////////// + +endmodule \ No newline at end of file diff --git a/sys/hdmi_lite.sv b/sys/hdmi_lite.sv new file mode 100644 index 0000000..ef80764 --- /dev/null +++ b/sys/hdmi_lite.sv @@ -0,0 +1,395 @@ +//============================================================================ +// +// HDMI Lite output module +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +//============================================================================ + + +module hdmi_lite +( + input reset, + + input clk_video, + input ce_pixel, + input video_vs, + input video_de, + input [23:0] video_d, + + input clk_hdmi, + input hdmi_hde, + input hdmi_vde, + output reg hdmi_de, + output [23:0] hdmi_d, + + input [11:0] screen_w, + input [11:0] screen_h, + input quadbuf, + + // 0-3 => scale 1-4 + input [1:0] scale_x, + input [1:0] scale_y, + input scale_auto, + + input clk_vbuf, + output [27:0] vbuf_address, + input [127:0] vbuf_readdata, + output [127:0] vbuf_writedata, + output [7:0] vbuf_burstcount, + output [15:0] vbuf_byteenable, + input vbuf_waitrequest, + input vbuf_readdatavalid, + output reg vbuf_read, + output reg vbuf_write +); + +localparam [7:0] burstsz = 64; + +reg [1:0] nbuf = 0; +wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0}; +wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0}; + +assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress; +assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount; + +wire [95:0] hf_out; +wire [7:0] hf_usedw; +reg hf_reset = 0; + +vbuf_fifo out_fifo +( + .aclr(hf_reset), + + .wrclk(clk_vbuf), + .wrreq(vbuf_readdatavalid), + .data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}), + .wrusedw(hf_usedw), + + .rdclk(~clk_hdmi), + .rdreq(hf_rdreq), + .q(hf_out) +); + +reg [11:0] rd_stride; +wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0]; + +reg [27:0] vbuf_raddress; +reg [7:0] vbuf_rburstcount; +always @(posedge clk_vbuf) begin + reg [18:0] rdcnt; + reg [7:0] bcnt; + reg vde1, vde2; + reg [1:0] mcnt; + reg [1:0] my; + reg [18:0] fsz; + reg [11:0] strd; + + vde1 <= hdmi_vde; + vde2 <= vde1; + + if(vbuf_readdatavalid) begin + rdcnt <= rdcnt + 1'd1; + if(bcnt) bcnt <= bcnt - 1'd1; + vbuf_raddress <= vbuf_raddress + 1'd1; + end + + if(!bcnt && reading) reading <= 0; + + vbuf_read <= 0; + if(~vbuf_waitrequest) begin + if(!hf_reset && rdcnt=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt; +wire de_in = hdmi_hde & hdmi_vde; + +always @(posedge clk_hdmi) begin + reg [71:0] px_out; + reg [1:0] mx; + reg vde; + + vde <= hdmi_vde; + + if(vde & ~hdmi_vde) begin + off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0; + off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0; + vh_height <= v_height; + vh_width <= v_width; + mx <= mult_x; + end + + pcnt <= pcnt + 1'd1; + if(pcnt == mx) begin + pcnt <= 0; + hload <= hload + 1'd1; + end + + if(~de_in || x (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11; +wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11; +wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y; +wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y; +wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x; +wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0); +wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0); +wire [23:0] t_fsz = l1_stride * t_height; + +reg [11:0] l1_width; +reg [11:0] l1_stride; +always @(posedge clk_video) begin + reg [7:0] loaded = 0; + reg [11:0] strd = 0; + reg old_de = 0; + reg old_vs = 0; + + old_vs <= video_vs; + if(~old_vs & video_vs) begin + cur_addr<= write_buf; + video_x <= 0; + video_y <= 0; + loaded <= 0; + strd <= 0; + nbuf <= nbuf + 1'd1; + + stride <= l1_stride; + framesz <= t_fsz[18:0]; + v_height<= t_height; + v_width <= t_width; + mult_x <= tmf_x; + mult_y <= tmf_y; + end + + if(pix_wr) begin + case(video_x[1:0]) + 0: pix_acc <= video_d; // zeroes upper bits too + 1: pix_acc[47:24] <= video_d; + 2: pix_acc[71:48] <= video_d; + 3: loaded <= loaded + 1'd1; + endcase + if(video_x= burstsz) || (old_de & ~video_de)) begin + if(loaded + infifo_tail) begin + flush_size <= loaded + infifo_tail; + flush_addr <= cur_addr; + flush_req <= ~flush_req; + loaded <= 0; + strd <= strd + loaded; + end + + cur_addr <= cur_addr + loaded + infifo_tail; + if(~video_de) begin + if(video_y +// Copyright (c) 2017,2018 Sorgelig +// SharpMZ series specific updates made by Philip Smart, 2018. +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = CLK_SYS/(PS2DIV*2) +// + +// WIDE=1 for 16 bit file I/O +// VDNUM 1-4 +module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0) +( + input clk_sys, + inout [44:0] HPS_BUS, + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + output reg [15:0] joystick_0, + output reg [15:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + + output [1:0] buttons, + output forced_scandoubler, + + output reg [31:0] status, + + //toggle to force notify of video mode change + input new_vmode, + + // SD config + output reg [VD:0] img_mounted, // signaling that new image has been mounted + output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted + output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted + + // SD block level access + input [31:0] sd_lba, + input [VD:0] sd_rd, // only single sd_rd can be active at any given time + input [VD:0] sd_wr, // only single sd_wr can be active at any given time + output reg sd_ack, + + // do not use in new projects. + // CID and CSD are fake except CSD image size field. + input sd_conf, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [AW:0] sd_buff_addr, + output reg [DW:0] sd_buff_dout, + input [DW:0] sd_buff_din, + output reg sd_buff_wr, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg ioctl_upload = 0, // signal indicating an active upload + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr, + output reg ioctl_rd, + output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2 + output reg [DW:0] ioctl_dout, + input [DW:0] ioctl_din, + input ioctl_wait, + + // RTC MSM6242B layout + output reg [64:0] RTC, + + // Seconds since 1970-01-01 00:00:00 + output reg [32:0] TIMESTAMP, + + // ps2 keyboard emulation + output ps2_kbd_clk_out, + output ps2_kbd_data_out, + input ps2_kbd_clk_in, + input ps2_kbd_data_in, + + input [2:0] ps2_kbd_led_status, + input [2:0] ps2_kbd_led_use, + + output ps2_mouse_clk_out, + output ps2_mouse_data_out, + input ps2_mouse_clk_in, + input ps2_mouse_data_in, + + // ps2 alternative interface. + + // [8] - extended, [9] - pressed, [10] - toggles with every press/release + output reg [10:0] ps2_key = 0, + + // [24] - toggles with every event + output reg [24:0] ps2_mouse = 0 +); + +localparam DW = (WIDE) ? 15 : 7; +localparam AW = (WIDE) ? 7 : 8; +localparam VD = VDNUM-1; + +wire io_wait = ioctl_wait; +wire io_enable= |HPS_BUS[35:34]; +wire io_strobe= HPS_BUS[33]; +wire io_wide = (WIDE) ? 1'b1 : 1'b0; +wire [15:0] io_din = HPS_BUS[31:16]; +reg [15:0] io_dout; + +assign HPS_BUS[37] = io_wait; +assign HPS_BUS[36] = clk_sys; +assign HPS_BUS[32] = io_wide; +assign HPS_BUS[15:0] = io_dout; + +reg [7:0] cfg; +assign buttons = cfg[1:0]; +//cfg[2] - vga_scaler handled in sys_top +//cfg[3] - csync handled in sys_top +assign forced_scandoubler = cfg[4]; +//cfg[5] - ypbpr handled in sys_top + +// command byte read by the io controller +wire [15:0] sd_cmd = +{ + 2'b00, + (VDNUM>=4) ? sd_wr[3] : 1'b0, + (VDNUM>=3) ? sd_wr[2] : 1'b0, + (VDNUM>=2) ? sd_wr[1] : 1'b0, + + (VDNUM>=4) ? sd_rd[3] : 1'b0, + (VDNUM>=3) ? sd_rd[2] : 1'b0, + (VDNUM>=2) ? sd_rd[1] : 1'b0, + + 4'h5, sd_conf, 1'b1, + sd_wr[0], + sd_rd[0] +}; + +///////////////// calc video parameters ////////////////// + +wire clk_100 = HPS_BUS[43]; +wire clk_vid = HPS_BUS[42]; +wire ce_pix = HPS_BUS[41]; +wire de = HPS_BUS[40]; +wire hs = HPS_BUS[39]; +wire vs = HPS_BUS[38]; +wire vs_hdmi = HPS_BUS[44]; + +reg [31:0] vid_hcnt = 0; +reg [31:0] vid_vcnt = 0; +reg [7:0] vid_nres = 0; +integer hcnt; + +always @(posedge clk_vid) begin + integer vcnt; + reg old_vs= 0, old_de = 0, old_vmode = 0; + reg calch = 0; + + if(ce_pix) begin + old_vs <= vs; + old_de <= de; + + if(~vs & ~old_de & de) vcnt <= vcnt + 1; + if(calch & de) hcnt <= hcnt + 1; + if(old_de & ~de) calch <= 0; + + if(old_vs & ~vs) begin + if(hcnt && vcnt) begin + old_vmode <= new_vmode; + if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1; + vid_hcnt <= hcnt; + vid_vcnt <= vcnt; + end + vcnt <= 0; + hcnt <= 0; + calch <= 1; + end + end +end + +reg [31:0] vid_htime = 0; +reg [31:0] vid_vtime = 0; +reg [31:0] vid_pix = 0; + +always @(posedge clk_100) begin + integer vtime, htime, hcnt; + reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2; + reg calch = 0; + + old_vs <= vs; + old_hs <= hs; + + old_vs2 <= old_vs; + old_hs2 <= old_hs; + + vtime <= vtime + 1'd1; + htime <= htime + 1'd1; + + if(~old_vs2 & old_vs) begin + vid_pix <= hcnt; + vid_vtime <= vtime; + vtime <= 0; + hcnt <= 0; + end + + if(old_vs2 & ~old_vs) calch <= 1; + + if(~old_hs2 & old_hs) begin + vid_htime <= htime; + htime <= 0; + end + + old_de <= de; + old_de2 <= old_de; + + if(calch & old_de) hcnt <= hcnt + 1; + if(old_de2 & ~old_de) calch <= 0; +end + +reg [31:0] vid_vtime_hdmi; +always @(posedge clk_100) begin + integer vtime; + reg old_vs, old_vs2; + + old_vs <= vs_hdmi; + old_vs2 <= old_vs; + + vtime <= vtime + 1'd1; + + if(~old_vs2 & old_vs) begin + vid_vtime_hdmi <= vtime; + vtime <= 0; + end +end + + +///////////////////////////////// HPS I/O //////////////////////////////////// + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; +localparam UIO_FILE_INFO = 8'h56; +localparam UIO_FILE_ADDR = 8'h57; +localparam UIO_FILE_ADDR_TX = 8'h58; +localparam UIO_FILE_ADDR_RX = 8'h59; +localparam UIO_CONFIG_RX = 8'h5A; +localparam UIO_CONFIG_TX = 8'h5B; + + +reg [31:0] ps2_key_raw = 0; +wire pressed = (ps2_key_raw[15:8] != 8'hf0); +wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); + +// Primary loop for HPS <-> FPGA I/O. Look at sys_top.v in the HPS I/O section +// for the ack pulse going back to the HPS when data is written. +// +// Basic mode of operation is the HPS writes a byte on io_din and reads back +// io_dout within the same clock cycle (clk_sys). io_enable is set active when +// an EnableFPGA is executed within the HPS Main MiSTer program. io_strobe is +// set active by the HPS when it writes a byte (sys_top.v acknowledges the +// strobe) and reset within the same clk_sys cycle. +// +always@(posedge clk_sys) begin + reg [15:0] cmd; + reg [15:0] byte_cnt; // counts bytes + reg [2:0] b_wr; + reg [2:0] stick_idx; + reg ps2skip = 0; + reg [24:0] addr; // Address signal to hps logic in emulator. + reg wr; // Write signal to hps logic in emulator. + reg rd; // Read signal to hps logic in emulator. + + // After the UIO_FILE_ADDR_TX command, wr will be set to 1, this is then transferred + // to the wire ioctl_wr at next clock cycle (1 cycle after address setup) and will be held + // high for 1 clock cycle of clk_sys. This provides the setup and hold time for the data + // before the write signal is generated. + // + ioctl_wr <= wr; + wr <= 0; + + // For read, the UIO_FILE_ADDR_RX command places the wire ioctl_rd to 1 on the clock + // immediately follwing the command along with the address. It is held + // high for 2 cycles, on the 2nd cycle the data is sampled. The read data + // belongs to the previous address as the HPS mechanism writes data + // synchronised with the sys_clk and reads back within that same cycle + // (ie. 1x sys_clk). Thus the HPS needs to write a 0 @ addr1 then write another + // 0 @ addr2 and the data read back belongs to addr1. + // + ioctl_rd <= rd; + if(ioctl_rd == 1) begin + io_dout <= ioctl_din[DW:0]; // This read is for previous address setup. + end + rd <= 0; + + sd_buff_wr <= b_wr[0]; + if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; + b_wr <= (b_wr<<1); + + {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0; + + if(~io_enable) + begin + if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24]; + if(cmd == 5 && !ps2skip) begin + ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; + if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed + if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released + if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed + end + if(cmd == 'h22) RTC[64] <= ~RTC[64]; + if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32]; + cmd <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + io_dout <= 0; + ps2skip <= 0; + addr <= 0; + end + else + begin + if(io_strobe) + begin + // Reset the input bus as needed. + if(cmd != UIO_CONFIG_RX) + begin + io_dout <= 0; + end + + // Increment but dont let the byte counter roll-over. + if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; + + // First byte after strobe is the command, store and setup for + // command processing. + if(byte_cnt == 0) + begin + cmd <= io_din; + + case(io_din) + 'h19: sd_ack_conf <= 1; + 'h17, + 'h18: sd_ack <= 1; + endcase + + sd_buff_addr <= 0; + img_mounted <= 0; + if(io_din == 5) ps2_key_raw <= 0; + end + else + begin + case(cmd) + // buttons and switches + 'h01: cfg <= io_din[7:0]; + 'h02: joystick_0 <= io_din; + 'h03: joystick_1 <= io_din; + + // store incoming ps2 mouse bytes + 'h04: begin + mouse_data <= io_din[7:0]; + mouse_we <= 1; + if(&io_din[15:8]) ps2skip <= 1; + if(~&io_din[15:8] & ~ps2skip) begin + case(byte_cnt) + 1: ps2_mouse[7:0] <= io_din[7:0]; + 2: ps2_mouse[15:8] <= io_din[7:0]; + 3: ps2_mouse[23:16] <= io_din[7:0]; + endcase + end + end + + // store incoming ps2 keyboard bytes + 'h05: begin + if(&io_din[15:8]) ps2skip <= 1; + if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]}; + kbd_data <= io_din[7:0]; + kbd_we <= 1; + end + + // reading config string + 'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8]; + end + + // reading sd card status + 'h16: begin + case(byte_cnt) + 1: io_dout <= sd_cmd; + 2: io_dout <= sd_lba[15:0]; + 3: io_dout <= sd_lba[31:16]; + endcase + end + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 'h19, + // send sector IO -> FPGA + // flag that download begins + 'h17: begin + sd_buff_dout <= io_din[DW:0]; + b_wr <= 1; + end + + // reading sd card write data + 'h18: begin + if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; + io_dout <= sd_buff_din; + end + + // joystick analog + 'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= io_din[2:0]; + if(byte_cnt == 2) begin + if(stick_idx == 0) joystick_analog_0 <= io_din; + if(stick_idx == 1) joystick_analog_1 <= io_din; + end + end + + // notify image selection + 'h1c: begin + img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1; + img_readonly <= io_din[7]; + end + + // send image info + 'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din; + + // status, 32bit version + 'h1e: if(byte_cnt==1) status[15:0] <= io_din; + else if(byte_cnt==2) status[31:16] <= io_din; + + // reading keyboard LED status + 'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]}; + + // reading ps2 keyboard/mouse control + 'h21: begin + if(byte_cnt == 1) begin + io_dout <= kbd_data_host; + kbd_rd <= 1; + end + + if(byte_cnt == 2) begin + io_dout <= mouse_data_host; + mouse_rd <= 1; + end + end + //RTC + 'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din; + + //Video res. + 'h23: begin + case(byte_cnt) + 1: io_dout <= vid_nres; + 2: io_dout <= vid_hcnt[15:0]; + 3: io_dout <= vid_hcnt[31:16]; + 4: io_dout <= vid_vcnt[15:0]; + 5: io_dout <= vid_vcnt[31:16]; + 6: io_dout <= vid_htime[15:0]; + 7: io_dout <= vid_htime[31:16]; + 8: io_dout <= vid_vtime[15:0]; + 9: io_dout <= vid_vtime[31:16]; + 10: io_dout <= vid_pix[15:0]; + 11: io_dout <= vid_pix[31:16]; + 12: io_dout <= vid_vtime_hdmi[15:0]; + 13: io_dout <= vid_vtime_hdmi[31:16]; + endcase + end + + //RTC + 'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din; + + UIO_FILE_ADDR: // Direct setup/change of address, each byte becomes the lower 7-0 bits of address. + begin + addr <= (addr << 8) | io_din[7:0]; + end + + UIO_FILE_INDEX: // Setup of index (0-255), for index addressing. + begin + ioctl_index <= io_din[7:0]; + end + + UIO_FILE_TX: // Standard file download, address starts at 0. + begin + if(io_din[7:0]) begin + addr <= 0; + ioctl_download <= 1; + end else begin + ioctl_addr <= addr; + ioctl_download <= 0; + end + end + + UIO_FILE_TX_DAT: // File data download, byte sent to output bus and wr is pulsed (for 1 clock after address/data setup). + begin + ioctl_addr <= addr; + ioctl_dout <= io_din[DW:0]; + wr <= 1; + addr <= addr + (WIDE ? 2'd2 : 2'd1); + end + + UIO_FILE_ADDR_TX: // Modified file download, starting address is sent. + begin + // Address - 1=:24, 1 = 23:16, 2 = 15:8, 3 = 7:0 + if(byte_cnt < 5) + begin + addr <= (addr << 8) | io_din[7:0]; + + // LSB byte signifies start of data receipt. + if(byte_cnt == 4) + begin + ioctl_download <= 1; + end + end + else + begin + ioctl_addr <= addr; + ioctl_dout <= io_din[DW:0]; + wr <= 1; + addr <= addr + (WIDE ? 2'd2 : 2'd1); + end + end + + UIO_FILE_ADDR_RX: // Modified file upload, starting address is sent. + begin + + // Address - 1=:24, 1 = 23:16, 2 = 15:8, 3 = 7:0 + if(byte_cnt < 5) + begin + addr <= (addr << 8) | io_din[7:0]; + + // 4th byte signifies address received, upload + // commences. Due to timings of an IO read, we + // set up the address and read signals + // 1 period before it is read, so at byte 4, + // we setup first read which occurs at byte 5. + // + if(byte_cnt == 4) + begin + ioctl_addr <= (addr << 8) | io_din[7:0]; + ioctl_upload <= 1; + ioctl_rd <= 1; + rd <= 1; + end + end + else + begin + // Normally the HPS sets io_din to 0 during + // receive operation. If it is set to non-zero + // the this is the end of upload marker. + // + if(io_din[7:0]) begin + ioctl_upload <= 0; + ioctl_rd <= 0; + end + else + begin + ioctl_addr <= addr; + ioctl_rd <= 1; + rd <= 1; + addr <= addr + (WIDE ? 2'd2 : 2'd1); + end + end + end + UIO_CONFIG_RX: + begin + if(byte_cnt == 1) + begin + ioctl_addr <= ({21'b100000000000000000000, io_din[3:0]}); + ioctl_rd <= 1; + rd <= 1; + ioctl_upload <= 1; + end + else + begin + if(io_din[7:0]) begin + ioctl_upload <= 0; + ioctl_rd <= 0; + end + end + io_dout <= ioctl_din[DW:0]; // This read is for previous address setup. + end + UIO_CONFIG_TX: + begin + case(byte_cnt) + 1: begin + ioctl_addr <= ({21'b100000000000000000000, io_din[3:0]}); + end + 2: begin + ioctl_dout <= io_din[DW:0]; + wr <= 1; + end + endcase + end + endcase + end + end + end +end + +/////////////////////////////// PS2 /////////////////////////////// +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +reg [7:0] kbd_data; +reg kbd_we; +wire [8:0] kbd_data_host; +reg kbd_rd; + +ps2_device keyboard +( + .clk_sys(clk_sys), + + .wdata(kbd_data), + .we(kbd_we), + + .ps2_clk(clk_ps2), + .ps2_clk_out(ps2_kbd_clk_out), + .ps2_dat_out(ps2_kbd_data_out), + + .ps2_clk_in(ps2_kbd_clk_in || !PS2WE), + .ps2_dat_in(ps2_kbd_data_in || !PS2WE), + + .rdata(kbd_data_host), + .rd(kbd_rd) +); + +reg [7:0] mouse_data; +reg mouse_we; +wire [8:0] mouse_data_host; +reg mouse_rd; + +ps2_device mouse +( + .clk_sys(clk_sys), + + .wdata(mouse_data), + .we(mouse_we), + + .ps2_clk(clk_ps2), + .ps2_clk_out(ps2_mouse_clk_out), + .ps2_dat_out(ps2_mouse_data_out), + + .ps2_clk_in(ps2_mouse_clk_in || !PS2WE), + .ps2_dat_in(ps2_mouse_data_in || !PS2WE), + + .rdata(mouse_data_host), + .rd(mouse_rd) +); + +endmodule + + +//reg [31:0] ps2_key_raw = 0; +//wire pressed = (ps2_key_raw[15:8] != 8'hf0); +//wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); +// +//always@(posedge clk_sys) begin +// reg [15:0] cmd; +// reg [9:0] byte_cnt; // counts bytes +// reg [2:0] b_wr; +// reg [2:0] stick_idx; +// reg [24:0] addr; +// reg ps2skip = 0; +// +// sd_buff_wr <= b_wr[0]; +// if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; +// b_wr <= (b_wr<<1); +// +// {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0; +// +// if(~io_enable) begin +// if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24]; +// if(cmd == 5 && !ps2skip) begin +// ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; +// if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed +// if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released +// if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed +// end +// if(cmd == 'h22) RTC[64] <= ~RTC[64]; +// if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32]; +// cmd <= 0; +// byte_cnt <= 0; +// sd_ack <= 0; +// sd_ack_conf <= 0; +// io_dout <= 0; +// ps2skip <= 0; +// addr <= 0; +// end else begin +// if(io_strobe) begin +// +// io_dout <= 0; +// if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; +// +// if(byte_cnt == 0) begin +// cmd <= io_din; +// +// case(io_din) +// 'h19: sd_ack_conf <= 1; +// 'h17, +// 'h18: sd_ack <= 1; +// endcase +// +// sd_buff_addr <= 0; +// img_mounted <= 0; +// if(io_din == 5) ps2_key_raw <= 0; +// end else begin +// +// case(cmd) +// // buttons and switches +// 'h01: cfg <= io_din[7:0]; +// 'h02: joystick_0 <= io_din; +// 'h03: joystick_1 <= io_din; +// +// // store incoming ps2 mouse bytes +// 'h04: begin +// mouse_data <= io_din[7:0]; +// mouse_we <= 1; +// if(&io_din[15:8]) ps2skip <= 1; +// if(~&io_din[15:8] & ~ps2skip) begin +// case(byte_cnt) +// 1: ps2_mouse[7:0] <= io_din[7:0]; +// 2: ps2_mouse[15:8] <= io_din[7:0]; +// 3: ps2_mouse[23:16] <= io_din[7:0]; +// endcase +// end +// end +// +// // store incoming ps2 keyboard bytes +// 'h05: begin +// if(&io_din[15:8]) ps2skip <= 1; +// if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]}; +// kbd_data <= io_din[7:0]; +// kbd_we <= 1; +// end +// +// // reading config string +// 'h14: begin +// // returning a byte from string +// if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8]; +// end +// +// // reading sd card status +// 'h16: begin +// case(byte_cnt) +// 1: io_dout <= sd_cmd; +// 2: io_dout <= sd_lba[15:0]; +// 3: io_dout <= sd_lba[31:16]; +// endcase +// end +// +// // send SD config IO -> FPGA +// // flag that download begins +// // sd card knows data is config if sd_dout_strobe is asserted +// // with sd_ack still being inactive (low) +// 'h19, +// // send sector IO -> FPGA +// // flag that download begins +// 'h17: begin +// sd_buff_dout <= io_din[DW:0]; +// b_wr <= 1; +// end +// +// // reading sd card write data +// 'h18: begin +// if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; +// io_dout <= sd_buff_din; +// end +// +// // joystick analog +// 'h1a: begin +// // first byte is joystick index +// if(byte_cnt == 1) stick_idx <= io_din[2:0]; +// if(byte_cnt == 2) begin +// if(stick_idx == 0) joystick_analog_0 <= io_din; +// if(stick_idx == 1) joystick_analog_1 <= io_din; +// end +// end +// +// // notify image selection +// 'h1c: begin +// img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1; +// img_readonly <= io_din[7]; +// end +// +// // send image info +// 'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din; +// +// // status, 32bit version +// 'h1e: if(byte_cnt==1) status[15:0] <= io_din; +// else if(byte_cnt==2) status[31:16] <= io_din; +// +// // reading keyboard LED status +// 'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]}; +// +// // reading ps2 keyboard/mouse control +// 'h21: begin +// if(byte_cnt == 1) begin +// io_dout <= kbd_data_host; +// kbd_rd <= 1; +// end +// +// if(byte_cnt == 2) begin +// io_dout <= mouse_data_host; +// mouse_rd <= 1; +// end +// end +// //RTC +// 'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din; +// +// //Video res. +// 'h23: begin +// case(byte_cnt) +// 1: io_dout <= vid_nres; +// 2: io_dout <= vid_hcnt[15:0]; +// 3: io_dout <= vid_hcnt[31:16]; +// 4: io_dout <= vid_vcnt[15:0]; +// 5: io_dout <= vid_vcnt[31:16]; +// 6: io_dout <= vid_htime[15:0]; +// 7: io_dout <= vid_htime[31:16]; +// 8: io_dout <= vid_vtime[15:0]; +// 9: io_dout <= vid_vtime[31:16]; +// 10: io_dout <= vid_pix[15:0]; +// 11: io_dout <= vid_pix[31:16]; +// 12: io_dout <= vid_vtime_hdmi[15:0]; +// 13: io_dout <= vid_vtime_hdmi[31:16]; +// endcase +// end +// +// //RTC +// 'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din; +// +// // Read emulator memory, main task performed in download +// // block, this component just puts the data onto the +// // io_dout bus. +// 'h59: io_dout <= 'h55; //ioctl_din[DW:0]; +// endcase +// end +// end +// end +//end + +//localparam UIO_FILE_TX = 8'h53; +//localparam UIO_FILE_TX_DAT = 8'h54; +//localparam UIO_FILE_INDEX = 8'h55; +//localparam UIO_FILE_INFO = 8'h56; +//localparam UIO_FILE_ADDR = 8'h57; +//localparam UIO_FILE_RX = 8'h58; +//localparam UIO_FILE_RX_DAT = 8'h59; +// +//always@(posedge clk_sys) begin +// reg [15:0] cmd; +// reg has_cmd; +// reg [24:0] addr; +// reg wr; +// reg rd; +// +// ioctl_wr <= wr; +// ioctl_rd <= rd; +// wr <= 0; +// rd <= 0; +// +// if(~io_enable) has_cmd <= 0; +// else begin +// if(io_strobe) begin +// +// if(!has_cmd) begin +// cmd <= io_din; +// has_cmd <= 1; +// end else begin +// +// case(cmd) +// UIO_FILE_ADDR: // Direct setup of address, each byte becomes the lower 7-0 bits of address. +// begin +// addr <= (addr << 8) | io_din[7:0]; +// end +// +// UIO_FILE_INDEX: +// begin +// ioctl_index <= io_din[7:0]; +// end +// +// UIO_FILE_TX: +// begin +// if(io_din[7:0]) begin +// addr <= 0; +// ioctl_download <= 1; +// end else begin +// ioctl_addr <= addr; +// ioctl_download <= 0; +// end +// end +// +// UIO_FILE_TX_DAT: +// begin +// ioctl_addr <= addr; +// ioctl_dout <= io_din[DW:0]; +// wr <= 1; +// addr <= addr + (WIDE ? 2'd2 : 2'd1); +// end +// +// UIO_FILE_RX: +// begin +// if(io_din[7:0]) begin +// addr <= 0; +// ioctl_upload <= 1; +// end else begin +// ioctl_addr <= addr; +// ioctl_upload <= 0; +// end +// end +// +// UIO_FILE_RX_DAT: +// begin +// ioctl_addr <= addr; +// rd <= 1; +// addr <= addr + (WIDE ? 2'd2 : 2'd1); +// end +// endcase +// end +// end +// end +//end + +////////////////////////////////////////////////////////////////////////////////// + + +module ps2_device #(parameter PS2_FIFO_BITS=5) +( + input clk_sys, + + input [7:0] wdata, + input we, + + input ps2_clk, + output reg ps2_clk_out, + output reg ps2_dat_out, + output reg tx_empty, + + input ps2_clk_in, + input ps2_dat_in, + + output [8:0] rdata, + input rd +); + + +(* ramstyle = "logic" *) reg [7:0] fifo[1<= 1)&&(tx_state < 9)) begin + ps2_dat_out <= tx_byte[0]; // data bits + tx_byte[6:0] <= tx_byte[7:1]; // shift down + if(tx_byte[0]) + parity <= !parity; + end + + // transmission of parity + if(tx_state == 9) ps2_dat_out <= parity; + + // transmission of stop bit + if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1 + + // advance state machine + if(tx_state < 11) tx_state <= tx_state + 1'd1; + else tx_state <= 0; + end + end + end + + if(~old_clk & ps2_clk) ps2_clk_out <= 1; + if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2)); + +end + +endmodule diff --git a/sys/hq2x.sv b/sys/hq2x.sv new file mode 100644 index 0000000..02b8543 --- /dev/null +++ b/sys/hq2x.sv @@ -0,0 +1,416 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <= 1024 ? 9 : \ + N <= 2048 ?10 : 11 ) + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 11 : 23; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [23:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [23:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [23:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [23:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [23:0] h2rgb; + input [11:0] v; +begin + h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]}; +end +endfunction + +function [11:0] rgb2h; + input [23:0] v; +begin + rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output logic [DWIDTH:0] q +); + +logic [DWIDTH:0] ram[0:NUMWORDS-1]; + +always_ff@(posedge clock) begin + if(wren) ram[wraddress] <= data; + q <= ram[rdaddress]; +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [23:0] rgb1, + input [23:0] rgb2, + output result +); + + wire [7:0] r = rgb1[7:1] - rgb2[7:1]; + wire [7:0] g = rgb1[15:9] - rgb2[15:9]; + wire [7:0] b = rgb1[23:17] - rgb2[23:17]; + wire [8:0] t = $signed(r) + $signed(b); + wire [8:0] gx = {g[7], g}; + wire [9:0] y = $signed(t) + $signed(gx); + wire [8:0] u = $signed(r) - $signed(b); + wire [9:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-96..96) + wire y_inside = (y < 10'h60 || y >= 10'h3a0); + + // if u is inside (-16, 16) + wire u_inside = (u < 9'h10 || u >= 9'h1f0); + + // if v is inside (-24, 24) + wire v_inside = (v < 10'h18 || v >= 10'h3e8); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [7:0] A, + input [7:0] B, + input [7:0] C, + output [7:0] O +); + + function [10:0] mul8x3; + input [7:0] op1; + input [2:0] op2; + begin + mul8x3 = 11'd0; + if(op2[0]) mul8x3 = mul8x3 + op1; + if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0}; + if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [10:0] Amul = mul8x3(A, Op[7:5]); + wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0}); + wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0}); + wire [10:0] At = Amul; + wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [11:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[11:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [23:0] E, + input [23:0] A, + input [23:0] B, + input [23:0] D, + input [23:0] F, + input [23:0] H, + output [23:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = {11{1'bx}}; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [23:0] Input1 = E; + wire [23:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [23:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]); + InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]); + InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]); +endmodule diff --git a/sys/i2c.v b/sys/i2c.v new file mode 100644 index 0000000..1b89b4f --- /dev/null +++ b/sys/i2c.v @@ -0,0 +1,69 @@ + +module i2c +( + input CLK, + + input START, + input [23:0] I2C_DATA, + output reg END = 1, + output reg ACK = 0, + + //I2C bus + output I2C_SCL, + inout I2C_SDA +); + + +// Clock Setting +parameter CLK_Freq = 50_000_000; // 50 MHz +parameter I2C_Freq = 400_000; // 400 KHz + +reg I2C_CLOCK; +always@(negedge CLK) begin + integer mI2C_CLK_DIV = 0; + if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin + mI2C_CLK_DIV <= mI2C_CLK_DIV + 1; + end else begin + mI2C_CLK_DIV <= 0; + I2C_CLOCK <= ~I2C_CLOCK; + end +end + +assign I2C_SCL = SCLK | I2C_CLOCK; +assign I2C_SDA = SDO ? 1'bz : 1'b0; + +reg SCLK = 1, SDO = 1; + +always @(posedge CLK) begin + reg old_clk; + reg old_st; + + reg [5:0] SD_COUNTER = 'b111111; + reg [0:31] SD; + + old_clk <= I2C_CLOCK; + old_st <= START; + + if(~old_st && START) begin + SCLK <= 1; + SDO <= 1; + ACK <= 0; + END <= 0; + SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011}; + SD_COUNTER <= 0; + end else begin + if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin + SD_COUNTER <= SD_COUNTER + 6'd1; + case(SD_COUNTER) + 01: SCLK <= 0; + 10,19,28: ACK <= ACK | I2C_SDA; + 29: SCLK <= 1; + 32: END <= 1; + endcase + end + + if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]]; + end +end + +endmodule diff --git a/sys/i2s.v b/sys/i2s.v new file mode 100644 index 0000000..d0480ce --- /dev/null +++ b/sys/i2s.v @@ -0,0 +1,136 @@ + +module i2s +#( + parameter CLK_RATE = 50000000, + parameter AUDIO_DW = 16, + parameter AUDIO_RATE = 96000 +) +( + input reset, + input clk_sys, + input half_rate, + + output reg sclk, + output reg lrclk, + output reg sdata, + + input [AUDIO_DW-1:0] left_chan, + input [AUDIO_DW-1:0] right_chan +); + +localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4); +localparam ERROR_BASE = 10000; +localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE); + +reg lpf_ce; +wire [AUDIO_DW-1:0] al, ar; + +lpf_i2s lpf_l +( + .CLK(clk_sys), + .CE(lpf_ce), + .IDATA(left_chan), + .ODATA(al) +); + +lpf_i2s lpf_r +( + .CLK(clk_sys), + .CE(lpf_ce), + + .IDATA(right_chan), + .ODATA(ar) +); + +always @(posedge clk_sys) begin + reg [31:0] count_q; + reg [31:0] error_q; + reg [7:0] bit_cnt; + reg skip = 0; + + reg [AUDIO_DW-1:0] left; + reg [AUDIO_DW-1:0] right; + + reg msclk; + reg ce; + + lpf_ce <= 0; + + if (reset) begin + count_q <= 0; + error_q <= 0; + ce <= 0; + bit_cnt <= 1; + lrclk <= 1; + sclk <= 1; + msclk <= 1; + end + else + begin + if(count_q == WHOLE_CYCLES-1) begin + if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin + error_q <= error_q + ERRORS_PER_BIT[31:0]; + count_q <= 0; + end else begin + error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE; + count_q <= count_q + 1; + end + end else if(count_q == WHOLE_CYCLES) begin + count_q <= 0; + end else begin + count_q <= count_q + 1; + end + + sclk <= msclk; + if(!count_q) begin + ce <= ~ce; + if(~half_rate || ce) begin + msclk <= ~msclk; + if(msclk) begin + skip <= ~skip; + if(skip) lpf_ce <= 1; + if(bit_cnt >= AUDIO_DW) begin + bit_cnt <= 1; + lrclk <= ~lrclk; + if(lrclk) begin + left <= al; + right <= ar; + end + end + else begin + bit_cnt <= bit_cnt + 1'd1; + end + sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; + end + end + end + end +end + +endmodule + +module lpf_i2s +( + input CLK, + input CE, + input [15:0] IDATA, + output reg [15:0] ODATA +); + +reg [511:0] acc; +reg [20:0] sum; + +always @(*) begin + integer i; + sum = 0; + for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]}; +end + +always @(posedge CLK) begin + if(CE) begin + acc <= {acc[495:0], IDATA}; + ODATA <= sum[20:5]; + end +end + +endmodule diff --git a/sys/ip/avalon_combiner.v b/sys/ip/avalon_combiner.v new file mode 100644 index 0000000..3a26c6a --- /dev/null +++ b/sys/ip/avalon_combiner.v @@ -0,0 +1,60 @@ +// avalon_combiner.v + +`timescale 1 ps / 1 ps +module avalon_combiner +( + input wire clk, // clock.clk + input wire rst, // reset.reset + + output wire [6:0] mixer_address, // ctl_mixer.address + output wire [3:0] mixer_byteenable, // .byteenable + output wire mixer_write, // .write + output wire [31:0] mixer_writedata, // .writedata + input wire mixer_waitrequest, // .waitrequest + + output wire [6:0] scaler_address, // ctl_scaler.address + output wire [3:0] scaler_byteenable, // .byteenable + input wire scaler_waitrequest, // .waitrequest + output wire scaler_write, // .write + output wire [31:0] scaler_writedata, // .writedata + + output wire [7:0] video_address, // ctl_video.address + output wire [3:0] video_byteenable, // .byteenable + input wire video_waitrequest, // .waitrequest + output wire video_write, // .write + output wire [31:0] video_writedata, // .writedata + + output wire clock, // control.clock + output wire reset, // .reset + input wire [8:0] address, // .address + input wire write, // .write + input wire [31:0] writedata, // .writedata + output wire waitrequest // .waitrequest +); + +assign clock = clk; +assign reset = rst; + +assign mixer_address = address[6:0]; +assign scaler_address = address[6:0]; +assign video_address = address[7:0]; + +assign mixer_byteenable = 4'b1111; +assign scaler_byteenable = 4'b1111; +assign video_byteenable = 4'b1111; + +wire en_scaler = (address[8:7] == 0); +wire en_mixer = (address[8:7] == 1); +wire en_video = address[8]; + +assign mixer_write = en_mixer & write; +assign scaler_write = en_scaler & write; +assign video_write = en_video & write; + +assign mixer_writedata = writedata; +assign scaler_writedata = writedata; +assign video_writedata = writedata; + +assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest); + +endmodule diff --git a/sys/ip/avalon_combiner_hw.tcl b/sys/ip/avalon_combiner_hw.tcl new file mode 100644 index 0000000..5eede9c --- /dev/null +++ b/sys/ip/avalon_combiner_hw.tcl @@ -0,0 +1,204 @@ +# TCL File Generated by Component Editor 17.0 +# Wed Dec 13 01:40:49 CST 2017 +# DO NOT MODIFY + + +# +# avalon_combiner "avalon_combiner" v17.0 +# sorgelig 2017.12.13.01:40:49 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module avalon_combiner +# +set_module_property DESCRIPTION "" +set_module_property NAME avalon_combiner +set_module_property VERSION 17.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR sorgelig +set_module_property DISPLAY_NAME avalon_combiner +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst reset Input 1 + + +# +# connection point ctl_mixer +# +add_interface ctl_mixer avalon start +set_interface_property ctl_mixer addressUnits WORDS +set_interface_property ctl_mixer associatedClock clock +set_interface_property ctl_mixer associatedReset reset +set_interface_property ctl_mixer bitsPerSymbol 8 +set_interface_property ctl_mixer burstOnBurstBoundariesOnly false +set_interface_property ctl_mixer burstcountUnits WORDS +set_interface_property ctl_mixer doStreamReads false +set_interface_property ctl_mixer doStreamWrites false +set_interface_property ctl_mixer holdTime 0 +set_interface_property ctl_mixer linewrapBursts false +set_interface_property ctl_mixer maximumPendingReadTransactions 0 +set_interface_property ctl_mixer maximumPendingWriteTransactions 0 +set_interface_property ctl_mixer readLatency 0 +set_interface_property ctl_mixer readWaitTime 1 +set_interface_property ctl_mixer setupTime 0 +set_interface_property ctl_mixer timingUnits Cycles +set_interface_property ctl_mixer writeWaitTime 0 +set_interface_property ctl_mixer ENABLED true +set_interface_property ctl_mixer EXPORT_OF "" +set_interface_property ctl_mixer PORT_NAME_MAP "" +set_interface_property ctl_mixer CMSIS_SVD_VARIABLES "" +set_interface_property ctl_mixer SVD_ADDRESS_GROUP "" + +add_interface_port ctl_mixer mixer_address address Output 7 +add_interface_port ctl_mixer mixer_byteenable byteenable Output 4 +add_interface_port ctl_mixer mixer_write write Output 1 +add_interface_port ctl_mixer mixer_writedata writedata Output 32 +add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1 + + +# +# connection point ctl_scaler +# +add_interface ctl_scaler avalon start +set_interface_property ctl_scaler addressUnits WORDS +set_interface_property ctl_scaler associatedClock clock +set_interface_property ctl_scaler associatedReset reset +set_interface_property ctl_scaler bitsPerSymbol 8 +set_interface_property ctl_scaler burstOnBurstBoundariesOnly false +set_interface_property ctl_scaler burstcountUnits WORDS +set_interface_property ctl_scaler doStreamReads false +set_interface_property ctl_scaler doStreamWrites false +set_interface_property ctl_scaler holdTime 0 +set_interface_property ctl_scaler linewrapBursts false +set_interface_property ctl_scaler maximumPendingReadTransactions 0 +set_interface_property ctl_scaler maximumPendingWriteTransactions 0 +set_interface_property ctl_scaler readLatency 0 +set_interface_property ctl_scaler readWaitTime 1 +set_interface_property ctl_scaler setupTime 0 +set_interface_property ctl_scaler timingUnits Cycles +set_interface_property ctl_scaler writeWaitTime 0 +set_interface_property ctl_scaler ENABLED true +set_interface_property ctl_scaler EXPORT_OF "" +set_interface_property ctl_scaler PORT_NAME_MAP "" +set_interface_property ctl_scaler CMSIS_SVD_VARIABLES "" +set_interface_property ctl_scaler SVD_ADDRESS_GROUP "" + +add_interface_port ctl_scaler scaler_address address Output 7 +add_interface_port ctl_scaler scaler_byteenable byteenable Output 4 +add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1 +add_interface_port ctl_scaler scaler_write write Output 1 +add_interface_port ctl_scaler scaler_writedata writedata Output 32 + + +# +# connection point ctl_video +# +add_interface ctl_video avalon start +set_interface_property ctl_video addressUnits WORDS +set_interface_property ctl_video associatedClock clock +set_interface_property ctl_video associatedReset reset +set_interface_property ctl_video bitsPerSymbol 8 +set_interface_property ctl_video burstOnBurstBoundariesOnly false +set_interface_property ctl_video burstcountUnits WORDS +set_interface_property ctl_video doStreamReads false +set_interface_property ctl_video doStreamWrites false +set_interface_property ctl_video holdTime 0 +set_interface_property ctl_video linewrapBursts false +set_interface_property ctl_video maximumPendingReadTransactions 0 +set_interface_property ctl_video maximumPendingWriteTransactions 0 +set_interface_property ctl_video readLatency 0 +set_interface_property ctl_video readWaitTime 1 +set_interface_property ctl_video setupTime 0 +set_interface_property ctl_video timingUnits Cycles +set_interface_property ctl_video writeWaitTime 0 +set_interface_property ctl_video ENABLED true +set_interface_property ctl_video EXPORT_OF "" +set_interface_property ctl_video PORT_NAME_MAP "" +set_interface_property ctl_video CMSIS_SVD_VARIABLES "" +set_interface_property ctl_video SVD_ADDRESS_GROUP "" + +add_interface_port ctl_video video_address address Output 8 +add_interface_port ctl_video video_byteenable byteenable Output 4 +add_interface_port ctl_video video_waitrequest waitrequest Input 1 +add_interface_port ctl_video video_write write Output 1 +add_interface_port ctl_video video_writedata writedata Output 32 + + +# +# connection point control +# +add_interface control conduit end +set_interface_property control associatedClock clock +set_interface_property control associatedReset reset +set_interface_property control ENABLED true +set_interface_property control EXPORT_OF "" +set_interface_property control PORT_NAME_MAP "" +set_interface_property control CMSIS_SVD_VARIABLES "" +set_interface_property control SVD_ADDRESS_GROUP "" + +add_interface_port control address address Input 9 +add_interface_port control write write Input 1 +add_interface_port control writedata writedata Input 32 +add_interface_port control waitrequest waitrequest Output 1 +add_interface_port control clock clock Output 1 +add_interface_port control reset reset Output 1 + diff --git a/sys/ip/de10_hps_hw.tcl b/sys/ip/de10_hps_hw.tcl new file mode 100644 index 0000000..a166ca0 --- /dev/null +++ b/sys/ip/de10_hps_hw.tcl @@ -0,0 +1,3706 @@ +# (C) 2001-2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# This IP is modified standard Altera HPS IP. +# Direct DDR3 SDRAM access has been removed since it won't work together with HPS DDR3 SDRAM access. +# FPGA access the memory through MPFE (FPGA2SDRAM bridge). +# By removing direct DDR3 SDRAM access synthesis time has been reduced by 3 times! + + +package require -exact qsys 12.0 +package require -exact altera_terp 1.0 +package require quartus::advanced_wysiwyg + +set_module_property NAME altera_hps_lite +set_module_property VERSION 17.0 +set_module_property AUTHOR "Altera Corporation/Sorgelig" +set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV} + +set_module_property DISPLAY_NAME "DE10-nano Hard Processor System" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE false +set_module_property HIDE_FROM_SOPC true +set_module_property HIDE_FROM_QUARTUS true + +add_documentation_link "HPS User Guide for Cyclone V" "http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf" +add_documentation_link "HPS User Guide for Arria V" "http://www.altera.com/literature/hb/arria-v/av_5v4.pdf" + +set alt_mem_if_tcl_libs_dir "$env(QUARTUS_ROOTDIR)/../ip/altera/alt_mem_if/alt_mem_if_tcl_packages" +if {[lsearch -exact $auto_path $alt_mem_if_tcl_libs_dir] == -1} { + lappend auto_path $alt_mem_if_tcl_libs_dir +} + +package require alt_mem_if::gui::system_info + +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/constants.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/procedures.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux_db.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/locations.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/ui.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clocks.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clock_manager.tcl + +proc add_storage_parameter {name { default_value {} } } { + add_parameter $name string $default_value "" + set_parameter_property $name derived true + set_parameter_property $name visible false +} + +proc add_reset_parameters {} { + set group_name "Resets" + add_display_item "FPGA Interfaces" $group_name "group" "" + + add_parameter S2FCLK_COLDRST_Enable boolean false "" + set_parameter_property S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output" + set_parameter_property S2FCLK_COLDRST_Enable group $group_name + + add_parameter S2FCLK_PENDINGRST_Enable boolean false "" + set_parameter_property S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals" + set_parameter_property S2FCLK_PENDINGRST_Enable group $group_name + + add_parameter F2SCLK_DBGRST_Enable boolean false "" + set_parameter_property F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request" + set_parameter_property F2SCLK_DBGRST_Enable group $group_name + + add_parameter F2SCLK_WARMRST_Enable boolean false "" + set_parameter_property F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request" + set_parameter_property F2SCLK_WARMRST_Enable group $group_name + + add_parameter F2SCLK_COLDRST_Enable boolean false "" + set_parameter_property F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request" + set_parameter_property F2SCLK_COLDRST_Enable group $group_name + +} + +proc list_h2f_interrupt_groups {} { + return { + "CAN" "CLOCKPERIPHERAL" "CTI" + "DMA" "EMAC" "FPGAMANAGER" + "GPIO" "I2CEMAC" "I2CPERIPHERAL" + "L4TIMER" "NAND" "OSCTIMER" + "QSPI" "SDMMC" "SPIMASTER" + "SPISLAVE" "UART" "USB" + "WATCHDOG" + } +} + +proc get_h2f_interrupt_descriptions {data_ref} { + upvar 1 $data_ref data + array set data { + "DMA" "Enable DMA interrupts" + "EMAC" "Enable EMAC interrupts (for EMAC0 and EMAC1)" + "USB" "Enable USB interrupts" + "CAN" "Enable CAN interrupts" + "SDMMC" "Enable SD/MMC interrupt" + "NAND" "Enable NAND interrupt" + "QSPI" "Enable Quad SPI interrupt" + "SPIMASTER" "Enable SPI master interrupts" + "SPISLAVE" "Enable SPI slave interrupts" + "I2CPERIPHERAL" "Enable I2C peripheral interrupts (for I2C0 and I2C1)" + "I2CEMAC" "Enable I2C-EMAC interrupts (for I2C2 and I2C3)" + "UART" "Enable UART interrupts" + "GPIO" "Enable GPIO interrupts" + "L4TIMER" "Enable L4 timer interrupts" + "OSCTIMER" "Enable OSC timer interrupts" + "WATCHDOG" "Enable watchdog interrupts" + "CLOCKPERIPHERAL" "Enable clock peripheral interrupts" + "FPGAMANAGER" "Enable FPGA manager interrupt" + "CTI" "Enable CTI interrupts" + } +} + +proc load_h2f_interrupt_table {functions_by_group_ref + width_by_function_ref + inverted_by_function_ref} { + upvar 1 $functions_by_group_ref functions_by_group + upvar 1 $width_by_function_ref width_by_function + upvar 1 $inverted_by_function_ref inverted_by_function + array set functions_by_group { + "DMA" {"dma" "dma_abort" } + "EMAC" {"emac0" "emac1" } + "USB" {"usb0" "usb1" } + "CAN" {"can0" "can1" } + "SDMMC" {"sdmmc" } + "NAND" {"nand" } + "QSPI" {"qspi" } + "SPIMASTER" {"spi0" "spi1" } + "SPISLAVE" {"spi2" "spi3" } + "I2CPERIPHERAL" {"i2c0" "i2c1" } + "I2CEMAC" {"i2c_emac0" "i2c_emac1" } + "UART" {"uart0" "uart1" } + "GPIO" {"gpio0" "gpio1" "gpio2"} + "L4TIMER" {"l4sp0" "l4sp1" } + "OSCTIMER" {"osc0" "osc1" } + "WATCHDOG" {"wdog0" "wdog1" } + "CLOCKPERIPHERAL" {"clkmgr" "mpuwakeup" } + "FPGAMANAGER" {"fpga_man" } + "CTI" {"cti" } + } + array set width_by_function { + "dma" 8 + "cti" 2 + } + array set inverted_by_function { + "cti" 1 + } +} + +proc add_interrupt_parameters {} { + set top_group_name "Interrupts" + add_display_item "FPGA Interfaces" $top_group_name "group" "" + + # add_display_item $group_name "f2h_interrupts_label" "text" "FPGA-to-HPS" + add_parameter F2SINTERRUPT_Enable boolean false + set_parameter_property F2SINTERRUPT_Enable enabled true + set_parameter_property F2SINTERRUPT_Enable display_name "Enable FPGA-to-HPS Interrupts" + set_parameter_property F2SINTERRUPT_Enable group $top_group_name + + set inner_group_name "HPS-to-FPGA" + add_display_item $top_group_name $inner_group_name "group" "" + get_h2f_interrupt_descriptions descriptions_by_group + set interrupt_groups [list_h2f_interrupt_groups] + foreach interrupt_group $interrupt_groups { + set parameter "S2FINTERRUPT_${interrupt_group}_Enable" + add_parameter $parameter boolean false + set_parameter_property $parameter enabled true + set_parameter_property $parameter display_name $descriptions_by_group($interrupt_group) + set_parameter_property $parameter group $inner_group_name + } +} + +proc add_dma_parameters {} { + set group_name "DMA Peripheral Request" + add_display_item "FPGA Interfaces" $group_name "group" "" + add_display_item $group_name "DMA Table" "group" "table" + + add_parameter DMA_PeriphId_DERIVED string_list {0 1 2 3 4 5 6 7} + set_parameter_property DMA_PeriphId_DERIVED display_name "Peripheral Request ID" + set_parameter_property DMA_PeriphId_DERIVED derived true + set_parameter_property DMA_PeriphId_DERIVED display_hint "FIXED_SIZE" + set_parameter_property DMA_PeriphId_DERIVED group "DMA Table" + + add_parameter DMA_Enable string_list {"No" "No" "No" "No" "No" "No" "No" "No"} + set_parameter_property DMA_Enable allowed_ranges {"Yes" "No"} + set_parameter_property DMA_Enable display_name "Enabled" + set_parameter_property DMA_Enable display_hint "FIXED_SIZE" + set_parameter_property DMA_Enable group "DMA Table" +} + +proc range_from_zero {end} { + set result [list] + for {set i 0} {$i <= $end} {incr i} { + lappend result $i + } + return $result +} + +proc create_generic_parameters {} { + + ::alt_mem_if::util::hwtcl_utils::_add_parameter SYS_INFO_DEVICE_FAMILY STRING "" + set_parameter_property SYS_INFO_DEVICE_FAMILY SYSTEM_INFO DEVICE_FAMILY + set_parameter_property SYS_INFO_DEVICE_FAMILY VISIBLE FALSE + + ::alt_mem_if::util::hwtcl_utils::_add_parameter DEVICE_FAMILY STRING "" + set_parameter_property DEVICE_FAMILY DERIVED true + set_parameter_property DEVICE_FAMILY VISIBLE FALSE + + return 1 +} + +create_generic_parameters + +add_display_item "" "FPGA Interfaces" "group" "tab" +add_display_item "" "Peripheral Pins" "group" "tab" +add_display_item "" "HPS Clocks" "group" "tab" +add_clock_tab "HPS Clocks" + +add_display_item "FPGA Interfaces" "General" "group" "" + +add_parameter MPU_EVENTS_Enable boolean true +set_parameter_property MPU_EVENTS_Enable display_name "Enable MPU standby and event signals" +set_parameter_property MPU_EVENTS_Enable description "Enables elaboration of the mpu_events interface." +set_parameter_property MPU_EVENTS_Enable group "General" + +add_parameter GP_Enable boolean false +set_parameter_property GP_Enable display_name "Enable general purpose signals" +set_parameter_property GP_Enable description "Enables elaboration of interface h2f_gp." +set_parameter_property GP_Enable group "General" + +add_parameter DEBUGAPB_Enable boolean false +set_parameter_property DEBUGAPB_Enable display_name "Enable Debug APB interface" +set_parameter_property DEBUGAPB_Enable description "Enables elaboration of Debug APB interfaces." +set_parameter_property DEBUGAPB_Enable group "General" + +add_parameter STM_Enable boolean false +set_parameter_property STM_Enable display_name "Enable System Trace Macrocell hardware events" +set_parameter_property STM_Enable description "Enables elaboration of interface stm_hwevents." +set_parameter_property STM_Enable group "General" + +add_parameter CTI_Enable boolean false +set_parameter_property CTI_Enable display_name "Enable FPGA Cross Trigger Interface" +set_parameter_property CTI_Enable description "Enables elaboration of interface cti_trigger, cti_clk_in." +set_parameter_property CTI_Enable group "General" + +add_parameter TPIUFPGA_Enable boolean false +set_parameter_property TPIUFPGA_Enable display_name "Enable FPGA Trace Port Interface Unit" +set_parameter_property TPIUFPGA_Enable description "Enables elaboration of TPIU FPGA interfaces." +set_parameter_property TPIUFPGA_Enable group "General" + +add_parameter TPIUFPGA_alt boolean false +set_parameter_property TPIUFPGA_alt display_name "Enable FPGA Trace Port Alternate FPGA Interface" +set_parameter_property TPIUFPGA_alt description "When the trace port is enabled, it creates an interface compatible with the Arria 10 Trace Interface. (This just moves the clock_in port into the same conduit)" +set_parameter_property TPIUFPGA_alt group "General" +set_parameter_property TPIUFPGA_alt enabled false + + +add_parameter BOOTFROMFPGA_Enable boolean false +set_parameter_property BOOTFROMFPGA_Enable enabled true +set_parameter_property BOOTFROMFPGA_Enable display_name "Enable boot from fpga signals" +set_parameter_property BOOTFROMFPGA_Enable description "Enables elaboration of interface boot_from_fpga." +set_parameter_property BOOTFROMFPGA_Enable group "General" + +add_parameter TEST_Enable boolean false +set_parameter_property TEST_Enable enabled true +set_parameter_property TEST_Enable display_name "Enable Test Interface" +set_parameter_property TEST_Enable group "General" + +add_parameter HLGPI_Enable boolean false +set_parameter_property HLGPI_Enable enabled true +set_parameter_property HLGPI_Enable display_name "Enable HLGPI Interface" +set_parameter_property HLGPI_Enable group "General" + +add_display_item "FPGA Interfaces" "Boot and Clock Selection" "group" "" +add_parameter BSEL_EN boolean false +set_parameter_property BSEL_EN enabled true +set_parameter_property BSEL_EN display_name "Enable boot selection from FPGA" +set_parameter_property BSEL_EN group "Boot and Clock Selection" +set_parameter_property BSEL_EN visible false +set_parameter_property BSEL_EN enabled false + +add_parameter BSEL integer 1 +set_parameter_property BSEL allowed_ranges {"1:FPGA" "2:NAND Flash (1.8v)" "3:NAND Flash (3.0v)" "4:SD/MMC External Transceiver (1.8v)" "5:SD/MMC Internal Transceiver (3.0v)" "6:Quad SPI Flash (1.8v)" "7:Quad SPI Flash (3.0v)"} +set_parameter_property BSEL display_name "Boot selection from FPGA" +set_parameter_property BSEL group "Boot and Clock Selection" +set_parameter_property BSEL visible false +set_parameter_property BSEL enabled false + +add_parameter CSEL_EN boolean false +set_parameter_property CSEL_EN enabled true +set_parameter_property CSEL_EN display_name "Enable clock selection from FPGA" +set_parameter_property CSEL_EN group "Boot and Clock Selection" +set_parameter_property CSEL_EN visible false +set_parameter_property CSEL_EN enabled false + +add_parameter CSEL integer 0 +set_parameter_property CSEL allowed_ranges {"0:CSEL_0" "1:CSEL_1" "2:CSEL_2" "3:CSEL_3"} +set_parameter_property CSEL display_name "Clock selection from FPGA" +set_parameter_property CSEL group "Boot and Clock Selection" +set_parameter_property CSEL visible false +set_parameter_property CSEL enabled false + +add_display_item "FPGA Interfaces" "AXI Bridges" "group" "" +add_parameter F2S_Width integer 2 +set_parameter_property F2S_Width allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"} +set_parameter_property F2S_Width display_name "FPGA-to-HPS interface width" +set_parameter_property F2S_Width hdl_parameter true +set_parameter_property F2S_Width group "AXI Bridges" + +add_parameter S2F_Width integer 2 +set_parameter_property S2F_Width allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"} +set_parameter_property S2F_Width display_name "HPS-to-FPGA interface width" +set_parameter_property S2F_Width hdl_parameter true +set_parameter_property S2F_Width group "AXI Bridges" + +add_parameter LWH2F_Enable string true +set_parameter_property LWH2F_Enable display_name "Lightweight HPS-to-FPGA interface width" +set_parameter_property LWH2F_Enable description "The lightweight HPS-to-FPGA bridge provides a secondary, fixed-width, smaller address space, lower-performance master interface to the FPGA fabric. Use the lightweight HPS-to-FPGA bridge for high-latency, low-bandwidth traffic, such as memory-mapped register accesses of FPGA peripherals. This approach diverts traffic from the high-performance HPS-to-FPGA bridge, which can improve overall performance." +set_parameter_property LWH2F_Enable allowed_ranges {"true:32-bit" "false:Unused"} +set_parameter_property LWH2F_Enable group "AXI Bridges" + + +set group_name "FPGA-to-HPS SDRAM Interface" +add_display_item "FPGA Interfaces" $group_name "group" "" +add_display_item $group_name "f2sdram_label" "text" "Click the '+' and '-' buttons to add and remove FPGA-to-HPS SDRAM ports." +set table_name "F2SDRAM Settings" +add_display_item $group_name $table_name "group" "table" + +add_parameter F2SDRAM_Name_DERIVED string_list {"f2h_sdram0"} +set_parameter_property F2SDRAM_Name_DERIVED derived true +set_parameter_property F2SDRAM_Name_DERIVED display_name "Name" +set_parameter_property F2SDRAM_Name_DERIVED group $table_name + +add_parameter F2SDRAM_Type string_list [list [F2HSDRAM_AXI3]] +set_parameter_property F2SDRAM_Type allowed_ranges [list [F2HSDRAM_AXI3] [F2HSDRAM_AVM] [F2HSDRAM_AVM_WRITEONLY] [F2HSDRAM_AVM_READONLY]] +set_parameter_property F2SDRAM_Type display_name "Type" +set_parameter_property F2SDRAM_Type group $table_name + +add_parameter F2SDRAM_Width integer_list {"64"} +set_parameter_property F2SDRAM_Width allowed_ranges "32,64,128,256" +set_parameter_property F2SDRAM_Width display_name "Width" +set_parameter_property F2SDRAM_Width group $table_name +set_parameter_update_callback F2SDRAM_Width on_altered_f2sdram_width +# TODO: f2sdram derived parameters for resource counts in the table +# TODO: f2sdram derived parameters for remaining resources, not a part of the table + +add_storage_parameter F2SDRAM_Width_Last_Size 1 +add_storage_parameter F2SDRAM_CMD_PORT_USED 0 +add_storage_parameter F2SDRAM_WR_PORT_USED 0 +add_storage_parameter F2SDRAM_RD_PORT_USED 0 +add_storage_parameter F2SDRAM_RST_PORT_USED 0 +set_parameter_property F2SDRAM_Width_Last_Size group $group_name +set_parameter_property F2SDRAM_CMD_PORT_USED group $group_name +set_parameter_property F2SDRAM_WR_PORT_USED group $group_name +set_parameter_property F2SDRAM_RD_PORT_USED group $group_name +set_parameter_property F2SDRAM_RST_PORT_USED group $group_name + +#Parameter to export Bonding_out signal from fpga2sdram Atom +add_parameter BONDING_OUT_ENABLED boolean false +set_parameter_property BONDING_OUT_ENABLED display_name "Enable BONDING-OUT signals" +set_parameter_property BONDING_OUT_ENABLED group $group_name +set_parameter_property BONDING_OUT_ENABLED enabled false +set_parameter_property BONDING_OUT_ENABLED visible false + + +proc on_altered_f2sdram_width { param } { + set old_size [get_parameter_value F2SDRAM_Width_Last_Size] + set current_value [get_parameter_value F2SDRAM_Width] + set current_size [llength $current_value] + + if {$current_size == $old_size + 1} { ;# look for case of newly added row + set last_element_index [expr {$current_size - 1}] + set new_value [lreplace $current_value $last_element_index $last_element_index "64"] + set_parameter_value F2SDRAM_Width $new_value + } +} + +add_reset_parameters + +add_dma_parameters + +add_interrupt_parameters + + set group_name "EMAC ptp interface" + add_display_item "FPGA Interfaces" $group_name "group" "" + + add_parameter EMAC0_PTP boolean false + set_parameter_property EMAC0_PTP display_name "Enable EMAC0 Precision Time Protocol (PTP) FPGA Interface" + set_parameter_property EMAC0_PTP hdl_parameter false + set_parameter_property EMAC0_PTP enabled false + set_parameter_property EMAC0_PTP group $group_name + set_parameter_property EMAC0_PTP description "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available." + + add_parameter EMAC1_PTP boolean false + set_parameter_property EMAC1_PTP display_name "Enable EMAC1 Precision Time Protocol (PTP) FPGA Interface" + set_parameter_property EMAC1_PTP hdl_parameter false + set_parameter_property EMAC1_PTP enabled false + set_parameter_property EMAC1_PTP group $group_name + set_parameter_property EMAC1_PTP description "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available." + + +proc make_mode_display_name {peripheral} { + set default_suffix "mode" + array set custom_suffix_by_peripheral { + USB0 "PHY interface mode" + USB1 "PHY interface mode" + } + if {[info exists custom_suffix_by_peripheral($peripheral)]} { + set suffix $custom_suffix_by_peripheral($peripheral) + } else { + set suffix $default_suffix + } + + set display_name "${peripheral} ${suffix}" + return $display_name +} + +proc add_peripheral_pin_muxing_parameters {} { + set TOP_LEVEL_GROUP_NAME "Peripheral Pins" + + + foreach group_name [list_group_names] { + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + foreach peripheral_name [peripherals_in_group $group_name] { + set pin_muxing_param_name "${peripheral_name}_PinMuxing" + set mode_param_name "${peripheral_name}_Mode" + add_parameter $pin_muxing_param_name string [UNUSED_MUX_VALUE] + set_parameter_property $pin_muxing_param_name enabled false + set_parameter_property $pin_muxing_param_name display_name "${peripheral_name} pin" + set_parameter_property $pin_muxing_param_name allowed_ranges [UNUSED_MUX_VALUE] + set_parameter_property $pin_muxing_param_name group $group_name + set_parameter_update_callback $pin_muxing_param_name on_altered_peripheral_pin_muxing $peripheral_name + + set mode_display_name [make_mode_display_name $peripheral_name] + add_parameter $mode_param_name string [NA_MODE_VALUE] + set_parameter_property $mode_param_name enabled false + set_parameter_property $mode_param_name display_name $mode_display_name + set_parameter_property $mode_param_name allowed_ranges [NA_MODE_VALUE] + set_parameter_property $mode_param_name group $group_name + + if {[string match "*EMAC*" $peripheral_name]} { + set_parameter_update_callback $mode_param_name on_emac_mode_switch_internal $peripheral_name + } + } + } +} +add_peripheral_pin_muxing_parameters + +proc add_gpio_parameters {} { + set TOP_LEVEL_GROUP_NAME "Peripheral Pins" + set group_name "Peripherals Mux Table" + set table_name "Conflict Table" + + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + #add_display_item $group_name $table_name "group" "table" + + add_parameter Customer_Pin_Name_DERIVED string_list {} + set_parameter_property Customer_Pin_Name_DERIVED display_name "Pin Name" + set_parameter_property Customer_Pin_Name_DERIVED derived true + set_parameter_property Customer_Pin_Name_DERIVED display_hint "FIXED_SIZE" + set_parameter_property Customer_Pin_Name_DERIVED visible false + # set_parameter_property Customer_Pin_Name_DERIVED group $table_name + + add_parameter GPIO_Conflict_DERIVED string_list {} + set_parameter_property GPIO_Conflict_DERIVED display_name "Used by" + set_parameter_property GPIO_Conflict_DERIVED derived true + set_parameter_property GPIO_Conflict_DERIVED display_hint "FIXED_SIZE" + set_parameter_property GPIO_Conflict_DERIVED visible false + #set_parameter_property GPIO_Conflict_DERIVED group $table_name + + add_parameter GPIO_Name_DERIVED string_list {} + set_parameter_property GPIO_Name_DERIVED display_name "GPIO" + set_parameter_property GPIO_Name_DERIVED derived true + set_parameter_property GPIO_Name_DERIVED display_hint "FIXED_SIZE" + set_parameter_property GPIO_Name_DERIVED visible false + #set_parameter_property GPIO_Name_DERIVED group $table_name + + # TODO: change? + set max_possible_gpio_options 100 + set enable_list [list] + for {set i 0} {$i < $max_possible_gpio_options} {incr i} { + lappend enable_list "No" + } + + add_parameter GPIO_Enable string_list $enable_list + set_parameter_property GPIO_Enable allowed_ranges {"Yes" "No"} + set_parameter_property GPIO_Enable display_name "GPIO Enabled" + set_parameter_property GPIO_Enable visible false + # set_parameter_property GPIO_Enable group $table_name + + add_parameter LOANIO_Name_DERIVED string_list {} + set_parameter_property LOANIO_Name_DERIVED display_name "Loan I/O" + set_parameter_property LOANIO_Name_DERIVED derived true + set_parameter_property LOANIO_Name_DERIVED display_hint "FIXED_SIZE" + set_parameter_property LOANIO_Name_DERIVED visible false + + add_parameter GPIO_Pin_Used_DERIVED boolean false + set_parameter_property GPIO_Pin_Used_DERIVED display_name "GPIO Pin Used" + set_parameter_property GPIO_Pin_Used_DERIVED derived true + set_parameter_property GPIO_Pin_Used_DERIVED display_hint "GPIO Pin Used" + set_parameter_property GPIO_Pin_Used_DERIVED visible false + + add_parameter LOANIO_Enable string_list $enable_list + set_parameter_property LOANIO_Enable allowed_ranges {"Yes" "No"} + set_parameter_property LOANIO_Enable display_name "Loan I/O Enabled" + set_parameter_property LOANIO_Enable visible false + #set_parameter_property LOANIO_Enable group $table_name + + + +} +add_gpio_parameters + +proc add_reset_parameters {} { + set group_name "Resets" + add_display_item "FPGA Interfaces" $group_name "group" "" + + add_parameter S2FCLK_COLDRST_Enable boolean false "" + set_parameter_property S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output" + set_parameter_property S2FCLK_COLDRST_Enable group $group_name + + add_parameter S2FCLK_PENDINGRST_Enable boolean false "" + set_parameter_property S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals" + set_parameter_property S2FCLK_PENDINGRST_Enable group $group_name + + add_parameter F2SCLK_DBGRST_Enable boolean false "" + set_parameter_property F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request" + set_parameter_property F2SCLK_DBGRST_Enable group $group_name + + add_parameter F2SCLK_WARMRST_Enable boolean false "" + set_parameter_property F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request" + set_parameter_property F2SCLK_WARMRST_Enable group $group_name + + add_parameter F2SCLK_COLDRST_Enable boolean false "" + set_parameter_property F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request" + set_parameter_property F2SCLK_COLDRST_Enable group $group_name + +} + +proc add_java_gui_parameters {} { + set TOP_LEVEL_GROUP_NAME "Peripheral Pins" + set group_name "Peripherals Mux Table" + + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + # add_display_item $group_name the_widget "group" "" + + add_parameter JAVA_CONFLICT_PIN string_list {} + set_parameter_property JAVA_CONFLICT_PIN derived true + set_parameter_property JAVA_CONFLICT_PIN visible false + + + add_parameter JAVA_GUI_PIN_LIST string_list {} + set_parameter_property JAVA_GUI_PIN_LIST derived true + set_parameter_property JAVA_GUI_PIN_LIST visible false + + set peripherals [list_peripheral_names] + set widget_parameter [list \ + Customer_Pin_Name_DERIVED Customer_Pin_Name_DERIVED \ + GPIO_Name_DERIVED GPIO_Name_DERIVED \ + LOANIO_Name_DERIVED LOANIO_Name_DERIVED \ + LOANIO_Enable LOANIO_Enable \ + GPIO_Enable GPIO_Enable \ + JAVA_CONFLICT_PIN GUI_Conflict_Pins_List \ + JAVA_GUI_PIN_LIST GUI_GPIO_Pins_List] + + foreach peripheral_name $peripherals { + add_parameter "JAVA_${peripheral_name}_DATA" string "" + set_parameter_property "JAVA_${peripheral_name}_DATA" derived true + set_parameter_property "JAVA_${peripheral_name}_DATA" visible false + + lappend widget_parameter "JAVA_${peripheral_name}_DATA" + lappend widget_parameter "${peripheral_name}_pin_muxing" + lappend widget_parameter "${peripheral_name}_PinMuxing" + lappend widget_parameter "${peripheral_name}_PinMuxing" + lappend widget_parameter "${peripheral_name}_Mode" + lappend widget_parameter "${peripheral_name}_Mode" + } + + add_display_item $group_name the_widget "group" + set_display_item_property the_widget widget [list ../widget/pin_mux_widget.jar Altera_hps_widget] + set_display_item_property the_widget widget_parameter_map $widget_parameter +} + +add_java_gui_parameters + +############################################## +# Clocks! +# +# All clock enable parameters go here. +# Clock frequency parameters also go here. All +# the parameters need to be declared regardless +# of whether the clock will be exercised. +# +# Validation logic will enable/show frequency +# parameters based on whether the actual clock +# is being elaborated. +# +# There are four categories of clocks in this +# component: inputs on SoC I/O +# outputs on SoC I/O +# inputs on FPGA pins +# outputs on FPGA pins +# +# Inputs on SoC I/O have user-input parameters +# so the data can be consumed by downstream +# embedded software tools. +# Outputs on SoC I/O need not have frequency +# information recorded. +# Inputs on FPGA pins have system info parameters +# so the data can be consumed by downstream +# embedded software tools. +# Outputs on FPGA pins have user input parameters +# to be consumed by Quartus via SDC. +# +############################################## +proc add_clock_parameters {} { + set TOP_LEVEL_GROUP_NAME "Input Clocks" + + set group_name "User Clocks" + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + # fake group + set group_name "FPGA Interface Clocks" + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + foreach interface { + f2h_axi_clock h2f_axi_clock h2f_lw_axi_clock + f2h_sdram0_clock f2h_sdram1_clock f2h_sdram2_clock + f2h_sdram3_clock f2h_sdram4_clock f2h_sdram5_clock + h2f_cti_clock h2f_tpiu_clock_in h2f_debug_apb_clock + } { + set parameter "[string toupper ${interface}]_FREQ" + add_parameter $parameter integer 100 "" + set_parameter_property $parameter display_name "${interface} clock frequency" + set_parameter_property $parameter system_info_type "CLOCK_RATE" + set_parameter_property $parameter system_info_arg $interface + set_parameter_property $parameter visible false + set_parameter_property $parameter group $group_name + } + + set peripherals [list_peripheral_names] + + # TODO: Remove the following for 12.0 + set group_name "Peripheral FPGA Clocks" + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + # Add parameter explicitly for cross-emac ptp since it doesn't belong to a single peripheral + set parameter [form_peripheral_fpga_input_clock_frequency_parameter emac_ptp_ref_clock] + add_parameter $parameter integer 100 "" + set_parameter_property $parameter display_name "EMAC emac_ptp_ref_clock clock frequency" + set_parameter_property $parameter group $group_name + set_parameter_property $parameter system_info_type "CLOCK_RATE" + set_parameter_property $parameter system_info_arg emac_ptp_ref_clock + set_parameter_property $parameter visible false + + foreach peripheral $peripherals { + set clocks [get_peripheral_fpga_input_clocks $peripheral] + foreach clock $clocks { + set parameter [form_peripheral_fpga_input_clock_frequency_parameter $clock] + add_parameter $parameter integer 100 "" + set_parameter_property $parameter display_name "${peripheral} ${clock} clock frequency" + set_parameter_property $parameter group $group_name + set_parameter_property $parameter system_info_type "CLOCK_RATE" + set_parameter_property $parameter system_info_arg $clock + set_parameter_property $parameter visible false + } + + set clocks [get_peripheral_fpga_output_clocks $peripheral] + foreach clock $clocks { + set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock] + if { [string match "*emac?_md*" $clock]} { + add_parameter $parameter float 2.5 "" + } elseif { [string match "*emac?_gtx_clk*" $clock] } { + add_parameter $parameter integer 125 "" + } else { + add_parameter $parameter integer 100 "" + if { [string compare $peripheral "SDIO" ] == 0 } { + set_parameter_property $parameter visible false + } + } + set_parameter_property $parameter display_name "${peripheral} ${clock} clock frequency" + set_parameter_property $parameter group $group_name + set_parameter_property $parameter units Megahertz + set_parameter_property $parameter allowedRanges {1:1000} + } + + } +} +add_clock_parameters + +add_parameter hps_device_family string "" "" +set_parameter_property hps_device_family derived true +set_parameter_property hps_device_family visible false + +add_parameter device_name string "" "" +set_parameter_property device_name system_info {DEVICE} +set_parameter_property device_name visible false + +add_parameter quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_arg hps_ip_enable_all_peripheral_fpga_interfaces +set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces visible false + +add_parameter quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_arg hps_ip_enable_emac0_peripheral_fpga_interface +set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface visible false + +add_parameter quartus_ini_hps_ip_enable_test_interface boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_arg hps_ip_enable_test_interface +set_parameter_property quartus_ini_hps_ip_enable_test_interface visible false + +add_parameter quartus_ini_hps_ip_fast_f2sdram_sim_model boolean "" "" +set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_arg hps_ip_fast_f2sdram_sim_model +set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model visible false + +add_parameter quartus_ini_hps_ip_suppress_sdram_synth boolean "" "" +set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_arg hps_ip_suppress_sdram_synth +set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth visible false + +add_parameter quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_arg hps_ip_enable_low_speed_serial_fpga_interfaces +set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces visible false + +add_parameter quartus_ini_hps_ip_enable_bsel_csel boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_arg hps_ip_enable_bsel_csel +set_parameter_property quartus_ini_hps_ip_enable_bsel_csel visible false + +add_parameter quartus_ini_hps_ip_f2sdram_bonding_out boolean "" "" +set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_arg hps_ip_enable_f2sdram_bonding_out +set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out visible false + + +add_parameter quartus_ini_hps_emif_pll boolean "" "" +set_parameter_property quartus_ini_hps_emif_pll system_info_type quartus_ini +set_parameter_property quartus_ini_hps_emif_pll system_info_arg hps_emif_pll +set_parameter_property quartus_ini_hps_emif_pll visible false + + +proc load_test_iface_definition {} { + set csv_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/test_iface.csv + + set data [list] + set count 0 + csv_foreach_row $csv_file cols { + incr count + if {$count == 1} { + continue + } + + lassign_trimmed $cols port width dir + lappend data $port $width $dir + } + return $data +} +add_storage_parameter test_iface_definition [load_test_iface_definition] + +# order of interfaces per peripheral should be kept +# order of ports per interface should be kept +proc load_periph_ifaces_db {} { + set interfaces_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_interfaces.csv + set peripherals_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_atoms.csv + set ports_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_interface_ports.csv + set pins_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_port_pins.csv + set bfm_types_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_bfm_types.csv + + # peripherals and interfaces + set peripherals([ORDERED_NAMES]) [list] + funset interface_ports + set count 0 + set PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START 4 + csv_foreach_row $interfaces_file cols { + incr count + # skip header + if {$count == 1} { + set ordered_names [list] + set length [llength $cols] + for {set col $PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START} {$col < $length} {incr col} { + set col_value [lindex $cols $col] + if {$col_value != ""} { + set property_to_col($col_value) $col + lappend ordered_names $col_value + } + } + set property_to_col([ORDERED_NAMES]) $ordered_names + continue + } + + set peripheral_name [string trim [lindex $cols 0]] + set interface_name [string trim [lindex $cols 1]] + set type [string trim [lindex $cols 2]] + set dir [string trim [lindex $cols 3]] + + funset peripheral + if {[info exists peripherals($peripheral_name)]} { + array set peripheral $peripherals($peripheral_name) + } else { + funset interfaces + set interfaces([ORDERED_NAMES]) [list] + set peripheral(interfaces) [array get interfaces] + set ordered_names $peripherals([ORDERED_NAMES]) + lappend ordered_names $peripheral_name + set peripherals([ORDERED_NAMES]) $ordered_names + } + funset interfaces + array set interfaces $peripheral(interfaces) + set ordered_names $interfaces([ORDERED_NAMES]) + lappend ordered_names $interface_name + set interfaces([ORDERED_NAMES]) $ordered_names + funset interface + set interface(type) $type + set interface(direction) $dir + funset properties + foreach property $property_to_col([ORDERED_NAMES]) { + set col $property_to_col($property) + set property_value [lindex $cols $col] + + if {$property_value != ""} { + # Add Meta Property + if { [string compare [string index ${property} 0] "@" ] == 0 } { + set interface(${property}) ${property_value} + } else { + set properties($property) $property_value + } + } + } + + set interface(properties) [array get properties] + + set interfaces($interface_name) [array get interface] + set peripheral(interfaces) [array get interfaces] + set peripherals($peripheral_name) [array get peripheral] + + funset ports + set ports([ORDERED_NAMES]) [list] + set interface_ports($interface_name) [array get ports] + } + set count 0 + csv_foreach_row $peripherals_file cols { ;# peripheral atom and location table + incr count + + # skip header + if {$count == 1} { + continue + } + + set peripheral_name [string trim [lindex $cols 0]] + set atom_name [string trim [lindex $cols 1]] + + funset peripheral + if {[info exists peripherals($peripheral_name)]} { + array set peripheral $peripherals($peripheral_name) + } else { + # Assume that if a peripheral hasn't be recognized until now, we won't be using it + continue + } + set peripheral(atom_name) $atom_name + set peripherals($peripheral_name) [array get peripheral] + } + add_parameter DB_periph_ifaces string [array get peripherals] "" + set_parameter_property DB_periph_ifaces derived true + set_parameter_property DB_periph_ifaces visible false + + set p [array get peripherals] + send_message debug "DB_periph_ifaces: ${p}" + + # ports + array set ports_to_pins {} + # # prepopulate interface_ports with names of interfaces that are known + # foreach {peripheral_name peripheral_string} [array get peripherals] { + # array set peripheral_array $peripheral_string + # foreach interface_name [array names peripheral_array] { + # set interface_ports($interface_name) {} + # } + # } + set count 0 + csv_foreach_row $ports_file cols { + incr count + + # skip header + if {$count == 1} continue + + set interface_name [string trim [lindex $cols 0]] + set port_name [string trim [lindex $cols 1]] + set role [string trim [lindex $cols 2]] + set dir [string trim [lindex $cols 3]] + set atom_signal_name [string trim [lindex $cols 4]] + + funset interface + array set interface $interface_ports($interface_name) + set ordered_names $interface([ORDERED_NAMES]) + lappend ordered_names $port_name + set interface([ORDERED_NAMES]) $ordered_names + + funset port + set port(role) $role + set port(direction) $dir + set port(atom_signal_name) $atom_signal_name + set interface($port_name) [array get port] + set interface_ports($interface_name) [array get interface] + + set ports_to_pins($port_name) {} + } + add_parameter DB_iface_ports string [array get interface_ports] "" + set_parameter_property DB_iface_ports derived true + set_parameter_property DB_iface_ports visible false + + set p [array get interface_ports] + send_message debug "DB_iface_ports: ${p}" + + # peripheral signals to ports + set count 0 + csv_foreach_row $pins_file cols { + incr count + + # skip header + if {$count == 1} continue + + set peripheral_name [string trim [lindex $cols 0]] + set pin_name [string trim [lindex $cols 1]] + set port_name [string trim [lindex $cols 2]] + + set is_multibit_signal [regexp {^([a-zA-Z0-9_]+)\[([0-9]+)\]} $port_name match real_name bit] + if {$is_multibit_signal == 0} { + set bit 0 + } else { + set port_name $real_name + } + + if {[info exists ports_to_pins($port_name)] == 0} { + send_message error "Peripheral ${peripheral_name} signal ${pin_name} is defined but corresponding FPGA signal ${port_name}\[${bit}\] is not" + } else { + funset port + array set port $ports_to_pins($port_name) + + if {[info exists port($bit)]} { + # collision! + send_message error "Signal ${port_name}\[${bit}\] is having original assignment ${peripheral_name}.${port($bit)} replaced with ${peripheral_name}.${pin_name}" + } + set port($bit) $pin_name + set ports_to_pins($port_name) [array get port] + } + } + add_parameter DB_port_pins string [array get ports_to_pins] "" + set_parameter_property DB_port_pins derived true + set_parameter_property DB_port_pins visible false + + set p [array get ports_to_pins] + send_message debug "DB_port_pins: ${p}" + + # bfm types + set count 0 + funset bfm_types + csv_foreach_row $bfm_types_file cols { + incr count + + # skip header + if {$count == 1} continue + + set bfm_type_name [string trim [lindex $cols 0]] + set property_name [string trim [lindex $cols 1]] + set value [string trim [lindex $cols 2]] + + if {[info exists bfm_types($bfm_type_name)] == 0} { + set bfm_types($bfm_type_name) {} + } + funset bfm_type + array set bfm_type $bfm_types($bfm_type_name) + set bfm_type($property_name) $value + set bfm_types($bfm_type_name) [array get bfm_type] + } + add_parameter DB_bfm_types string [array get bfm_types] "" + set_parameter_property DB_bfm_types derived true + set_parameter_property DB_bfm_types visible false + # TODO: what to do so that mode information on a peripheral.pin basis can be used for elaboration??? +} + +# only run during class creation +load_periph_ifaces_db + +####################### +##### Composition ##### +####################### + +namespace eval ::fpga_interfaces { + source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl +} + +namespace eval ::hps_io { + namespace eval internal { + source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl + } + variable pins + + proc add_peripheral {peripheral_name atom_name location} { + internal::add_module_instance $peripheral_name $atom_name $location + } + + # oe used in tristate output and inout + # out used in output and inout + # in used in input and inout + proc add_pin {peripheral_name pin_name dir location in_port out_port oe_port} { + variable pins + lappend pins [list $peripheral_name $pin_name $dir $location $in_port $out_port $oe_port] + } + + proc process_pins {} { + variable pins + + set interface_name "hps_io" + set hps_io_interface_created 0 + funset ports_used ;# set of inst/ports used + funset port_wire ;# map of ports to aliased wires + foreach pin $pins { ;# Check for multiple uses of the same port and create wires for those cases + lassign $pin peripheral_name pin_name dir location in_port out_port oe_port + + # check to see if port is used multiple times + foreach port_part [list $in_port $out_port $oe_port] { + if {$port_part != "" && [info exists ports_used($port_part)]} { + # Assume only outputs will be used multiple times. Inputs would be an error + if {[info exists port_wire($port_part)] == 0} { + set port_wire($port_part) [internal::allocate_wire] + # Drive new wire with port + internal::set_wire_port_fragments $port_wire($port_part) driven_by $port_part + } + } + set ports_used($port_part) 1 + } + } + + set qip [list] + foreach pin $pins { + lassign $pin peripheral_name pin_name dir location in_port out_port oe_port + foreach port_part_ref {in_port out_port oe_port} { ;# Replace ports with wires if needed + set port_part [set $port_part_ref] + if {[info exists port_wire($port_part)]} { + set $port_part_ref [internal::wire_tofragment $port_wire($port_part)] + } + } + + # Hook things up + set instance_name [string tolower $peripheral_name] ;# is this necessary??? + if {$hps_io_interface_created == 0} { + set hps_io_interface_created 1 + internal::add_interface $interface_name conduit input + } + set export_signal_name "hps_io_${instance_name}_${pin_name}" + internal::add_interface_port $interface_name $export_signal_name $export_signal_name $dir 1 + if {[string compare $dir "input"] == 0} { + internal::set_port_fragments $interface_name $export_signal_name $in_port + internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *" + } elseif {[string compare $dir "output"] == 0} { + if {[string compare $oe_port "" ] == 0} { + internal::set_port_fragments $interface_name $export_signal_name $out_port + internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" + } else { + internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port + internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" + } + } else { + internal::set_port_fragments $interface_name $export_signal_name $in_port + internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port + internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *" + internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" + } + set path_to_pin "hps_io|border|${export_signal_name}\[0\]" + set location_assignment "set_instance_assignment -name HPS_LOCATION ${location} -entity %entityName% -to ${path_to_pin}" + lappend qip $location_assignment + } + set_qip_strings $qip + } + + proc init {} { + internal::init + variable pins [list] + } + + proc serialize {var_name} { + upvar 1 $var_name data + process_pins + internal::serialize data + } +} + +set_module_property composition_callback compose + +proc compose {} { + # synchronize device families between the EMIF and HPS parameter sets + set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] + fpga_interfaces::init + fpga_interfaces::set_bfm_types [array get DB_bfm_types] + + hps_io::init + validate + elab 0 + + update_hps_to_fpga_clock_frequency_parameters + + + fpga_interfaces::serialize fpga_interfaces_data + + add_instance fpga_interfaces altera_interface_generator + set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data] + + expose_border fpga_interfaces $fpga_interfaces_data(interfaces) + + declare_cmsis_svd $fpga_interfaces_data(interfaces) + + clear_array temp_array +} + +proc logicalview_dtg {} { + + set hard_peripheral_logical_view_dir $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/hard_peripheral_logical_view + + source "$hard_peripheral_logical_view_dir/common/hps_utils.tcl" + + source "$hard_peripheral_logical_view_dir/hps_periphs/hps_periphs.tcl" + + set f2h_present [ expr [ get_parameter_value F2S_Width ] != 0] + set h2f_present [ expr [ get_parameter_value S2F_Width ] != 0] + set F2S_Width [ get_parameter_value F2S_Width ] + set S2F_Width [ get_parameter_value S2F_Width ] + set h2f_lw_present [ expr [ string compare [ get_parameter_value LWH2F_Enable ] "true" ] == 0 ] + set LWH2F_Enable [ get_parameter_value LWH2F_Enable ] + set device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] + + # Need to add whole bunch of device tree generation parameters here (dtg) + # Getting whether is it single or dual core by checking the device family. List of single core: + # Cyclone V SE + regsub "^.* V" $device_family "" se_family + regsub " " $se_family "" se_family + + set number_of_a9 0 + if { [string toupper $se_family] == "SE"} { + set number_of_a9 1 + } else { + set number_of_a9 2 + } + + set F2SDRAM_Width [get_parameter_value F2SDRAM_Width] + set F2SDRAM_Type [get_parameter_value F2SDRAM_Type] + set quartus_ini_hps_ip_f2sdram_bonding_out [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] + set BONDING_OUT_ENABLED [get_parameter_value BONDING_OUT_ENABLED] + add_instance clk_0 hps_clk_src + hps_utils_add_instance_clk_reset clk_0 bridges hps_bridge_avalon + set_instance_parameter_value bridges F2S_Width $F2S_Width + set_instance_parameter_value bridges S2F_Width $S2F_Width + set_instance_parameter_value bridges BONDING_OUT_ENABLED $BONDING_OUT_ENABLED + set_instance_parameter_value bridges LWH2F_Enable $LWH2F_Enable + set_instance_parameter_value bridges quartus_ini_hps_ip_f2sdram_bonding_out $quartus_ini_hps_ip_f2sdram_bonding_out + add_interface h2f_reset reset output + set_interface_property h2f_reset EXPORT_OF bridges.h2f_reset + set_interface_property h2f_reset PORT_NAME_MAP "h2f_rst_n h2f_rst_n" + + set rows [llength $F2SDRAM_Width] + set type_list $F2SDRAM_Type + set append_type_list "" + set append_type_width "" + set total_command_port 0 + set total_write_port 0 + set total_read_port 0 + if {$rows > 0} { + for {set i 0} {${i} < $rows} {incr i} { + set type_choice [lindex $type_list $i] + set type_width [lindex $F2SDRAM_Width $i] + if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { + set type_id 1 + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { + set type_id 2 + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + } + } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { + set type_id 3 + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_read_port [expr $total_read_port + 4] + } else { + set total_read_port [expr $total_read_port + 1] + } + } else { + set type_id 0 + if { [ expr $total_command_port % 2 ] } { + incr total_command_port 1 + } + set total_command_port [expr $total_command_port + 2] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + } + + if {$total_command_port > 6} { + if {$type_id == 0} { + send_message error "No command ports available to allocate AXI Interface f2h_sdram${i}" + } else { + send_message error "No command ports available to allocate Avalon-MM Interface f2h_sdram${i}" + } + } + if {$total_read_port > 4} { + if {$type_id == 0} { + send_message error "No read ports available to allocate AXI Interface f2h_sdram${i}" + } else { + send_message error "No read ports available to allocate Avalon-MM Interface f2h_sdram${i}" + } + } + if {$total_write_port > 4} { + if {$type_id == 0} { + send_message error "No write ports available to allocate AXI Interface f2h_sdram${i}" + } else { + send_message error "No write ports available to allocate Avalon-MM Interface f2h_sdram${i}" + } + } + if {$total_command_port < 7 && $total_write_port < 5 && $total_read_port < 5} { + lappend append_type_list $type_id + lappend append_type_width $type_width + } + } + } + set_instance_parameter_value bridges F2SDRAM_Type $append_type_list + set_instance_parameter_value bridges F2SDRAM_Width $append_type_width + set total_command_port 0 + set total_write_port 0 + set total_read_port 0 + set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] + + if {$rows > 0} { + for {set i 0} {${i} < $rows} {incr i} { + + set type_choice [lindex $type_list $i] + set type_width [lindex $F2SDRAM_Width $i] + + if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { + set type "avalon" + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE" + } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { + set type "avalon" + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + } + set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE" + } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { + set type "avalon" + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_read_port [expr $total_read_port + 4] + } else { + set total_read_port [expr $total_read_port + 1] + } + set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ" + } else { + set type "axi" + if { [ expr $total_command_port % 2 ] } { + incr total_command_port 1 + } + set total_command_port [expr $total_command_port + 2] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + set sdram_data "f2h_sdram${i}_ARADDR f2h_sdram${i}_ARADDR f2h_sdram${i}_ARLEN f2h_sdram${i}_ARLEN f2h_sdram${i}_ARID f2h_sdram${i}_ARID f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARBURST f2h_sdram${i}_ARBURST f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARPROT f2h_sdram${i}_ARPROT f2h_sdram${i}_ARVALID f2h_sdram${i}_ARVALID f2h_sdram${i}_ARCACHE f2h_sdram${i}_ARCACHE f2h_sdram${i}_AWADDR f2h_sdram${i}_AWADDR f2h_sdram${i}_AWLEN f2h_sdram${i}_AWLEN f2h_sdram${i}_AWID f2h_sdram${i}_AWID f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWBURST f2h_sdram${i}_AWBURST f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWPROT f2h_sdram${i}_AWPROT f2h_sdram${i}_AWVALID f2h_sdram${i}_AWVALID f2h_sdram${i}_AWCACHE f2h_sdram${i}_AWCACHE f2h_sdram${i}_BRESP f2h_sdram${i}_BRESP f2h_sdram${i}_BID f2h_sdram${i}_BID f2h_sdram${i}_BVALID f2h_sdram${i}_BVALID f2h_sdram${i}_BREADY f2h_sdram${i}_BREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RDATA f2h_sdram${i}_RDATA f2h_sdram${i}_RRESP f2h_sdram${i}_RRESP f2h_sdram${i}_RLAST f2h_sdram${i}_RLAST f2h_sdram${i}_RID f2h_sdram${i}_RID f2h_sdram${i}_RVALID f2h_sdram${i}_RVALID f2h_sdram${i}_WLAST f2h_sdram${i}_WLAST f2h_sdram${i}_WVALID f2h_sdram${i}_WVALID f2h_sdram${i}_WDATA f2h_sdram${i}_WDATA f2h_sdram${i}_WSTRB f2h_sdram${i}_WSTRB f2h_sdram${i}_WREADY f2h_sdram${i}_WREADY f2h_sdram${i}_WID f2h_sdram${i}_WID" + } + + if {$total_command_port > 6 || $total_write_port > 4 || $total_read_port > 4} { + break + } + add_interface f2h_sdram${i}_clock clock Input + set_interface_property f2h_sdram${i}_clock EXPORT_OF bridges.f2h_sdram${i}_clock + set_interface_property f2h_sdram${i}_clock PORT_NAME_MAP "f2h_sdram${i}_clk f2h_sdram${i}_clk" + add_interface f2h_sdram${i}_data $type slave + set_interface_property f2h_sdram${i}_data EXPORT_OF bridges.f2h_sdram${i}_data + set_interface_property f2h_sdram${i}_data PORT_NAME_MAP "$sdram_data" + } + + if $bonding_out_signal { + set bon_out_signal "f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_2 f2h_sdram_BONOUT_2" + add_interface f2h_sdram_bon_out conduit Output + set_interface_property f2h_sdram_bon_out EXPORT_OF bridges.f2h_sdram_bon_out + set_interface_property f2h_sdram_bon_out PORT_NAME_MAP "$bon_out_signal" + } + + } + + set declared_svd_file 0 + set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd] + if { $h2f_present } { + hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f {0xc0000000} + if { $number_of_a9 > 1 } { + hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f {0xc0000000} + } + + add_interface h2f_axi_clock clock Input + set_interface_property h2f_axi_clock EXPORT_OF bridges.h2f_axi_clock + set_interface_property h2f_axi_clock PORT_NAME_MAP "h2f_axi_clk h2f_axi_clk" + + add_interface h2f_axi_master axi master + set_interface_property h2f_axi_master EXPORT_OF bridges.h2f + set_interface_property h2f_axi_master PORT_NAME_MAP "h2f_AWID h2f_AWID h2f_AWADDR h2f_AWADDR h2f_AWLEN h2f_AWLEN h2f_AWSIZE h2f_AWSIZE h2f_AWBURST h2f_AWBURST h2f_AWLOCK h2f_AWLOCK h2f_AWCACHE h2f_AWCACHE h2f_AWPROT h2f_AWPROT h2f_AWVALID h2f_AWVALID h2f_AWREADY h2f_AWREADY h2f_WID h2f_WID h2f_WDATA h2f_WDATA h2f_WSTRB h2f_WSTRB h2f_WLAST h2f_WLAST h2f_WVALID h2f_WVALID h2f_WREADY h2f_WREADY h2f_BID h2f_BID h2f_BRESP h2f_BRESP h2f_BVALID h2f_BVALID h2f_BREADY h2f_BREADY h2f_ARID h2f_ARID h2f_ARADDR h2f_ARADDR h2f_ARLEN h2f_ARLEN h2f_ARSIZE h2f_ARSIZE h2f_ARBURST h2f_ARBURST h2f_ARLOCK h2f_ARLOCK h2f_ARCACHE h2f_ARCACHE h2f_ARPROT h2f_ARPROT h2f_ARVALID h2f_ARVALID h2f_ARREADY h2f_ARREADY h2f_RID h2f_RID h2f_RDATA h2f_RDATA h2f_RRESP h2f_RRESP h2f_RLAST h2f_RLAST h2f_RVALID h2f_RVALID h2f_RREADY h2f_RREADY" + set_interface_property h2f_axi_master SVD_ADDRESS_GROUP "hps" + set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000 + if {!$declared_svd_file} { + set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + } + + if { $f2h_present } { + add_interface f2h_axi_clock clock Input + set_interface_property f2h_axi_clock EXPORT_OF bridges.f2h_axi_clock + set_interface_property f2h_axi_clock PORT_NAME_MAP "f2h_axi_clk f2h_axi_clk" + + add_interface f2h_axi_slave axi slave + set_interface_property f2h_axi_slave EXPORT_OF bridges.f2h + set_interface_property f2h_axi_slave PORT_NAME_MAP "f2h_AWID f2h_AWID f2h_AWADDR f2h_AWADDR f2h_AWLEN f2h_AWLEN f2h_AWSIZE f2h_AWSIZE f2h_AWBURST f2h_AWBURST f2h_AWLOCK f2h_AWLOCK f2h_AWCACHE f2h_AWCACHE f2h_AWPROT f2h_AWPROT f2h_AWVALID f2h_AWVALID f2h_AWREADY f2h_AWREADY f2h_AWUSER f2h_AWUSER f2h_WID f2h_WID f2h_WDATA f2h_WDATA f2h_WSTRB f2h_WSTRB f2h_WLAST f2h_WLAST f2h_WVALID f2h_WVALID f2h_WREADY f2h_WREADY f2h_BID f2h_BID f2h_BRESP f2h_BRESP f2h_BVALID f2h_BVALID f2h_BREADY f2h_BREADY f2h_ARID f2h_ARID f2h_ARADDR f2h_ARADDR f2h_ARLEN f2h_ARLEN f2h_ARSIZE f2h_ARSIZE f2h_ARBURST f2h_ARBURST f2h_ARLOCK f2h_ARLOCK f2h_ARCACHE f2h_ARCACHE f2h_ARPROT f2h_ARPROT f2h_ARVALID f2h_ARVALID f2h_ARREADY f2h_ARREADY f2h_ARUSER f2h_ARUSER f2h_RID f2h_RID f2h_RDATA f2h_RDATA f2h_RRESP f2h_RRESP f2h_RLAST f2h_RLAST f2h_RVALID f2h_RVALID f2h_RREADY f2h_RREADY" + } + + if { $h2f_lw_present } { + hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f_lw {0xff200000} + if { $number_of_a9 > 1 } { + hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f_lw {0xff200000} + } + + add_interface h2f_lw_axi_clock clock Input + set_interface_property h2f_lw_axi_clock EXPORT_OF bridges.h2f_lw_axi_clock + set_interface_property h2f_lw_axi_clock PORT_NAME_MAP "h2f_lw_axi_clk h2f_lw_axi_clk" + + add_interface h2f_lw_axi_master axi start + set_interface_property h2f_lw_axi_master EXPORT_OF bridges.h2f_lw + set_interface_property h2f_lw_axi_master PORT_NAME_MAP "h2f_lw_AWID h2f_lw_AWID h2f_lw_AWADDR h2f_lw_AWADDR h2f_lw_AWLEN h2f_lw_AWLEN h2f_lw_AWSIZE h2f_lw_AWSIZE h2f_lw_AWBURST h2f_lw_AWBURST h2f_lw_AWLOCK h2f_lw_AWLOCK h2f_lw_AWCACHE h2f_lw_AWCACHE h2f_lw_AWPROT h2f_lw_AWPROT h2f_lw_AWVALID h2f_lw_AWVALID h2f_lw_AWREADY h2f_lw_AWREADY h2f_lw_WID h2f_lw_WID h2f_lw_WDATA h2f_lw_WDATA h2f_lw_WSTRB h2f_lw_WSTRB h2f_lw_WLAST h2f_lw_WLAST h2f_lw_WVALID h2f_lw_WVALID h2f_lw_WREADY h2f_lw_WREADY h2f_lw_BID h2f_lw_BID h2f_lw_BRESP h2f_lw_BRESP h2f_lw_BVALID h2f_lw_BVALID h2f_lw_BREADY h2f_lw_BREADY h2f_lw_ARID h2f_lw_ARID h2f_lw_ARADDR h2f_lw_ARADDR h2f_lw_ARLEN h2f_lw_ARLEN h2f_lw_ARSIZE h2f_lw_ARSIZE h2f_lw_ARBURST h2f_lw_ARBURST h2f_lw_ARLOCK h2f_lw_ARLOCK h2f_lw_ARCACHE h2f_lw_ARCACHE h2f_lw_ARPROT h2f_lw_ARPROT h2f_lw_ARVALID h2f_lw_ARVALID h2f_lw_ARREADY h2f_lw_ARREADY h2f_lw_RID h2f_lw_RID h2f_lw_RDATA h2f_lw_RDATA h2f_lw_RRESP h2f_lw_RRESP h2f_lw_RLAST h2f_lw_RLAST h2f_lw_RVALID h2f_lw_RVALID h2f_lw_RREADY h2f_lw_RREADY" + set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP "hps" + set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000 + if {!$declared_svd_file} { + set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + } + + if {!$declared_svd_file} { + set_module_assignment "cmsis.svd.file" $svd_path + set_module_assignment "cmsis.svd.suffix" "hps" + } + + clocks_logicalview_dtg + + if { $number_of_a9 > 0 } { + hps_utils_add_instance_clk_reset clk_0 arm_a9_0 arm_a9 + } + + if { $number_of_a9 > 1 } { + hps_utils_add_instance_clk_reset clk_0 arm_a9_1 arm_a9 + } + + + hps_instantiate_arm_gic_0 $number_of_a9 + + hps_instantiate_L2 $number_of_a9 + + hps_instantiate_dma $number_of_a9 + + hps_instantiate_sysmgr $number_of_a9 + + hps_instantiate_clkmgr $number_of_a9 + + hps_instantiate_rstmgr $number_of_a9 + + hps_instantiate_fpgamgr $number_of_a9 + + hps_instantiate_uart0 $number_of_a9 "UART0_PinMuxing" [get_parameter_value l4_sp_clk_mhz] + + hps_instantiate_uart1 $number_of_a9 "UART1_PinMuxing" [get_parameter_value l4_sp_clk_mhz] + + hps_instantiate_timer0 $number_of_a9 + + hps_instantiate_timer1 $number_of_a9 + + hps_instantiate_timer2 $number_of_a9 + + hps_instantiate_timer3 $number_of_a9 + + hps_instantiate_wd_timer0 $number_of_a9 + + hps_instantiate_wd_timer1 $number_of_a9 + + hps_instantiate_gpio0 $number_of_a9 + + hps_instantiate_gpio1 $number_of_a9 + + hps_instantiate_gpio2 $number_of_a9 + + hps_instantiate_i2c0 $number_of_a9 "I2C0_PinMuxing" + + hps_instantiate_i2c1 $number_of_a9 "I2C1_PinMuxing" + + hps_instantiate_i2c2 $number_of_a9 "I2C2_PinMuxing" + + hps_instantiate_i2c3 $number_of_a9 "I2C3_PinMuxing" + + hps_instantiate_nand0 $number_of_a9 "NAND_PinMuxing" + + hps_instantiate_spim0 $number_of_a9 "SPIM0_PinMuxing" + + hps_instantiate_spim1 $number_of_a9 "SPIM1_PinMuxing" + + hps_instantiate_qspi $number_of_a9 "QSPI_PinMuxing" + + hps_instantiate_sdmmc $number_of_a9 "SDIO_PinMuxing" + + hps_instantiate_usb0 $number_of_a9 "USB0_PinMuxing" + + hps_instantiate_usb1 $number_of_a9 "USB1_PinMuxing" + + hps_instantiate_gmac0 $number_of_a9 "EMAC0_PinMuxing" + + hps_instantiate_gmac1 $number_of_a9 "EMAC1_PinMuxing" + + hps_instantiate_dcan0 $number_of_a9 "CAN0_PinMuxing" + + hps_instantiate_dcan1 $number_of_a9 "CAN1_PinMuxing" + + hps_instantiate_l3regs $number_of_a9 + + hps_instantiate_sdrctl $number_of_a9 + + hps_instantiate_axi_ocram $number_of_a9 + + hps_instantiate_axi_sdram $number_of_a9 + + hps_instantiate_timer $number_of_a9 + + hps_instantiate_scu $number_of_a9 + + add_connection arm_gic_0.arm_gic_ppi timer.interrupt_sender + set_connection_parameter_value arm_gic_0.arm_gic_ppi/timer.interrupt_sender irqNumber 13 + + if { $f2h_present } { + hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave0 {0xfffed000} + hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave1 {0xfffec100} + hps_utils_add_slave_interface bridges.axi_f2h L2.axi_slave0 {0xfffef000} + hps_utils_add_slave_interface bridges.axi_f2h dma.axi_slave0 {0xffe01000} + hps_utils_add_slave_interface bridges.axi_f2h sysmgr.axi_slave0 {0xffd08000} + hps_utils_add_slave_interface bridges.axi_f2h clkmgr.axi_slave0 {0xffd04000} + hps_utils_add_slave_interface bridges.axi_f2h rstmgr.axi_slave0 {0xffd05000} + hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave0 {0xff706000} + hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave1 {0xffb90000} + hps_utils_add_slave_interface bridges.axi_f2h uart0.axi_slave0 {0xffc02000} + hps_utils_add_slave_interface bridges.axi_f2h uart1.axi_slave0 {0xffc03000} + hps_utils_add_slave_interface bridges.axi_f2h timer0.axi_slave0 {0xffc08000} + hps_utils_add_slave_interface bridges.axi_f2h timer1.axi_slave0 {0xffc09000} + hps_utils_add_slave_interface bridges.axi_f2h timer2.axi_slave0 [hps_timer2_base] + hps_utils_add_slave_interface bridges.axi_f2h timer3.axi_slave0 [hps_timer3_base] + hps_utils_add_slave_interface bridges.axi_f2h gpio0.axi_slave0 {0xff708000} + hps_utils_add_slave_interface bridges.axi_f2h gpio1.axi_slave0 {0xff709000} + hps_utils_add_slave_interface bridges.axi_f2h gpio2.axi_slave0 {0xff70a000} + hps_utils_add_slave_interface bridges.axi_f2h i2c0.axi_slave0 {0xffc04000} + hps_utils_add_slave_interface bridges.axi_f2h i2c1.axi_slave0 {0xffc05000} + hps_utils_add_slave_interface bridges.axi_f2h i2c2.axi_slave0 {0xffc06000} + hps_utils_add_slave_interface bridges.axi_f2h i2c3.axi_slave0 {0xffc07000} + hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave0 {0xff900000} + hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave1 {0xffb80000} + hps_utils_add_slave_interface bridges.axi_f2h spim0.axi_slave0 [hps_spim0_base] + hps_utils_add_slave_interface bridges.axi_f2h spim1.axi_slave0 [hps_spim1_base] + hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave0 {0xff705000} + hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave1 {0xffa00000} + hps_utils_add_slave_interface bridges.axi_f2h sdmmc.axi_slave0 {0xff704000} + hps_utils_add_slave_interface bridges.axi_f2h usb0.axi_slave0 {0xffb00000} + hps_utils_add_slave_interface bridges.axi_f2h usb1.axi_slave0 {0xffb40000} + hps_utils_add_slave_interface bridges.axi_f2h gmac0.axi_slave0 {0xff700000} + hps_utils_add_slave_interface bridges.axi_f2h gmac1.axi_slave0 {0xff702000} + hps_utils_add_slave_interface bridges.axi_f2h axi_ocram.axi_slave0 {0xffff0000} + hps_utils_add_slave_interface bridges.axi_f2h axi_sdram.axi_slave0 [hps_sdram_base] + hps_utils_add_slave_interface bridges.axi_f2h timer.axi_slave0 {0xfffec600} + hps_utils_add_slave_interface bridges.axi_f2h dcan0.axi_slave0 [hps_dcan0_base] + hps_utils_add_slave_interface bridges.axi_f2h dcan1.axi_slave0 [hps_dcan1_base] + hps_utils_add_slave_interface bridges.axi_f2h l3regs.axi_slave0 [hps_l3regs_base] + hps_utils_add_slave_interface bridges.axi_f2h sdrctl.axi_slave0 [hps_sdrctl_base] + } + + ##### F2H ##### + if [is_enabled F2SINTERRUPT_Enable] { + set any_interrupt_enabled 1 + set iname "f2h_irq" + set pname "f2h_irq" + add_interface "${iname}0" interrupt receiver + set_interface_property f2h_irq0 EXPORT_OF arm_gic_0.f2h_irq_0_irq_rx_offset_40 + set_interface_property f2h_irq0 PORT_NAME_MAP "f2h_irq_p0 irq_siq_40" + + add_interface "${iname}1" interrupt receiver + set_interface_property f2h_irq1 EXPORT_OF arm_gic_0.f2h_irq_32_irq_rx_offset_72 + set_interface_property f2h_irq1 PORT_NAME_MAP "f2h_irq_p1 irq_siq_72" + } +} + +set_module_property OPAQUE_ADDRESS_MAP false +set_module_property STRUCTURAL_COMPOSITION_CALLBACK compose_logicalview +proc compose_logicalview {} { + # synchronize device families between the EMIF and HPS parameter sets + set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] + fpga_interfaces::init + fpga_interfaces::set_bfm_types [array get DB_bfm_types] + + hps_io::init + validate + elab 1 + + update_hps_to_fpga_clock_frequency_parameters + + + fpga_interfaces::serialize fpga_interfaces_data + + add_instance fpga_interfaces altera_interface_generator + set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data] + + expose_border fpga_interfaces $fpga_interfaces_data(interfaces) + + #declare_cmsis_svd $fpga_interfaces_data(interfaces) + + logicalview_dtg +} + +proc declare_cmsis_svd {interfaces_str} { + array set interfaces $interfaces_str + set interface_names $interfaces([ORDERED_NAMES]) + + set h2f_exists 0 + set lwh2f_exists 0 + foreach interface_name $interface_names { + if {[string compare $interface_name "h2f_axi_master"] == 0} { + set h2f_exists 1 + } elseif {[string compare $interface_name "h2f_lw_axi_master"] == 0} { + set lwh2f_exists 1 + } + } + + set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd] + set address_group hps + set declared_svd_file 0 + + if {$h2f_exists} { + if {!$declared_svd_file} { + set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + set_interface_property h2f_axi_master SVD_ADDRESS_GROUP $address_group + set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000 + } + if {$lwh2f_exists} { + if {!$declared_svd_file} { + set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP $address_group + set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000 + } + if {!$declared_svd_file} { + set_module_assignment "cmsis.svd.file" $svd_path + set_module_assignment "cmsis.svd.suffix" $address_group + } +} + + +###################### +##### Validation ##### +###################### + +proc validate {} { + set device_family [get_parameter_value hps_device_family] + set device [get_device] + ensure_pin_muxing_data $device_family + update_table_derived_parameters + + validate_F2SDRAM + update_S2F_CLK_mux_options + update_pin_muxing_ui $device_family + + # funset placement_by_pin + validate_pin_muxing $device_family placement_by_pin + update_gpio_ui placement_by_pin + + validate_TEST + + validate_interrupt $device_family + + validate_clocks + +} + +proc validate_TEST {} { + set ini [get_parameter_value quartus_ini_hps_ip_enable_test_interface] + set_parameter_property TEST_Enable visible $ini +} + +proc hide_param { paramName hide} { + +} +proc update_hps_to_fpga_clock_frequency_parameters {} { + set u0 [get_parameter_value S2FCLK_USER0CLK_Enable] + set u1 [get_parameter_value S2FCLK_USER1CLK_Enable] + #set u2 [get_parameter_value S2FCLK_USER2CLK_Enable] + + for { set i 0 } { $i < 2 } { incr i } { + set_parameter_property "S2FCLK_USER${i}CLK_FREQ" enabled [expr "\$u${i}"] + + if { [string compare true [expr "\$u${i}"] ] == 0 } { + fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRateKnown true + fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRate [expr [get_parameter_value "S2FCLK_USER${i}CLK_FREQ"] * 1000000 ] + } + } +} + +proc update_table_derived_parameters {} { + update_f2sdram_names + update_dma_peripheral_ids +} + +proc update_f2sdram_names {} { + set num_rows [llength [get_parameter_value F2SDRAM_Width]] + set names [list] + + for {set index 0} {$index < $num_rows} {incr index} { + set name "f2h_sdram${index}" + lappend names $name + } + set_parameter_value F2SDRAM_Name_DERIVED ${names} +} + +proc update_dma_peripheral_ids {} { + set periph_id_list {0 1 2 3 4 5 6 7} + set_parameter_value DMA_PeriphId_DERIVED $periph_id_list +} + +proc is_enabled {parameter} { + if { [string compare [get_parameter_value $parameter] "true" ] == 0 } { + return 1 + } else { + return 0 + } +} + +proc validate_F2SDRAM {} { + set type_list [get_parameter_value F2SDRAM_Type] + set width_list [get_parameter_value F2SDRAM_Width] + set rows [llength $width_list] + + set command_ports_bit 0 + set read_ports_bit 0 + set write_ports_bit 0 + + set command_ports_mask 0 + set read_ports_mask 0 + set write_ports_mask 0 + set reset_ports_mask 0 + + for {set index 0} {${index} < ${rows}} {incr index} { + # check for invalid combinations of type/width + set mytype [lindex $type_list $index] + set mywidth [lindex $width_list $index] + + if {$mywidth < 64} { + send_message warning "Setting the slave port width of interface f2h_sdram${index} to ${mywidth} results in bandwidth under-utilization. Altera recommends you set the interface data width to 64-bit or greater." + } + + # count used ports + # command + if { [string compare $mytype [F2HSDRAM_AXI3]] == 0 } { + if { [ expr $command_ports_bit % 2 ] } { + incr command_ports_bit 1 + } + set command_ports_mask [ expr $command_ports_mask | ( 3 << $command_ports_bit) ] + incr command_ports_bit 2 + } else { + set command_ports_mask [ expr $command_ports_mask | ( 1 << $command_ports_bit) ] + incr command_ports_bit 1 + } + + # read + if {$mytype != [F2HSDRAM_AVM_WRITEONLY]} { + if {$mywidth <= 64} { + set read_ports_mask [ expr $read_ports_mask | ( 1 << $read_ports_bit) ] + incr read_ports_bit 1 + } elseif {$mywidth == 128} { + set read_ports_mask [ expr $read_ports_mask | ( 3 << $read_ports_bit) ] + incr read_ports_bit 2 + } else { + set read_ports_mask [ expr $read_ports_mask | ( 15 << $read_ports_bit) ] + incr read_ports_bit 4 + } + } + + # write + if {$mytype != [F2HSDRAM_AVM_READONLY]} { + if {$mywidth <= 64} { + set write_ports_mask [ expr $write_ports_mask | ( 1 << $write_ports_bit) ] + incr write_ports_bit 1 + } elseif {$mywidth == 128} { + set write_ports_mask [ expr $write_ports_mask | ( 3 << $write_ports_bit) ] + incr write_ports_bit 2 + } else { + set write_ports_mask [ expr $write_ports_mask | ( 15 << $write_ports_bit) ] + incr write_ports_bit 4 + } + } + + # reset + set reset_ports_mask [ expr ($command_ports_mask << 8) | ($write_ports_mask << 4) | ($read_ports_mask) ] + + } + # check for port over-use + if {$command_ports_bit > 6} { + send_message error "The current FPGA to SDRAM configuration is using more command ports than are available." + } + if {$read_ports_bit > 4} { + send_message error "The current FPGA to SDRAM configuration is using more read ports than are available." + } + if {$write_ports_bit > 4} { + send_message error "The current FPGA to SDRAM configuration is using more write ports than are available." + } + + # Store ports used & number of elements to determine when new rows are added + set_parameter_value F2SDRAM_Width_Last_Size $rows + set_parameter_value F2SDRAM_CMD_PORT_USED [ format "0x%X" $command_ports_mask ] + set_parameter_value F2SDRAM_RD_PORT_USED [ format "0x%X" $read_ports_mask ] + set_parameter_value F2SDRAM_WR_PORT_USED [ format "0x%X" $write_ports_mask ] + set_parameter_value F2SDRAM_RST_PORT_USED [ format "0x%X" $reset_ports_mask ] + + # Bonding_out signals will be exported if f2sdram selected + if { ${rows} > 0 } { + set param [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] + set_parameter_property BONDING_OUT_ENABLED visible $param + set_parameter_property BONDING_OUT_ENABLED enabled $param + } else { + set_parameter_property BONDING_OUT_ENABLED enabled false + } + +} + +proc update_S2F_CLK_mux_options {} { + # TODO: retrieve mux options + # TODO: set allowed_ranges on muxes +} + +proc dec2bin {i} { + set res {} + while {$i>0} { + set res [ expr {$i%2} ]$res + set i [expr {$i/2}] + } + if {$res == {}} { + set res 0 + } + return $res +} + +##################################################################### +# +# Gets valid modes for a peripheral with a given pin muxing option. +# Parameters: * peripheral_ref: name of an array pointing to the +# Peripheral HPS I/O Data +# +# Update parameter value with label +proc get_valid_modes {peripheral_name pin_muxing_option peripheral_ref fpga_available} { +##################################################################### + upvar 1 $peripheral_ref peripheral + + if {[info exists peripheral(pin_sets)]} { + array set pin_sets $peripheral(pin_sets) + } + + if {[info exists pin_sets($pin_muxing_option)]} { + array set pin_set $pin_sets($pin_muxing_option) + set pin_set_modes $pin_set(valid_modes) + if {[string match -nocase "trace" $peripheral_name]} { + set valid_modes [list "HPS:8-bit Data" "HPSx4:4-bit Data"] + } elseif {[string match -nocase "usb*" $peripheral_name]} { + set valid_modes [list "SDR:SDR with PHY clock output mode" "SDR without external clock:SDR with PHY clock input mode"] + } else { + set valid_modes [lsort -ascii -increasing $pin_set_modes] + } + } elseif {$fpga_available && [string compare $pin_muxing_option [FPGA_MUX_VALUE]] == 0} { + set valid_modes [list "Full"] + } else { + set valid_modes [list [NA_MODE_VALUE]] + } + return $valid_modes +} + +proc is_peripheral_low_speed_serial_interface {peripheral_name} { + if {[string match -nocase "i2c*" $peripheral_name] || + [string match -nocase "can*" $peripheral_name] || + [string match -nocase "spi*" $peripheral_name] || + [string match -nocase "uart*" $peripheral_name] + } { + return 1 + } + return 0 +} + +# updates the _PinMuxing and _Mode parameter allowed ranges +# -uses a data structure to keep track of choices +# -allowed ranges can come from FPGA Peripheral Interfaces or IOs +# -when a pin muxing option is selected, the mode allowed ranges are +# set according to what's specified from the source (FPGA or pin i/o) +proc update_pin_muxing_ui {device_family} { + + set peripheral_names [list_peripheral_names] + foreach peripheral $peripheral_names { + + get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral\ + selected_pin_muxing_option pin_muxing_options mode_options + + set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral] + set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral] + + set pin_muxing_options [lsort -ascii $pin_muxing_options] + set pin_muxing_options [linsert $pin_muxing_options 0 [UNUSED_MUX_VALUE]] + set_parameter_property $pin_muxing_param_name enabled true + set_parameter_property $pin_muxing_param_name visible true + set_parameter_property $pin_muxing_param_name allowed_ranges $pin_muxing_options + set_parameter_property $mode_param_name visible true + + + set selected_mode_option [get_parameter_value $mode_param_name] + + # Disable I2C parameters so they can only be changed by altering EMAC parameters + # in the HPS IP GUI + if {([string compare $peripheral "I2C2" ] == 0 || [string compare $peripheral "I2C3" ] == 0) + && [string match "*EMAC*" $selected_mode_option]} { + set_parameter_property $pin_muxing_param_name enabled false + set_parameter_property $mode_param_name enabled false + } else { + set_parameter_property $mode_param_name enabled true + } + set_parameter_property $mode_param_name allowed_ranges $mode_options + + # Disabled peripherals that not supported by certain device family + if {[check_device_family_equivalence $device_family ARRIAV]} { + foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] { + if {[string compare $excluded_peripheral $peripheral] == 0} { + set_parameter_property $pin_muxing_param_name enabled false + set_parameter_property $pin_muxing_param_name visible false + set_parameter_property $mode_param_name enabled false + set_parameter_property $mode_param_name visible false + } + } + } + } + + # Only show I2C's "Used by EMACx" modes when EMAC is using I2C + if {[is_pin_mux_data_available hps_ip_pin_muxing_model]} { + foreach emac {EMAC0 EMAC1} { + set emac_pin_set [get_parameter_value [format [PIN_MUX_PARAM_FORMAT] $emac]] + set emac_mode [get_parameter_value [format [MODE_PARAM_FORMAT] $emac]] + + funset i2c_name + get_linked_peripheral hps_ip_pin_muxing_model $emac $emac_pin_set\ + i2c_name i2c_pin_set i2c_mode + + if {[info exists i2c_name] && ![string match "*${i2c_name}*" $emac_mode]} { + # remove EMAC mode + set i2c_mode_param [format [MODE_PARAM_FORMAT] $i2c_name] + set i2c_valid_modes [get_parameter_property $i2c_mode_param ALLOWED_RANGES] + + set new_i2c_valid_modes [list] + foreach mode $i2c_valid_modes { + if {![string match "*${emac}*" $mode]} { + lappend new_i2c_valid_modes $mode + } + } + set_parameter_property $i2c_mode_param ALLOWED_RANGES $new_i2c_valid_modes + } + } + } +} + +proc validate_interrupt {device_family} { + set interrupt_groups [list_h2f_interrupt_groups] + set excluded "CAN" + foreach interrupt_group $interrupt_groups { + set parameter "S2FINTERRUPT_${interrupt_group}_Enable" + set_parameter_property $parameter enabled true + set_parameter_property $parameter visible true + if {[check_device_family_equivalence $device_family ARRIAV] && [string compare $excluded $interrupt_group] == 0} { + set_parameter_property $parameter enabled false + set_parameter_property $parameter visible false + } + } +} + +proc update_gpio_ui {placement_by_pin_ref} { + upvar 1 $placement_by_pin_ref placement_by_pin + # TODO: caching of what needs to be updated? + set customer_pin_names [list] + set gpio_names [list] + set loanio_names [list] + set conflicts [list] + + set customer_pin_names [hps_ip_pin_muxing_model::get_customer_pin_names] + + foreach_gpio_entry hps_ip_pin_muxing_model\ + entry gpio_index gpio_name pin gplin_used gplin_select\ + { + lappend gpio_names $gpio_name + + set conflict "" + if {[info exists placement_by_pin($pin)]} { + set conflict [join $placement_by_pin($pin) ", "] + } + lappend conflicts $conflict + } + foreach_loan_io_entry hps_ip_pin_muxing_model\ + entry loanio_index loanio_name pin gplin_used gplin_select\ + { + lappend loanio_names $loanio_name + } + set_parameter_value Customer_Pin_Name_DERIVED $customer_pin_names + set_parameter_value GPIO_Name_DERIVED $gpio_names + set_parameter_value LOANIO_Name_DERIVED $loanio_names + set_parameter_value GPIO_Conflict_DERIVED $conflicts +} + +proc peripheral_to_wys_atom_name {device_family peripheral} { + set generic_atom_name [hps_io_peripheral_to_generic_atom_name $peripheral] + set wys_atom_name [generic_atom_to_wys_atom $device_family $generic_atom_name] + return $wys_atom_name +} + +# TODO: deal with going out of bounds (gpio_index > 70) +proc gpio_index_to_gpio_port_index {gpio_index} { + set group [expr {$gpio_index / 29}] + set port_index [expr {$gpio_index % 29}] + + set result [list $group $port_index] + return $result +} + + + +proc validate_pin_muxing {device_family placement_by_pin_ref} { + upvar 1 $placement_by_pin_ref placement_by_pin + + # see which pins are being used more than once + # peripherals + funset pin_to_peripheral ;# pin names to peripheral that is occupying + funset conflict_pin_list ; + + foreach peripheral_name [list_peripheral_names] { + set pins_used 0 + set mapping_msg "Peripheral $peripheral_name pin mapping:" + set comma " " + set periph_inst [string tolower "${peripheral_name}_inst"] + foreach_used_peripheral_pin hps_ip_pin_muxing_model $peripheral_name\ + signal_name\ + map\ + pin\ + location\ + mux_select\ + { + # Validate + set entry_exists [info exists pin_to_peripheral($pin)] + if {$entry_exists == 1} { + set conflicting_peripheral $pin_to_peripheral($pin) + # only emit an error once per unique pair of conflicting peripherals + if {[info exists known_conflicts($conflicting_peripheral)] == 0} { + set known_conflicts($conflicting_peripheral) 1 + # TODO: more detailed error message e.g. which pins? explicitly say the bank and modes? + send_message error "Refer to the Peripherals Mux Table for more details. The selected peripherals '$conflicting_peripheral' and '$peripheral_name' are conflicting. " + } + set conflict_pin_list($pin) 1 + } else { + set pin_to_peripheral($pin) $peripheral_name + } + + # Render pins + lassign $map in_port out_port oe_port + set goes_out 0 + set goes_in 0 + + # by default, all signals are assumed to be from the same instance + if {$in_port != ""} { + set in_port "${periph_inst}:${in_port}" + set goes_in 1 + } + if {$out_port != ""} { + set out_port "${periph_inst}:${out_port}" + set goes_out 1 + } + if {$oe_port != ""} { + set oe_port "${periph_inst}:${oe_port}" + set goes_out 1 + } + + if {$goes_in && $goes_out} { + set dir bidir + } elseif {$goes_out} { + set dir output + } else { + set dir input + } + + hps_io::add_pin $periph_inst $signal_name $dir $location $in_port $out_port $oe_port + + if {[info exists placement_by_pin($pin)] == 0} { + set placement_by_pin($pin) [list] + } + lappend placement_by_pin($pin) "${peripheral_name}.${signal_name}" + + set mapping_msg "${mapping_msg}${comma}${signal_name}:${pin}" + set comma ", " + set pins_used 1 + } + if {$pins_used} { + # send_message info $mapping_msg + set wys_atom_name [peripheral_to_wys_atom_name $device_family $peripheral_name] + set location [locations::get_hps_io_peripheral_location $peripheral_name] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $location + } + } + + # HLGPI input only pins + set hlgpi_pins [hps_ip_pin_muxing_model::get_hlgpi_pins] + set hlgpi_count [llength $hlgpi_pins] + set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] + set periph_inst "gpio_inst" + set gpio_unused 1 + set device [get_device] + + if { [ string range $device 0 3 ] == "5CSE" && [ string range $device 8 9 ] == "19" } { + send_message info "HLGPI is not available for Device $device (484 pins)" + set_parameter_property HLGPI_Enable enabled false + } else { + set_parameter_property HLGPI_Enable enabled true + } + + if { [is_enabled HLGPI_Enable] && [get_parameter_property HLGPI_Enable enabled] } { + for {set hlgpi_pin_index 0} {$hlgpi_pin_index < $hlgpi_count} {incr hlgpi_pin_index} { + # HLGPI connected to gpio[26:13] + set gpio_port_index [ expr {$hlgpi_pin_index + 13} ] + set hlgpi_pin [ lindex $hlgpi_pins $hlgpi_pin_index] + + if {$gpio_unused} { + set atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location + set gpio_unused 0 + } + + set signal_name "HLGPI${hlgpi_pin_index}" + set pin_location [::pin_mux_db::get_location_of_pin $hlgpi_pin] + set in_port "${periph_inst}:GPIO2_PORTA_I($gpio_port_index:$gpio_port_index)" + set out_port "" + set oe_port "" + + hps_io::add_pin ${periph_inst} $signal_name input $pin_location $in_port $out_port $oe_port + } + } + + # gpio + funset gpio_port_placement_set ;# set of gpio ports that are being used + set enable_list [get_parameter_value GPIO_Enable] + set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] + set periph_inst "gpio_inst" + + # check and set GPIO_Pin_Used_DERIVED parameter + set_parameter_value GPIO_Pin_Used_DERIVED false + + foreach_gpio_entry hps_ip_pin_muxing_model\ + entry gpio_index gpio_name pin gplin_used gplin_select\ + { + set enabled 0 + set enable_value [lindex $enable_list $entry] + if { [string compare $enable_value "Yes" ] == 0 } { + set enabled 1 + } + if {$enabled} { + set entry_exists [info exists pin_to_peripheral($pin)] + if {$entry_exists} { + set conflicting_peripheral $pin_to_peripheral($pin) + send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral '$conflicting_peripheral' and '${gpio_name}' are conflicting." + set conflict_pin_list($pin) 1 + } else { + set pin_to_peripheral($pin) $gpio_name + } + + if {[info exists gpio_port_placement_set($gpio_index)]} { + send_message error "Refer to the Peripherals Mux Table for more details. GPIO${gpio_index} cannot be used twice." + set conflict_pin_list($pin) 1 + } else { + set gpio_port_placement_set($gpio_index) 1 + } + + if {$gpio_unused} { + set atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location + set gpio_unused 0 + } + + lassign [gpio_index_to_gpio_port_index $gpio_index] gpio_group gpio_port_index + set in_port "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)" + set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)" + set oe_port "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)" + + set pin_location [::pin_mux_db::get_location_of_pin $pin] + hps_io::add_pin $periph_inst $gpio_name bidir $pin_location $in_port $out_port $oe_port + + # set GPIO_Pin_Used_DERIVED to true if GPIO pins used + set_parameter_value GPIO_Pin_Used_DERIVED true + } + } + + # loan i/o + set enable_list [get_parameter_value LOANIO_Enable] + set loanio_used 0 + set loanio_count 0 + foreach_loan_io_entry hps_ip_pin_muxing_model\ + entry loanio_index loanio_name pin gplin_used gplin_select\ + { + if {$loanio_count < $loanio_index} { + set loanio_count $loanio_index + } + set enabled 0 + set enable_value [lindex $enable_list $entry] + if { [string compare $enable_value "Yes" ] == 0 } { + set enabled 1 + } + + if {$enabled} { + set entry_exists [info exists pin_to_peripheral($pin)] + if {$entry_exists} { + set conflicting_peripheral $pin_to_peripheral($pin) + send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral for '$conflicting_peripheral' and '${loanio_name}' are conflicting." + set conflict_pin_list($pin) 1 + } else { + set pin_to_peripheral($pin) $loanio_name + } + + if {[info exists gpio_port_placement_set($loanio_index)]} { + send_message error "Refer to the Peripherals Mux Table for more details. GPIO${loanio_index} cannot be used twice." + set conflict_pin_list($pin) 1 + } else { + set gpio_port_placement_set($loanio_index) 1 + } + + set loanio_used 1 + if {$gpio_unused} { + set atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location + set gpio_unused 0 + } + + lassign [gpio_index_to_gpio_port_index $loanio_index] gpio_group gpio_port_index + set in_port "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)" + set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)" + set oe_port "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)" + + set pin_location [::pin_mux_db::get_location_of_pin $pin] + hps_io::add_pin $periph_inst $loanio_name bidir $pin_location $in_port $out_port $oe_port + + } + } + incr loanio_count ;# count is one greater than the highest index + if $loanio_used { + set wys_atom_name [peripheral_to_wys_atom_name $device_family "LOANIO"] + set location {} + set periph_inst "loan_io_inst" + set iface_name "h2f_loan_io" + set z "h2f_loan_" + fpga_interfaces::add_module_instance ${periph_inst} $wys_atom_name $location + fpga_interfaces::add_interface $iface_name conduit Input + set pin_muxing [get_parameter_value pin_muxing] + fpga_interfaces::add_interface_port $iface_name "${z}in" in Output ${loanio_count} $periph_inst loanio_in + fpga_interfaces::add_interface_port $iface_name "${z}out" out Input ${loanio_count} $periph_inst loanio_out + fpga_interfaces::add_interface_port $iface_name "${z}oe" oe Input ${loanio_count} $periph_inst loanio_oe + + # add loanIO to GPIO atom connection + set loanio_periph_inst "loan_io_inst" + set loanio_iface_name "loanio_gpio" + set loanio_z "loanio_gpio_" + set gpio_periph_inst "gpio_inst" + set gpio_iface_name "gpio_loanio" + set gpio_z "gpio_loanio_" + set gpio_port_size 29 + set start_index 0 + + if {$gpio_unused} { + set gpio_wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] + set gpio_atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${gpio_periph_inst} ${gpio_wys_atom_name} ${gpio_atom_location} + set gpio_unused 0 + } + + fpga_interfaces::add_interface $loanio_iface_name conduit Input "NO_EXPORT" + ::hps_io::internal::add_interface $gpio_iface_name conduit Output "NO_EXPORT" + + for {set i 0} {$i <= 2} {incr i} { + if {[expr ($loanio_count - $start_index)] < $gpio_port_size} { + set gpio_port_size [expr ($loanio_count - $start_index)] + } + set end_index [expr ($start_index + $gpio_port_size - 1)] + + fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_i" "loanio${i}_i" Input ${gpio_port_size} + fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_oe" "loanio${i}_oe" Output ${gpio_port_size} + fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_o" "loanio${i}_o" Output ${gpio_port_size} + + fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_i" "${loanio_periph_inst}:GPIO_IN($end_index:$start_index)" + fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_oe" "${loanio_periph_inst}:GPIO_OE($end_index:$start_index)" + fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_o" "${loanio_periph_inst}:GPIO_OUT($end_index:$start_index)" + + ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_i" "loanio${i}_i" Output ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_I" + ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_oe" "loanio${i}_oe" Input ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_OE" + ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_o" "loanio${i}_o" Input ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_O" + + set start_index [expr ($end_index + 1)] + } + } + set conflicts [list] + set pins [list] + foreach_gpio_entry hps_ip_pin_muxing_model\ + entry gpio_index gpio_name pin gplin_used gplin_select\ + { + set entry_exists [info exists conflict_pin_list($pin)] + if {$entry_exists} { + set conflict "Yes" + } else { + set conflict "No" + } + lappend conflicts $conflict + lappend pins $pin + } + set_parameter_value JAVA_CONFLICT_PIN $conflicts + set_parameter_value JAVA_GUI_PIN_LIST $pins +} + +##################################################### +# +# Sets a valid mode for the peripheral when its pin +# muxing option changes. Will try to retain the +# original mode if available. +# +proc on_altered_peripheral_pin_muxing {peripheral_name} { +##################################################### + set mode_param_name "${peripheral_name}_Mode" + set mode_option [get_parameter_value $mode_param_name] + + get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral_name\ + selected_pin_muxing_option pin_muxing_options new_valid_modes + + # filter the label name of the parameter value if exist + if {[lsearch $new_valid_modes $mode_option] == -1} { + regsub ":.*" [lindex $new_valid_modes 0] "" new_mode_option + } else { + set new_mode_option $mode_option + } + set_parameter_value $mode_param_name $new_mode_option + + if {[string match "*EMAC*" $peripheral_name]} { + on_emac_mode_switch_internal $peripheral_name + } +} + +# Adds the pin muxing model argument +proc on_emac_mode_switch_internal {peripheral_name} { + on_emac_mode_switch hps_ip_pin_muxing_model $peripheral_name +} + +proc validate_and_update_ddr {} { + set desired_operational_freq [get_parameter_value DDR_DesiredFreq] + if {$desired_operational_freq < 0.0} { + send_message error "The operational frequency of the DDR Controller cannot be negative." + } else { + send_message warning "The recommended DDR Controller clock frequency and phase shift information is not correct." + + set_parameter_value DDR_PLLC0RecommendedFreq_DERIVED $desired_operational_freq + set_parameter_value DDR_PLLC1RecommendedFreq_DERIVED [expr $desired_operational_freq * 2.0] + set_parameter_value DDR_PLLC2RecommendedFreq_DERIVED $desired_operational_freq + set_parameter_value DDR_PLLC3RecommendedFreq_DERIVED $desired_operational_freq + + set_parameter_value DDR_PLLC0RecommendedPhase_DERIVED 0.0 + set_parameter_value DDR_PLLC1RecommendedPhase_DERIVED 1.0 + set_parameter_value DDR_PLLC2RecommendedPhase_DERIVED 2.0 + set_parameter_value DDR_PLLC3RecommendedPhase_DERIVED 3.0 + } + + for {set index 0} {${index} < 4} {incr index} { + set p_name "DDR_PLLC${index}ActualFreq" + set value [get_parameter_value $p_name] + if {$value < 0.0} { + send_message error "DDR PLL Output C${index} cannot have a negative clock frequency." + } + + set p_name "DDR_PLLC${index}ActualPhase" + set value [get_parameter_value $p_name] + if {$value < 0.0} { + send_message error "DDR PLL Output C${index} cannot have a negative clock phase shift." + } + } +} + + +###################### +##### Elaboration ##### +###################### + +proc elab {logical_view} { + # TODO: add RTL information for each + set device_family [get_parameter_value hps_device_family] + + elab_clocks_resets $device_family + + elab_MPU_EVENTS $device_family + elab_DEBUGAPB $device_family + elab_STM $device_family + elab_CTI $device_family + elab_TPIUFPGA $device_family + elab_GP $device_family + elab_BOOTFROMFPGA $device_family + + if {$logical_view == 0} { + elab_F2S $device_family + elab_LWH2F $device_family + elab_S2F $device_family + elab_F2SDRAM $device_family + + } + + elab_DMA $device_family + elab_INTERRUPTS $device_family $logical_view + + elab_emac_ptp $device_family + + elab_TEST $device_family + + # Handle Special Case EMAC signal... ptp_ref_clk + set emac0_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC0] + set emac1_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC1] + set emac0_pin_mux_value [get_parameter_value $emac0_pin_mux_param_name] + set emac1_pin_mux_value [get_parameter_value $emac1_pin_mux_param_name] + set emac0_pin_mux_allowed_ranges [get_parameter_property $emac0_pin_mux_param_name allowed_ranges] + set emac1_pin_mux_allowed_ranges [get_parameter_property $emac1_pin_mux_param_name allowed_ranges] + + set emac0_ptp_enabled [expr {[string compare $emac0_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac0_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}] + set emac1_ptp_enabled [expr {[string compare $emac1_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac1_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}] + + set emac0_io_enabled [expr {[string compare $emac0_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac0_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}] + set emac1_io_enabled [expr {[string compare $emac1_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac1_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}] + + set emac0_ptp [get_parameter_value EMAC0_PTP] + set emac1_ptp [get_parameter_value EMAC1_PTP] + + if {$emac0_ptp && $emac0_io_enabled} { + set emac0_ptp_enabled 1 + } + if {$emac1_ptp && $emac1_io_enabled} { + set emac1_ptp_enabled 1 + } + + if {$emac0_ptp_enabled || $emac1_ptp_enabled } { + set instance_name clocks_resets + fpga_interfaces::add_interface emac_ptp_ref_clock clock Input + fpga_interfaces::add_interface_port emac_ptp_ref_clock emac_ptp_ref_clk clk Input 1 $instance_name ptp_ref_clk + } + + # TODO: elab peripherals that mux signals to the fpga + elab_FPGA_Peripheral_Signals $device_family + + set_parameter_value DEVICE_FAMILY [get_parameter_value SYS_INFO_DEVICE_FAMILY] +} + +proc elab_MPU_EVENTS {device_family} { + if [is_enabled MPU_EVENTS_Enable] { + set instance_name mpu_events + set atom_name hps_interface_mpu_event_standby + set location [locations::get_fpga_location $instance_name $atom_name] + + set iface_name "h2f_mpu_events" + set z "h2f_mpu_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name ${z}eventi eventi Input 1 $instance_name eventi + fpga_interfaces::add_interface_port $iface_name ${z}evento evento Output 1 $instance_name evento + fpga_interfaces::add_interface_port $iface_name ${z}standbywfe standbywfe Output 2 $instance_name standbywfe + fpga_interfaces::add_interface_port $iface_name ${z}standbywfi standbywfi Output 2 $instance_name standbywfi + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_DEBUGAPB {device_family} { + set instance_name debug_apb + set atom_name hps_interface_dbg_apb + set location [locations::get_fpga_location $instance_name $atom_name] + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + if [is_enabled DEBUGAPB_Enable] { + set clock_name "h2f_debug_apb_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name "h2f_dbg_apb_clk" clk Input 1 $instance_name P_CLK + + set reset_name "h2f_debug_apb_reset" + fpga_interfaces::add_interface $reset_name reset Output + fpga_interfaces::add_interface_port $reset_name "h2f_dbg_apb_rst_n" reset_n Output 1 $instance_name P_RESET_N + fpga_interfaces::set_interface_property $reset_name associatedClock $clock_name + + set iface_name "h2f_debug_apb" + set z "h2f_dbg_apb_" + fpga_interfaces::add_interface $iface_name apb master + fpga_interfaces::add_interface_port $iface_name "${z}PADDR" paddr Output 18 $instance_name P_ADDR + fpga_interfaces::add_interface_port $iface_name "${z}PADDR31" paddr31 Output 1 $instance_name P_ADDR_31 + fpga_interfaces::add_interface_port $iface_name "${z}PENABLE" penable Output 1 $instance_name P_ENABLE + fpga_interfaces::add_interface_port $iface_name "${z}PRDATA" prdata Input 32 $instance_name P_RDATA + fpga_interfaces::add_interface_port $iface_name "${z}PREADY" pready Input 1 $instance_name P_READY + fpga_interfaces::add_interface_port $iface_name "${z}PSEL" psel Output 1 $instance_name P_SEL + fpga_interfaces::add_interface_port $iface_name "${z}PSLVERR" pslverr Input 1 $instance_name P_SLV_ERR + fpga_interfaces::add_interface_port $iface_name "${z}PWDATA" pwdata Output 32 $instance_name P_WDATA + fpga_interfaces::add_interface_port $iface_name "${z}PWRITE" pwrite Output 1 $instance_name P_WRITE + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset $reset_name + + set iface_name "h2f_debug_apb_sideband" + set z "h2f_dbg_apb_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name "${z}PCLKEN" pclken Input 1 $instance_name P_CLK_EN + fpga_interfaces::add_interface_port $iface_name "${z}DBG_APB_DISABLE" dbg_apb_disable Input 1 $instance_name DBG_APB_DISABLE + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset $reset_name + + } else { + # Tie low when FPGA debug apb not being used + fpga_interfaces::set_instance_port_termination ${instance_name} "P_CLK_EN" 1 0 0:0 0 + fpga_interfaces::set_instance_port_termination ${instance_name} "DBG_APB_DISABLE" 1 0 0:0 0 + } +} + +proc elab_STM {device_family} { + if [is_enabled STM_Enable] { + set instance_name stm_event + set atom_name hps_interface_stm_event + set location [locations::get_fpga_location $instance_name $atom_name] + + fpga_interfaces::add_interface f2h_stm_hw_events conduit Input + fpga_interfaces::add_interface_port f2h_stm_hw_events f2h_stm_hwevents stm_hwevents Input 28 $instance_name stm_event + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_CTI {device_family} { + set instance_name cross_trigger_interface + set atom_name hps_interface_cross_trigger + set location [locations::get_fpga_location $instance_name $atom_name] + + if [is_enabled CTI_Enable] { + set iface_name "h2f_cti" + set z "h2f_cti_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name ${z}trig_in trig_in Input 8 $instance_name trig_in + fpga_interfaces::add_interface_port $iface_name ${z}trig_in_ack trig_in_ack Output 8 $instance_name trig_inack + fpga_interfaces::add_interface_port $iface_name ${z}trig_out trig_out Output 8 $instance_name trig_out + fpga_interfaces::add_interface_port $iface_name ${z}trig_out_ack trig_out_ack Input 8 $instance_name trig_outack + # case:105603 hide asicctl output signal + # fpga_interfaces::add_interface_port $iface_name ${z}asicctl asicctl Output 8 $instance_name asicctl + fpga_interfaces::add_interface_port $iface_name ${z}fpga_clk_en fpga_clk_en Input 1 $instance_name clk_en + fpga_interfaces::set_interface_property $iface_name associatedClock h2f_cti_clock + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + + fpga_interfaces::add_interface h2f_cti_clock clock Input + fpga_interfaces::add_interface_port h2f_cti_clock h2f_cti_clk clk Input 1 $instance_name clk + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_TPIUFPGA {device_family} { + set instance_name tpiu + set atom_name hps_interface_tpiu_trace + set location [locations::get_fpga_location $instance_name $atom_name] + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + if { [string compare [get_parameter_value TPIUFPGA_Enable] "true" ] == 0 } { + set_parameter_property TPIUFPGA_alt enabled true + set iface_name "h2f_tpiu" + set z "h2f_tpiu_" + fpga_interfaces::add_interface $iface_name conduit input + fpga_interfaces::add_interface_port $iface_name ${z}clk_ctl clk_ctl Input 1 $instance_name traceclk_ctl + fpga_interfaces::add_interface_port $iface_name ${z}data data Output 32 $instance_name trace_data + + # case 245159 + if {[string compare [get_parameter_value TPIUFPGA_alt] "true" ] == 0} { + fpga_interfaces::add_interface_port $iface_name ${z}clkin clkin Input 1 $instance_name traceclkin + } else { + set iface_name "h2f_tpiu_clock_in" + fpga_interfaces::add_interface $iface_name clock input + fpga_interfaces::add_interface_port $iface_name ${z}clk_in clk Input 1 $instance_name traceclkin + } + + set clock_in_rate [get_parameter_value H2F_TPIU_CLOCK_IN_FREQ] + set clock_rate [expr {$clock_in_rate / 2}] + set iface_name "h2f_tpiu_clock" + fpga_interfaces::add_interface $iface_name clock output + fpga_interfaces::add_interface_port $iface_name ${z}clk clk Output 1 $instance_name traceclk + fpga_interfaces::set_interface_property $iface_name clockRateKnown true + fpga_interfaces::set_interface_property $iface_name clockRate $clock_rate + + add_clock_constraint_if_valid $clock_rate "*|fpga_interfaces|${instance_name}|traceclk" + + } else { + set_parameter_property TPIUFPGA_alt enabled false + fpga_interfaces::set_instance_port_termination ${instance_name} "traceclk_ctl" 1 1 0:0 1 + } +} + +proc elab_GP {device_family} { + if [is_enabled GP_Enable] { + set instance_name h2f_gp + set atom_name hps_interface_mpu_general_purpose + set location [locations::get_fpga_location $instance_name $atom_name] + + set iface_name "h2f_gp" + set z "h2f_gp_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name ${z}in gp_in Input 32 $instance_name gp_in + fpga_interfaces::add_interface_port $iface_name ${z}out gp_out Output 32 $instance_name gp_out + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_BOOTFROMFPGA {device_family} { + set instance_name boot_from_fpga + set atom_name hps_interface_boot_from_fpga + set location [locations::get_fpga_location $instance_name $atom_name] + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set bsel_en [expr { [string compare [get_parameter_value BSEL_EN] "true" ] == 0 } ] + set bsel [get_parameter_value BSEL] + set csel_en [expr { [string compare [get_parameter_value CSEL_EN] "true" ] == 0 } ] + set csel [get_parameter_value CSEL] + set boot_from_fpga_enable [expr { [string compare [get_parameter_value BOOTFROMFPGA_Enable] "true" ] == 0 } ] + set ini_string [get_parameter_value quartus_ini_hps_ip_enable_bsel_csel] + set ini_enabled [expr { [string compare $ini_string "true" ] == 0 } ] + + # force disable bsel/csel by default + if {!$ini_enabled} { + set bsel_en 0 + set bsel 1 + set csel_en 0 + set csel 1 + } + + # when INI enabled, the controls should appear in the GUI + foreach parameter {BSEL BSEL_EN CSEL CSEL_EN} { + set_parameter_property $parameter visible $ini_string + set_parameter_property $parameter enabled $ini_string + } + + fpga_interfaces::set_instance_port_termination ${instance_name} "bsel" 3 0 2:0 $bsel + fpga_interfaces::set_instance_port_termination ${instance_name} "csel" 2 0 1:0 $csel + + if {$bsel_en} { + fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 1 + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 0 + } + + if {$csel_en} { + fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 1 + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 0 + } + + if {$boot_from_fpga_enable} { + set iface_name "f2h_boot_from_fpga" + set z "f2h_boot_from_fpga_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name "${z}ready" boot_from_fpga_ready Input 1 $instance_name boot_from_fpga_ready + fpga_interfaces::add_interface_port $iface_name "${z}on_failure" boot_from_fpga_on_failure Input 1 $instance_name boot_from_fpga_on_failure + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_ready" 1 0 0:0 0 + fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_on_failure" 1 0 0:0 0 + } + + if {$boot_from_fpga_enable} { + send_message info "Ensure that valid Cortex A9 boot code is available to the HPS system when enabling boot from FPGA and h2f_axi_master interface is connecting to slave component start at address 0x0." + } + + if {$bsel_en && $bsel == 1 && !$boot_from_fpga_enable} { + send_message warning "Boot from FPGA ready must be enabled to correctly boot from the FPGA." + } +} + + +proc elab_F2S {device_family} { + set instance_name fpga2hps + set atom_name hps_interface_fpga2hps + set location [locations::get_fpga_location $instance_name $atom_name] + set termination_value 3 + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set addr_width 32 + set width [get_parameter_value F2S_Width] + if {$width > 0} { + set data_width 32 + set strb_width 4 + set termination_value 0 + if {$width == 2} { + set data_width 64 + set strb_width 8 + set termination_value 1 + } elseif {$width == 3} { + set data_width 128 + set strb_width 16 + set termination_value 2 + } + + set clock_name "f2h_axi_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name f2h_axi_clk clk Input 1 $instance_name clk + + set iface_name "f2h_axi_slave" + set z "f2h_" + + fpga_interfaces::add_interface $iface_name axi slave + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + fpga_interfaces::set_interface_property $iface_name readAcceptanceCapability 8 + fpga_interfaces::set_interface_property $iface_name writeAcceptanceCapability 8 + fpga_interfaces::set_interface_property $iface_name combinedAcceptanceCapability 16 + fpga_interfaces::set_interface_property $iface_name readDataReorderingDepth 16 + fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width + fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width + + fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Input 8 $instance_name awid + fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Input $addr_width $instance_name awaddr + fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Input 4 $instance_name awlen + fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Input 3 $instance_name awsize + fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Input 2 $instance_name awburst + fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Input 2 $instance_name awlock + fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Input 4 $instance_name awcache + fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Input 3 $instance_name awprot + fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Input 1 $instance_name awvalid + fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Output 1 $instance_name awready + fpga_interfaces::add_interface_port $iface_name ${z}AWUSER awuser Input 5 $instance_name awuser + + fpga_interfaces::add_interface_port $iface_name ${z}WID wid Input 8 $instance_name wid + fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Input $data_width $instance_name wdata + fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Input $strb_width $instance_name wstrb + fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Input 1 $instance_name wlast + fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Input 1 $instance_name wvalid + fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Output 1 $instance_name wready + + fpga_interfaces::add_interface_port $iface_name ${z}BID bid Output 8 $instance_name bid + fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Output 2 $instance_name bresp + fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Output 1 $instance_name bvalid + fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Input 1 $instance_name bready + + + fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Input 8 $instance_name arid + fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Input $addr_width $instance_name araddr + fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Input 4 $instance_name arlen + fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Input 3 $instance_name arsize + fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Input 2 $instance_name arburst + fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Input 2 $instance_name arlock + fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Input 4 $instance_name arcache + fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Input 3 $instance_name arprot + fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Input 1 $instance_name arvalid + fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Output 1 $instance_name arready + fpga_interfaces::add_interface_port $iface_name ${z}ARUSER aruser Input 5 $instance_name aruser + + fpga_interfaces::add_interface_port $iface_name ${z}RID rid Output 8 $instance_name rid + fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Output $data_width $instance_name rdata + fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Output 2 $instance_name rresp + fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Output 1 $instance_name rlast + fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Output 1 $instance_name rvalid + fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Input 1 $instance_name rready + } + fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0 1:0 $termination_value +} + +proc elab_S2F {device_family} { + set instance_name hps2fpga + set atom_name hps_interface_hps2fpga + set location [locations::get_fpga_location $instance_name $atom_name] + set termination_value 3 + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set addr_width 30 + set id_width 12 + set width [get_parameter_value S2F_Width] + if {$width > 0} { + set data_width 32 + set strb_width 4 + set termination_value 0 + + if {$width == 2} { + set data_width 64 + set strb_width 8 + set termination_value 1 + + } elseif {$width == 3} { + set data_width 128 + set strb_width 16 + set termination_value 2 + } + + set clock_name "h2f_axi_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name h2f_axi_clk clk Input 1 $instance_name clk + + set iface_name "h2f_axi_master" + set z "h2f_" + + fpga_interfaces::add_interface $iface_name axi master + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + fpga_interfaces::set_interface_property $iface_name readIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name writeIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name combinedIssuingCapability 16 + +# set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps golden_ref_design_CMSIS_1_1_to_arm_v2.svd] +# send_message info "REMOVE! SVD_PATH = $svd_path" +# fpga_interfaces::set_interface_property $iface_name CMSIS_SVD_FILE $svd_path +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_GROUP hps +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_OFFSET [expr {0xC0000000}] + fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width + fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width + fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width + + fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Output $id_width $instance_name awid + fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Output $addr_width $instance_name awaddr + fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Output 4 $instance_name awlen + fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Output 3 $instance_name awsize + fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Output 2 $instance_name awburst + fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Output 2 $instance_name awlock + fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Output 4 $instance_name awcache + fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Output 3 $instance_name awprot + fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Output 1 $instance_name awvalid + fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Input 1 $instance_name awready + + fpga_interfaces::add_interface_port $iface_name ${z}WID wid Output $id_width $instance_name wid + fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Output $data_width $instance_name wdata + fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Output $strb_width $instance_name wstrb + fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Output 1 $instance_name wlast + fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Output 1 $instance_name wvalid + fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Input 1 $instance_name wready + + fpga_interfaces::add_interface_port $iface_name ${z}BID bid Input $id_width $instance_name bid + fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Input 2 $instance_name bresp + fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Input 1 $instance_name bvalid + fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Output 1 $instance_name bready + + fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Output $id_width $instance_name arid + fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Output $addr_width $instance_name araddr + fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Output 4 $instance_name arlen + fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Output 3 $instance_name arsize + fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Output 2 $instance_name arburst + fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Output 2 $instance_name arlock + fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Output 4 $instance_name arcache + fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Output 3 $instance_name arprot + fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Output 1 $instance_name arvalid + fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Input 1 $instance_name arready + + fpga_interfaces::add_interface_port $iface_name ${z}RID rid Input $id_width $instance_name rid + fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Input $data_width $instance_name rdata + fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Input 2 $instance_name rresp + fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Input 1 $instance_name rlast + fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Input 1 $instance_name rvalid + fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Output 1 $instance_name rready + + } + fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0 1:0 $termination_value +} + +proc elab_LWH2F {device_family} { + set instance_name hps2fpga_light_weight + set atom_name hps_interface_hps2fpga_light_weight + set location [locations::get_fpga_location $instance_name $atom_name] + + if [is_enabled LWH2F_Enable] { + set addr_width 21 + set data_width 32 + set strb_width 4 + set id_width 12 + set clock_name "h2f_lw_axi_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name h2f_lw_axi_clk clk Input 1 $instance_name clk + + set iface_name "h2f_lw_axi_master" + set z "h2f_lw_" + fpga_interfaces::add_interface $iface_name axi master +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_GROUP hps +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_OFFSET [expr {0xFC000000}] + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + fpga_interfaces::set_interface_property $iface_name readIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name writeIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name combinedIssuingCapability 16 + fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width + fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width + fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width + + fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Output $id_width $instance_name awid + fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Output $addr_width $instance_name awaddr + fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Output 4 $instance_name awlen + fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Output 3 $instance_name awsize + fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Output 2 $instance_name awburst + fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Output 2 $instance_name awlock + fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Output 4 $instance_name awcache + fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Output 3 $instance_name awprot + fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Output 1 $instance_name awvalid + fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Input 1 $instance_name awready + + fpga_interfaces::add_interface_port $iface_name ${z}WID wid Output $id_width $instance_name wid + fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Output $data_width $instance_name wdata + fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Output $strb_width $instance_name wstrb + fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Output 1 $instance_name wlast + fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Output 1 $instance_name wvalid + fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Input 1 $instance_name wready + + fpga_interfaces::add_interface_port $iface_name ${z}BID bid Input $id_width $instance_name bid + fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Input 2 $instance_name bresp + fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Input 1 $instance_name bvalid + fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Output 1 $instance_name bready + + fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Output $id_width $instance_name arid + fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Output $addr_width $instance_name araddr + fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Output 4 $instance_name arlen + fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Output 3 $instance_name arsize + fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Output 2 $instance_name arburst + fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Output 2 $instance_name arlock + fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Output 4 $instance_name arcache + fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Output 3 $instance_name arprot + fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Output 1 $instance_name arvalid + fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Input 1 $instance_name arready + + fpga_interfaces::add_interface_port $iface_name ${z}RID rid Input $id_width $instance_name rid + fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Input $data_width $instance_name rdata + fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Input 2 $instance_name rresp + fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Input 1 $instance_name rlast + fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Input 1 $instance_name rvalid + fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Output 1 $instance_name rready + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_F2SDRAM {device_family} { + f2sdram::init_registers + + set instance_name f2sdram + set atom_name hps_interface_fpga2sdram + set location [locations::get_fpga_location $instance_name $atom_name] + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set use_fast_sim_model [expr { [string compare [get_parameter_value quartus_ini_hps_ip_fast_f2sdram_sim_model] "true" ] == 0 }] + set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] + #newly added + set width_list [get_parameter_value F2SDRAM_Width] + set rows [llength $width_list] + if {$rows > 0} { + # TODO: move outside of 'if' once registers are rendered + + + set type_list [get_parameter_value F2SDRAM_Type] + for {set i 0} {${i} < $rows} {incr i} { + set width [lindex $width_list $i] + set type_choice [lindex $type_list $i] + + set type "axi" + set type_id 0 + if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { + set type "avalon" + set type_id 1 + } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { + set type "avalon" + set type_id 2 + } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { + set type "avalon" + set type_id 3 + } + + set sim_is_synth [expr !$use_fast_sim_model] + + # To make sure bonding_out_signal only being added once even thought there are more than one f2sdram + if {$i == 0 } { + set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] + } else { + set bonding_out_signal 0 + } + + f2sdram::add_port registers $i $type_id $width $instance_name $sim_is_synth $bonding_out_signal + } + f2sdram::add_sdc $use_fast_sim_model + fpga_interfaces::set_property IMPLEMENT_F2SDRAM_MEMORY_BACKED_SIM $use_fast_sim_model + + } + # write the registers out + f2sdram::render_registers registers $instance_name +} + +proc elab_clocks_resets {device_family} { + set instance_name clocks_resets + set atom_name hps_interface_clocks_resets + set location [locations::get_fpga_location $instance_name $atom_name] + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + fpga_interfaces::add_interface h2f_reset reset Output + fpga_interfaces::add_interface_port h2f_reset h2f_rst_n reset_n Output 1 $instance_name + fpga_interfaces::set_interface_property h2f_reset synchronousEdges none + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks none + + if [is_enabled S2FCLK_COLDRST_Enable] { + fpga_interfaces::add_interface h2f_cold_reset reset Output + fpga_interfaces::add_interface_port h2f_cold_reset h2f_cold_rst_n reset_n Output 1 $instance_name + fpga_interfaces::set_interface_property h2f_cold_reset synchronousEdges none + fpga_interfaces::set_interface_property h2f_cold_reset associatedResetSinks none + } + + if [is_enabled F2SCLK_COLDRST_Enable] { + fpga_interfaces::add_interface f2h_cold_reset_req reset Input + fpga_interfaces::add_interface_port f2h_cold_reset_req f2h_cold_rst_req_n reset_n Input 1 $instance_name + fpga_interfaces::set_interface_property f2h_cold_reset_req synchronousEdges none + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks f2h_cold_reset_req + if [is_enabled S2FCLK_COLDRST_Enable] { + fpga_interfaces::set_interface_property h2f_cold_reset associatedResetSinks f2h_cold_reset_req + } + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_cold_rst_req_n" 1 1 0:0 1 + } + + if [is_enabled S2FCLK_PENDINGRST_Enable] { + fpga_interfaces::add_interface h2f_warm_reset_handshake conduit Output + fpga_interfaces::add_interface_port h2f_warm_reset_handshake h2f_pending_rst_req_n h2f_pending_rst_req_n Output 1 $instance_name + fpga_interfaces::add_interface_port h2f_warm_reset_handshake f2h_pending_rst_ack_n f2h_pending_rst_ack_n Input 1 $instance_name f2h_pending_rst_ack + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_pending_rst_ack" 1 1 0:0 1 + } + + if [is_enabled F2SCLK_DBGRST_Enable] { + fpga_interfaces::add_interface f2h_debug_reset_req reset Input + fpga_interfaces::add_interface_port f2h_debug_reset_req f2h_dbg_rst_req_n reset_n Input 1 $instance_name + fpga_interfaces::set_interface_property f2h_debug_reset_req synchronousEdges none + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_dbg_rst_req_n" 1 1 0:0 1 + } + + if [is_enabled F2SCLK_WARMRST_Enable] { + fpga_interfaces::add_interface f2h_warm_reset_req reset Input + fpga_interfaces::add_interface_port f2h_warm_reset_req f2h_warm_rst_req_n reset_n Input 1 $instance_name + fpga_interfaces::set_interface_property f2h_warm_reset_req synchronousEdges none + + if [is_enabled F2SCLK_COLDRST_Enable] { + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req f2h_cold_reset_req} + } else { + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req} + } + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_warm_rst_req_n" 1 1 0:0 1 + } + + if [is_enabled S2FCLK_USER0CLK_Enable] { + fpga_interfaces::add_interface h2f_user0_clock clock Output + fpga_interfaces::add_interface_port h2f_user0_clock h2f_user0_clk clk Output 1 $instance_name + set frequency [get_parameter_value S2FCLK_USER0CLK_FREQ] + set frequency [expr {$frequency * [MHZ_TO_HZ]}] + fpga_interfaces::set_interface_property h2f_user0_clock clockRateKnown true + fpga_interfaces::set_interface_property h2f_user0_clock clockRate $frequency + add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user0_clk" + } + + if [is_enabled S2FCLK_USER1CLK_Enable] { + fpga_interfaces::add_interface h2f_user1_clock clock Output + fpga_interfaces::add_interface_port h2f_user1_clock h2f_user1_clk clk Output 1 $instance_name + set frequency [get_parameter_value S2FCLK_USER1CLK_FREQ] + set frequency [expr {$frequency * [MHZ_TO_HZ]}] + fpga_interfaces::set_interface_property h2f_user1_clock clockRateKnown true + fpga_interfaces::set_interface_property h2f_user1_clock clockRate $frequency + add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user1_clk" + } + + set_parameter_property S2FCLK_USER2CLK enabled false + + if [is_enabled F2SCLK_PERIPHCLK_Enable] { + fpga_interfaces::add_interface f2h_periph_ref_clock clock Input + fpga_interfaces::add_interface_port f2h_periph_ref_clock f2h_periph_ref_clk clk Input 1 $instance_name + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_periph_ref_clk" 1 0 + } + + + if [is_enabled F2SCLK_SDRAMCLK_Enable] { + fpga_interfaces::add_interface f2h_sdram_ref_clock clock Input + fpga_interfaces::add_interface_port f2h_sdram_ref_clock f2h_sdram_ref_clk clk Input 1 $instance_name + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_sdram_ref_clk" 1 0 + } +} + +# Elaborate peripheral request interfaces for the fpga and +# the clk/reset per pair +# TODO: Make sure the DMA RTL contains the wrapper +proc elab_DMA {device_family} { + set instance_name dma + set atom_name hps_interface_dma + set location [locations::get_fpga_location $instance_name $atom_name] + + set can_message 0 + set available_list [get_parameter_value DMA_Enable] + if {[llength $available_list] > 0} { + set dma_used 0 + set periph_id 0 + foreach entry $available_list { + if {[string compare $entry "Yes" ] == 0} { + elab_DMA_entry $periph_id $instance_name + set dma_used 1 + if {$periph_id >= 4} { + set can_message 1 + } + } + incr periph_id + } + if $dma_used { + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } + if $can_message { + send_message info "DMA Peripheral Request Interfaces 4-7 may be consumed by an HPS CAN Controller" + } + } +} + +proc elab_DMA_make_conduit_name {periph_id} { + return "f2h_dma_req${periph_id}" +} + +proc elab_DMA_entry {periph_id instance_name} { + set iname [elab_DMA_make_conduit_name $periph_id] + set atom_signal_prefix "channel${periph_id}" + fpga_interfaces::add_interface $iname conduit Output + fpga_interfaces::add_interface_port $iname "${iname}_req" "dma_req" Input 1 $instance_name ${atom_signal_prefix}_req + fpga_interfaces::add_interface_port $iname "${iname}_single" "dma_single" Input 1 $instance_name ${atom_signal_prefix}_single + fpga_interfaces::add_interface_port $iname "${iname}_ack" "dma_ack" Output 1 $instance_name ${atom_signal_prefix}_xx_ack +} + + +proc elab_emac_ptp {device_family} { + # added for case http://fogbugz.altera.com/default.asp?307450 + for {set i 0} {$i < 2} {incr i} { + set emac_fpga_enabled false + set emac_io_enabled false + + set emac_pin_mux_value [get_parameter_value EMAC${i}_PinMuxing] + set emac_ptp [get_parameter_value EMAC${i}_PTP] + + if {[string compare $emac_pin_mux_value [FPGA_MUX_VALUE]] == 0} { + set emac_fpga_enabled true + } + if {[string compare $emac_pin_mux_value "HPS I/O Set 0"] == 0} { + set emac_io_enabled true + } + + set_parameter_property EMAC${i}_PTP enabled $emac_io_enabled + + if {$emac_io_enabled && $emac_ptp } { + set instance_name peripheral_emac${i} + set atom_name hps_interface_peripheral_emac + set wys_atom_name arriav_hps_interface_peripheral_emac + set location [locations::get_fpga_location $instance_name $atom_name] + + set iface_name "emac${i}" + + fpga_interfaces::add_interface $iface_name conduit input + fpga_interfaces::add_interface_port $iface_name emac${i}_ptp_aux_ts_trig_i ptp_aux_ts_trig_i Input 1 $instance_name ptp_aux_ts_trig_i + fpga_interfaces::add_interface_port $iface_name emac${i}_ptp_pps_o ptp_pps_o Output 1 $instance_name ptp_pps_o + + + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } + + } +} + +proc elab_INTERRUPTS {device_family logical_view} { + set instance_name interrupts + set atom_name hps_interface_interrupts + set location [locations::get_fpga_location $instance_name $atom_name] + set any_interrupt_enabled 0 + + ##### F2H ##### + if [is_enabled F2SINTERRUPT_Enable] { + set any_interrupt_enabled 1 + set iname "f2h_irq" + set pname "f2h_irq" + if { $logical_view == 0 } { + fpga_interfaces::add_interface "${iname}0" interrupt receiver + fpga_interfaces::add_interface_port "${iname}0" "${pname}_p0" irq Input 32 + fpga_interfaces::set_port_fragments "${iname}0" "${pname}_p0" "${instance_name}:irq(31:0)" + + fpga_interfaces::add_interface "${iname}1" interrupt receiver + fpga_interfaces::add_interface_port "${iname}1" "${pname}_p1" irq Input 32 + fpga_interfaces::set_port_fragments "${iname}1" "${pname}_p1" "${instance_name}:irq(63:32)" + } + } + + ##### H2F ##### + load_h2f_interrupt_table\ + functions_by_group width_by_function inverted_by_function + + set interrupt_groups [list_h2f_interrupt_groups] + foreach group $interrupt_groups { + set parameter "S2FINTERRUPT_${group}_Enable" + set enabled [is_enabled $parameter] + + if {!$enabled} { + continue + } + set any_interrupt_enabled 1 + + foreach function $functions_by_group($group) { + set width 1 + if {[info exists width_by_function($function)]} { + set width $width_by_function($function) + } + + set suffix "" + set inverted [info exists inverted_by_function($function)] + if {$inverted} { + set suffix "_n" + } + + #skip fpga_interfaces interrupt declaration for uart + if { ($logical_view == 1) && ( + $function == "uart0" || + $function == "uart1" )} { + continue + } + + set prefix "h2f_${function}_" + set interface "${prefix}interrupt" + set port "${prefix}irq" + + if {$width > 1} { ;# for buses, use index in interface/port names + for {set i 0} {$i < $width} {incr i} { + set indexed_interface "${interface}${i}" + set indexed_port "${port}${i}${suffix}" + fpga_interfaces::add_interface\ + $indexed_interface interrupt sender + fpga_interfaces::add_interface_port\ + $indexed_interface $indexed_port irq Output 1\ + $instance_name $indexed_port + } + } else { + set port "$port${suffix}" + fpga_interfaces::add_interface\ + $interface interrupt sender + fpga_interfaces::add_interface_port\ + $interface $port irq Output 1 $instance_name $port + } + } + } + + if {$any_interrupt_enabled} { + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_TEST {device_family} { + set parameter_enabled [expr {[string compare [get_parameter_value TEST_Enable] "true" ] == 0}] + set ini_enabled [expr {[string compare [get_parameter_value quartus_ini_hps_ip_enable_test_interface] "true" ] == 0}] + + if {$parameter_enabled && $ini_enabled} { + set instance_name test_interface + set atom_name hps_interface_test + set location [locations::get_fpga_location $instance_name $atom_name] + + set iname "test" + set z "test_" + + set data [get_parameter_value test_iface_definition] + + fpga_interfaces::add_interface $iname conduit input + foreach {port width dir} $data { + fpga_interfaces::add_interface_port $iname "${z}${port}" $port $dir $width $instance_name $port + } + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +# TODO: Mode usage data +proc elab_FPGA_Peripheral_Signals {device_family} { + # disable and hide all parameters related to fpga outputs + set emac0_fpga [get_parameter_value quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface] + set lssis_fpga [get_parameter_value quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces] + set all_fpga "true" + + set peripherals [list_peripheral_names] + foreach peripheral $peripherals { + if { [string compare $peripheral "SDIO" ] == 0 } { + continue + } + set visible false + if {[string compare $all_fpga "true" ] == 0} { + set visible true + } elseif {[string compare $emac0_fpga "true" ] == 0 && [string compare -nocase $peripheral "emac0"] == 0} { + set visible true + } elseif {[string compare $lssis_fpga "true" ] == 0 && [is_peripheral_low_speed_serial_interface $peripheral_name]} { + set visible true + } + if {[string compare -nocase $peripheral "emac0" ] == 0 || [string compare -nocase $peripheral "emac1" ] == 0} { + set visible true + } + set clocks [get_peripheral_fpga_output_clocks $peripheral] + foreach clock $clocks { + set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock] + set_parameter_property $parameter enabled false + set_parameter_property $parameter visible $visible + set clock_output_set($clock) 1 + } + + set clocks [get_peripheral_fpga_input_clocks $peripheral] + foreach clock $clocks { + set clock_input_set($clock) 1 + } + } + + array set fpga_ifaces [get_parameter_value DB_periph_ifaces] + array set iface_ports [get_parameter_value DB_iface_ports] + array set port_pins [get_parameter_value DB_port_pins] + foreach peripheral_name $fpga_ifaces([ORDERED_NAMES]) { ;# Peripherals + set pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name] + set pin_mux_value [get_parameter_value $pin_mux_param_name] + set allowed_ranges [get_parameter_property $pin_mux_param_name allowed_ranges] + + if {[string compare $pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $allowed_ranges [FPGA_MUX_VALUE]] != -1} { + funset peripheral + array set peripheral $fpga_ifaces($peripheral_name) + funset interfaces + array set interfaces $peripheral(interfaces) + + set instance_name [invent_peripheral_instance_name $peripheral_name] + + foreach interface_name $interfaces([ORDERED_NAMES]) { ;# Interfaces + funset interface + array set interface $interfaces($interface_name) + fpga_interfaces::add_interface $interface_name $interface(type) $interface(direction) + foreach {property_key property_value} $interface(properties) { + fpga_interfaces::set_interface_property $interface_name $property_key $property_value + } + #send_message info "NEA: peripheral_name $peripheral_name interface_name $interface_name " + + if { [string match "EMAC?" $peripheral_name] && [string match "*x_reset" $interface_name ] } { + fpga_interfaces::set_interface_property $interface_name associatedResetSinks none + } + + foreach {meta_property} [array names interface] { + # Meta Property if leading with an @ + if {[string compare [string index ${meta_property} 0] "@"] == 0} { + fpga_interfaces::set_interface_meta_property $interface_name [string replace ${meta_property} 0 0] $interface($meta_property) + } + } + + set once_per_clock 1 + funset ports + array set ports $iface_ports($interface_name) + foreach port_name $ports([ORDERED_NAMES]) { ;# Ports + funset port + array set port $ports($port_name) + + # TODO: determine width based on pins available via mode + set width [calculate_port_width $port_pins($port_name)] + + fpga_interfaces::add_interface_port $interface_name $port_name $port(role) $port(direction) $width $instance_name $port(atom_signal_name) + + set frequency 0 + # enable and show clock frequency parameters for outputs + if {[info exists clock_output_set($interface_name)]} { + set parameter [form_peripheral_fpga_output_clock_frequency_parameter $interface_name] + set_parameter_property $parameter enabled true + set frequency [get_parameter_value $parameter] + set frequency [expr {$frequency * [MHZ_TO_HZ]}] + fpga_interfaces::set_interface_property $interface_name clockRateKnown true + fpga_interfaces::set_interface_property $interface_name clockRate $frequency + } + + if {[string compare -nocase $interface(type) "clock"] == 0 && $once_per_clock} { + set once_per_clock 0 + add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|[string tolower $port(atom_signal_name)]" + } + } + } + + # device-specific atom + set atom_name $peripheral(atom_name) + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + set location [locations::get_fpga_location $peripheral_name $atom_name] + + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } + } +} + +# derives the WYS (device family-specific) atom name from the generic one +proc generic_atom_to_wys_atom {device_family atom_name} { + # TODO: base this on a table of data instead of on code + set result "" + if {[check_device_family_equivalence $device_family CYCLONEV]} { + set result "cyclonev_${atom_name}" + } elseif {[check_device_family_equivalence $device_family ARRIAV]} { + set result "arriav_${atom_name}" + } + return $result +} + +# invents an instance name from the peripheral's name +# assumes that the instance name is the same across a peripheral +proc invent_peripheral_instance_name {peripheral_name} { + return "peripheral_[string tolower $peripheral_name]" +} + +# TODO: do width calculation at db load time so we don't do it every elaboration! +# then make it accessible by a mode to width array for every peripheral with fpga periph interface +# TODO: also validate the static data, checking if the mode signals make sense aka only contiguous, 0-indexed mappings +proc calculate_port_width {pin_array_string} { + array set pins $pin_array_string + # TODO: -do we need to be able to support ports that don't start with pins at 0? + # -e.g. pins D0-D7 are indexed 0-7. if want D4-D7, can we do indexes 4-7? + # -for now, no! + set bit_index 0 + while {[info exists pins($bit_index)]} { + incr bit_index + } + return $bit_index +} + +proc pin_to_bank {pin} { + set io_index [string first "IO" $pin] + return [string range $pin 0 [expr {$io_index - 1}]] +} + +proc sort_pins {pins} { + set pin_suffixes [list] + foreach pin $pins { + set io_index [string first "IO" $pin] + set suffix_start [expr {$io_index + 2}] + set length [string length $pin] + set suffix [string range $pin $suffix_start [expr {$length - 1}]] + lappend pin_suffixes $suffix + } + set result [list] + set indices [lsort-indices -increasing -integer $pin_suffixes] + foreach index $indices { + lappend result [lindex $pins $index] + } + return $result +} + +proc set_peripheral_pin_muxing_description {peripheral_name pin_muxing_description mode_description} { + set parameter "[string toupper $peripheral_name]_PinMuxing" + set_display_item_property $parameter DESCRIPTION $pin_muxing_description + + set parameter "[string toupper $peripheral_name]_Mode" + set_display_item_property $parameter DESCRIPTION $mode_description +} + +# Expects same set of keys between both parameters +proc create_pin_muxing_description_table_html {signals_by_option_str pins_by_option_str} { + array set pins_by_option $pins_by_option_str + + set options [list] + foreach {option signals} $signals_by_option_str { + lappend options $option + + set pins $pins_by_option($option) + + foreach signal $signals pin $pins { + set key "${option}.${signal}" + set pins_by_option_and_signal($key) $pin + set signal_set($signal) 1 + } + } + + set sorted_signals [lsort -increasing -ascii [array names signal_set]] + set sorted_options [lsort -increasing -ascii $options] + + set ALIGN_CENTER {align="center"} + + set html "" ;# start of table, first row cell empty for signal column + foreach option $sorted_options { + set html "${html}" + } + set html "${html}" + foreach signal $sorted_signals { + set html "${html}" ;# new row w/ first cell (header) being the signal name + foreach option $sorted_options { + set key "${option}.${signal}" + if {[info exists pins_by_option_and_signal($key)]} { + set pin $pins_by_option_and_signal($key) + } else { + set pin "" + } + set html "${html}" + } + set html "${html}" + } + set html "${html}
${option}
${signal}${pin}
" + return $html +} + +proc create_mode_description_table_html {signals_by_mode_str} { + set modes [list] + + foreach {mode signals} $signals_by_mode_str { + lappend modes $mode + foreach signal $signals { + set key "${mode}.${signal}" + set membership_by_mode_and_signal($key) 1 + set signal_set($signal) 1 + } + } + + set sorted_signals [lsort -increasing -ascii [array names signal_set]] + set sorted_modes [lsort -increasing -ascii $modes] + + set ALIGN_CENTER {align="center"} + + set html "" ;# start of table, first row cell empty for signal column + foreach mode $sorted_modes { + set html "${html}" + } + set html "${html}" + foreach signal $sorted_signals { + set html "${html}" ;# new row w/ first cell (header) being the signal name + + foreach mode $sorted_modes { + set key "${mode}.${signal}" + if {[info exists membership_by_mode_and_signal($key)]} { + set member_marker "X" + } else { + set member_marker "" + } + set html "${html}" + } + set html "${html}" + } + set html "${html}
${mode}
${signal}${member_marker}
" + return $html +} + +proc get_quartus_edition {} { + set code { + set version "" + regexp {([a-zA-Z]+) (Edition|Version)$} $quartus(version) total version + return $version + } + set safe_code [string map {\n ; \t ""} $code] + set package_name "advanced_device" + set result [lindex [run_quartus_tcl_command "${package_name}:${safe_code}"] 0] + return $result +} + +proc is_soc_device {device} { + return [::pin_mux_db::verify_soc_device $device] +} + +proc set_peripheral_pin_muxing_descriptions {peripherals_ref} { + upvar 1 $peripherals_ref peripherals + + foreach peripheral_name [array names peripherals] { + set signals_by_option [list] + set pins_by_option [list] + + funset peripheral + array set peripheral $peripherals($peripheral_name) + funset pin_sets + array set pin_sets $peripheral(pin_sets) + + foreach pin_set_name [array names pin_sets] { + funset pin_set + array set pin_set $pin_sets($pin_set_name) + set signals $pin_set(signals) + lappend signals_by_option $pin_set_name $signals + set pins $pin_set(pins) + lappend pins_by_option $pin_set_name $pins + } + set signals_by_mode $peripheral(signals_by_mode) + + set table_html [create_pin_muxing_description_table_html $signals_by_option $pins_by_option] + set pin_muxing_description "" + + set table_html [create_mode_description_table_html $signals_by_mode] + set mode_description "Signal Membership Per Mode Usage Option:
${table_html}" + set_peripheral_pin_muxing_description $peripheral_name $pin_muxing_description $mode_description + } +} + +# Add pin muxing details to soc_io peripheral/signal data +add_storage_parameter pin_muxing {} +add_storage_parameter pin_muxing_check "" +proc ensure_pin_muxing_data {device_family} { + if {[check_device_family_equivalence $device_family [get_module_property SUPPORTED_DEVICE_FAMILIES]] == 0} { + return + } + + set device [get_device] + + if {![is_soc_device $device]} { + send_message error "Selected device '${device}' is not an SoC device. Please choose a valid SoC device to use the Hard Processor System." + return + } + + set device_configuration "${device_family}+${device}" + + set old_device_configuration [get_parameter_value pin_muxing_check] + if {$old_device_configuration == $device_configuration} { + return + } + + set load_rc [::pin_mux_db::load $device] + if {!$load_rc} { + send_message error "The pin information for the Hard Processor System could not be determined. Please check whether your edition of Quartus Prime supports the selected device." + return + } + locations::load $device + + load_peripherals_pin_muxing_model pin_muxing_peripherals + set_peripheral_pin_muxing_descriptions pin_muxing_peripherals + + set gpio_pins [::pin_mux_db::get_gpio_pins] + set loanio_pins [::pin_mux_db::get_loan_io_pins] + set customer_pin_names [::pin_mux_db::get_customer_pin_names] + set hlgpi_pins [::pin_mux_db::get_hlgpi_pins] + + set pin_muxing [list [array get pin_muxing_peripherals] $gpio_pins $loanio_pins $customer_pin_names $hlgpi_pins] + set_parameter_value pin_muxing $pin_muxing + set_parameter_value pin_muxing_check $device_configuration + + #### update pin_muxing data to use in java GUI #### + set pinmux_peripherals [array get pin_muxing_peripherals] + array set periph_key_value $pinmux_peripherals + + foreach {key value} [array get periph_key_value] { + set_parameter_value JAVA_${key}_DATA "$key \{$value\}" + } +} + +proc get_device {} { + + set device_name [get_parameter_value device_name] + return $device_name +} + +proc construct_hps_parameter_map {} { + set parameters [get_parameters] + foreach parameter $parameters { + set value [get_parameter_value $parameter] + set result($parameter) $value + } + return [array get result] +} + +################################################################################ +# Implements interface of util/pin_mux.tcl +# +namespace eval hps_ip_pin_muxing_model { +################################################################################ + proc get_peripherals_model {} { + set pin_muxing [get_parameter_value pin_muxing] + set peripherals [lindex $pin_muxing 0] + return $peripherals + } + proc get_emac0_fpga_ini {} { + return [is_enabled quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface] + } + proc get_lssis_fpga_ini {} { + return [is_enabled quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces] + } + proc get_all_fpga_ini {} { + return [is_enabled quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces] + } + proc get_peripheral_pin_muxing_selection {peripheral_name} { + set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name] + set selection [get_parameter_value $pin_muxing_param_name] + return $selection + } + proc get_peripheral_mode_selection {peripheral_name} { + set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral_name] + set selection [get_parameter_value $mode_param_name] + return $selection + } + proc get_gpio_pins {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 1] + return $pins + } + proc get_loanio_pins {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 2] + return $pins + } + proc get_customer_pin_names {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 3] + return $pins + } + proc get_hlgpi_pins {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 4] + return $pins + } + proc get_unsupported_peripheral {peripheral_name} { + set device_family [get_parameter_value hps_device_family] + set skip 0 + if {[check_device_family_equivalence $device_family ARRIAV]} { + foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] { + if {[string compare $excluded_peripheral $peripheral_name] == 0} { + set skip 1 + } + } + } + return $skip + } +} + + +## Add documentation links for user guide and/or release notes +add_documentation_link "User Guide" https://www.altera.com/products/soc/overview.html diff --git a/sys/ip/in_split.v b/sys/ip/in_split.v new file mode 100644 index 0000000..e750ff9 --- /dev/null +++ b/sys/ip/in_split.v @@ -0,0 +1,52 @@ +// in_split.v + + +`timescale 1 ps / 1 ps +module in_split ( + input wire clk, // input.clk + input wire ce, // .ce + input wire de, // .de + input wire h_sync, // .h_sync + input wire v_sync, // .v_sync + input wire f, // .f + input wire [23:0] data, // .data + output wire vid_clk, // Output.vid_clk + output reg vid_datavalid, // .vid_datavalid + output reg [1:0] vid_de, // .vid_de + output reg [1:0] vid_f, // .vid_f + output reg [1:0] vid_h_sync, // .vid_h_sync + output reg [1:0] vid_v_sync, // .vid_v_sync + output reg [47:0] vid_data, // .vid_data + output wire vid_locked, // .vid_locked + output wire [7:0] vid_color_encoding, // .vid_color_encoding + output wire [7:0] vid_bit_width, // .vid_bit_width + input wire clipping, // .clipping + input wire overflow, // .overflow + input wire sof, // .sof + input wire sof_locked, // .sof_locked + input wire refclk_div, // .refclk_div + input wire padding // .padding + ); + + assign vid_bit_width = 0; + assign vid_color_encoding = 0; + assign vid_locked = 1; + assign vid_clk = clk; + + always @(posedge clk) begin + reg odd = 0; + + vid_datavalid <= 0; + if(ce) begin + vid_de[odd] <= de; + vid_f[odd] <= f; + vid_h_sync[odd] <= h_sync; + vid_v_sync[odd] <= v_sync; + if(odd) vid_data[47:24] <= data; + else vid_data[23:0] <= data; + + odd <= ~odd; + vid_datavalid <= odd; + end + end +endmodule diff --git a/sys/ip/in_split_hw.tcl b/sys/ip/in_split_hw.tcl new file mode 100644 index 0000000..403555a --- /dev/null +++ b/sys/ip/in_split_hw.tcl @@ -0,0 +1,104 @@ +# TCL File Generated by Component Editor 17.0 +# Thu Jan 25 18:50:29 CST 2018 +# DO NOT MODIFY + + +# +# in_split "Input Splitter" v17.0 +# Sorgelig 2018.01.25.18:50:29 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module in_split +# +set_module_property DESCRIPTION "" +set_module_property NAME in_split +set_module_property VERSION 17.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR Sorgelig +set_module_property DISPLAY_NAME "Input Splitter" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point input +# +add_interface input conduit end +set_interface_property input associatedClock "" +set_interface_property input associatedReset "" +set_interface_property input ENABLED true +set_interface_property input EXPORT_OF "" +set_interface_property input PORT_NAME_MAP "" +set_interface_property input CMSIS_SVD_VARIABLES "" +set_interface_property input SVD_ADDRESS_GROUP "" + +add_interface_port input clk clk Input 1 +add_interface_port input ce ce Input 1 +add_interface_port input de de Input 1 +add_interface_port input h_sync h_sync Input 1 +add_interface_port input v_sync v_sync Input 1 +add_interface_port input f f Input 1 +add_interface_port input data data Input 24 + + +# +# connection point Output +# +add_interface Output conduit end +set_interface_property Output associatedClock "" +set_interface_property Output associatedReset "" +set_interface_property Output ENABLED true +set_interface_property Output EXPORT_OF "" +set_interface_property Output PORT_NAME_MAP "" +set_interface_property Output CMSIS_SVD_VARIABLES "" +set_interface_property Output SVD_ADDRESS_GROUP "" + +add_interface_port Output vid_clk vid_clk Output 1 +add_interface_port Output vid_datavalid vid_datavalid Output 1 +add_interface_port Output vid_de vid_de Output 2 +add_interface_port Output vid_f vid_f Output 2 +add_interface_port Output vid_h_sync vid_h_sync Output 2 +add_interface_port Output vid_v_sync vid_v_sync Output 2 +add_interface_port Output vid_data vid_data Output 48 +add_interface_port Output vid_locked vid_locked Output 1 +add_interface_port Output vid_color_encoding vid_color_encoding Output 8 +add_interface_port Output vid_bit_width vid_bit_width Output 8 +add_interface_port Output clipping clipping Input 1 +add_interface_port Output overflow overflow Input 1 +add_interface_port Output sof sof Input 1 +add_interface_port Output sof_locked sof_locked Input 1 +add_interface_port Output refclk_div refclk_div Input 1 +add_interface_port Output padding padding Input 1 + diff --git a/sys/ip/out_mix.v b/sys/ip/out_mix.v new file mode 100644 index 0000000..e135b1c --- /dev/null +++ b/sys/ip/out_mix.v @@ -0,0 +1,44 @@ +// out_mix.v + +`timescale 1 ps / 1 ps +module out_mix ( + input wire clk, // Output.clk + output reg de, // .de + output reg h_sync, // .h_sync + output reg v_sync, // .v_sync + output reg [23:0] data, // .data + output reg vid_clk, // input.vid_clk + input wire [1:0] vid_datavalid, // .vid_datavalid + input wire [1:0] vid_h_sync, // .vid_h_sync + input wire [1:0] vid_v_sync, // .vid_v_sync + input wire [47:0] vid_data, // .vid_data + input wire underflow, // .underflow + input wire vid_mode_change, // .vid_mode_change + input wire [1:0] vid_std, // .vid_std + input wire [1:0] vid_f, // .vid_f + input wire [1:0] vid_h, // .vid_h + input wire [1:0] vid_v // .vid_v + ); + + reg r_de; + reg r_h_sync; + reg r_v_sync; + reg [23:0] r_data; + + always @(posedge clk) begin + vid_clk <= ~vid_clk; + + if(~vid_clk) begin + {r_de,de} <= vid_datavalid; + {r_h_sync, h_sync} <= vid_h_sync; + {r_v_sync, v_sync} <= vid_v_sync; + {r_data, data} <= vid_data; + end else begin + de <= r_de; + h_sync <= r_h_sync; + v_sync <= r_v_sync; + data <= r_data; + end + end + +endmodule diff --git a/sys/ip/out_mix_hw.tcl b/sys/ip/out_mix_hw.tcl new file mode 100644 index 0000000..b388891 --- /dev/null +++ b/sys/ip/out_mix_hw.tcl @@ -0,0 +1,97 @@ +# TCL File Generated by Component Editor 17.0 +# Thu Jan 25 06:51:26 CST 2018 +# DO NOT MODIFY + + +# +# out_mix "Output Mixer" v1.0 +# Sorgelig 2018.01.25.06:51:26 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module out_mix +# +set_module_property DESCRIPTION "" +set_module_property NAME out_mix +set_module_property VERSION 17.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR Sorgelig +set_module_property DISPLAY_NAME "Output Mixer" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point Output +# +add_interface Output conduit end +set_interface_property Output associatedClock "" +set_interface_property Output associatedReset "" +set_interface_property Output ENABLED true +set_interface_property Output EXPORT_OF "" +set_interface_property Output PORT_NAME_MAP "" +set_interface_property Output CMSIS_SVD_VARIABLES "" +set_interface_property Output SVD_ADDRESS_GROUP "" + +add_interface_port Output clk clk Input 1 +add_interface_port Output de de Output 1 +add_interface_port Output h_sync h_sync Output 1 +add_interface_port Output v_sync v_sync Output 1 +add_interface_port Output data data Output 24 + + +# +# connection point input +# +add_interface input conduit end +set_interface_property input associatedClock "" +set_interface_property input associatedReset "" +set_interface_property input ENABLED true +set_interface_property input EXPORT_OF "" +set_interface_property input PORT_NAME_MAP "" +set_interface_property input CMSIS_SVD_VARIABLES "" +set_interface_property input SVD_ADDRESS_GROUP "" + +add_interface_port input vid_clk vid_clk Output 1 +add_interface_port input vid_datavalid vid_datavalid Input 2 +add_interface_port input vid_h_sync vid_h_sync Input 2 +add_interface_port input vid_v_sync vid_v_sync Input 2 +add_interface_port input vid_data vid_data Input 48 +add_interface_port input underflow underflow Input 1 +add_interface_port input vid_mode_change vid_mode_change Input 1 +add_interface_port input vid_std vid_std Input 2 +add_interface_port input vid_f vid_f Input 2 +add_interface_port input vid_h vid_h Input 2 +add_interface_port input vid_v vid_v Input 2 + diff --git a/sys/ip/reset_source.v b/sys/ip/reset_source.v new file mode 100644 index 0000000..1b81394 --- /dev/null +++ b/sys/ip/reset_source.v @@ -0,0 +1,50 @@ +// reset_source.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module reset_source +( + input wire clk, // clock.clk + input wire reset_hps, // reset_hps.reset + output wire reset_sys, // reset_sys.reset + output wire reset_cold, // reset_cold.reset + input wire cold_req, // reset_ctl.cold_req + output wire reset, // .reset + input wire reset_req, // .reset_req + input wire reset_vip, // .reset_vip + input wire warm_req, // .warm_req + output wire reset_warm // reset_warm.reset +); + +assign reset_cold = cold_req; +assign reset_warm = warm_req; + +wire reset_m = sys_reset | reset_hps | reset_req; +assign reset = reset_m; +assign reset_sys = reset_m | reset_vip; + +reg sys_reset = 1; +always @(posedge clk) begin + integer timeout = 0; + reg reset_lock = 0; + + reset_lock <= reset_lock | cold_req; + + if(timeout < 2000000) begin + sys_reset <= 1; + timeout <= timeout + 1; + reset_lock <= 0; + end + else begin + sys_reset <= reset_lock; + end +end + +endmodule diff --git a/sys/ip/reset_source_hw.tcl b/sys/ip/reset_source_hw.tcl new file mode 100644 index 0000000..cba39f7 --- /dev/null +++ b/sys/ip/reset_source_hw.tcl @@ -0,0 +1,152 @@ +# TCL File Generated by Component Editor 17.0 +# Tue Feb 20 07:55:55 CST 2018 +# DO NOT MODIFY + + +# +# reset_source "reset_source" v17.0 +# Sorgelig 2018.02.20.07:55:55 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module reset_source +# +set_module_property DESCRIPTION "" +set_module_property NAME reset_source +set_module_property VERSION 17.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR Sorgelig +set_module_property DISPLAY_NAME reset_source +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset_hps +# +add_interface reset_hps reset end +set_interface_property reset_hps associatedClock "" +set_interface_property reset_hps synchronousEdges NONE +set_interface_property reset_hps ENABLED true +set_interface_property reset_hps EXPORT_OF "" +set_interface_property reset_hps PORT_NAME_MAP "" +set_interface_property reset_hps CMSIS_SVD_VARIABLES "" +set_interface_property reset_hps SVD_ADDRESS_GROUP "" + +add_interface_port reset_hps reset_hps reset Input 1 + + +# +# connection point reset_sys +# +add_interface reset_sys reset start +set_interface_property reset_sys associatedClock "" +set_interface_property reset_sys associatedDirectReset "" +set_interface_property reset_sys associatedResetSinks "" +set_interface_property reset_sys synchronousEdges NONE +set_interface_property reset_sys ENABLED true +set_interface_property reset_sys EXPORT_OF "" +set_interface_property reset_sys PORT_NAME_MAP "" +set_interface_property reset_sys CMSIS_SVD_VARIABLES "" +set_interface_property reset_sys SVD_ADDRESS_GROUP "" + +add_interface_port reset_sys reset_sys reset Output 1 + + +# +# connection point reset_ctl +# +add_interface reset_ctl conduit end +set_interface_property reset_ctl associatedClock "" +set_interface_property reset_ctl associatedReset "" +set_interface_property reset_ctl ENABLED true +set_interface_property reset_ctl EXPORT_OF "" +set_interface_property reset_ctl PORT_NAME_MAP "" +set_interface_property reset_ctl CMSIS_SVD_VARIABLES "" +set_interface_property reset_ctl SVD_ADDRESS_GROUP "" + +add_interface_port reset_ctl cold_req cold_req Input 1 +add_interface_port reset_ctl reset reset Output 1 +add_interface_port reset_ctl reset_req reset_req Input 1 +add_interface_port reset_ctl warm_req warm_req Input 1 +add_interface_port reset_ctl reset_vip reset_vip Input 1 + + +# +# connection point reset_warm +# +add_interface reset_warm reset start +set_interface_property reset_warm associatedClock "" +set_interface_property reset_warm associatedDirectReset "" +set_interface_property reset_warm associatedResetSinks "" +set_interface_property reset_warm synchronousEdges NONE +set_interface_property reset_warm ENABLED true +set_interface_property reset_warm EXPORT_OF "" +set_interface_property reset_warm PORT_NAME_MAP "" +set_interface_property reset_warm CMSIS_SVD_VARIABLES "" +set_interface_property reset_warm SVD_ADDRESS_GROUP "" + +add_interface_port reset_warm reset_warm reset Output 1 + + +# +# connection point reset_cold +# +add_interface reset_cold reset start +set_interface_property reset_cold associatedClock "" +set_interface_property reset_cold associatedDirectReset "" +set_interface_property reset_cold associatedResetSinks "" +set_interface_property reset_cold synchronousEdges NONE +set_interface_property reset_cold ENABLED true +set_interface_property reset_cold EXPORT_OF "" +set_interface_property reset_cold PORT_NAME_MAP "" +set_interface_property reset_cold CMSIS_SVD_VARIABLES "" +set_interface_property reset_cold SVD_ADDRESS_GROUP "" + +add_interface_port reset_cold reset_cold reset Output 1 + diff --git a/sys/lpf48k.sv b/sys/lpf48k.sv new file mode 100644 index 0000000..2a32981 --- /dev/null +++ b/sys/lpf48k.sv @@ -0,0 +1,100 @@ +// low pass filter +// Revision 1.00 +// +// Copyright (c) 2008 Takayuki Hara. +// All rights reserved. +// +// Redistribution and use of this source code or any derivative works, are +// permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// 3. Redistributions may not be sold, nor may they be used in a commercial +// product or activity without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// LPF (cut off 48kHz at 3.58MHz) + +module lpf48k #(parameter MSB = 15) +( + input RESET, + input CLK, + input CE, + input ENABLE, + + input [MSB:0] IDATA, + output [MSB:0] ODATA +); + +wire [7:0] LPF_TAP_DATA[0:71] = +'{ + 8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09, + 8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B, + 8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D, + 8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, + 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, + 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D, + 8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B, + 8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09, + 8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51 +}; + +reg [7:0] FF_ADDR = 0; +reg [MSB+10:0] FF_INTEG = 0; +wire [MSB+8:0] W_DATA; +wire W_ADDR_END; + +assign W_ADDR_END = ((FF_ADDR == 71)); + +reg [MSB:0] OUT; + +assign ODATA = ENABLE ? OUT : IDATA; + +always @(posedge RESET or posedge CLK) begin + if (RESET) FF_ADDR <= 0; + else + begin + if (CE) begin + if (W_ADDR_END) FF_ADDR <= 0; + else FF_ADDR <= FF_ADDR + 1'd1; + end + end +end + +assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA; + +always @(posedge RESET or posedge CLK) begin + if (RESET) FF_INTEG <= 0; + else + begin + if (CE) begin + if (W_ADDR_END) FF_INTEG <= 0; + else FF_INTEG <= FF_INTEG + W_DATA; + end + end +end + +always @(posedge RESET or posedge CLK) begin + if (RESET) OUT <= 0; + else + begin + if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10]; + end +end + +endmodule diff --git a/sys/osd.v b/sys/osd.v new file mode 100644 index 0000000..f6e8915 --- /dev/null +++ b/sys/osd.v @@ -0,0 +1,199 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd +( + input clk_sys, + + input io_osd, + input io_strobe, + input [15:0] io_din, + + input clk_video, + input [23:0] din, + output [23:0] dout, + input de_in, + output reg de_out +); + +parameter OSD_COLOR = 3'd4; +parameter OSD_X_OFFSET = 12'd0; +parameter OSD_Y_OFFSET = 12'd0; + +localparam OSD_WIDTH = 12'd256; +localparam OSD_HEIGHT = 12'd64; + +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096]; + +reg highres = 0; +reg info = 0; +reg [8:0] infoh; +reg [8:0] infow; +reg [11:0] infox; +reg [21:0] infoy; + +always@(posedge clk_sys) begin + reg [11:0] bcnt; + reg [7:0] cmd; + reg has_cmd; + reg old_strobe; + + old_strobe <= io_strobe; + + if(~io_osd) begin + bcnt <= 0; + has_cmd <= 0; + cmd <= 0; + if(cmd[7:4] == 4) osd_enable <= cmd[0]; + end else begin + if(~old_strobe & io_strobe) begin + if(!has_cmd) begin + has_cmd <= 1; + cmd <= io_din[7:0]; + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(io_din[7:4] == 4) begin + if(!io_din[0]) highres <= 0; + info <= io_din[2]; + bcnt <= 0; + end + // command 0x20: OSDCMDWRITE + if(io_din[7:4] == 2) begin + if(io_din[3]) highres <= 1; + bcnt <= {io_din[3:0], 8'h00}; + end + end else begin + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(cmd[7:4] == 4) begin + if(bcnt == 0) infox <= io_din[11:0]; + if(bcnt == 1) infoy <= io_din[11:0]; + if(bcnt == 2) infow <= {io_din[5:0], 3'b000}; + if(bcnt == 3) infoh <= {io_din[5:0], 3'b000}; + end + + // command 0x20: OSDCMDWRITE + if(cmd[7:4] == 2) osd_buffer[bcnt] <= io_din[7:0]; + + bcnt <= bcnt + 1'd1; + end + end + end +end + +reg ce_pix; +always @(negedge clk_video) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg deD; + + cnt <= cnt + 1; + deD <= de_in; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(~deD && de_in) cnt <= 0; + + if(deD && ~de_in) begin + pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0; + pixcnt <= 0; + end +end + +reg [23:0] h_cnt; +reg [21:0] v_cnt; +reg [21:0] dsp_width; +reg [21:0] dsp_height; +reg [7:0] osd_byte; +reg [21:0] osd_vcnt; +reg [21:0] fheight; + +reg [21:0] finfoy; +wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT< {dsp_width, 2'b00}) begin + v_cnt <= 0; + dsp_height <= v_cnt; + + if(osd_enable) begin + if(v_cnt<320) begin + multiscan <= 0; + fheight <= hrheight; + finfoy <= infoy; + end + else if(v_cnt<640) begin + multiscan <= 1; + fheight <= hrheight << 1; + finfoy <= infoy << 1; + end + else if(v_cnt<960) begin + multiscan <= 2; + fheight <= hrheight + (hrheight<<1); + finfoy <= infoy + (infoy << 1); + end + else begin + multiscan <= 3; + fheight <= hrheight << 2; + finfoy <= infoy << 2; + end + end + else begin + fheight <= 0; + end + end + h_cnt <= 0; + + osd_div <= osd_div + 1'd1; + if(osd_div == multiscan) begin + osd_div <= 0; + osd_vcnt <= osd_vcnt + 1'd1; + end + if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0; + end + + osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}]; + end +end + +// area in which OSD is being displayed +wire [21:0] h_osd_start = info ? infox : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET; +wire [21:0] h_osd_end = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH); +wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET; +wire [21:0] v_osd_end = v_osd_start + fheight; + +wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1; + +wire osd_de = osd_enable && fheight && + (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) && + (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +wire osd_pixel = osd_byte[osd_vcnt[2:0]]; + +reg [23:0] rdout; +assign dout = rdout; + +always @(posedge clk_video) begin + rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]}, + {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]}, + {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; + de_out <= de_in; +end + +endmodule diff --git a/sys/pattern_vg.v b/sys/pattern_vg.v new file mode 100644 index 0000000..1392e1b --- /dev/null +++ b/sys/pattern_vg.v @@ -0,0 +1,120 @@ +module pattern_vg +#( + parameter B=8, // number of bits per channel + X_BITS=13, + Y_BITS=13, + FRACTIONAL_BITS = 12 +) + +( + input reset, clk_in, + input wire [X_BITS-1:0] x, + input wire [Y_BITS-1:0] y, + input wire vn_in, hn_in, dn_in, + input wire [B-1:0] r_in, g_in, b_in, + output reg vn_out, hn_out, den_out, + output reg [B-1:0] r_out, g_out, b_out, + input wire [X_BITS-1:0] total_active_pix, + input wire [Y_BITS-1:0] total_active_lines, + input wire [7:0] pattern, + input wire [B+FRACTIONAL_BITS-1:0] ramp_step +); + +reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values + + +//wire bar_0 = y<90; +wire bar_1 = y>=90 & y<180; +wire bar_2 = y>=180 & y<270; +wire bar_3 = y>=270 & y<360; +wire bar_4 = y>=360 & y<450; +wire bar_5 = y>=450 & y<540; +wire bar_6 = y>=540 & y<630; +wire bar_7 = y>=630 & y<720; + + +wire red_enable = bar_1 | bar_3 | bar_5 | bar_7; +wire green_enable = bar_2 | bar_3 | bar_6 | bar_7; +wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7; + +always @(posedge clk_in) + begin + vn_out <= vn_in; + hn_out <= hn_in; + den_out <= dn_in; + if (reset) + ramp_values <= 0; + else if (pattern == 8'b0) // no pattern + begin + r_out <= r_in; + g_out <= g_in; + b_out <= b_in; + end + else if (pattern == 8'b1) // border + begin + if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1))) + begin + r_out <= 8'hFF; + g_out <= 8'hFF; + b_out <= 8'hFF; + end + else // Double-border (OzOnE)... + if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20))) + begin + r_out <= 8'hD0; + g_out <= 8'hB0; + b_out <= 8'hB0; + end + else + begin + r_out <= r_in; + g_out <= g_in; + b_out <= b_in; + end + end + else if (pattern == 8'd2) // moireX + begin + if ((dn_in) && x[0] == 1'b1) + begin + r_out <= 8'hFF; + g_out <= 8'hFF; + b_out <= 8'hFF; + end + else + begin + r_out <= 8'b0; + g_out <= 8'b0; + b_out <= 8'b0; + end + end + else if (pattern == 8'd3) // moireY + begin + if ((dn_in) && y[0] == 1'b1) + begin + r_out <= 8'hFF; + g_out <= 8'hFF; + b_out <= 8'hFF; + end + else + begin + r_out <= 8'b0; + g_out <= 8'b0; + b_out <= 8'b0; + end + end + else if (pattern == 8'd4) // Simple RAMP + begin + r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; + g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; + b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; + + if ((x == total_active_pix - 1) && (dn_in)) + ramp_values <= 0; + else if ((x == 0) && (dn_in)) + ramp_values <= ramp_step; + else if (dn_in) + ramp_values <= ramp_values + ramp_step; + end +end + +endmodule diff --git a/sys/scandoubler.v b/sys/scandoubler.v new file mode 100644 index 0000000..2276c35 --- /dev/null +++ b/sys/scandoubler.v @@ -0,0 +1,188 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + output ce_pix_out, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input hb_in, + input vb_in, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output hb_out, + output vb_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 3 : 7; + +assign vs_out = vso[3]; +assign ce_pix_out = ce_x4; + +//Compensate picture shift after HQ2x +assign vb_out = vbo[2]; +assign hb_out = &hbo[5:4]; + +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + req_line_reset <= 0; + + if(hb_in) req_line_reset <= 1; + end +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4), + .inputpixel({b_d,g_d,r_d}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h; +reg [1:0] sd_line; +reg [2:0] vbo; +reg [5:0] hbo; + +reg [DWIDTH:0] r_d; +reg [DWIDTH:0] g_d; +reg [DWIDTH:0] b_d; + +reg [3:0] vso; + +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + reg [11:0] hde_start, hde_end; + + reg hs, hs2, vs, hb; + + if(ce_x1) begin + hs <= hs_in; + hb <= hb_in; + + r_d <= r_in; + g_d <= g_in; + b_d <= b_in; + + if(hb && !hb_in) begin + hde_start <= {hcnt,1'b0}; + vbo <= {vbo[1:0], vb_in}; + end + if(!hb && hb_in) hde_end <= {hcnt,1'b0}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + vso <= (vso<<1) | vs_in; + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + hbo[5:1] <= hbo[4:0]; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + if(~&hbo) sd_h <= sd_h + 1'd1; + + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + + //prepare to read in advance + if(sd_hcnt == (hde_start-2)) begin + sd_h <= 0; + sd_line <= sd_line + 1'd1; + end + + if(sd_hcnt == hde_start) hbo[0] <= 0; + if(sd_hcnt == hde_end) hbo[0] <= 1; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + end +end + +endmodule diff --git a/sys/sigma_delta_dac.v b/sys/sigma_delta_dac.v new file mode 100644 index 0000000..d0d6be0 --- /dev/null +++ b/sys/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= INV; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= SigmaLatch[MSBI+2] ^ INV; + end +end + +endmodule diff --git a/sys/spdif.v b/sys/spdif.v new file mode 100644 index 0000000..671dcb2 --- /dev/null +++ b/sys/spdif.v @@ -0,0 +1,426 @@ +//----------------------------------------------------------------- +// SPDIF Transmitter +// V0.1 +// Ultra-Embedded.com +// Copyright 2012 +// +// Email: admin@ultra-embedded.com +// +// License: GPL +// If you would like a version with a more permissive license for +// use in closed source commercial applications please contact me +// for details. +//----------------------------------------------------------------- +// +// This file is open source HDL; you can redistribute it and/or +// modify it under the terms of the GNU General Public License as +// published by the Free Software Foundation; either version 2 of +// the License, or (at your option) any later version. +// +// This file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public +// License along with this file; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +// USA +//----------------------------------------------------------------- +// altera message_off 10762 +// altera message_off 10240 + +module spdif + +//----------------------------------------------------------------- +// Params +//----------------------------------------------------------------- +#( + parameter CLK_RATE = 50000000, + parameter AUDIO_RATE = 48000, + + // Generated params + parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128), + parameter ERROR_BASE = 10000, + parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE) +) + +//----------------------------------------------------------------- +// Ports +//----------------------------------------------------------------- +( + input clk_i, + input rst_i, + input half_rate, + + // Output + output spdif_o, + + // Audio interface (16-bit x 2 = RL) + input [15:0] audio_r, + input [15:0] audio_l, + output sample_req_o +); + +reg lpf_ce; +always @(negedge clk_i) begin + reg [3:0] div; + + div <= div + 1'd1; + if(div == 13) div <= 0; + + lpf_ce <= !div; +end + +wire [15:0] al, ar; + +lpf48k #(15) lpf_l +( + .RESET(rst_i), + .CLK(clk_i), + .CE(lpf_ce), + .ENABLE(1), + + .IDATA(audio_l), + .ODATA(al) +); + +lpf48k #(15) lpf_r +( + .RESET(rst_i), + .CLK(clk_i), + .CE(lpf_ce), + .ENABLE(1), + + .IDATA(audio_r), + .ODATA(ar) +); + +reg bit_clk_q; + +// Clock pulse generator +always @ (posedge rst_i or posedge clk_i) begin + reg [31:0] count_q; + reg [31:0] error_q; + reg ce; + + if (rst_i) begin + count_q <= 0; + error_q <= 0; + bit_clk_q <= 1; + ce <= 0; + end + else + begin + if(count_q == WHOLE_CYCLES-1) begin + if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin + error_q <= error_q + ERRORS_PER_BIT[31:0]; + count_q <= 0; + end else begin + error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE; + count_q <= count_q + 1; + end + end else if(count_q == WHOLE_CYCLES) begin + count_q <= 0; + end else begin + count_q <= count_q + 1; + end + + bit_clk_q <= 0; + if(!count_q) begin + ce <= ~ce; + if(~half_rate || ce) bit_clk_q <= 1; + end + end +end + +//----------------------------------------------------------------- +// Core SPDIF +//----------------------------------------------------------------- + +wire [31:0] sample_i = {ar, al}; + +spdif_core +u_core +( + .clk_i(clk_i), + .rst_i(rst_i), + + .bit_out_en_i(bit_clk_q), + + .spdif_o(spdif_o), + + .sample_i(sample_i), + .sample_req_o(sample_req_o) +); + +endmodule + +module spdif_core +( + input clk_i, + input rst_i, + + // SPDIF bit output enable + // Single cycle pulse synchronous to clk_i which drives + // the output bit rate. + // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz + // For 48KHz, 48000×32×2×2 = 6,144,000Hz + input bit_out_en_i, + + // Output + output spdif_o, + + // Audio interface (16-bit x 2 = RL) + input [31:0] sample_i, + output reg sample_req_o +); + +//----------------------------------------------------------------- +// Registers +//----------------------------------------------------------------- +reg [15:0] audio_sample_q; +reg [8:0] subframe_count_q; + +reg load_subframe_q; +reg [7:0] preamble_q; +wire [31:0] subframe_w; + +reg [5:0] bit_count_q; +reg bit_toggle_q; + +reg spdif_out_q; + +reg [5:0] parity_count_q; + +//----------------------------------------------------------------- +// Subframe Counter +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i ) +begin + if (rst_i == 1'b1) + subframe_count_q <= 9'd0; + else if (load_subframe_q) + begin + // 192 frames (384 subframes) in an audio block + if (subframe_count_q == 9'd383) + subframe_count_q <= 9'd0; + else + subframe_count_q <= subframe_count_q + 9'd1; + end +end + +//----------------------------------------------------------------- +// Sample capture +//----------------------------------------------------------------- +reg [15:0] sample_buf_q; + +always @ (posedge rst_i or posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + audio_sample_q <= 16'h0000; + sample_buf_q <= 16'h0000; + sample_req_o <= 1'b0; + end + else if (load_subframe_q) + begin + // Start of frame (first subframe)? + if (subframe_count_q[0] == 1'b0) + begin + // Use left sample + audio_sample_q <= sample_i[15:0]; + + // Store right sample + sample_buf_q <= sample_i[31:16]; + + // Request next sample + sample_req_o <= 1'b1; + end + else + begin + // Use right sample + audio_sample_q <= sample_buf_q; + + sample_req_o <= 1'b0; + end + end + else + sample_req_o <= 1'b0; +end + +// Timeslots 3 - 0 = Preamble +assign subframe_w[3:0] = 4'b0000; + +// Timeslots 7 - 4 = 24-bit audio LSB +assign subframe_w[7:4] = 4'b0000; + +// Timeslots 11 - 8 = 20-bit audio LSB +assign subframe_w[11:8] = 4'b0000; + +// Timeslots 27 - 12 = 16-bit audio +assign subframe_w[27:12] = audio_sample_q; + +// Timeslots 28 = Validity +assign subframe_w[28] = 1'b0; // Valid + +// Timeslots 29 = User bit +assign subframe_w[29] = 1'b0; + +// Timeslots 30 = Channel status bit +assign subframe_w[30] = 1'b0; + +// Timeslots 31 = Even Parity bit (31:4) +assign subframe_w[31] = 1'b0; + +//----------------------------------------------------------------- +// Preamble +//----------------------------------------------------------------- +localparam PREAMBLE_Z = 8'b00010111; +localparam PREAMBLE_Y = 8'b00100111; +localparam PREAMBLE_X = 8'b01000111; + +reg [7:0] preamble_r; + +always @ * +begin + // Start of audio block? + // Z(B) - Left channel + if (subframe_count_q == 9'd0) + preamble_r = PREAMBLE_Z; // Z(B) + // Right Channel? + else if (subframe_count_q[0] == 1'b1) + preamble_r = PREAMBLE_Y; // Y(W) + // Left Channel (but not start of block)? + else + preamble_r = PREAMBLE_X; // X(M) +end + +always @ (posedge rst_i or posedge clk_i ) +if (rst_i == 1'b1) + preamble_q <= 8'h00; +else if (load_subframe_q) + preamble_q <= preamble_r; + +//----------------------------------------------------------------- +// Parity Counter +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + parity_count_q <= 6'd0; + end + // Time to output a bit? + else if (bit_out_en_i) + begin + // Preamble bits? + if (bit_count_q < 6'd8) + begin + parity_count_q <= 6'd0; + end + // Normal timeslots + else if (bit_count_q < 6'd62) + begin + // On first pass through this timeslot, count number of high bits + if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1) + parity_count_q <= parity_count_q + 6'd1; + end + end +end + +//----------------------------------------------------------------- +// Bit Counter +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i) +begin + if (rst_i == 1'b1) + begin + bit_count_q <= 6'b0; + load_subframe_q <= 1'b1; + end + // Time to output a bit? + else if (bit_out_en_i) + begin + // 32 timeslots (x2 for double frequency) + if (bit_count_q == 6'd63) + begin + bit_count_q <= 6'd0; + load_subframe_q <= 1'b1; + end + else + begin + bit_count_q <= bit_count_q + 6'd1; + load_subframe_q <= 1'b0; + end + end + else + load_subframe_q <= 1'b0; +end + +//----------------------------------------------------------------- +// Bit half toggle +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i) +if (rst_i == 1'b1) + bit_toggle_q <= 1'b0; +// Time to output a bit? +else if (bit_out_en_i) + bit_toggle_q <= ~bit_toggle_q; + +//----------------------------------------------------------------- +// Output bit (BMC encoded) +//----------------------------------------------------------------- +reg bit_r; + +always @ * +begin + bit_r = spdif_out_q; + + // Time to output a bit? + if (bit_out_en_i) + begin + // Preamble bits? + if (bit_count_q < 6'd8) + begin + bit_r = preamble_q[bit_count_q[2:0]]; + end + // Normal timeslots + else if (bit_count_q < 6'd62) + begin + if (subframe_w[bit_count_q / 2] == 1'b0) + begin + if (bit_toggle_q == 1'b0) + bit_r = ~spdif_out_q; + else + bit_r = spdif_out_q; + end + else + bit_r = ~spdif_out_q; + end + // Parity timeslot + else + begin + // Even number of high bits, make odd + if (parity_count_q[0] == 1'b0) + begin + if (bit_toggle_q == 1'b0) + bit_r = ~spdif_out_q; + else + bit_r = spdif_out_q; + end + else + bit_r = ~spdif_out_q; + end + end +end + +always @ (posedge rst_i or posedge clk_i ) +if (rst_i == 1'b1) + spdif_out_q <= 1'b0; +else + spdif_out_q <= bit_r; + +assign spdif_o = spdif_out_q; + +endmodule diff --git a/sys/sync_vg.v b/sys/sync_vg.v new file mode 100644 index 0000000..caaf681 --- /dev/null +++ b/sys/sync_vg.v @@ -0,0 +1,78 @@ +module sync_vg +#( + parameter X_BITS=12, Y_BITS=12 +) +( + input wire clk, + input wire reset, + + input wire [Y_BITS-1:0] v_total, + input wire [Y_BITS-1:0] v_fp, + input wire [Y_BITS-1:0] v_bp, + input wire [Y_BITS-1:0] v_sync, + input wire [X_BITS-1:0] h_total, + input wire [X_BITS-1:0] h_fp, + input wire [X_BITS-1:0] h_bp, + input wire [X_BITS-1:0] h_sync, + input wire [X_BITS-1:0] hv_offset, + + output reg vs_out, + output reg hs_out, + output reg hde_out, + output reg vde_out, + output reg [Y_BITS-1:0] v_count_out, + output reg [X_BITS-1:0] h_count_out, + output reg [X_BITS-1:0] x_out, + output reg [Y_BITS-1:0] y_out +); + +reg [X_BITS-1:0] h_count; +reg [Y_BITS-1:0] v_count; + +/* horizontal counter */ +always @(posedge clk) + if (reset) + h_count <= 0; + else + if (h_count < h_total - 1) + h_count <= h_count + 1'd1; + else + h_count <= 0; + +/* vertical counter */ +always @(posedge clk) + if (reset) + v_count <= 0; + else + if (h_count == h_total - 1) + begin + if (v_count == v_total - 1) + v_count <= 0; + else + v_count <= v_count + 1'd1; + end + +always @(posedge clk) + if (reset) + { vs_out, hs_out, hde_out, vde_out } <= 0; + else begin + hs_out <= ((h_count < h_sync)); + + hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1); + vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1); + + if ((v_count == 0) && (h_count == hv_offset)) + vs_out <= 1'b1; + else if ((v_count == v_sync) && (h_count == hv_offset)) + vs_out <= 1'b0; + + /* H_COUNT_OUT and V_COUNT_OUT */ + h_count_out <= h_count; + v_count_out <= v_count; + + /* X and Y coords for a backend pattern generator */ + x_out <= h_count - (h_sync + h_bp); + y_out <= v_count - (v_sync + v_bp); + end + +endmodule diff --git a/sys/sys.qip b/sys/sys.qip new file mode 100644 index 0000000..0f6e57e --- /dev/null +++ b/sys/sys.qip @@ -0,0 +1,24 @@ +set_global_assignment -name VERILOG_FILE sys/sys_top.v +set_global_assignment -name SDC_FILE sys/sys_top.sdc +#set_global_assignment -name QIP_FILE sys/pll.qip +#set_global_assignment -name QIP_FILE sys/pll_hdmi.qip +#set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip +set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv +set_global_assignment -name VERILOG_FILE sys/scandoubler.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/video_cleaner.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv +set_global_assignment -name VERILOG_FILE sys/osd.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv +set_global_assignment -name VERILOG_FILE sys/sync_vg.v +set_global_assignment -name VERILOG_FILE sys/pattern_vg.v +set_global_assignment -name VERILOG_FILE sys/i2c.v +set_global_assignment -name VERILOG_FILE sys/i2s.v +set_global_assignment -name VERILOG_FILE sys/spdif.v +set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv +set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv +set_global_assignment -name VERILOG_FILE sys/hps_io.v diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc new file mode 100644 index 0000000..f8f6de6 --- /dev/null +++ b/sys/sys_top.sdc @@ -0,0 +1,53 @@ +# Specify root clocks +create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] +create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] + +derive_pll_clocks + +# Specify PLL-generated clock(s) +#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ +# -name SDRAM_CLK [get_ports {SDRAM_CLK}] + +#create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ +# -name HDMI_CLK [get_ports HDMI_TX_CLK] + +#create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ +# -name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}] + + +derive_clock_uncertainty + + +# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) +#set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] +#set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] + +#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ +# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ +# -setup 2 + +#set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +#set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +# Decouple different clock groups (to simplify routing) +# -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \ +# -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \ +set_clock_groups -asynchronous \ + -group [get_clocks { *|h2f_user0_clk}] \ + -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}] + +#set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] +#set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] + +# Put constraints on input ports +set_false_path -from [get_ports {KEY*}] -to * +set_false_path -from [get_ports {BTN_*}] -to * + +# Put constraints on output ports +set_false_path -from * -to [get_ports {LED_*}] +set_false_path -from * -to [get_ports {VGA_*}] +set_false_path -from * -to [get_ports {AUDIO_SPDIF}] +set_false_path -from * -to [get_ports {AUDIO_L}] +set_false_path -from * -to [get_ports {AUDIO_R}] diff --git a/sys/sys_top.v b/sys/sys_top.v new file mode 100644 index 0000000..a1d9e05 --- /dev/null +++ b/sys/sys_top.v @@ -0,0 +1,998 @@ +//============================================================================ +// +// MiSTer hardware abstraction module +// (c)2017,2018 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +module sys_top +( + /////////// CLOCK ////////// + input FPGA_CLK1_50, + input FPGA_CLK2_50, + input FPGA_CLK3_50, + + //////////// VGA /////////// + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive) + output VGA_VS, + input VGA_EN, // active low + + /////////// AUDIO ////////// + output AUDIO_L, + output AUDIO_R, + output AUDIO_SPDIF, + + //////////// HDMI ////////// +`ifndef LITE + output HDMI_I2C_SCL, + inout HDMI_I2C_SDA, + + output HDMI_MCLK, + output HDMI_SCLK, + output HDMI_LRCLK, + output HDMI_I2S, + + output HDMI_TX_CLK, + output HDMI_TX_DE, + output [23:0] HDMI_TX_D, + output HDMI_TX_HS, + output HDMI_TX_VS, + + input HDMI_TX_INT, +`endif + + //////////// SDR /////////// +`ifndef LITE + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE, +`endif + + //////////// I/O /////////// + output LED_USER, + output LED_HDD, + output LED_POWER, + input BTN_USER, + input BTN_OSD, + input BTN_RESET, + + //////////// SDIO /////////// + //inout [3:0] SDIO_DAT, + //inout SDIO_CMD, + //output SDIO_CLK, + //input SDIO_CD, + + ////////// MB KEY /////////// + input [1:0] KEY, + + ////////// MB SWITCH //////// + input [3:0] SW, + + ////////// MB LED /////////// + output [7:0] LED +); + + +//assign SDIO_DAT[2:1] = 2'bZZ; + + +////////////////////////// LEDs /////////////////////////////////////// + +reg [7:0] led_overtake = 0; +reg [7:0] led_state = 0; + +wire led_p = led_power[1] ? ~led_power[0] : 1'b0; +wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); +wire led_u = ~led_user; +wire [7:0] led_mb; + +assign LED = led_mb; +assign LED_POWER = led_p ? 1'bZ : 1'b0; +assign LED_HDD = led_d ? 1'bZ : 1'b0; +assign LED_USER = led_u ? 1'bZ : 1'b0; + +//LEDs on main board +//assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); + + +////////////////////////// Buttons /////////////////////////////////// +reg btn_user, btn_osd; +always @(posedge FPGA_CLK2_50) begin + integer div; + reg [7:0] deb_user; + reg [7:0] deb_osd; + + div <= div + 1'b1; + if(div > 100000) div <= 0; + + if(!div) begin + deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])}; + if(&deb_user) btn_user <= 1; + if(!deb_user) btn_user <= 0; + + deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])}; + if(&deb_osd) btn_osd <= 1; + if(!deb_osd) btn_osd <= 0; + end +end + +reg btn_reset = 1; +always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET; + + +///////////////////////// HPS I/O ///////////////////////////////////// + +// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) +// used to avoid lockups while JTAG loading +wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout}; +wire [31:0] gp_out; + +wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future. +wire io_wait; +wire io_wide; +wire [15:0] io_dout; +wire [15:0] io_din = gp_outr[15:0]; +wire io_clk = gp_outr[17]; +wire io_fpga = gp_outr[18]; +wire io_osd = gp_outr[19]; +wire io_uio = gp_outr[20]; +//wire io_sdd = gp_outr[21]; // used only in ST core + +reg io_ack; +reg rack; +wire io_strobe = ~rack & io_clk; + +always @(posedge clk_sys) begin + if(~io_wait | io_strobe) begin + rack <= io_clk; + io_ack <= rack; + end +end + +reg [31:0] gp_outr; +always @(posedge clk_sys) begin + reg [31:0] gp_outd; + gp_outr <= gp_outd; + gp_outd <= gp_out; +end + +wire [7:0] core_type = 'hA7; // A7 - Sharp MZ series core. + +// HPS will not communicate to core if magic is different +wire [31:0] core_magic = {24'h5CA623, core_type}; + +cyclonev_hps_interface_mpu_general_purpose h2f_gp +( + .gp_in({~gp_out[31] ? core_magic : gp_in}), + .gp_out(gp_out) +); + + +reg [15:0] cfg; + +reg cfg_got = 0; +reg cfg_set = 0; +//wire [2:0] hdmi_res = cfg[10:8]; +wire dvi_mode = cfg[7]; +wire audio_96k = cfg[6]; +wire ypbpr_en = cfg[5]; +wire csync = cfg[3]; + +wire vga_scaler= cfg[2]; + +reg cfg_custom_t = 0; +reg [5:0] cfg_custom_p1; +reg [31:0] cfg_custom_p2; + +reg [4:0] vol_att = 0; + +reg vip_newcfg = 0; +always@(posedge clk_sys) begin + reg [7:0] cmd; + reg has_cmd; + reg old_strobe; + reg [7:0] cnt = 0; + + old_strobe <= io_strobe; + + if(~io_uio) has_cmd <= 0; + else + if(~old_strobe & io_strobe) begin + if(!has_cmd) begin + has_cmd <= 1; + cmd <= io_din[7:0]; + cnt <= 0; + end + else begin + if(cmd == 1) begin + cfg <= io_din; + cfg_set <= 1; + end + if(cmd == 'h20) begin + cfg_set <= 0; + cnt <= cnt + 1'd1; + if(cnt<8) begin + if(!cnt) vip_newcfg <= ~cfg_ready; + case(cnt) + 0: if(WIDTH != io_din[11:0]) begin WIDTH <= io_din[11:0]; vip_newcfg <= 1; end + 1: if(HFP != io_din[11:0]) begin HFP <= io_din[11:0]; vip_newcfg <= 1; end + 2: if(HS != io_din[11:0]) begin HS <= io_din[11:0]; vip_newcfg <= 1; end + 3: if(HBP != io_din[11:0]) begin HBP <= io_din[11:0]; vip_newcfg <= 1; end + 4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; vip_newcfg <= 1; end + 5: if(VFP != io_din[11:0]) begin VFP <= io_din[11:0]; vip_newcfg <= 1; end + 6: if(VS != io_din[11:0]) begin VS <= io_din[11:0]; vip_newcfg <= 1; end + 7: if(VBP != io_din[11:0]) begin VBP <= io_din[11:0]; vip_newcfg <= 1; end + endcase + if(cnt == 1) begin + cfg_custom_p1 <= 0; + cfg_custom_p2 <= 0; + cfg_custom_t <= ~cfg_custom_t; + end + end + else begin + if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0]; + if(cnt[1:0]==1) cfg_custom_p2[15:0] <= io_din; + if(cnt[1:0]==2) begin + cfg_custom_p2[31:16] <= io_din; + cfg_custom_t <= ~cfg_custom_t; + cnt[1:0] <= 0; + end + end + end + if(cmd == 'h25) {led_overtake, led_state} <= io_din; + if(cmd == 'h26) vol_att <= io_din[4:0]; + if(cmd == 'h27) VSET <= io_din[11:0]; + end + end +end + +`ifndef LITE +always @(posedge clk_sys) begin + reg vsd, vsd2; + if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; + else begin + vsd <= HDMI_TX_VS; + vsd2 <= vsd; + if(~vsd2 & vsd) cfg_got <= cfg_set; + end +end +`endif + +/////////////////////////// RESET /////////////////////////////////// + +reg reset_req = 0; +always @(posedge FPGA_CLK2_50) begin + reg [1:0] resetd, resetd2; + reg old_reset; + + //latch the reset + old_reset <= reset; + if(~old_reset & reset) reset_req <= 1; + + //special combination to set/clear the reset + //preventing of accidental reset control + if(resetd==1) reset_req <= 1; + if(resetd==2 && resetd2==0) reset_req <= 0; + + resetd <= gp_out[31:30]; + resetd2 <= resetd; +end + +wire clk_ctl; + +`ifndef LITE +///////////////////////// VIP version /////////////////////////////// +wire iHdmiClk = ~HDMI_TX_CLK; // Internal HDMI clock, inverted in relation to external clock +wire reset; + +vip vip +( + //Reset/Clock + .reset_reset_req(reset_req | ~cfg_ready), + .reset_reset(reset), + .reset_reset_vip(0), + + //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. + .reset_cold_req(~btn_reset), + .reset_warm_req(0), + + //control + .ctl_address(ctl_address), + .ctl_write(ctl_write), + .ctl_writedata(ctl_writedata), + .ctl_waitrequest(ctl_waitrequest), + .ctl_clock(clk_ctl), + .ctl_reset(ctl_reset), + + //64-bit DDR3 RAM access + .ramclk1_clk(ram_clk), + .ram1_address(ram_address), + .ram1_burstcount(ram_burstcount), + .ram1_waitrequest(ram_waitrequest), + .ram1_readdata(ram_readdata), + .ram1_readdatavalid(ram_readdatavalid), + .ram1_read(ram_read), + .ram1_writedata(ram_writedata), + .ram1_byteenable(ram_byteenable), + .ram1_write(ram_write), + + //Spare 64-bit DDR3 RAM access + //currently unused + //can combine with ram1 to make a wider RAM bus (although will increase the latency) + .ramclk2_clk(0), + .ram2_address(0), + .ram2_burstcount(0), + .ram2_waitrequest(), + .ram2_readdata(), + .ram2_readdatavalid(), + .ram2_read(0), + .ram2_writedata(0), + .ram2_byteenable(0), + .ram2_write(0), + + //Video input + .in_clk(clk_vid), + .in_data({r_out, g_out, b_out}), + .in_de(de), + .in_v_sync(vs), + .in_h_sync(hs), + .in_ce(ce_pix), + .in_f(0), + + //HDMI output + .hdmi_clk(iHdmiClk), + .hdmi_data(hdmi_data), + .hdmi_de(hdmi_de), + .hdmi_v_sync(HDMI_TX_VS), + .hdmi_h_sync(HDMI_TX_HS) +); + +wire [8:0] ctl_address; +wire ctl_write; +wire [31:0] ctl_writedata; +wire ctl_waitrequest; +wire ctl_reset; +wire [7:0] ARX, ARY; + +vip_config vip_config +( + .clk(clk_ctl), + .reset(ctl_reset), + + .ARX(ARX), + .ARY(ARY), + .CFG_SET(vip_newcfg & cfg_got), + + .WIDTH(WIDTH), + .HFP(HFP), + .HBP(HBP), + .HS(HS), + .HEIGHT(HEIGHT), + .VFP(VFP), + .VBP(VBP), + .VS(VS), + .VSET(VSET), + + .address(ctl_address), + .write(ctl_write), + .writedata(ctl_writedata), + .waitrequest(ctl_waitrequest) +); +`endif + + +///////////////////////// Lite version //////////////////////////////// + +//`ifdef LITE + +`ifndef LITE +wire [11:0] x; +wire [11:0] y; + +sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg +( + .clk(iHdmiClk), + .reset(reset), + .v_total(HEIGHT+VFP+VBP+VS), + .v_fp(VFP), + .v_bp(VBP), + .v_sync(VS), + .h_total(WIDTH+HFP+HBP+HS), + .h_fp(HFP), + .h_bp(HBP), + .h_sync(HS), + .hv_offset(0), + .vde_out(vde), + .hde_out(hde), + .vs_out(vs_hdmi), + .v_count_out(), + .h_count_out(), + .x_out(x), + .y_out(y), + .hs_out(hs_hdmi) +); + +wire vde, hde; +wire vs_hdmi; +wire hs_hdmi; + +/* +pattern_vg +#( + .B(8), // Bits per channel + .X_BITS(12), + .Y_BITS(12), + .FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern +) +pattern_vg +( + .reset(reset), + .clk_in(iHdmiClk), + .x(x), + .y(y), + .vn_in(vs_hdmi), + .hn_in(hs_hdmi), + .dn_in(vde & hde), + .r_in(0), + .g_in(0), + .b_in(0), + .vn_out(HDMI_TX_VS), + .hn_out(HDMI_TX_HS), + .den_out(HDMI_TX_DE), + .r_out(hdmi_data[23:16]), + .g_out(hdmi_data[15:8]), + .b_out(hdmi_data[7:0]), + .total_active_pix(WIDTH), + .total_active_lines(HEIGHT), + .pattern(4), + .ramp_step(20'h0333) +); +*/ + +`endif + +wire reset; +sysmem_lite sysmem +( + //Reset/Clock + .reset_reset_req(reset_req), + .reset_reset(reset), + .ctl_clock(clk_ctl), + + //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. + .reset_cold_req(~btn_reset), + .reset_warm_req(0), + + //64-bit DDR3 RAM access + .ramclk1_clk(ram_clk), + .ram1_address(ram_address), + .ram1_burstcount(ram_burstcount), + .ram1_waitrequest(ram_waitrequest), + .ram1_readdata(ram_readdata), + .ram1_readdatavalid(ram_readdatavalid), + .ram1_read(ram_read), + .ram1_writedata(ram_writedata), + .ram1_byteenable(ram_byteenable), + .ram1_write(ram_write), + + //Spare 64-bit DDR3 RAM access + //currently unused + //can combine with ram1 to make a wider RAM bus (although will increase the latency) + .ramclk2_clk(0), + .ram2_address(0), + .ram2_burstcount(0), + .ram2_waitrequest(), + .ram2_readdata(), + .ram2_readdatavalid(), + .ram2_read(0), + .ram2_writedata(0), + .ram2_byteenable(0), + .ram2_write(0) + +`ifndef LITE + , + // HDMI frame buffer + .vbuf_clk(clk_ctl), + .vbuf_address(vbuf_address), + .vbuf_burstcount(vbuf_burstcount), + .vbuf_waitrequest(vbuf_waitrequest), + .vbuf_writedata(vbuf_writedata), + .vbuf_byteenable(vbuf_byteenable), + .vbuf_write(vbuf_write), + .vbuf_readdata(vbuf_readdata), + .vbuf_readdatavalid(vbuf_readdatavalid), + .vbuf_read(vbuf_read) +`endif +); + +`ifndef LITE +wire [27:0] vbuf_address; +wire [7:0] vbuf_burstcount; +wire vbuf_waitrequest; +wire [127:0] vbuf_readdata; +wire vbuf_readdatavalid; +wire vbuf_read; +wire [127:0] vbuf_writedata; +wire [15:0] vbuf_byteenable; +wire vbuf_write; + +assign HDMI_TX_VS = vs_hdmi; +assign HDMI_TX_HS = hs_hdmi; + +hdmi_lite hdmi_lite +( + .reset(reset), + + .clk_video(clk_vid), + .ce_pixel(ce_pix), + .video_vs(vs), + .video_de(de), + .video_d({r_out,g_out,b_out}), + + .clk_hdmi(HDMI_TX_CLK), + .hdmi_hde(hde), + .hdmi_vde(vde), + .hdmi_d(hdmi_data), + .hdmi_de(hdmi_de), + + .screen_w(WIDTH), + .screen_h(HEIGHT), + .quadbuf(1), + .scale_x(0), + .scale_y(0), + .scale_auto(1), + + .clk_vbuf(clk_ctl), + .vbuf_address(vbuf_address), + .vbuf_burstcount(vbuf_burstcount), + .vbuf_waitrequest(vbuf_waitrequest), + .vbuf_writedata(vbuf_writedata), + .vbuf_byteenable(vbuf_byteenable), + .vbuf_write(vbuf_write), + .vbuf_readdata(vbuf_readdata), + .vbuf_readdatavalid(vbuf_readdatavalid), + .vbuf_read(vbuf_read) +); + +`endif + + +///////////////////////// HDMI output ///////////////////////////////// + +`ifndef LITE +pll_hdmi pll_hdmi +( + .refclk(FPGA_CLK1_50), + .rst(reset_req), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + .outclk_0(HDMI_TX_CLK) +); +`endif + +//1920x1080@60 PCLK=148.5MHz CEA +reg [11:0] WIDTH = 1920; +reg [11:0] HFP = 88; +reg [11:0] HS = 48; +reg [11:0] HBP = 148; +reg [11:0] HEIGHT = 1080; +reg [11:0] VFP = 4; +reg [11:0] VS = 5; +reg [11:0] VBP = 36; +reg [11:0] VSET = 0; + +`ifndef LITE +wire [63:0] reconfig_to_pll; +wire [63:0] reconfig_from_pll; +`endif +reg cfg_write; +reg [5:0] cfg_address; +reg [31:0] cfg_data; + +`ifndef LITE +pll_hdmi_cfg pll_hdmi_cfg +( + .mgmt_clk(FPGA_CLK1_50), + .mgmt_reset(reset_req), + .mgmt_waitrequest(cfg_waitrequest), + .mgmt_read(0), + .mgmt_readdata(), + .mgmt_write(cfg_write), + .mgmt_address(cfg_address), + .mgmt_writedata(cfg_data), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) +); +`endif + +`ifndef LITE +reg cfg_ready = 0; +wire cfg_waitrequest; +`else +reg cfg_ready = 1; +wire cfg_waitrequest = 1; +`endif + +always @(posedge FPGA_CLK1_50) begin + reg gotd = 0, gotd2 = 0; + reg custd = 0, custd2 = 0; + reg old_wait = 0; + + gotd <= cfg_got; + gotd2 <= gotd; + + cfg_write <= 0; + + custd <= cfg_custom_t; + custd2 <= custd; + if(custd2 != custd & ~gotd) begin + cfg_address <= cfg_custom_p1; + cfg_data <= cfg_custom_p2; + cfg_write <= 1; + end + + if(~gotd2 & gotd) begin + cfg_address <= 2; + cfg_data <= 0; + cfg_write <= 1; + end + + old_wait <= cfg_waitrequest; + if(old_wait & ~cfg_waitrequest & gotd) cfg_ready <= 1; +end + +`ifndef LITE +hdmi_config hdmi_config +( + .iCLK(FPGA_CLK1_50), + .iRST_N(cfg_ready & ~HDMI_TX_INT), + + .I2C_SCL(HDMI_I2C_SCL), + .I2C_SDA(HDMI_I2C_SDA), + + .dvi_mode(dvi_mode), + .audio_96k(audio_96k) +); + +wire [23:0] hdmi_data; +wire hdmi_de; + +osd hdmi_osd +( + .clk_sys(clk_sys), + + .io_osd(io_osd), + .io_strobe(io_strobe), + .io_din(io_din), + + .clk_video(iHdmiClk), + .din(hdmi_data), + .dout(HDMI_TX_D), + .de_in(hdmi_de), + .de_out(HDMI_TX_DE) +); + +assign HDMI_MCLK = 0; +i2s i2s +( + .reset(~cfg_ready), + .clk_sys(FPGA_CLK3_50), + .half_rate(~audio_96k), + + .sclk(HDMI_SCLK), + .lrclk(HDMI_LRCLK), + .sdata(HDMI_I2S), + + //Could inverse the MSB but it will shift 0 level to -MAX level + .left_chan (audio_l >> !audio_s), + .right_chan(audio_r >> !audio_s) +); +`endif + + +///////////////////////// VGA output ////////////////////////////////// + +wire [23:0] vga_q; +osd vga_osd +( + .clk_sys(clk_sys), + + .io_osd(io_osd), + .io_strobe(io_strobe), + .io_din(io_din), + + .clk_video(clk_vid), + .din(de ? {r_out, g_out, b_out} : 24'd0), + .dout(vga_q), + .de_in(de) +); + +wire [23:0] vga_o; + +vga_out vga_out +( + .ypbpr_full(1), + .ypbpr_en(ypbpr_en), + .dout(vga_o), +`ifdef LITE + .din(vga_q) +`else + .din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q) +`endif +); + +`ifdef LITE + wire vs1 = vs; + wire hs1 = hs; +`else + wire vs1 = vga_scaler ? HDMI_TX_VS : vs; + wire hs1 = vga_scaler ? HDMI_TX_HS : hs; +`endif + +assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1; +assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1; +assign VGA_R = VGA_EN ? 6'bZZZZZZ : vga_o[23:18]; +assign VGA_G = VGA_EN ? 6'bZZZZZZ : vga_o[15:10]; +assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2]; +//assign VGA_VS = ~vs1; +//assign VGA_HS = ~hs1; +//assign VGA_R = vga_o[23:18]; +//assign VGA_G = vga_o[15:10]; +//assign VGA_B = vga_o[7:2]; + +// For core -> VGA direct connectivity, comment out vga_osd, vga_out and the above assign statements, then +// uncomment these signals for direct core -> VGA connectivity. +// +//assign VGA_VS = ~vs; +//assign VGA_HS = ~hs; +//assign VGA_R = r_out; +//assign VGA_G = g_out; +//assign VGA_B = b_out; + +///////////////////////// Audio output //////////////////////////////// + +wire al, ar, aspdif; + +sigma_delta_dac #(15) dac_l +( + .CLK(FPGA_CLK3_50), + .RESET(reset), + .DACin({audio_l[15] ^ audio_s, audio_l[14:0]}), + .DACout(al) +); + +sigma_delta_dac #(15) dac_r +( + .CLK(FPGA_CLK3_50), + .RESET(reset), + .DACin({audio_r[15] ^ audio_s, audio_r[14:0]}), + .DACout(ar) +); + +spdif toslink +( + .clk_i(FPGA_CLK3_50), + + .rst_i(reset), + .half_rate(0), + + .audio_l(audio_l >> !audio_s), + .audio_r(audio_r >> !audio_s), + + .spdif_o(aspdif) +); + +`ifndef LITE +assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif; +assign AUDIO_R = SW[0] ? HDMI_I2S : ar; +assign AUDIO_L = SW[0] ? HDMI_SCLK : al; +`else +assign AUDIO_SPDIF = aspdif; +assign AUDIO_R = ar; +assign AUDIO_L = al; +`endif + +reg [15:0] audio_l; +reg [15:0] audio_r; + +always @(posedge FPGA_CLK3_50) begin + reg signed [15:0] al; + reg signed [15:0] ar; + + case({audio_s,audio_mix}) + 'b000: al <= audio_ls; + 'b001: al <= audio_ls - (audio_ls >> 3) + (audio_rs >> 3); + 'b010: al <= audio_ls - (audio_ls >> 2) + (audio_rs >> 2); + 'b011: al <= (audio_ls >> 1) + (audio_rs >> 1); + 'b100: al <= audio_ls; + 'b101: al <= audio_ls - (audio_ls >>> 3) + (audio_rs >>> 3); + 'b110: al <= audio_ls - (audio_ls >>> 2) + (audio_rs >>> 2); + 'b111: al <= (audio_ls >>> 1) + (audio_rs >>> 1); + endcase + + case({audio_s,audio_mix}) + 'b000: ar <= audio_rs; + 'b001: ar <= audio_rs - (audio_rs >> 3) + (audio_ls >> 3); + 'b010: ar <= audio_rs - (audio_rs >> 2) + (audio_ls >> 2); + 'b011: ar <= (audio_rs >> 1) + (audio_ls >> 1); + 'b100: ar <= audio_rs; + 'b101: ar <= audio_rs - (audio_rs >>> 3) + (audio_ls >>> 3); + 'b110: ar <= audio_rs - (audio_rs >>> 2) + (audio_ls >>> 2); + 'b111: ar <= (audio_rs >>> 1) + (audio_ls >>> 1); + endcase + + if(vol_att[4]) begin + audio_l <= 0; + audio_r <= 0; + end + else + if(audio_s) begin + audio_l <= al >>> vol_att[3:0]; + audio_r <= ar >>> vol_att[3:0]; + end + else + begin + audio_l <= al >> vol_att[3:0]; + audio_r <= ar >> vol_att[3:0]; + end +end + +/////////////////// User module connection //////////////////////////// + +wire signed [15:0] audio_ls, audio_rs; +wire audio_s; +wire [1:0] audio_mix; +wire [7:0] r_out, g_out, b_out; +wire vs, hs, de; +wire clk_sys, clk_vid, ce_pix; + +wire ram_clk; +wire [28:0] ram_address; +wire [7:0] ram_burstcount; +wire ram_waitrequest; +wire [63:0] ram_readdata; +wire ram_readdatavalid; +wire ram_read; +wire [63:0] ram_writedata; +wire [7:0] ram_byteenable; +wire ram_write; + +wire led_user; +wire [1:0] led_power; +wire [1:0] led_disk; + +wire vs_emu, hs_emu; +sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs); +sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs); +//assign vs = vs_emu; +//assign hs = hs_emu; + +emu emu +( + .CLK_50M(FPGA_CLK3_50), + .RESET(reset), + + // 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 16b 16b + // 44 43 42 41 40 39 38 37 36 35 34 33 32 31:16 15:0 + .HPS_BUS({HDMI_TX_VS, clk_ctl, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), + + .CLK_VIDEO(clk_vid), + .CE_PIXEL(ce_pix), + + .VGA_R(r_out), + .VGA_G(g_out), + .VGA_B(b_out), + .VGA_HS(hs_emu), + .VGA_VS(vs_emu), + .VGA_DE(de), + + .LED_USER(led_user), + .LED_POWER(led_power), + .LED_DISK(led_disk), + .LED_MB(led_mb), + + `ifndef LITE + .VIDEO_ARX(ARX), + .VIDEO_ARY(ARY), + `endif + + .AUDIO_L(audio_ls), + .AUDIO_R(audio_rs), + .AUDIO_S(audio_s), + .AUDIO_MIX(audio_mix), + //.TAPE_IN(0), + + // SCK -> CLK + // MOSI -> CMD + // MISO <- DAT0 + // Z -> DAT1 + // Z -> DAT2 + // CS -> DAT3 + //.SD_SCK(SDIO_CLK), + //.SD_MOSI(SDIO_CMD), + //.SD_MISO(SDIO_DAT[0]), + //.SD_CS(SDIO_DAT[3]), + //.SD_CD(VGA_EN ? VGA_HS : SDIO_CD), + + .DDRAM_CLK(ram_clk), + .DDRAM_ADDR(ram_address), + .DDRAM_BURSTCNT(ram_burstcount), + .DDRAM_BUSY(ram_waitrequest), + .DDRAM_DOUT(ram_readdata), + .DDRAM_DOUT_READY(ram_readdatavalid), + .DDRAM_RD(ram_read), + .DDRAM_DIN(ram_writedata), + .DDRAM_BE(ram_byteenable), + .DDRAM_WE(ram_write) + +`ifndef LITE + , + .SDRAM_DQ(SDRAM_DQ), + .SDRAM_A(SDRAM_A), + .SDRAM_DQML(SDRAM_DQML), + .SDRAM_DQMH(SDRAM_DQMH), + .SDRAM_BA(SDRAM_BA), + .SDRAM_nCS(SDRAM_nCS), + .SDRAM_nWE(SDRAM_nWE), + .SDRAM_nRAS(SDRAM_nRAS), + .SDRAM_nCAS(SDRAM_nCAS), + .SDRAM_CLK(SDRAM_CLK), + .SDRAM_CKE(SDRAM_CKE) +`endif + ); + + endmodule + + module sync_fix + ( + input clk, + + input sync_in, + output sync_out + ); + + assign sync_out = sync_in ^ pol; + + reg pol; + always @(posedge clk) begin + integer pos = 0, neg = 0, cnt = 0; + reg s1,s2; + + s1 <= sync_in; + s2 <= s1; + + if(~s2 & s1) neg <= cnt; + if(s2 & ~s1) pos <= cnt; + + cnt <= cnt + 1; + if(s2 != s1) cnt <= 0; + + pol <= pos > neg; + end + +endmodule diff --git a/sys/sysmem.sv b/sys/sysmem.sv new file mode 100644 index 0000000..886b9b3 --- /dev/null +++ b/sys/sysmem.sv @@ -0,0 +1,531 @@ +`timescale 1 ps / 1 ps +module sysmem_lite +( + input ramclk1_clk, // ramclk1.clk + input [28:0] ram1_address, // ram1.address + input [7:0] ram1_burstcount, // .burstcount + output ram1_waitrequest, // .waitrequest + output [63:0] ram1_readdata, // .readdata + output ram1_readdatavalid, // .readdatavalid + input ram1_read, // .read + input [63:0] ram1_writedata, // .writedata + input [7:0] ram1_byteenable, // .byteenable + input ram1_write, // .write + + input ramclk2_clk, // ramclk2.clk + input [28:0] ram2_address, // ram2.address + input [7:0] ram2_burstcount, // .burstcount + output ram2_waitrequest, // .waitrequest + output [63:0] ram2_readdata, // .readdata + output ram2_readdatavalid, // .readdatavalid + input ram2_read, // .read + input [63:0] ram2_writedata, // .writedata + input [7:0] ram2_byteenable, // .byteenable + input ram2_write, // .write + + output ctl_clock, + input reset_cold_req, // reset.cold_req + output reset_reset, // .reset + input reset_reset_req, // .reset_req + input reset_warm_req, // .warm_req + + input vbuf_clk, // vbuf.clk + input [27:0] vbuf_address, // vbuf.address + input [7:0] vbuf_burstcount, // .burstcount + output vbuf_waitrequest, // .waitrequest + output [127:0] vbuf_readdata, // .readdata + output vbuf_readdatavalid, // .readdatavalid + input vbuf_read, // .read + input [127:0] vbuf_writedata, // .writedata + input [15:0] vbuf_byteenable, // .byteenable + input vbuf_write // .write +); + +assign ctl_clock = clk_vip_clk; + +wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps +wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n +wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n +wire clk_vip_clk; + +sysmem_HPS_fpga_interfaces fpga_interfaces ( + .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n + .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n + .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk + .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n + .f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk + .f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address + .f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount + .f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest + .f2h_sdram0_READDATA (vbuf_readdata), // .readdata + .f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid + .f2h_sdram0_READ (vbuf_read), // .read + .f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata + .f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable + .f2h_sdram0_WRITE (vbuf_write), // .write + .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk + .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address + .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount + .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest + .f2h_sdram1_READDATA (ram1_readdata), // .readdata + .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid + .f2h_sdram1_READ (ram1_read), // .read + .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata + .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable + .f2h_sdram1_WRITE (ram1_write), // .write + .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk + .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address + .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount + .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest + .f2h_sdram2_READDATA (ram2_readdata), // .readdata + .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid + .f2h_sdram2_READ (ram2_read), // .read + .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata + .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable + .f2h_sdram2_WRITE (ram2_write) // .write +); + +reset_source reset_source ( + .clk (clk_vip_clk), // clock.clk + .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset + .reset_sys (), // reset_sys.reset + .cold_req (reset_cold_req), // reset_ctl.cold_req + .reset (reset_reset), // .reset + .reset_req (reset_reset_req), // .reset_req + .reset_vip (0), // .reset_vip + .warm_req (reset_warm_req), // .warm_req + .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset + .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset +); + +endmodule + +`timescale 1 ps / 1 ps +module sysmem +( + input ramclk1_clk, // ramclk1.clk + input [28:0] ram1_address, // ram1.address + input [7:0] ram1_burstcount, // .burstcount + output ram1_waitrequest, // .waitrequest + output [63:0] ram1_readdata, // .readdata + output ram1_readdatavalid, // .readdatavalid + input ram1_read, // .read + input [63:0] ram1_writedata, // .writedata + input [7:0] ram1_byteenable, // .byteenable + input ram1_write, // .write + + input ramclk2_clk, // ramclk2.clk + input [28:0] ram2_address, // ram2.address + input [7:0] ram2_burstcount, // .burstcount + output ram2_waitrequest, // .waitrequest + output [63:0] ram2_readdata, // .readdata + output ram2_readdatavalid, // .readdatavalid + input ram2_read, // .read + input [63:0] ram2_writedata, // .writedata + input [7:0] ram2_byteenable, // .byteenable + input ram2_write, // .write + + input reset_cold_req, // reset.cold_req + output reset_reset, // .reset + input reset_reset_req, // .reset_req + input reset_warm_req, // .warm_req + + input [27:0] ram_vip_address, // ram_vip.address + input [7:0] ram_vip_burstcount, // .burstcount + output ram_vip_waitrequest, // .waitrequest + output [127:0] ram_vip_readdata, // .readdata + output ram_vip_readdatavalid, // .readdatavalid + input ram_vip_read, // .read + input [127:0] ram_vip_writedata, // .writedata + input [15:0] ram_vip_byteenable, // .byteenable + input ram_vip_write, // .write + + output clk_vip_clk, // clk_vip.clk + output reset_vip_reset // reset_vip.reset +); + +wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps +wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n +wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n + +sysmem_HPS_fpga_interfaces fpga_interfaces ( + .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n + .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n + .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk + .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n + .f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk + .f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address + .f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount + .f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest + .f2h_sdram0_READDATA (ram_vip_readdata), // .readdata + .f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid + .f2h_sdram0_READ (ram_vip_read), // .read + .f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata + .f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable + .f2h_sdram0_WRITE (ram_vip_write), // .write + .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk + .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address + .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount + .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest + .f2h_sdram1_READDATA (ram1_readdata), // .readdata + .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid + .f2h_sdram1_READ (ram1_read), // .read + .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata + .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable + .f2h_sdram1_WRITE (ram1_write), // .write + .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk + .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address + .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount + .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest + .f2h_sdram2_READDATA (ram2_readdata), // .readdata + .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid + .f2h_sdram2_READ (ram2_read), // .read + .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata + .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable + .f2h_sdram2_WRITE (ram2_write) // .write +); + +reset_source reset_source ( + .clk (clk_vip_clk), // clock.clk + .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset + .reset_sys (reset_vip_reset), // reset_sys.reset + .cold_req (reset_cold_req), // reset_ctl.cold_req + .reset (reset_reset), // .reset + .reset_req (reset_reset_req), // .reset_req + .warm_req (reset_warm_req), // .warm_req + .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset + .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset +); + +endmodule + +module sysmem_HPS_fpga_interfaces +( + // h2f_reset + output wire [1 - 1 : 0 ] h2f_rst_n + + // f2h_cold_reset_req + ,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n + + // f2h_warm_reset_req + ,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n + + // h2f_user0_clock + ,output wire [1 - 1 : 0 ] h2f_user0_clk + + // f2h_sdram0_data + ,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS + ,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT + ,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST + ,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA + ,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID + ,input wire [1 - 1 : 0 ] f2h_sdram0_READ + ,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA + ,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE + ,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE + + // f2h_sdram0_clock + ,input wire [1 - 1 : 0 ] f2h_sdram0_clk + + // f2h_sdram1_data + ,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS + ,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT + ,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST + ,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA + ,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID + ,input wire [1 - 1 : 0 ] f2h_sdram1_READ + ,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA + ,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE + ,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE + + // f2h_sdram1_clock + ,input wire [1 - 1 : 0 ] f2h_sdram1_clk + + // f2h_sdram2_data + ,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS + ,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT + ,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST + ,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA + ,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID + ,input wire [1 - 1 : 0 ] f2h_sdram2_READ + ,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA + ,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE + ,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE + + // f2h_sdram2_clock + ,input wire [1 - 1 : 0 ] f2h_sdram2_clk +); + + +wire [29 - 1 : 0] intermediate; +assign intermediate[0:0] = ~intermediate[1:1]; +assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7]; +assign intermediate[2:2] = intermediate[9:9]; +assign intermediate[3:3] = intermediate[9:9]; +assign intermediate[5:5] = intermediate[9:9]; +assign intermediate[6:6] = intermediate[9:9]; +assign intermediate[10:10] = intermediate[9:9]; +assign intermediate[11:11] = ~intermediate[12:12]; +assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16]; +assign intermediate[13:13] = intermediate[18:18]; +assign intermediate[15:15] = intermediate[18:18]; +assign intermediate[19:19] = intermediate[18:18]; +assign intermediate[20:20] = ~intermediate[21:21]; +assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25]; +assign intermediate[22:22] = intermediate[27:27]; +assign intermediate[24:24] = intermediate[27:27]; +assign intermediate[28:28] = intermediate[27:27]; +assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0]; +assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11]; +assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20]; +assign intermediate[4:4] = f2h_sdram0_READ[0:0]; +assign intermediate[7:7] = f2h_sdram0_WRITE[0:0]; +assign intermediate[9:9] = f2h_sdram0_clk[0:0]; +assign intermediate[14:14] = f2h_sdram1_READ[0:0]; +assign intermediate[16:16] = f2h_sdram1_WRITE[0:0]; +assign intermediate[18:18] = f2h_sdram1_clk[0:0]; +assign intermediate[23:23] = f2h_sdram2_READ[0:0]; +assign intermediate[25:25] = f2h_sdram2_WRITE[0:0]; +assign intermediate[27:27] = f2h_sdram2_clk[0:0]; + +cyclonev_hps_interface_clocks_resets clocks_resets( + .f2h_warm_rst_req_n({ + f2h_warm_rst_req_n[0:0] // 0:0 + }) +,.f2h_pending_rst_ack({ + 1'b1 // 0:0 + }) +,.f2h_dbg_rst_req_n({ + 1'b1 // 0:0 + }) +,.h2f_rst_n({ + h2f_rst_n[0:0] // 0:0 + }) +,.f2h_cold_rst_req_n({ + f2h_cold_rst_req_n[0:0] // 0:0 + }) +,.h2f_user0_clk({ + h2f_user0_clk[0:0] // 0:0 + }) +); + + +cyclonev_hps_interface_dbg_apb debug_apb( + .DBG_APB_DISABLE({ + 1'b0 // 0:0 + }) +,.P_CLK_EN({ + 1'b0 // 0:0 + }) +); + + +cyclonev_hps_interface_tpiu_trace tpiu( + .traceclk_ctl({ + 1'b1 // 0:0 + }) +); + + +cyclonev_hps_interface_boot_from_fpga boot_from_fpga( + .boot_from_fpga_ready({ + 1'b0 // 0:0 + }) +,.boot_from_fpga_on_failure({ + 1'b0 // 0:0 + }) +,.bsel_en({ + 1'b0 // 0:0 + }) +,.csel_en({ + 1'b0 // 0:0 + }) +,.csel({ + 2'b01 // 1:0 + }) +,.bsel({ + 3'b001 // 2:0 + }) +); + + +cyclonev_hps_interface_fpga2hps fpga2hps( + .port_size_config({ + 2'b11 // 1:0 + }) +); + + +cyclonev_hps_interface_hps2fpga hps2fpga( + .port_size_config({ + 2'b11 // 1:0 + }) +); + + +cyclonev_hps_interface_fpga2sdram f2sdram( + .cfg_rfifo_cport_map({ + 16'b0010000100000000 // 15:0 + }) +,.cfg_wfifo_cport_map({ + 16'b0010000100000000 // 15:0 + }) +,.rd_ready_3({ + 1'b1 // 0:0 + }) +,.cmd_port_clk_2({ + intermediate[28:28] // 0:0 + }) +,.rd_ready_2({ + 1'b1 // 0:0 + }) +,.cmd_port_clk_1({ + intermediate[19:19] // 0:0 + }) +,.rd_ready_1({ + 1'b1 // 0:0 + }) +,.cmd_port_clk_0({ + intermediate[10:10] // 0:0 + }) +,.rd_ready_0({ + 1'b1 // 0:0 + }) +,.wrack_ready_2({ + 1'b1 // 0:0 + }) +,.wrack_ready_1({ + 1'b1 // 0:0 + }) +,.wrack_ready_0({ + 1'b1 // 0:0 + }) +,.cmd_ready_2({ + intermediate[21:21] // 0:0 + }) +,.cmd_ready_1({ + intermediate[12:12] // 0:0 + }) +,.cmd_ready_0({ + intermediate[1:1] // 0:0 + }) +,.cfg_port_width({ + 12'b000000010110 // 11:0 + }) +,.rd_valid_3({ + f2h_sdram2_READDATAVALID[0:0] // 0:0 + }) +,.rd_valid_2({ + f2h_sdram1_READDATAVALID[0:0] // 0:0 + }) +,.rd_valid_1({ + f2h_sdram0_READDATAVALID[0:0] // 0:0 + }) +,.rd_clk_3({ + intermediate[22:22] // 0:0 + }) +,.rd_data_3({ + f2h_sdram2_READDATA[63:0] // 63:0 + }) +,.rd_clk_2({ + intermediate[13:13] // 0:0 + }) +,.rd_data_2({ + f2h_sdram1_READDATA[63:0] // 63:0 + }) +,.rd_clk_1({ + intermediate[3:3] // 0:0 + }) +,.rd_data_1({ + f2h_sdram0_READDATA[127:64] // 63:0 + }) +,.rd_clk_0({ + intermediate[2:2] // 0:0 + }) +,.rd_data_0({ + f2h_sdram0_READDATA[63:0] // 63:0 + }) +,.cfg_axi_mm_select({ + 6'b000000 // 5:0 + }) +,.cmd_valid_2({ + intermediate[26:26] // 0:0 + }) +,.cmd_valid_1({ + intermediate[17:17] // 0:0 + }) +,.cmd_valid_0({ + intermediate[8:8] // 0:0 + }) +,.cfg_cport_rfifo_map({ + 18'b000000000011010000 // 17:0 + }) +,.wr_data_3({ + 2'b00 // 89:88 + ,f2h_sdram2_BYTEENABLE[7:0] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram2_WRITEDATA[63:0] // 63:0 + }) +,.wr_data_2({ + 2'b00 // 89:88 + ,f2h_sdram1_BYTEENABLE[7:0] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram1_WRITEDATA[63:0] // 63:0 + }) +,.wr_data_1({ + 2'b00 // 89:88 + ,f2h_sdram0_BYTEENABLE[15:8] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram0_WRITEDATA[127:64] // 63:0 + }) +,.cfg_cport_type({ + 12'b000000111111 // 11:0 + }) +,.wr_data_0({ + 2'b00 // 89:88 + ,f2h_sdram0_BYTEENABLE[7:0] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram0_WRITEDATA[63:0] // 63:0 + }) +,.cfg_cport_wfifo_map({ + 18'b000000000011010000 // 17:0 + }) +,.wr_clk_3({ + intermediate[24:24] // 0:0 + }) +,.wr_clk_2({ + intermediate[15:15] // 0:0 + }) +,.wr_clk_1({ + intermediate[6:6] // 0:0 + }) +,.wr_clk_0({ + intermediate[5:5] // 0:0 + }) +,.cmd_data_2({ + 18'b000000000000000000 // 59:42 + ,f2h_sdram2_BURSTCOUNT[7:0] // 41:34 + ,3'b000 // 33:31 + ,f2h_sdram2_ADDRESS[28:0] // 30:2 + ,intermediate[25:25] // 1:1 + ,intermediate[23:23] // 0:0 + }) +,.cmd_data_1({ + 18'b000000000000000000 // 59:42 + ,f2h_sdram1_BURSTCOUNT[7:0] // 41:34 + ,3'b000 // 33:31 + ,f2h_sdram1_ADDRESS[28:0] // 30:2 + ,intermediate[16:16] // 1:1 + ,intermediate[14:14] // 0:0 + }) +,.cmd_data_0({ + 18'b000000000000000000 // 59:42 + ,f2h_sdram0_BURSTCOUNT[7:0] // 41:34 + ,4'b0000 // 33:30 + ,f2h_sdram0_ADDRESS[27:0] // 29:2 + ,intermediate[7:7] // 1:1 + ,intermediate[4:4] // 0:0 + }) +); + +endmodule diff --git a/sys/vga_out.sv b/sys/vga_out.sv new file mode 100644 index 0000000..e316000 --- /dev/null +++ b/sys/vga_out.sv @@ -0,0 +1,65 @@ + +module vga_out +( + input ypbpr_full, + input ypbpr_en, + + input [23:0] din, + output [23:0] dout +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +wire [5:0] red = din[23:18]; +wire [5:0] green = din[15:10]; +wire [5:0] blue = din[7:2]; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16]; +assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8]; +assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0]; + + +endmodule diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv new file mode 100644 index 0000000..36227ba --- /dev/null +++ b/sys/video_cleaner.sv @@ -0,0 +1,91 @@ +// +// +// Copyright (c) 2018 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +module video_cleaner +( + input clk_vid, + input ce_pix, + + input [7:0] R, + input [7:0] G, + input [7:0] B, + + input HSync, + input VSync, + input HBlank, + input VBlank, + + // video output signals + output reg [7:0] VGA_R, + output reg [7:0] VGA_G, + output reg [7:0] VGA_B, + output reg VGA_VS, + output reg VGA_HS, + output VGA_DE, + + // optional aligned blank + output reg HBlank_out, + output reg VBlank_out +); + +wire hs, vs; +s_fix sync_v(clk_vid, HSync, hs); +s_fix sync_h(clk_vid, VSync, vs); + +wire hbl = hs | HBlank; +wire vbl = vs | VBlank; + +assign VGA_DE = ~(HBlank_out | VBlank_out); + +always @(posedge clk_vid) begin + if(ce_pix) begin + HBlank_out <= hbl; + + VGA_VS <= vs; + VGA_HS <= hs; + VGA_R <= R; + VGA_G <= G; + VGA_B <= B; + + if(HBlank_out & ~hbl) VBlank_out <= vbl; + end +end + +endmodule + +module s_fix +( + input clk, + + input sync_in, + output sync_out +); + +assign sync_out = sync_in ^ pol; + +reg pol; +always @(posedge clk) begin + integer pos = 0, neg = 0, cnt = 0; + reg s1,s2; + + s1 <= sync_in; + s2 <= s1; + + if(~s2 & s1) neg <= cnt; + if(s2 & ~s1) pos <= cnt; + + cnt <= cnt + 1; + if(s2 != s1) cnt <= 0; + + pol <= pos > neg; +end + +endmodule diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv new file mode 100644 index 0000000..c9d358d --- /dev/null +++ b/sys/video_mixer.sv @@ -0,0 +1,167 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 4 bits per component +// For half depth 8 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + output ce_pix_out, + + input scandoubler, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // High quality 2x scaling + input hq2x, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // Positive pulses. + input HSync, + input VSync, + input HBlank, + input VBlank, + + // video output signals + output reg [7:0] VGA_R, + output reg [7:0] VGA_G, + output reg [7:0] VGA_B, + output reg VGA_VS, + output reg VGA_HS, + output reg VGA_DE +); + +localparam DWIDTH = HALF_DEPTH ? 3 : 7; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .hb_in(HBlank), + .vb_in(VBlank), + .r_in(R), + .g_in(G), + .b_in(B), + + .ce_pix_out(ce_pix_sd), + .hs_out(hs_sd), + .vs_out(vs_sd), + .hb_out(hb_sd), + .vb_out(vb_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler ? R_sd : R); +wire [DWIDTH:0] gt = (scandoubler ? G_sd : G); +wire [DWIDTH:0] bt = (scandoubler ? B_sd : B); + +generate + if(HALF_DEPTH) begin + wire [7:0] r = mono ? {gt,rt} : {rt,rt}; + wire [7:0] g = mono ? {gt,rt} : {gt,gt}; + wire [7:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [7:0] r = rt; + wire [7:0] g = gt; + wire [7:0] b = bt; + end +endgenerate + +wire hs = (scandoubler ? hs_sd : HSync); +wire vs = (scandoubler ? vs_sd : VSync); + +assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix; + + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire hde = scandoubler ? ~hb_sd : ~HBlank; +wire vde = scandoubler ? ~vb_sd : ~VBlank; + +always @(posedge clk_sys) begin + reg old_hde; + + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]}; + VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]}; + VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]}; + end + + 2: begin // reduce 50% = 1/2 + VGA_R <= {1'b0, r[7:1]}; + VGA_G <= {1'b0, g[7:1]}; + VGA_B <= {1'b0, b[7:1]}; + end + + 3: begin // reduce 75% = 1/4 + VGA_R <= {2'b00, r[7:2]}; + VGA_G <= {2'b00, g[7:2]}; + VGA_B <= {2'b00, b[7:2]}; + end + + default: begin + VGA_R <= r; + VGA_G <= g; + VGA_B <= b; + end + endcase + + VGA_VS <= vs; + VGA_HS <= hs; + + old_hde <= hde; + if(~old_hde && hde) VGA_DE <= vde; + if(old_hde && ~hde) VGA_DE <= 0; +end + +endmodule diff --git a/sys/vip.qsys b/sys/vip.qsys new file mode 100644 index 0000000..1f8a5d7 --- /dev/null +++ b/sys/vip.qsys @@ -0,0 +1,1177 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + Avalon-MM Bidirectional,Avalon-MM Bidirectional,Avalon-MM Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sys/vip_config.sv b/sys/vip_config.sv new file mode 100644 index 0000000..b003798 --- /dev/null +++ b/sys/vip_config.sv @@ -0,0 +1,159 @@ + +module vip_config +( + input clk, + input reset, + + input [7:0] ARX, + input [7:0] ARY, + input CFG_SET, + + input [11:0] WIDTH, + input [11:0] HFP, + input [11:0] HBP, + input [11:0] HS, + input [11:0] HEIGHT, + input [11:0] VFP, + input [11:0] VBP, + input [11:0] VS, + + input [11:0] VSET, + + output reg [8:0] address, + output reg write, + output reg [31:0] writedata, + input waitrequest +); + + +reg newres = 1; + +wire [21:0] init[23] = +'{ + //video mode + {newres, 2'd2, 7'd04, 12'd0 }, //Bank + {newres, 2'd2, 7'd30, 12'd0 }, //Valid + {newres, 2'd2, 7'd05, 12'd0 }, //Progressive/Interlaced + {newres, 2'd2, 7'd06, w }, //Active pixel count + {newres, 2'd2, 7'd07, h }, //Active line count + {newres, 2'd2, 7'd09, hfp }, //Horizontal Front Porch + {newres, 2'd2, 7'd10, hs }, //Horizontal Sync Length + {newres, 2'd2, 7'd11, hb }, //Horizontal Blanking (HFP+HBP+HSync) + {newres, 2'd2, 7'd12, vfp }, //Vertical Front Porch + {newres, 2'd2, 7'd13, vs }, //Vertical Sync Length + {newres, 2'd2, 7'd14, vb }, //Vertical blanking (VFP+VBP+VSync) + {newres, 2'd2, 7'd30, 12'd1 }, //Valid + {newres, 2'd2, 7'd00, 12'd1 }, //Go + + //mixer + { 1'd1, 2'd1, 7'd03, w }, //Bkg Width + { 1'd1, 2'd1, 7'd04, h }, //Bkg Height + { 1'd1, 2'd1, 7'd08, posx }, //Pos X + { 1'd1, 2'd1, 7'd09, posy }, //Pos Y + { 1'd1, 2'd1, 7'd10, 12'd1 }, //Enable Video 0 + { 1'd1, 2'd1, 7'd00, 12'd1 }, //Go + + //scaler + { 1'd1, 2'd0, 7'd03, videow }, //Output Width + { 1'd1, 2'd0, 7'd04, videoh }, //Output Height + { 1'd1, 2'd0, 7'd00, 12'd1 }, //Go + + 22'h3FFFFF +}; + +reg [11:0] w; +reg [11:0] hfp; +reg [11:0] hbp; +reg [11:0] hs; +reg [11:0] hb; +reg [11:0] h; +reg [11:0] vfp; +reg [11:0] vbp; +reg [11:0] vs; +reg [11:0] vb; + +reg [11:0] videow; +reg [11:0] videoh; + +reg [11:0] posx; +reg [11:0] posy; + +always @(posedge clk) begin + reg [7:0] state = 0; + reg [7:0] arx, ary; + reg [7:0] arxd, aryd; + reg [11:0] vset, vsetd; + reg cfg, cfgd; + reg [31:0] wcalc; + reg [31:0] hcalc; + reg [12:0] timeout = 0; + + arxd <= ARX; + aryd <= ARY; + vsetd <= VSET; + + cfg <= CFG_SET; + cfgd <= cfg; + + write <= 0; + if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin + arx <= arxd; + ary <= aryd; + vset <= vsetd; + timeout <= '1; + state <= 0; + if(reset || (~cfgd && cfg)) newres <= 1; + end + else + if(timeout > 0) + begin + timeout <= timeout - 1'd1; + state <= 1; + if(!(timeout & 'h1f)) case(timeout>>5) + 5: begin + w <= WIDTH; + hfp <= HFP; + hbp <= HBP; + hs <= HS; + h <= HEIGHT; + vfp <= VFP; + vbp <= VBP; + vs <= VS; + end + 4: begin + hb <= hfp+hbp+hs; + vb <= vfp+vbp+vs; + end + 3: begin + wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary; + hcalc <= (w*ary)/arx; + end + 2: begin + videow <= (!vset && (wcalc > w)) ? w : wcalc[11:0]; + videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0]; + end + 1: begin + posx <= (w - videow)>>1; + posy <= (h - videoh)>>1; + end + endcase + end + else + if(~waitrequest && state) + begin + state <= state + 1'd1; + write <= 0; + if((state&3)==3) begin + if(init[state>>2] == 22'h3FFFFF) begin + state <= 0; + newres <= 0; + end + else begin + writedata <= 0; + {write, address, writedata[11:0]} <= init[state>>2]; + end + end + end +end + +endmodule diff --git a/sysid.vhd b/sysid.vhd new file mode 100644 index 0000000..c5a67a6 --- /dev/null +++ b/sysid.vhd @@ -0,0 +1,50 @@ +--Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your +--use of Altera Corporation's design tools, logic functions and other +--software and tools, and its AMPP partner logic functions, and any +--output files any of the foregoing (including device programming or +--simulation files), and any associated documentation or information are +--expressly subject to the terms and conditions of the Altera Program +--License Subscription Agreement or other applicable license agreement, +--including, without limitation, that your use is for the sole purpose +--of programming logic devices manufactured by Altera and sold by Altera +--or its authorized distributors. Please refer to the applicable +--agreement for further details. + + +-- turn off superfluous VHDL processor warnings +-- altera message_level Level1 +-- altera message_off 10034 10035 10036 10037 10230 10240 10030 + +library altera; +use altera.altera_europa_support_lib.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity sysid is + port ( + -- inputs: + signal address : IN STD_LOGIC; + signal clock : IN STD_LOGIC; + signal reset_n : IN STD_LOGIC; + + -- outputs: + signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end entity sysid; + + +architecture europa of sysid is + +begin + + --control_slave, which is an e_avalon_slave + readdata <= A_WE_StdLogicVector((std_logic'(address) = '1'), std_logic_vector'("01011011000101101111000000111011"), std_logic_vector'("00000000000000000000000000000000")); + +end europa; + diff --git a/tools/ConvertToMif.sh b/tools/ConvertToMif.sh new file mode 100755 index 0000000..7af0139 --- /dev/null +++ b/tools/ConvertToMif.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +BASE=`basename $1` + +echo "Converting ${BASE}.bin to Memory Initialization File ${BASE}.mif..." +srec_cat ${BASE}.bin -binary -Output ${BASE}.mif -Memory_Initialization_File + diff --git a/tools/Z80Assembler.jar b/tools/Z80Assembler.jar new file mode 100755 index 0000000..1ec9364 Binary files /dev/null and b/tools/Z80Assembler.jar differ diff --git a/tools/assemble_roms.sh b/tools/assemble_roms.sh new file mode 100755 index 0000000..87b78a8 --- /dev/null +++ b/tools/assemble_roms.sh @@ -0,0 +1,62 @@ +#!/bin/bash +######################################################################################################### +## +## Name: assemble_roms.sh +## Created: August 2018 +## Author(s): Philip Smart +## Description: Sharp MZ series ROM assembly tool +## This script takes Sharp MZ ROMS in assembler format and compiles/assembles them +## into a ROM file using the GLASS Z80 assembler. +## +## Credits: +## Copyright: (c) 2018 Philip Smart +## +## History: August 2018 - Initial script written. +## +######################################################################################################### +## This source file is free software: you can redistribute it and#or modify +## it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This source file is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +######################################################################################################### + +JARDIR=../tools +ASM=glass.jar +BUILDROMLIST="monitor_SA1510 monitor_80c_SA1510 monitor_mz-1r12 quickdisk_mz-1e05 quickdisk_mz-1e14 monitor_1Z-013A monitor_80c_1Z-013A" +BUILDMZFLIST="hi-ramcheck tapecheck" +ASMDIR=../asm +ROMDIR=../roms +MZFDIR=../mzf + +# Go through list and build image. +# +for f in ${BUILDROMLIST} ${BUILDMZFLIST} +do + echo "Assembling: $f..." + + # Assemble the source. + echo "java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMDIR}/${f}.obj ${ASMDIR}/${f}.sym" + java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMDIR}/${f}.obj ${ASMDIR}/${f}.sym + + # On successful compile, perform post actions else go onto next build. + # + if [ $? = 0 ] + then + # The object file is binary, no need to link, copy according to build group. + if [[ ${BUILDROMLIST} = *"${f}"* ]]; then + echo "Copy ${ASMDIR}/${f}.obj to ${ROMDIR}/${f}.rom" + cp ${ASMDIR}/${f}.obj ${ROMDIR}/${f}.rom + else + echo "Copy ${ASMDIR}/${f}.obj to ${MZFDIR}/${f}.mzf" + cp ${ASMDIR}/${f}.obj ${MZFDIR}/${f}.mzf + fi + fi +done diff --git a/tools/build_meminitfiles.sh b/tools/build_meminitfiles.sh new file mode 100755 index 0000000..fc6ba55 --- /dev/null +++ b/tools/build_meminitfiles.sh @@ -0,0 +1,97 @@ +#!/bin/bash +######################################################################################################### +## +## Name: build_meminitfiles.sh +## Created: August 2018 +## Author(s): Philip Smart +## Description: Sharp MZ series combined rom build script. +## This script takes the necessary ROM files and builds the required combined +## rom files for the emulator and converts them to MIF format. +## Change the names below if you want this script to build combined MIF files with +## different content. +## +## Credits: +## Copyright: (c) 2018 Philip Smart +## +## History: August 2018 - Initial script written. +## +######################################################################################################### +## This source file is free software: you can redistribute it and#or modify +## it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This source file is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +######################################################################################################### + +ROMTOOL=../tools/romtool.pl +ROMDIR=../roms +MIFDIR=../mif +MZFDIR=../mzf +ASMDIR=../asm + +${ROMTOOL} --command=KEYMAP \ + --a_keymap=${ROMDIR}/key_80a.rom \ + --b_keymap=${ROMDIR}/key_80b.rom \ + --c_keymap=${ROMDIR}/key_80c.rom \ + --k_keymap=${ROMDIR}/key_80k.rom \ + --7_keymap=${ROMDIR}/key_700.rom \ + --12_keymap=${ROMDIR}/key_1200.rom \ + --binout=${ROMDIR}/combined_keymap.rom \ + --mifout=${MIFDIR}/combined_keymap.mif +${ROMTOOL} --command=64KRAM \ + --ramchecker=${MZFDIR}/hi-ramcheck.mzf \ + --a_mrom=${ROMDIR}/monitor_SA1510.rom \ + --mzf=${MZFDIR}/tapecheck.mzf \ + --binout=${ROMDIR}/combined_mainmemory.rom \ + --mifout=${MIFDIR}/combined_mainmemory.mif +${ROMTOOL} --command=MONROM \ + --a_mrom=${ROMDIR}/monitor_SA1510.rom \ + --b_mrom=${ROMDIR}/MZ80B.rom \ + --c_mrom=${ROMDIR}/NEWMON.rom \ + --k_mrom=${ROMDIR}/SP1002.rom \ + --7_mrom=${ROMDIR}/monitor_1Z-013A.rom \ + --8_mrom=${ROMDIR}/monitor_1Z-013A.rom \ + --12_mrom=${ROMDIR}/SP1002.rom \ + --20_mrom=${ROMDIR}/MZ80B.rom \ + --a_80c_mrom=${ROMDIR}/monitor_80c_SA1510.rom \ + --b_80c_mrom=${ROMDIR}/MZ80B.rom \ + --c_80c_mrom=${ROMDIR}/NEWMON.rom \ + --k_80c_mrom=${ROMDIR}/SP1002.rom \ + --7_80c_mrom=${ROMDIR}/monitor_80c_1Z-013A.rom \ + --8_80c_mrom=${ROMDIR}/monitor_80c_1Z-013A.rom \ + --12_80c_mrom=${ROMDIR}/SP1002.rom \ + --20_80c_mrom=${ROMDIR}/MZ80B.rom \ + --a_userrom=${ROMDIR}/userrom.rom \ + --b_userrom=${ROMDIR}/userrom.rom \ + --c_userrom=${ROMDIR}/userrom.rom \ + --k_userrom=${ROMDIR}/userrom.rom \ + --7_userrom=${ROMDIR}/userrom.rom \ + --8_userrom=${ROMDIR}/userrom.rom \ + --12_userrom=${ROMDIR}/userrom.rom \ + --20_userrom=${ROMDIR}/userrom.rom \ + --a_fdcrom=${ROMDIR}/fdcrom.rom \ + --b_fdcrom=${ROMDIR}/fdcrom.rom \ + --c_fdcrom=${ROMDIR}/fdcrom.rom \ + --k_fdcrom=${ROMDIR}/fdcrom.rom \ + --7_fdcrom=${ROMDIR}/fdcrom.rom \ + --8_fdcrom=${ROMDIR}/fdcrom.rom \ + --12_fdcrom=${ROMDIR}/fdcrom.rom \ + --20_fdcrom=${ROMDIR}/fdcrom.rom \ + --binout=${ROMDIR}/combined_mrom.rom \ + --mifout=${MIFDIR}/combined_mrom.mif +${ROMTOOL} --command=CGROM \ + --a_cgrom=${ROMDIR}/mz-80acg.rom \ + --b_cgrom=${ROMDIR}/MZ80K_cgrom.rom \ + --c_cgrom=${ROMDIR}/MZ80K_cgrom.rom \ + --k_cgrom=${ROMDIR}/MZ80K_cgrom.rom \ + --7_cgrom=${ROMDIR}/MZ700_cgrom.rom \ + --12_cgrom=${ROMDIR}/mz-80acg.rom \ + --binout=${ROMDIR}/combined_cgrom.rom \ + --mifout=${MIFDIR}/combined_cgrom.mif diff --git a/tools/dz80 b/tools/dz80 new file mode 100755 index 0000000..bc59a66 Binary files /dev/null and b/tools/dz80 differ diff --git a/tools/glass.jar b/tools/glass.jar new file mode 100755 index 0000000..7cb301c Binary files /dev/null and b/tools/glass.jar differ