Create license.txt

.gitignore

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+*.swp
+.*.swp
+*.swo
+.*.swo
+CPLD/build/VideoInterface.csv
+CPLD/build/VideoInterface.qsf.bak
+CPLD/build/db/
+CPLD/build/incremental_db/
+CPLD/build/old/
+CPLD/build/output_files/
+CPLD/build/simulation/
+FPGA/build/.qsys_edit/
+FPGA/build/Clock_50to100.cnx
+FPGA/build/Clock_50to100.cnxerr
+FPGA/build/PLLJ_PLLSPE_INFO.txt
+FPGA/build/VideoController.out.sdc
+FPGA/build/VideoController.srf
+FPGA/build/VideoController_assignment_defaults.qdf
+FPGA/build/db/
+FPGA/build/incremental_db/
+FPGA/build/old/
+FPGA/build/output_files/
+FPGA/build/simulation/
+FPGA/build/test.bsf
+FPGA/build/test.cmp
+FPGA/build/test.html
+FPGA/build/test.qsys
+FPGA/build/test.sopcinfo
+FPGA/build/test/
+FPGA/build/test_generation.rpt
+FPGA/build/test_generation_1.rpt
+FPGA/devices/
+FPGA/functions.vhd
+schematics/MZ80-80CLR/
+FPGA/build/VideoController.qws
+docker/QuartusPrime/Dockerfile.13.0.1.old
+docker/QuartusPrime/Quartus-web-13.0.1.232-linux.tar
+docker/QuartusPrime/files/13.0/
+docker/QuartusPrime/files/13.1/
+docker/QuartusPrime/files/17.1/
+docker/QuartusPrime/local/
+docker/QuartusPrime/quartus_docker.sh
+pin2lib.py
+schematics/MZ80_80CLR_v2.0a.pdf
+CPLD/VideoInterface.vhd.orig
+CPLD/VideoInterface_Toplevel.vhd.orig
+CPLD/VideoInterface_pkg.vhd.orig
+CPLD/build/VideoInterface.out.sdc
+CPLD/build/VideoInterface.qsf.orig
+CPLD/build/VideoInterface_constraints.sdc.orig
+FPGA/VideoController.vhd.inpro
+FPGA/VideoController.vhd.orig
+FPGA/VideoController_Toplevel.vhd.orig
+FPGA/VideoController_pkg.vhd.orig
+FPGA/build/VideoController-Unconstrained Paths.rpt
+FPGA/build/VideoController.qsf.orig
+FPGA/build/VideoController_constraints.sdc.orig
+FPGA/build/abc.qip
+FPGA/build/greybox_tmp/
+video_22082020.tar.gz
+CPLD/VideoInterface.vhd.16mhz
+CPLD/VideoInterface_Toplevel.vhd.16mhz
+FPGA/build/core
+FPGA/vidsav
+CPLD/build/VideoInterface.qws

CPLD/VideoInterface.vhd

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+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            VideoInterface.vhd
+-- Created:         June 2020
+-- Author(s):       Philip Smart
+-- Description:     MZ80A Video Module v2.0 CPLD logic definition file.
+--                  This module contains the definition of the logic used in v2.0 of the Sharp MZ80A 
+--                  Video Module. The design uses a CPLD for glue logic and voltage translation and a
+--                  Cyclone III to realise the video circuitry.
+--                  The sizing of the CPLD is probably overkill but like most developments, more is better
+--                  until the design is finalised as it gives you more options.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-20 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         June 2020 - Initial creation.
+--                  Sep 2020  - First release.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.VideoInterface_pkg.all;
+
+entity VideoInterface is
+    --generic (
+    --);
+    port (    
+        -- Primary video clock.
+        CLOCK_50                  : in    std_logic;                                     -- 50Hz base clock for system board, video timing and gate clocking.
+
+        -- Z80 Address and Data. Address is muxed with video addressing, not direct.
+        A                         : in    std_logic_vector(10 downto 0);                 -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
+        D                         : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus, from the Colour Card CN! connector.
+
+        -- Z80 Control signals.
+        WRn                       : in    std_logic;                                     -- Z80 Write signal from the Colour Card CN! connector.
+        RDn                       : in    std_logic;                                     -- Z80 Read signal from the Colour Card CN! connector.
+        RESETn                    : in    std_logic;                                     -- Z80 RESET signal from the tranZPUter board.
+
+        -- Video and Mainboard signals.
+        SRVIDEO_OUT               : out   std_logic;                                     -- Shift Register 74LS165 Video Output onto mainboard.
+        CLK_31_5K_OUT             : out   std_logic;                                     -- 31.5KHz time base for the 8253 on mainboard. Signal was from the MB14298.
+        CLK_1MHZ_OUT              : out   std_logic;                                     -- 1MHZ video timing clock output to mainboard. Signal was from the MB14298.
+        CLK_2MHZ_OUT              : out   std_logic;                                     -- 2MHZ main CPU clock output to mainboard. Signal was from the MB14298.
+        HBLNK_OUTn                : out   std_logic;                                     -- Horizontal Blanking output. Signal was from the MB14298.
+        HSY_OUT                   : out   std_logic;                                     -- Horizontal sync output. Signal was from the MB14298.
+        SYNCH_OUT                 : out   std_logic;                                     -- Vertical sync output. Signal was from the MB14298.
+        VBLNK_OUTn                : out   std_logic;                                     -- Vertical blanking output. Signal was from the MB14298.
+        MB_HBLNKn                 : in    std_logic;                                     -- Mainboard Horizontal Blanking from the Colour Card CN! connector.
+        MB_SYNCH                  : in    std_logic;                                     -- Mainboard Vertical sync from the Colour Card CN! connector.
+        MB_V_HBLNKn               : in    std_logic;                                     -- Mainboard combined vertical/horizontal sync from the Colour Card CN! connector.
+        MB_VIDEO                  : in    std_logic;                                     -- Mainboard Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
+        MB_LOAD                   : in    std_logic;                                     -- Mainboard shift register load signal from the Colour Card CN! connector.
+        VRAM_CS_INn               : in    std_logic;                                     -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
+        GTn                       : in    std_logic;                                     -- GATE signal from the Colour Card CN! connector.
+        CSn                       : in    std_logic;                                     -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
+        OUTCLK                    : out   std_logic;                                     -- CPU signal serialiser clock.
+        INDATA                    : in    std_logic_vector(3 downto 0);                  -- Incoming serialised CPU signals.
+
+        -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
+        VADDR                     : out   std_logic_vector(15 downto 0);                 -- Z80 Address bus, multiplexed with video address.
+        VDATA                     : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus from mainboard Colour Card CD connector..
+        VRAMD                     : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus from the VRAM chip, gated according to state signals.
+      --VMEM_CSn                  : out   std_logic;                                     -- Extended memory select to FPGA.
+        VVRAM_CS_INn              : out   std_logic;                                     -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
+        VWAITn                    : in    std_logic;                                     -- WAIT signal from FPGA asserted during active frame display period.
+        VZ80_IORQn                : out   std_logic;                                     -- IORQn to FPGA.
+        VZ80_RDn                  : out   std_logic;                                     -- Z80_RDn from tranZPUter to FPGA.
+        VCSn                      : out   std_logic;                                     -- Video RAM Attribute Chip Select (CSn) to FPGA.
+        VGTn                      : out   std_logic;                                     -- Video Gate (GTn) 
+        VZ80_WRn                  : out   std_logic;                                     -- WRn to FPGA.
+        --
+        VSRVIDEO_OUT              : in    std_logic;                                     -- Video out from 74LS165 on mainboard, pre-GATE.
+        VHBLNK_OUTn               : in    std_logic;                                     -- Horizontal blanking.
+        VHSY_OUT                  : in    std_logic;                                     -- Horizontal Sync.
+        VSYNCH_OUT                : in    std_logic;                                     -- Veritcal Sync.
+        VVBLNK_OUTn               : in    std_logic;                                     -- Vertical blanking.
+        --
+        VMB_HBLNKn                : out   std_logic;                                     -- Horizontal Blanking from the Colour Card CN! connector.
+        VMB_SYNCH                 : out   std_logic;                                     -- Vertical sync from the Colour Card CN! connector.
+        VMB_V_HBLNKn              : out   std_logic;                                     -- combined vertical/horizontal sync from the Colour Card CN! connector.
+        VMB_VIDEO                 : out   std_logic;                                     -- Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
+        VMB_LOAD                  : out   std_logic                                      -- shift register load signal from the Colour Card CN! connector.
+
+        -- Reserved.
+      --TBA                       : in    std_logic_vector(1 downto 0)                   -- Reserved signals.
+    );
+end entity;
+
+architecture rtl of VideoInterface is
+
+    -- Clock generation wires.
+    signal CLOCK_48               :       std_logic;                                     -- 16MHz used for the Video main frequency.
+    signal CLK24Mi                :       std_logic;                                     -- 24MHz used for internal clocking.
+    signal CLK16Mi                :       std_logic;                                     -- 16MHz used for internal clocking.
+    signal CLK4_8Mi               :       std_logic;                                     -- 4.8MHz used for the CPU main frequency in custom mode.
+    signal CLK4Mi                 :       std_logic;                                     -- 4MHz used for the CPU main frequency in MZ80B mode.
+    signal CLK3_54Mi              :       std_logic;                                     -- 3.54MHz used for the CPU main frequency in MZ700 mode.
+    signal CLK2Mi                 :       std_logic;                                     -- 2MHz used for the CPU main frequency.
+    signal CLK1Mi                 :       std_logic;                                     -- 1MHz used for video timing.
+    signal CLK31500i              :       std_logic;                                     -- 8253 Clock base frequency used for RTC,
+
+    signal ENASERCLK              :       std_logic;                                     -- Enable serializer clock.
+    signal S_IORQn                :       std_logic;                                     -- Serialiser signal - IORQn
+    signal S_VIDEO_RDn            :       std_logic;                                     -- Serialiser signal - Video FPGA RDn
+    signal S_VIDEO_WRn            :       std_logic;                                     -- Serialiser signal - Video FPGA WRn
+    signal INBUF                  :       std_logic_vector(11 downto 0);
+    signal INCOUNT                :       integer range 0 to 3;
+    signal VA                     :       std_logic_vector(15 downto 0);
+
+    -- CPLD configuration signals.
+    signal MODE_CPLD_MZ80K        :       std_logic;
+    signal MODE_CPLD_MZ80C        :       std_logic;
+    signal MODE_CPLD_MZ1200       :       std_logic;
+    signal MODE_CPLD_MZ80A        :       std_logic;
+    signal MODE_CPLD_MZ700        :       std_logic;
+    signal MODE_CPLD_MZ800        :       std_logic;
+    signal MODE_CPLD_MZ80B        :       std_logic;
+    signal MODE_CPLD_MZ2000       :       std_logic;
+    signal MODE_CPLD_SWITCH       :       std_logic;
+    signal MODE_CPLD_MB_VIDEOn    :       std_logic;                                     -- Mainboard video, 0 = enabled, 1 = disabled. 
+    signal CPLD_CFG_DATA          :       std_logic_vector(7 downto 0);                  -- CPLD Configuration register.
+
+    -- IO Decode signals.
+    signal CS_IO_6XXn             :       std_logic;                                     -- IO decode for the 0x60-0x6f region used by the CPLD.
+    signal CS_IO_EXXn             :       std_logic;                                     -- Chip select for block E0:EF
+    signal CS_IO_FXXn             :       std_logic;                                     -- Chip select for block F0:FF
+    signal CS_CPLD_CFGn           :       std_logic;                                     -- Select to set the CPLD configuration register.
+    signal CS_FB_VMn              :       std_logic;                                     -- Chip Select for the Video Mode register.
+    signal CS_FB_PAGEn            :       std_logic;                                     -- Chip Select for the Page select register.
+    signal CS_80B_PIOn            :       std_logic;                                     -- Chip select for MZ80B PIO when in MZ80B mode.
+    signal CS_LAST_LEVEL          :       std_logic_vector(4 downto 0);                  -- Register to store the previous chip select level for edge detection.
+    signal CS_DXXXn               :       std_logic;                                     -- Chip select range for the VRAM/ARAM.
+    signal CS_EXXXn               :       std_logic;                                     -- Chip select range for the memory mapped I/O.
+    signal CS_DVRAMn              :       std_logic;                                     -- Chip select for the Video RAM.
+    signal CS_DARAMn              :       std_logic;                                     -- Chip select for the Attribute RAM.
+
+    -- Video module signal mirrors.
+    signal MODE_VIDEO_MZ80A       :       std_logic := '1';                              -- The machine is running in MZ80A mode.
+    signal MODE_VIDEO_MZ700       :       std_logic := '0';                              -- The machine is running in MZ700 mode.
+    signal MODE_VIDEO_MZ800       :       std_logic := '0';                              -- The machine is running in MZ800 mode.
+    signal MODE_VIDEO_MZ80B       :       std_logic := '0';                              -- The machine is running in MZ80B mode.
+    signal MODE_VIDEO_MZ80K       :       std_logic := '0';                              -- The machine is running in MZ80K mode.
+    signal MODE_VIDEO_MZ80C       :       std_logic := '0';                              -- The machine is running in MZ80C mode.
+    signal MODE_VIDEO_MZ1200      :       std_logic := '0';                              -- The machine is running in MZ1200 mode.
+    signal MODE_VIDEO_MZ2000      :       std_logic := '0';                              -- The machine is running in MZ2000 mode.
+    signal GRAM_PAGE_ENABLE       :       std_logic;                                     -- Graphics mode page enable.
+    signal GRAM_MZ80B_ENABLE      :       std_logic;                                     -- MZ80B Graphics memory enabled flag.
+    signal MZ80B_VRAM_HI_ADDR     :       std_logic;                                     -- Video RAM located at D000:FFFF when high.
+    signal MZ80B_VRAM_LO_ADDR     :       std_logic;                                     -- Video RAM located at 5000:7FFF when high.
+
+    function to_std_logic(L: boolean) return std_logic is
+    begin
+        if L then
+            return('1');
+        else
+            return('0');
+        end if;
+    end function to_std_logic;
+begin
+
+    -- A tranZPUter signal serializer. Signals required by the Video Module but not accessible physically (without hardware hacks) are captured and serialised by the tranZPUter
+    -- as a set of x 4 blocks, clocked by the video interace CPLD, As the mainboard can not run faster than 4MHz, a 24MHz serialiser clock should be sufficient to bring the
+    -- signals across but can be increased as necessary.
+    -- Reset synchronises the Video Module CPLD with the tranZPUter CPLD and the signals are sent during valid mainboard accesses. During tranZPUter accesses, both
+    -- S_VIDEO_RDn and S_VIDEO_WRn are sent as 0, an invalid state, to indicate the signals are not valid.
+    --
+    SIGNALSERIALIZER: process(RESETn, CLK16Mi, ENASERCLK)
+        variable RCV_CYCLE              : integer range 0 to 1;
+    begin
+        -- Each reset the FPGA and CPLD are in sync, set the signals to the starting level ready to commence serialization.
+        if RESETn = '0' then
+            ENASERCLK                   <= '0';
+            RCV_CYCLE                   := 0;
+            INCOUNT                     <= 1;
+            INBUF                       <= "000000000000";
+            VA(15 downto 11)            <= (others => '0');
+            S_IORQn                     <= '1';
+            S_VIDEO_RDn                 <= '1';
+            S_VIDEO_WRn                 <= '1';
+
+        elsif falling_edge(CLK16Mi) then
+
+            case RCV_CYCLE is
+                -- Cycle starts by enabling the clock which the tranZPUter sees the rising edge and captures the 16 signals and places the 
+                -- first block of 4 onto the mux-bus.
+                when 0 =>
+                    ENASERCLK           <= '1';
+                    RCV_CYCLE           := 1;
+
+                -- Each clock period, a block of signals are placed on the bus with sufficient time for the signals to settle and to capture them.
+                when 1 =>
+                    if INCOUNT > 0 then
+                        INBUF(3 downto 0) <= INDATA; --INBUF(7 downto 4);
+                        --INBUF(7 downto 4) <= INDATA;
+                        INCOUNT         <= INCOUNT - 1;
+                    else
+                        -- If S_VIDEO_WRn and S_VIDEO_RDn are both zero it indicates an invalid data set so dont act on it.
+                        --
+                        if INDATA(3 downto 1) /= "000" then
+                            VA(15 downto 11) <= INDATA(0) & INBUF(3 downto 0);
+                            S_VIDEO_RDn <= INDATA(1);
+                            S_VIDEO_WRn <= INDATA(2);
+                            S_IORQn     <= INDATA(3);
+                        else
+                            VA(15 downto 11) <= (others => '0');
+                            S_VIDEO_RDn <= '1';
+                            S_VIDEO_WRn <= '1';
+                            S_IORQn     <= '1';
+                        end if;
+                        INCOUNT         <= 1;
+                    end if;
+                    RCV_CYCLE           := 1;
+            end case;
+        end if;
+
+        -- Enable the clock directly onto the bus clock line when data required.
+        if ENASERCLK = '1' then
+            OUTCLK <= CLK16Mi;
+        else
+            OUTCLK <= '0';
+        end if;
+    end process;
+
+    -- Signals originating on the mainboard or the FPGA are brougnt into the clock domain of the CPLD, which is also the clock domain of the mainboard
+    -- as the CPLD provides the mainboard clocks.
+    --
+    VIDEOSIGNALS: process(RESETn, CLOCK_50)
+    begin
+        if RESETn = '0' then
+            SRVIDEO_OUT                 <= '0';
+            HBLNK_OUTn                  <= '0';
+            HSY_OUT                     <= '0';
+            SYNCH_OUT                   <= '0';
+            VBLNK_OUTn                  <= '0';
+            VMB_HBLNKn                  <= '0';
+            VMB_LOAD                    <= '0';
+            VMB_SYNCH                   <= '0';
+            VMB_V_HBLNKn                <= '0';
+            VMB_VIDEO                   <= '0';
+
+        elsif rising_edge(CLOCK_50) then
+            SRVIDEO_OUT                 <= VSRVIDEO_OUT;
+            HBLNK_OUTn                  <= VHBLNK_OUTn;
+            HSY_OUT                     <= VHSY_OUT;
+            SYNCH_OUT                   <= VSYNCH_OUT;
+            VBLNK_OUTn                  <= VVBLNK_OUTn;
+
+            VMB_HBLNKn                  <= MB_HBLNKn;
+            VMB_LOAD                    <= MB_LOAD;
+            VMB_SYNCH                   <= MB_SYNCH;
+            VMB_V_HBLNKn                <= MB_V_HBLNKn;
+            VMB_VIDEO                   <= MB_VIDEO;
+        end if;
+    end process;
+
+    -- The main crystal runs at 50MHz but most of the system board signals are in binary 2 values (except for MZ700 mode). We thus create a 48MHz
+    -- clock by skipping 2 out of 50 clock periods, 1 on each level, to create the desired clock.
+    --
+    CLOCK48MHZ: process(RESETn, CLOCK_50)
+        variable counter48Mi            : unsigned(6 downto 0);                -- Binary divider to create 48Mi clock.
+    begin
+        if RESETn = '0' then
+            counter48Mi                 := (others => '0');
+
+        elsif rising_edge(CLOCK_50) then
+
+            counter48Mi := counter48Mi + 1;
+
+            if counter48Mi = 50 then
+                counter48Mi             := (others => '0');
+            end if;
+        end if;
+
+        if counter48Mi /= 25 and counter48Mi /= 49 then
+            CLOCK_48                    <= CLOCK_50;
+        else
+            CLOCK_48                    <= '1';
+        end if;
+    end process;
+
+    -- The 48MHz clock is used to create the base system clocks, 16MHz being the original machine base clock along with 4, 2 and 1MHz.
+    -- This logic was originally performed by the MB14298 Gate Array on the mainboard.
+    --
+    SYSCLOCKS: process(RESETn, CLOCK_48, CLK24Mi, CLK4_8Mi, CLK4Mi, CLK3_54Mi, CLK2Mi, CLK1Mi, CLK31500i, CPLD_CFG_DATA)
+        variable counter24Mi            : unsigned(1 downto 0);                -- Binary divider to create 24Mi clock.
+        variable counter16Mi            : unsigned(1 downto 0);                -- Binary divider to create 16Mi clock.
+        variable counter4_8Mi           : unsigned(2 downto 0);                -- Binary divider to create 4_8Mi clock.
+        variable counter4Mi             : unsigned(3 downto 0);                -- Binary divider to create 4Mi clock.
+        variable counter2Mi             : unsigned(3 downto 0);                -- Binary divider to create 2Mi clock.
+        variable counter1Mi             : unsigned(4 downto 0);                -- Binary divider to create 1Mi clock.
+        variable counter31500i          : unsigned(10 downto 0);               -- Binary divider to create 31500i clock.
+    begin
+        if RESETn = '0' then
+            counter24Mi                 := (others => '0');
+            counter16Mi                 := (others => '0');
+            counter4_8Mi                := (others => '0');
+            counter4Mi                  := (others => '0');
+            counter2Mi                  := (others => '0');
+            counter1Mi                  := (others => '0');
+            counter31500i               := (others => '0');
+            CLK24Mi                     <= '0';
+            CLK16Mi                     <= '0';
+            CLK4_8Mi                    <= '0';
+            CLK4Mi                      <= '0';
+            CLK2Mi                      <= '0';
+            CLK1Mi                      <= '0';
+            CLK31500i                   <= '0';
+
+        elsif rising_edge(CLOCK_48) then
+
+            counter24Mi                 := counter24Mi + 1;
+            counter16Mi                 := counter16Mi + 1;
+            counter4_8Mi                := counter4_8Mi + 1;
+            counter4Mi                  := counter4Mi + 1;
+            counter2Mi                  := counter2Mi + 1;
+            counter1Mi                  := counter1Mi + 1;
+            counter31500i               := counter31500i + 1;
+
+            -- 24000000Hz 
+            if counter24Mi = 1 then
+                CLK24Mi                 <= not CLK24Mi;
+                counter24Mi             := (others => '0');
+            end if;
+
+            -- 16000000Hz 
+            if counter16Mi = 2 or counter16Mi = 3 then
+                CLK16Mi                 <= not CLK16Mi;
+                if counter16Mi = 3 then
+                    counter16Mi         := (others => '0');
+                end if;
+            end if;
+
+            -- 4800000Hz 
+            if counter4_8Mi = 5 then
+                CLK4_8Mi                <= not CLK4_8Mi;
+                counter4_8Mi            := (others => '0');
+            end if;
+
+            -- 4000000Hz 
+            if counter4Mi = 6 then
+                CLK4Mi                  <= not CLK4Mi;
+                counter4Mi              := (others => '0');
+            end if;
+
+            -- 2000000Hz 
+            if counter2Mi = 12 then 
+                CLK2Mi                  <= not CLK2Mi;
+                counter2Mi              := (others => '0');
+            end if;
+
+            -- 1000000Hz 
+            if counter1Mi = 24 then
+                CLK1Mi                  <= not CLK1Mi;
+                counter1Mi              := (others => '0');
+            end if;
+
+            -- 31500Hz 
+            if counter31500i = 761 or counter31500i = 1523 then
+                CLK31500i               <= not CLK31500i;
+                if counter31500i = 1523 then
+                    counter31500i       := (others => '0');
+                end if;
+            end if;
+        end if;
+
+        -- Setup board speeds according to mode.
+        --
+        CLK_31_5K_OUT                   <= CLK31500i;
+        CLK_1MHZ_OUT                    <= CLK1Mi;
+        case to_integer(unsigned(CPLD_CFG_DATA(6 downto 4))) is
+            when MODE_FREQ_MZ80A =>
+                CLK_2MHZ_OUT            <= CLK2Mi;
+
+            when MODE_FREQ_MZ80B =>
+                CLK_2MHZ_OUT            <= CLK4Mi;
+
+            when MODE_FREQ_MZ700 =>
+                CLK_2MHZ_OUT            <= CLK3_54Mi;
+
+            when MODE_FREQ_CUSTOM =>
+                CLK_2MHZ_OUT            <= CLK4_8Mi;
+
+            when others =>
+                CLK_2MHZ_OUT            <= CLK2Mi;
+        end case;
+    end process;
+
+    -- Process to subdivide the main 50MHz clock to obtain the MZ700 frequencies.
+    --
+    MZ700CLOCKS: process(RESETn, CLOCK_50, CLK3_54Mi)
+        variable counter3_54Mi          : unsigned(4 downto 0);                -- Binary divider to create the 3.54Mi clock.
+    begin
+
+        if RESETn = '0' then
+            counter3_54Mi               := (others => '0');
+            CLK3_54Mi                   <= '0';
+
+        elsif rising_edge(CLOCK_50) then
+
+            counter3_54Mi               := counter3_54Mi + 1;
+
+            -- 3540000Hz 
+            if counter3_54Mi = 7 then
+                CLK3_54Mi               <= not CLK3_54Mi;
+                counter3_54Mi           := (others => '0');
+            end if;
+        end if;
+    end process;
+
+    -- Control Registers - This mirrors the Video Module control registers as we need to know when video memory is to be mapped into main memory.
+    --
+    -- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF8->.
+    --   0xF8=<val> sets the mode that of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000.
+    --   0xFD=<val> memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue.
+    --
+    CTRLREGISTERS: process( RESETn, CLK16Mi, GRAM_PAGE_ENABLE, MZ80B_VRAM_HI_ADDR, MZ80B_VRAM_LO_ADDR )
+    begin
+        -- Ensure default values at reset.
+        if RESETn = '0' then
+            MODE_VIDEO_MZ80A      <= '0';
+            MODE_VIDEO_MZ700      <= '1';
+            MODE_VIDEO_MZ800      <= '0';
+            MODE_VIDEO_MZ80B      <= '0';
+            MODE_VIDEO_MZ80K      <= '0';
+            MODE_VIDEO_MZ80C      <= '0';
+            MODE_VIDEO_MZ1200     <= '0';
+            MODE_VIDEO_MZ2000     <= '0';
+            GRAM_PAGE_ENABLE      <= '0';
+            MZ80B_VRAM_HI_ADDR    <= '0';
+            MZ80B_VRAM_LO_ADDR    <= '0';
+            MODE_CPLD_SWITCH      <= '0';
+            CPLD_CFG_DATA         <= "00000011";
+    
+        elsif rising_edge(CLK16Mi) then
+
+            -- Write to config register.
+            -- CPLD Configuration register.
+            --
+            -- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
+            -- by host software such as RFS.
+            --
+            -- [2:0] - Mode/emulated machine.
+            --         000 = MZ-80K
+            --         001 = MZ-80C
+            --         010 = MZ-1200
+            --         011 = MZ-80A
+            --         100 = MZ-700
+            --         101 = MZ-800
+            --         110 = MZ-80B
+            --         111 = MZ-2000
+            -- [3]   - Mainboard Video - 1 = Enable, 0 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
+            --                                                     can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
+            -- [6:4] = Mainboard/CPU clock.
+            --         000 = Sharp MZ80A 2MHz System Clock.
+            --         001 = Sharp MZ80B 4MHz System Clock.
+            --         010 = Sharp MZ700 3.54MHz System Clock.
+            --         011 -111 = Reserved, defaults to 2MHz System Clock.
+            --
+            if(CS_CPLD_CFGn = '0' and CS_LAST_LEVEL(0) = '1' and S_VIDEO_WRn = '0') then
+
+                -- Set the mode switch event flag if the mode changes.
+                if CPLD_CFG_DATA(2 downto 0) /= D(2 downto 0) then
+                    MODE_CPLD_SWITCH  <= '1';
+                end if;
+
+                -- Store the new value into the register, used for read operations.
+                CPLD_CFG_DATA         <= D;
+            else
+                MODE_CPLD_SWITCH      <= '0';
+            end if;
+
+            -- Setup the video mode.
+            if CS_FB_VMn = '0' and CS_LAST_LEVEL(1) = '1' and S_VIDEO_WRn = '0' then
+                MODE_VIDEO_MZ80K  <= '0';
+                MODE_VIDEO_MZ80C  <= '0';
+                MODE_VIDEO_MZ1200 <= '0';
+                MODE_VIDEO_MZ80A  <= '0';
+                MODE_VIDEO_MZ700  <= '0';
+                MODE_VIDEO_MZ800  <= '0';
+                MODE_VIDEO_MZ80B  <= '0';
+                MODE_VIDEO_MZ2000 <= '0';
+
+                -- Bits [2:0] define the machine compatibility.
+                --
+                case to_integer(unsigned(D(2 downto 0))) is
+                    when MODE_MZ80K =>
+                        MODE_VIDEO_MZ80K  <= '1';
+                    when MODE_MZ80C =>
+                        MODE_VIDEO_MZ80C  <= '1';
+                    when MODE_MZ1200 =>
+                        MODE_VIDEO_MZ1200 <= '1';
+                    when MODE_MZ80A =>
+                        MODE_VIDEO_MZ80A  <= '1';
+                    when MODE_MZ700 =>
+                        MODE_VIDEO_MZ700  <= '1';
+                    when MODE_MZ800 =>
+                        MODE_VIDEO_MZ800  <= '1';
+                    when MODE_MZ80B =>
+                        MODE_VIDEO_MZ80B  <= '1';
+                    when MODE_MZ2000 =>
+                        MODE_VIDEO_MZ2000 <= '1';
+                    when others =>
+                end case;
+            end if;
+
+            -- memory page register. [0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = Off, 1 = Enabled. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
+            if CS_FB_PAGEn = '0' and CS_LAST_LEVEL(2) = '1' and S_VIDEO_WRn = '0' then
+                GRAM_PAGE_ENABLE          <= D(0);
+            end if;
+
+            -- MZ80B Z80 PIO.
+            if CS_80B_PIOn = '0' and CS_LAST_LEVEL(3) = '1' and MODE_VIDEO_MZ80B = '1' and S_VIDEO_WRn = '0' then
+
+                -- Write to PIO A.
+                -- 7 = Assigns addresses $DOOO-$FFFF to V-RAM.
+                -- 6 = Assigns addresses $5000-$7FFF to V-RAM.
+                -- 5 = Changes screen to 80-character mode (L: 40-character mode).
+                if VA(1 downto 0) = "00" then
+                    MZ80B_VRAM_HI_ADDR    <= D(7);
+                    MZ80B_VRAM_LO_ADDR    <= D(6);
+                end if;
+            end if;
+
+            -- Remember the previous level so we can detect the edge transition. As the clock of this process is not necessarily running at the clock of the CPU
+            -- this step is important to guarantee transaction integrity.
+            CS_LAST_LEVEL                 <= '0' & CS_80B_PIOn & CS_FB_PAGEn & CS_FB_VMn & CS_CPLD_CFGn; 
+
+        end if;
+
+        -- MZ80B Graphics RAM is enabled whenever one of the two control lines goes active.
+        GRAM_MZ80B_ENABLE         <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR;
+    end process;
+
+    -- Voltage translation. The FPGA is max 3.3v tolerant (as are nearly all FPGA's) so the 5V signals from the mainboard would have to go through a diode clamp 
+    -- or converter. Given the pricing of the MAX7000 series chips it is easier and cheaper to use a CPLD to perform the voltage translation as they are 5V tolerant
+    -- and the mainboard accepts 3.3V output voltages.
+    --
+    VADDR                         <= VA(15 downto 11) & A(10 downto 0);
+
+    -- Data bus is muxed between the Z80 data bus and VRAMD which is the gated data bus after the video buffers.
+    -- The write signal WRn from the motherboard is actually a gated Write with video memory or I/O select. The read signal RDn from the motherboard is a gated Read with video memory or I/O select.
+    -- The logic has been updated in the tranZPUter to combine the Video Select with Z80 RD/WR such that use of S_VIDEO_RDn = 0 for read and S_VIDEO_WRn = 0 for write works as intended for all memory/IO operations. To
+    -- differentiate between memory and access, I/O operations use S_IORQn = 0.
+    --
+    VDATA                         <= D                           when S_VIDEO_WRn = '0'                            -- All memory write data sent to FPGA in region C000:FFFF
+                                     else
+                                     (others => 'Z');
+    D                             <= VDATA                       when S_VIDEO_RDn = '0' and CS_EXXXn = '1'         -- C000:FFFF or FPGA IO Registers via data bus.
+                                     else
+                                     (others => 'Z');
+    VRAMD                         <= (others => 'Z');
+    VA(10 downto 0)               <= A(10 downto 0);                                                               -- Lower 11 address bits taken from address bus.
+    VZ80_IORQn                    <= S_IORQn;
+    VZ80_WRn                      <= S_VIDEO_WRn;                                                                  -- Write based on Z80_WRn and Video FPGA select signal from tranZPUter.
+    VZ80_RDn                      <= S_VIDEO_RDn;                                                                  -- Read signal based on Z80_RDn and Video FPGA select from tranZPUter.
+    VGTn                          <= GTn;
+    VCSn                          <= CSn;
+    VVRAM_CS_INn                  <= VRAM_CS_INn;
+
+    -- Standard access to VRAM/ARAM.
+    CS_DXXXn                      <= '0'                         when S_IORQn = '1'     and VA(15 downto 12) = "1101"
+                                     else '1';
+    CS_DVRAMn                     <= '0'                         when S_IORQn = '1'     and VA(15 downto 11) = "11010"
+                                     else '1';
+    CS_DARAMn                     <= '0'                         when S_IORQn = '1'     and VA(15 downto 11) = "11011"
+                                     else '1';
+    CS_EXXXn                      <= '0'                         when S_IORQn = '1'     and VA(15 downto 11) = "11100" and GRAM_PAGE_ENABLE = '0' and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
+                                     else '1';
+
+    --
+    -- CPU / RAM signals and selects.
+    --
+    CS_IO_6XXn                    <= '0'                         when S_IORQn = '0'     and VA(7 downto 4) = "0110"
+                                      else '1';
+    CS_IO_EXXn                    <= '0'                         when S_IORQn = '0'     and VA(7 downto 4) = "1110"
+                                     else '1';
+    CS_IO_FXXn                    <= '0'                         when S_IORQn = '0'     and VA(7 downto 4) = "1111"
+                                      else '1';
+    CS_CPLD_CFGn                  <= '0'                         when CS_IO_6XXn = '0'  and VA(3 downto 0) = "1110"                  -- IO 6E
+                                      else '1';
+    -- 0xF8 set the video mode. [2:0] = mode, 000 = MZ80A, 001 = MZ-700, 010 = MZ-80B, 011 = MZ-800, 111 = Pixel graphics.
+    CS_FB_VMn                     <= '0'                         when CS_IO_FXXn = '0'  and VA(3 downto 0) = "1000"
+                                      else '1';
+    -- 0xFD set the Video memory page in block C000:FFFF bit 0, set the CGROM upload access in bit 7.
+    CS_FB_PAGEn                   <= '0'                         when CS_IO_FXXn = '0'  and VA(3 downto 0) = "1101"
+                                      else '1';
+    -- MZ80B/MZ2000 I/O Registers E0-EB,
+    CS_80B_PIOn                   <= '0'                         when CS_IO_EXXn = '0'  and VA(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1'
+                                      else '1';
+
+
+    -- Set the mainboard video state, 0 = enabled, 1 = disabled.
+    MODE_CPLD_MB_VIDEOn           <= CPLD_CFG_DATA(3);
+    -- Set CPLD mode flag according to value given in config 2:0 
+    MODE_CPLD_MZ80K               <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80K
+                                     else '0';
+    MODE_CPLD_MZ80C               <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80C
+                                     else '0';
+    MODE_CPLD_MZ1200              <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ1200
+                                     else '0';
+    MODE_CPLD_MZ80A               <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80A
+                                     else '0';
+    MODE_CPLD_MZ700               <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ700
+                                     else '0';
+    MODE_CPLD_MZ800               <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ800
+                                     else '0';
+    MODE_CPLD_MZ80B               <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80B
+                                     else '0';
+    MODE_CPLD_MZ2000              <= '1'                         when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ2000
+                                     else '0';
+end architecture;

CPLD/VideoInterface_Toplevel.vhd

@@ -0,0 +1,201 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            VideoInterface_Toplevel.vhd
+-- Created:         June 2020
+-- Author(s):       Philip Smart
+-- Description:     MZ80A Video Module CPLD Top Level module.
+--                                                     
+--                  This module contains the basic pin definition of the CPLD<->logic<-->FPGA  needed in
+--                  the project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-20 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         June 2020 - Initial creation.
+--                  Sep 2020  - First release. 
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.VideoInterface_pkg.all;
+library altera;
+use altera.altera_syn_attributes.all;
+
+entity VideoInterfaceCPLD is
+    port (
+        -- Primary video clock.
+        CLOCK_50                  : in    std_logic;                                     -- 50MHz base clock for system board, video timing and gate clocking.
+
+        -- Z80 Address and Data. Address is muxed with video addressing, not direct.
+        A                         : in    std_logic_vector(10 downto 0);                 -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
+        D                         : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus, from the Colour Card CN! connector.
+
+        -- Z80 Control signals.
+        WRn                       : in    std_logic;                                     -- Z80 Write signal from the Colour Card CN! connector.
+        RDn                       : in    std_logic;                                     -- Z80 Read signal from the Colour Card CN! connector.
+        RESETn                    : in    std_logic;                                     -- Z80 RESET signal from the tranZPUter board.
+        MB_RESETn                 : in    std_logic;                                     -- Z80 RESET signal from the tranZPUter board.
+
+        -- Video and Mainboard signals.
+        SRVIDEO_OUT               : out   std_logic;                                     -- Shift Register 74LS165 Video Output onto mainboard.
+        CLK_31_5K_OUT             : out   std_logic;                                     -- 31.5KHz time base for the 8253 on mainboard. Signal was from the MB14298.
+        CLK_1MHZ_OUT              : out   std_logic;                                     -- 1MHZ video timing clock output to mainboard. Signal was from the MB14298.
+        CLK_2MHZ_OUT              : out   std_logic;                                     -- 2MHZ main CPU clock output to mainboard. Signal was from the MB14298.
+        HBLNK_OUTn                : out   std_logic;                                     -- Horizontal Blanking output. Signal was from the MB14298.
+        HSY_OUT                   : out   std_logic;                                     -- Horizontal sync output. Signal was from the MB14298.
+        SYNCH_OUT                 : out   std_logic;                                     -- Vertical sync output. Signal was from the MB14298.
+        VBLNK_OUTn                : out   std_logic;                                     -- Vertical blanking output. Signal was from the MB14298.
+        MB_HBLNKn                 : in    std_logic;                                     -- Mainboard Horizontal Blanking from the Colour Card CN! connector.
+        MB_SYNCH                  : in    std_logic;                                     -- Mainboard Vertical sync from the Colour Card CN! connector.
+        MB_V_HBLNKn               : in    std_logic;                                     -- Mainboard combined vertical/horizontal sync from the Colour Card CN! connector.
+        MB_VIDEO                  : in    std_logic;                                     -- Mainboard Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
+        MB_LOAD                   : in    std_logic;                                     -- Mainboard shift register load signal from the Colour Card CN! connector.
+        VRAM_CS_INn               : in    std_logic;                                     -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
+        GTn                       : in    std_logic;                                     -- GATE signal from the Colour Card CN! connector.
+        CSn                       : in    std_logic;                                     -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
+        OUTCLK                    : out   std_logic;                                     -- CPU signal serialiser clock.
+        INDATA                    : in    std_logic_vector(3 downto 0);                  -- Incoming serialised CPU signals.
+
+        -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
+        VADDR                     : out   std_logic_vector(15 downto 0);                 -- Z80 Address bus, multiplexed with video address.
+        VDATA                     : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus from mainboard Colour Card CD connector..
+        VRAMD                     : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus from the VRAM chip, gated according to state signals.
+      --VMEM_CSn                  : out   std_logic;                                     -- Extended memory select to FPGA.
+        VZ80_IORQn                : out   std_logic;                                     -- IORQn to FPGA.
+        VZ80_RDn                  : out   std_logic;                                     -- RDn to FPGA.
+        VZ80_WRn                  : out   std_logic;                                     -- WRn to FPGA.
+        VVRAM_CS_INn              : out   std_logic;                                     -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
+        VWAITn                    : in    std_logic;                                     -- WAIT signal from FPGA asserted during active frame display period.
+        VCSn                      : out   std_logic;                                     -- Video RAM Attribute Chip Select (CSn) to FPGA.
+        VGTn                      : out   std_logic;                                     -- Video Gate (GTn) 
+        VRESETn                   : out   std_logic;                                     -- Reset to FPGA.
+        --
+        VSRVIDEO_OUT              : in    std_logic;                                     -- Video out from 74LS165 on mainboard, pre-GATE.
+        VHBLNK_OUTn               : in    std_logic;                                     -- Horizontal blanking.
+        VHSY_OUT                  : in    std_logic;                                     -- Horizontal Sync.
+        VSYNCH_OUT                : in    std_logic;                                     -- Veritcal Sync.
+        VVBLNK_OUTn               : in    std_logic;                                     -- Vertical blanking.
+                --
+        VMB_HBLNKn                : out   std_logic;                                     -- Horizontal Blanking from the Colour Card CN! connector.
+        VMB_SYNCH                 : out   std_logic;                                     -- Vertical sync from the Colour Card CN! connector.
+        VMB_V_HBLNKn              : out   std_logic;                                     -- combined vertical/horizontal sync from the Colour Card CN! connector.
+        VMB_VIDEO                 : out   std_logic;                                     -- Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
+        VMB_LOAD                  : out   std_logic                                      -- shift register load signal from the Colour Card CN! connector.
+
+        -- Reserved.
+      --TBA                       : in    std_logic_vector(1 downto 0)                   -- Reserved signals.
+    );
+END entity;
+
+architecture rtl of VideoInterfaceCPLD is
+
+    signal CPLDRESETn             :       std_logic;
+    signal RESET_COUNTER          :       unsigned(2 downto 0);
+
+begin
+
+    myVirtualToplevel : entity work.VideoInterface
+    --generic map
+    --(
+    --)
+    port map
+    (    
+        -- Primary video clock.
+        CLOCK_50        => CLOCK_50,                                                     -- 50MHz base clock for system board, video timing and gate clocking.
+
+        -- Z80 Address and Data. Address is muxed with video addressing, not direct.
+        A               => A,                                                            -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
+        D               => D,                                                            -- Z80 Data bus, from the Colour Card CN! connector.
+
+        -- Z80 Control signals.
+        WRn             => WRn,                                                          -- Z80 Write signal from the Colour Card CN! connector.
+        RDn             => RDn,                                                          -- Z80 Read signal from the Colour Card CN! connector.
+        RESETn          => CPLDRESETn,                                                   -- Z80 RESET signal from the tranZPUter board.
+     -- IORQn           => IORQn,                                                        -- Z80 IORQ signal from the tranZPUter board.
+
+        -- Video and Mainboard signals.
+        SRVIDEO_OUT     => SRVIDEO_OUT,                                                  -- Shift Register 74LS165 Video Output onto mainboard.
+        CLK_31_5K_OUT   => CLK_31_5K_OUT,                                                -- 31.5KHz time base for the 8253 on mainboard. Signal was from the MB14298.
+        CLK_1MHZ_OUT    => CLK_1MHZ_OUT,                                                 -- 1MHZ video timing clock output to mainboard. Signal was from the MB14298.
+        CLK_2MHZ_OUT    => CLK_2MHZ_OUT,                                                 -- 2MHZ main CPU clock output to mainboard. Signal was from the MB14298.
+        HBLNK_OUTn      => HBLNK_OUTn,                                                   -- Horizontal Blanking output. Signal was from the MB14298.
+        HSY_OUT         => HSY_OUT,                                                      -- Horizontal sync output. Signal was from the MB14298.
+        SYNCH_OUT       => SYNCH_OUT,                                                    -- Vertical sync output. Signal was from the MB14298.
+        VBLNK_OUTn      => VBLNK_OUTn,                                                   -- Vertical blanking output. Signal was from the MB14298.
+        MB_HBLNKn       => MB_HBLNKn,                                                    -- Mainboard Horizontal Blanking from the Colour Card CN! connector.
+        MB_SYNCH        => MB_SYNCH,                                                     -- Mainboard Vertical sync from the Colour Card CN! connector.
+        MB_V_HBLNKn     => MB_V_HBLNKn,                                                  -- Mainboard combined vertical/horizontal sync from the Colour Card CN! connector.
+        MB_VIDEO        => MB_VIDEO,                                                     -- Mainboard Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
+        MB_LOAD         => MB_LOAD,                                                      -- Mainboard shift register load signal from the Colour Card CN! connector.
+        VRAM_CS_INn     => VRAM_CS_INn,                                                  -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
+        GTn             => GTn,                                                          -- GATE signal from the Colour Card CN! connector.
+        CSn             => CSn,                                                          -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
+     -- MEM_CSn         => MEM_CSn,                                                      -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board.
+        OUTCLK          => OUTCLK,                                                       -- CPU signal serialiser clock.
+        INDATA          => INDATA,                                                       -- Incoming serialised CPU signals.
+
+        -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
+        VADDR           => VADDR,                                                        -- Z80 Address bus, multiplexed with video address.
+        VDATA           => VDATA,                                                        -- Z80 Data bus from mainboard Colour Card CD connector..
+        VRAMD           => VRAMD,                                                        -- Z80 Data bus from the VRAM chip, gated according to state signals.
+      --VMEM_CSn        => VMEM_CSn,                                                     -- Extended memory select to FPGA.
+        VZ80_IORQn      => VZ80_IORQn,                                                   -- IORQn to FPGA.
+        VZ80_RDn        => VZ80_RDn,                                                     -- RDn to FPGA.
+        VZ80_WRn        => VZ80_WRn,                                                     -- WRn to FPGA.
+        VVRAM_CS_INn    => VVRAM_CS_INn,                                                 -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
+        VWAITn          => VWAITn,                                                       -- WAIT signal from FPGA asserted during active frame display period.
+        VCSn            => VCSn,                                                         -- Video RAM Attribute Chip Select (CSn) to FPGA.
+        VGTn            => VGTn,                                                         -- Video Gate (GTn) 
+
+        VSRVIDEO_OUT    => VSRVIDEO_OUT,                                                 -- Video out from 74LS165 on mainboard, pre-GATE.
+        VHBLNK_OUTn     => VHBLNK_OUTn,                                                  -- Horizontal blanking.
+        VHSY_OUT        => VHSY_OUT,                                                     -- Horizontal Sync.
+        VSYNCH_OUT      => VSYNCH_OUT,                                                   -- Veritcal Sync.
+        VVBLNK_OUTn     => VVBLNK_OUTn,                                                  -- Vertical blanking.
+
+        VMB_HBLNKn      => VMB_HBLNKn,                                                   -- Horizontal Blanking from the Colour Card CN! connector.
+        VMB_SYNCH       => VMB_SYNCH,                                                    -- Vertical sync from the Colour Card CN! connector.
+        VMB_V_HBLNKn    => VMB_V_HBLNKn,                                                 -- combined vertical/horizontal sync from the Colour Card CN! connector.
+        VMB_VIDEO       => VMB_VIDEO,                                                    -- Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
+        VMB_LOAD        => VMB_LOAD                                                      -- shift register load signal from the Colour Card CN! connector.
+
+        -- Reserved.
+      --TBA             => TBA                                                           -- Reserved signals.
+    );
+
+    -- Process to reset the CPLD based on a minimum number of clock cycles to tie in with the FPGA. We dont want the
+    -- CPU starting up until the FPGA is ready.
+    --
+    CPLDRESET: process(RESETn, MB_RESETn, CLOCK_50)
+    begin
+        if RESETn = '0' or MB_RESETn = '0' then
+            RESET_COUNTER        <= (others => '1');
+            CPLDRESETn           <= '0';
+        elsif rising_edge(CLOCK_50) then
+            if RESET_COUNTER /= 0 then
+                RESET_COUNTER    <= RESET_COUNTER - 1;
+            else
+                CPLDRESETn       <= '1';
+            end if;
+        end if;
+    end process;
+
+    -- Reset to FPGA uses the mainboard reset.
+    VRESETn             <= RESETn;
+
+
+end architecture;

CPLD/VideoInterface_pkg.vhd

@@ -0,0 +1,191 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            VideoInterface_pkg.vhd
+-- Created:         June 2020
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ80A Video Module v2.0 CPLD configuration file.
+--                                                     
+--                  This module contains parameters for the CPLD in v2.0 of the Sharp MZ80A Video Module
+--                  project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-20 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         June 2020 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+package VideoInterface_pkg is
+
+    ------------------------------------------------------------ 
+    -- Constants
+    ------------------------------------------------------------ 
+
+    -- Potential logic state constants.
+    constant YES                      : std_logic := '1';
+    constant NO                       : std_logic := '0';
+    constant HI                       : std_logic := '1';
+    constant LO                       : std_logic := '0';
+    constant ONE                      : std_logic := '1';
+    constant ZERO                     : std_logic := '0';
+    constant HIZ                      : std_logic := 'Z';
+
+    -- Target hardware modes.
+    constant MODE_MZ80K               : integer   := 0;
+    constant MODE_MZ80C               : integer   := 1;
+    constant MODE_MZ1200              : integer   := 2;
+    constant MODE_MZ80A               : integer   := 3;
+    constant MODE_MZ700               : integer   := 4;
+    constant MODE_MZ800               : integer   := 5;
+    constant MODE_MZ80B               : integer   := 6;
+    constant MODE_MZ2000              : integer   := 7;
+
+    -- Target Bus frequency modes.
+    constant MODE_FREQ_MZ80A          : integer   := 0;
+    constant MODE_FREQ_MZ80B          : integer   := 1;
+    constant MODE_FREQ_MZ700          : integer   := 2;
+    constant MODE_FREQ_CUSTOM         : integer   := 7;
+
+    -- Memory management modes.
+    constant TZMM_ORIG                : integer   := 00;                     -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
+    constant TZMM_BOOT                : integer   := 01;                     -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
+    constant TZMM_TZFS                : integer   := 02;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
+    constant TZMM_TZFS2               : integer   := 03;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
+    constant TZMM_TZFS3               : integer   := 04;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
+    constant TZMM_TZFS4               : integer   := 05;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
+    constant TZMM_CPM                 : integer   := 06;                     -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
+    constant TZMM_CPM2                : integer   := 07;                     -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
+                                                                             -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
+    constant TZMM_COMPAT              : integer   := 08;                     -- Compatible monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
+    constant TZMM_MZ700_0             : integer   := 10;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
+    constant TZMM_MZ700_1             : integer   := 11;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
+    constant TZMM_MZ700_2             : integer   := 12;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
+    constant TZMM_MZ700_3             : integer   := 13;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
+    constant TZMM_MZ700_4             : integer   := 14;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
+    constant TZMM_TZPU0               : integer   := 24;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
+    constant TZMM_TZPU1               : integer   := 25;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
+    constant TZMM_TZPU2               : integer   := 26;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
+    constant TZMM_TZPU3               : integer   := 27;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
+    constant TZMM_TZPU4               : integer   := 28;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
+    constant TZMM_TZPU5               : integer   := 29;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
+    constant TZMM_TZPU6               : integer   := 30;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
+    constant TZMM_TZPU7               : integer   := 31;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
+
+    ------------------------------------------------------------ 
+    -- Configurable parameters.
+    ------------------------------------------------------------ 
+    -- Target hardware.
+    constant CPLD_HOST_HW             : integer  := MODE_MZ80A;
+
+    -- Target video hardware.
+    constant CPLD_HAS_FPGA_VIDEO      : std_logic := '1';
+
+    -- Version of hdl.
+    constant CPLD_VERSION             : integer   := 1;
+
+    -- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
+    --
+    constant USE_K64F_CTL_CLOCK       : integer   := 1;
+
+
+    ------------------------------------------------------------ 
+    -- Function prototypes
+    ------------------------------------------------------------ 
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer;
+
+    -- Function to return the value of a bit as an integer for array indexing etc.
+    function bit_to_integer( s : std_logic ) return natural;
+
+    ------------------------------------------------------------ 
+    -- Records
+    ------------------------------------------------------------ 
+
+    ------------------------------------------------------------ 
+    -- Components
+    ------------------------------------------------------------
+
+end VideoInterface_pkg;
+
+------------------------------------------------------------ 
+-- Function definitions.
+------------------------------------------------------------ 
+package body VideoInterface_pkg is
+    
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer is
+    begin
+        if a > b then
+            return a;
+        else
+            return b;
+        end if;
+        return a;
+    end function IntMax;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural is
+        variable tmp : positive     := 1;
+        variable log : natural      := 0;
+    begin
+        if arg = 1 then
+            return 0;
+        end if;
+
+        while arg > tmp loop
+            tmp := tmp * 2;
+            log := log + 1;
+        end loop;
+        return log;
+    end function;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer is
+        variable ticks         : real;
+        variable fracTicks     : real;
+    begin
+        ticks         := (Real(period) * Real(clock)) / 1000000000.0;
+        fracTicks     := ticks - CEIL(ticks);
+        if fracTicks > 0.0001 then
+            return Integer(CEIL(ticks + 1.0));
+        else
+            return Integer(CEIL(ticks));
+        end if;
+    end function;
+
+    -- Function to return the value of a bit as an integer for array indexing etc.
+    function bit_to_integer( s : std_logic ) return natural is
+    begin
+        if s = '1' then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function;
+
+end package body;

CPLD/build/VideoInterface.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "16:29:32  June 24, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "VideoInterface"

CPLD/build/VideoInterface.qsf

@@ -0,0 +1,217 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		tranZPUterSW_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX7000AE
+set_global_assignment -name DEVICE "EPM7512AETC144-12"
+set_global_assignment -name TOP_LEVEL_ENTITY VideoInterfaceCPLD
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32  JUNE 24, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
+
+# Global clocks.
+# ==============
+set_location_assignment PIN_125 -to CLOCK_50
+
+# Z80 Address Bus
+# ===============
+#set_location_assignment PIN_90 -to A[13]
+#set_location_assignment PIN_88 -to A[12]
+#set_location_assignment PIN_87 -to A[11]
+set_location_assignment PIN_98 -to A[10]
+set_location_assignment PIN_101 -to A[9]
+set_location_assignment PIN_103 -to A[8]
+set_location_assignment PIN_106 -to A[7]
+set_location_assignment PIN_108 -to A[6]
+set_location_assignment PIN_110 -to A[5]
+set_location_assignment PIN_112 -to A[4]
+set_location_assignment PIN_114 -to A[3]
+set_location_assignment PIN_117 -to A[2]
+set_location_assignment PIN_119 -to A[1]
+set_location_assignment PIN_121 -to A[0]
+
+
+# Video Interface Address Bus
+# ===========================
+set_location_assignment PIN_69 -to VADDR[15]
+set_location_assignment PIN_68 -to VADDR[14]
+set_location_assignment PIN_42 -to VADDR[13]
+set_location_assignment PIN_41 -to VADDR[12]
+set_location_assignment PIN_40 -to VADDR[11]
+set_location_assignment PIN_39 -to VADDR[10]
+set_location_assignment PIN_38 -to VADDR[9]
+set_location_assignment PIN_37 -to VADDR[8]
+set_location_assignment PIN_36 -to VADDR[7]
+set_location_assignment PIN_35 -to VADDR[6]
+set_location_assignment PIN_34 -to VADDR[5]
+set_location_assignment PIN_32 -to VADDR[4]
+set_location_assignment PIN_31 -to VADDR[3]
+set_location_assignment PIN_30 -to VADDR[2]
+set_location_assignment PIN_29 -to VADDR[1]
+set_location_assignment PIN_28 -to VADDR[0]
+
+# Clock outputs.
+# ==============
+set_location_assignment PIN_7 -to CLK_1MHZ_OUT
+set_location_assignment PIN_10 -to CLK_2MHZ_OUT
+set_location_assignment PIN_9 -to CLK_31_5K_OUT
+
+# Z80 control signals
+# ===================
+set_location_assignment PIN_92 -to CSn
+set_location_assignment PIN_93 -to GTn
+#set_location_assignment PIN_84 -to IORQn
+#set_location_assignment PIN_83 -to MEM_CSn
+set_location_assignment PIN_86 -to MB_RESETn
+set_location_assignment PIN_127 -to RESETn
+set_location_assignment PIN_91 -to RDn
+set_location_assignment PIN_96 -to WRn
+set_location_assignment PIN_16 -to VRAM_CS_INn
+
+set_location_assignment PIN_90 -to INDATA[3]
+set_location_assignment PIN_88 -to INDATA[2]
+set_location_assignment PIN_87 -to INDATA[1]
+set_location_assignment PIN_84 -to INDATA[0]
+set_location_assignment PIN_83 -to OUTCLK
+
+# Z80 Data Bus
+# ============
+set_location_assignment PIN_107 -to D[7]
+set_location_assignment PIN_109 -to D[6]
+set_location_assignment PIN_111 -to D[5]
+set_location_assignment PIN_113 -to D[4]
+set_location_assignment PIN_116 -to D[3]
+set_location_assignment PIN_118 -to D[2]
+set_location_assignment PIN_120 -to D[1]
+set_location_assignment PIN_122 -to D[0]
+
+# Video Data Bus
+# ==============
+set_location_assignment PIN_53 -to VDATA[7]
+set_location_assignment PIN_54 -to VDATA[6]
+set_location_assignment PIN_55 -to VDATA[5]
+set_location_assignment PIN_56 -to VDATA[4]
+set_location_assignment PIN_60 -to VDATA[3]
+set_location_assignment PIN_61 -to VDATA[2]
+set_location_assignment PIN_62 -to VDATA[1]
+set_location_assignment PIN_63 -to VDATA[0]
+
+# VRAM Data Bus
+# =============
+set_location_assignment PIN_18 -to VRAMD[7]
+set_location_assignment PIN_19 -to VRAMD[6]
+set_location_assignment PIN_21 -to VRAMD[5]
+set_location_assignment PIN_22 -to VRAMD[4]
+set_location_assignment PIN_23 -to VRAMD[3]
+set_location_assignment PIN_14 -to VRAMD[2]
+set_location_assignment PIN_12 -to VRAMD[1]
+set_location_assignment PIN_11 -to VRAMD[0]
+
+# Mainboard video signals on the CN1 connector.
+# =============================================
+set_location_assignment PIN_94 -to MB_HBLNKn
+set_location_assignment PIN_100 -to MB_LOAD
+set_location_assignment PIN_97 -to MB_SYNCH
+set_location_assignment PIN_99 -to MB_V_HBLNKn
+set_location_assignment PIN_102 -to MB_VIDEO
+
+# Mainboard video signals on the CN1 connector passed to the FPGA.
+# ================================================================
+set_location_assignment PIN_75 -to VMB_HBLNKn
+set_location_assignment PIN_74 -to VMB_LOAD
+set_location_assignment PIN_72 -to VMB_SYNCH
+set_location_assignment PIN_71 -to VMB_V_HBLNKn
+set_location_assignment PIN_70 -to VMB_VIDEO
+ 
+# Generated video signals.
+# ========================
+set_location_assignment PIN_1 -to HBLNK_OUTn
+set_location_assignment PIN_2 -to HSY_OUT
+set_location_assignment PIN_15 -to SRVIDEO_OUT
+set_location_assignment PIN_8 -to SYNCH_OUT
+set_location_assignment PIN_6 -to VBLNK_OUTn
+
+# FPGA Generated video signals.
+# =============================
+set_location_assignment PIN_80 -to VHBLNK_OUTn
+set_location_assignment PIN_79 -to VHSY_OUT
+set_location_assignment PIN_81 -to VSRVIDEO_OUT
+set_location_assignment PIN_78 -to VSYNCH_OUT
+set_location_assignment PIN_77 -to VVBLNK_OUTn
+
+# Video control signals.
+# ======================
+set_location_assignment PIN_46 -to VCSn
+set_location_assignment PIN_47 -to VGTn
+set_location_assignment PIN_44 -to VZ80_IORQn
+#set_location_assignment PIN_43 -to VMEM_CSn
+set_location_assignment PIN_67 -to VWAITn
+set_location_assignment PIN_45 -to VZ80_RDn
+set_location_assignment PIN_49 -to VRESETn
+set_location_assignment PIN_27 -to VVRAM_CS_INn
+set_location_assignment PIN_48 -to VZ80_WRn
+
+# Reserved.
+# =========
+#set_location_assignment PIN_66 -to TBA[1]
+#set_location_assignment PIN_65 -to TBA[0]
+
+set_global_assignment -name VHDL_FILE ../VideoInterface_Toplevel.vhd
+set_global_assignment -name VHDL_FILE ../VideoInterface_pkg.vhd
+set_global_assignment -name VHDL_FILE ../VideoInterface.vhd
+set_global_assignment -name SDC_FILE VideoInterface_constraints.sdc
+
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
+set_global_assignment -name AUTO_RESOURCE_SHARING OFF
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
+
+set_global_assignment -name AUTO_LCELL_INSERTION OFF
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF

CPLD/build/VideoInterface.srf

@@ -0,0 +1,59 @@
+{ "" "" "" "Found combinational loop of 2 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Macrocell buffer inserted after node \"Z80_BUSACKn\"" {  } {  } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Found combinational loop of 5 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(127): object \"MODE_CPLD_MZ80K\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(157): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ800\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(153): object \"MODE_VIDEO_MZ700\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(158): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(136): object \"MODE_CPLD_MB_VIDEOn\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(134): object \"MODE_CPLD_MZ2000\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(133): object \"MODE_CPLD_MZ80B\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(132): object \"MODE_CPLD_MZ800\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(131): object \"MODE_CPLD_MZ700\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(130): object \"MODE_CPLD_MZ80A\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(129): object \"MODE_CPLD_MZ1200\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(135): object \"MODE_CPLD_SWITCH\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(128): object \"MODE_CPLD_MZ80C\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"GRAM_PAGE_ENABLE\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MZ80B_VRAM_HI_ADDR\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(162): object \"MZ80B_VRAM_LO_ADDR\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(150): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(151): object \"MODE_VIDEO_MZ700\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"MODE_VIDEO_MZ800\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ700\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ800\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(158): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(128): object \"MODE_CPLD_MZ80K\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(129): object \"MODE_CPLD_MZ80C\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(130): object \"MODE_CPLD_MZ1200\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(131): object \"MODE_CPLD_MZ80A\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(132): object \"MODE_CPLD_MZ700\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(133): object \"MODE_CPLD_MZ800\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(134): object \"MODE_CPLD_MZ80B\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(135): object \"MODE_CPLD_MZ2000\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(136): object \"MODE_CPLD_SWITCH\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(137): object \"MODE_CPLD_MB_VIDEOn\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ700\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(157): object \"MODE_VIDEO_MZ800\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(162): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(149): object \"CS_DXXXn\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(151): object \"CS_DVRAMn\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"CS_DARAMn\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""}

CPLD/build/VideoInterface_constraints.sdc

@@ -0,0 +1,232 @@
+## Generated SDC file "VideoInterface.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
+
+## DATE    "Mon Aug 17 12:55:02 2020"
+
+##
+## DEVICE  "EPM7512AETC144-12"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {CLOCK_50} -period 20.00 -waveform { 0.000 10.00 } [get_ports { CLOCK_50 }]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+create_clock -name {VideoInterface:myVirtualToplevel|CLK16Mi} -period 62.5 [get_keepers {VideoInterface:myVirtualToplevel|CLK16Mi}]
+create_clock -name {VideoInterface:myVirtualToplevel|CLK24Mi} -period 41.667 [get_keepers {VideoInterface:myVirtualToplevel|CLK24Mi}]
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CLOCK_50}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[13]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[12]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[11]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[10]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[9]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[8]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[7]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[6]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[5]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[4]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[3]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[2]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[1]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {A[0]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {IORQn}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MEM_CSn}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {WRn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CSn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {GTn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {RESETn}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {RDn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {INDATA[3]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {INDATA[2]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {INDATA[1]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {INDATA[0]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAM_CS_INn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[7]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[6]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[5]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[4]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[3]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[2]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[1]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[0]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[7]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[6]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[5]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[4]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[3]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[2]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[1]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[0]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[7]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[6]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[5]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[4]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[3]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[2]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[1]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[0]}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MB_RESETn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MB_HBLNKn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MB_LOAD}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MB_SYNCH}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MB_V_HBLNKn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {MB_VIDEO}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VSRVIDEO_OUT}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VSYNCH_OUT}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VVBLNK_OUTn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VHBLNK_OUTn}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VHSY_OUT}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[7]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[6]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[5]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[4]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[3]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[2]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[1]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {D[0]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[15]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[14]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[13]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[12]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[11]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[10]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[9]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[8]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[7]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[6]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[5]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[4]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[3]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[2]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[1]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VADDR[0]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[7]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[6]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[5]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[4]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[3]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[2]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[1]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VDATA[0]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[7]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[6]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[5]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[4]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[3]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[2]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[1]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRAMD[0]}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {HBLNK_OUTn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {HSY_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {SRVIDEO_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {SYNCH_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VBLNK_OUTn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VCSn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VGTn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VZ80_IORQn}]
+#set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMEM_CSn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VZ80_RDn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VRESETn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VVRAM_CS_INn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VWAITn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VZ80_WRn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMB_HBLNKn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMB_LOAD}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMB_SYNCH}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMB_V_HBLNKn}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMB_VIDEO}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CLK_1MHZ_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CLK_2MHZ_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CLK_31_5K_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {OUTCLK}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_clocks {VideoInterface:myVirtualToplevel|CLK16Mi}] -to [get_clocks {CLOCK_50}]
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

FPGA/VideoController_Toplevel.vhd

@@ -0,0 +1,227 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            VideoController_Toplevel.vhd
+-- Created:         June 2020
+-- Author(s):       Philip Smart
+-- Description:     MZ80A Video Module FPGA Top Level module.
+--                                                     
+--                  This module contains the definition of the video controller used in v2.0 of the Sharp MZ80A 
+--                  Video Module. The controller emulates the video logic of the Sharp MZ80A, MZ-700 and
+--                  MZ80B including pixel graphics.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-20 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         June 2020 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.VideoController_pkg.all;
+library altera;
+use altera.altera_syn_attributes.all;
+
+entity VideoControllerFPGA is
+    port (
+        -- Primary and video clocks.
+        CLOCK_50                  : in    std_logic;                                     -- 50MHz base clock for video timing and gate clocking.
+
+        -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
+        -- Addres Bus
+        VADDR                     : in    std_logic_vector(15 downto 0);                 -- Z80 Address bus, multiplexed with video address.
+
+        -- Data Bus
+        VDATA                     : inout std_logic_vector(7 downto 0);                  -- Z80 Data bus from mainboard Colour Card CD connector..
+
+        -- Control signals.
+        VZ80_IORQn                : in    std_logic;                                     -- IORQn to FPGA.
+        VZ80_RDn                  : in    std_logic;                                     -- RDn to FPGA.
+        VZ80_WRn                  : in    std_logic;                                     -- WRn to FPGA.
+        VWAITn                    : out   std_logic;                                     -- WAIT signal to CPU when accessing video RAM when busy.
+
+        -- VGA signals.
+        VGA_R                     : out   std_logic_vector(3 downto 0);                  -- 16 level Red output.
+        VGA_G                     : out   std_logic_vector(3 downto 0);                  -- 16 level Green output.
+        VGA_B                     : out   std_logic_vector(3 downto 0);                  -- 16 level Blue output.
+        VGA_HS                    : out   std_logic;                                     -- Horizontal sync.
+        VGA_VS                    : out   std_logic;                                     -- Vertical sync.
+
+        -- Composite signals.
+        CSYNCn                    : out   std_logic;                                     -- Composite sync negative polarity.
+        CSYNC                     : out   std_logic;                                     -- Comnposite sync.
+        VSRVIDEO_OUT              : out   std_logic;                                     -- Video out from 74LS165 on mainboard, pre-GATE.
+        VHBLNK_OUTn               : out   std_logic;                                     -- Horizontal blanking.
+        VHSY_OUT                  : out   std_logic;                                     -- Horizontal Sync.
+        VSYNCH_OUT                : out   std_logic;                                     -- Veritcal Sync.
+        VVBLNK_OUTn               : out   std_logic;                                     -- Vertical blanking.
+
+        -- Reset.
+        VRESETn                   : in    std_logic                                      -- Reset to FPGA.
+        -- Reserved.
+      --TBA                       : in    std_logic_vector(4 downto 0)                   -- Reserved signal paths to the CPLD.
+    );
+END entity;
+
+architecture rtl of VideoControllerFPGA is
+
+    signal SYS_CLK                :       std_logic;
+    signal IF_CLK                 :       std_logic;
+    signal VIDCLK_8MHZ            :       std_logic;
+    signal VIDCLK_16MHZ           :       std_logic;
+    signal VIDCLK_25_175MHZ       :       std_logic;
+    signal VIDCLK_40MHZ           :       std_logic;
+    signal VIDCLK_65MHZ           :       std_logic;
+    signal VIDCLK_8_86719MHZ      :       std_logic;
+    signal VIDCLK_17_7344MHZ      :       std_logic;
+    signal VIDCLK_PSEUDO          :       std_logic;
+    signal PLL_LOCKED             :       std_logic;
+    signal PLL_LOCKED2            :       std_logic;
+    signal PLL_LOCKED3            :       std_logic;
+    signal PLL_LOCKED4            :       std_logic;
+    signal RESETn                 :       std_logic;
+    signal RESET_COUNTER          :       unsigned(5 downto 0);
+begin
+
+    -- Instantiate a PLL to generate the system clock and base video clocks.
+    --
+    VCPLL1 : entity work.Video_Clock
+    port map
+    (
+         inclk0                  => CLOCK_50,
+         areset                  => '0',
+         c0                      => SYS_CLK,
+         c1                      => IF_CLK,
+         c2                      => VIDCLK_8MHZ,
+         c3                      => VIDCLK_16MHZ,
+         c4                      => VIDCLK_40MHZ,
+         locked                  => PLL_LOCKED
+    );
+
+    -- Instantiate a 2nd PLL to generate additional video clocks for VGA and Sharp MZ700 modes.
+    VCPLL2 : entity work.Video_Clock_II
+    port map
+    (
+         inclk0                  => CLOCK_50,
+         areset                  => not VRESETn,
+         c0                      => VIDCLK_65MHZ,
+         c1                      => VIDCLK_25_175MHZ,
+         locked                  => PLL_LOCKED2
+    );
+
+    -- Instantiate a 3rd PLL to generate clock for pseudo monochrome generation on internal monitor.
+    VCPLL3 : entity work.Video_Clock_III
+    port map
+    (
+         inclk0                  => CLOCK_50,
+         areset                  => not VRESETn,
+         c0                      => VIDCLK_PSEUDO,
+         locked                  => PLL_LOCKED3
+    );
+
+    -- Instantiate a 4th PLL to generate clocks for MZ-700 video modes.
+    VCPLL4 : entity work.Video_Clock_IV
+    port map
+    (
+         inclk0                  => CLOCK_50,
+         areset                  => not VRESETn,
+         c0                      => VIDCLK_8_86719MHZ,
+         c1                      => VIDCLK_17_7344MHZ,
+         locked                  => PLL_LOCKED4
+    );
+
+    -- Add the Serial Flash Loader megafunction to enable in-situ programming of the EPCS16 configuration memory.
+    --
+    SFL : entity work.sfl
+    port map
+    (
+        noe_in                      => '0' 
+    );
+
+    vcToplevel : entity work.VideoController
+    --generic map
+    --(
+    --)
+    port map
+    (    
+        -- Primary and video clocks.
+        SYS_CLK                  => SYS_CLK,                                             -- 120MHz main FPGA clock.
+        IF_CLK                   => IF_CLK,                                              -- 16MHz interface clock.
+        VIDCLK_8MHZ              => VIDCLK_8MHZ,                                         -- 2x 8MHz base clock for video timing and gate clocking.
+        VIDCLK_16MHZ             => VIDCLK_16MHZ,                                        -- 2x 16MHz base clock for video timing and gate clocking.
+        VIDCLK_65MHZ             => VIDCLK_65MHZ,                                        -- 2x 65MHz base clock for video timing and gate clocking.
+        VIDCLK_25_175MHZ         => VIDCLK_25_175MHZ,                                    -- 2x 25.175MHz base clock for video timing and gate clocking.
+        VIDCLK_40MHZ             => VIDCLK_40MHZ,                                        -- 2x 40MHz base clock for video timing and gate clocking.
+        VIDCLK_8_86719MHZ        => VIDCLK_8_86719MHZ,                                   -- 2x original MZ700 video clock.
+        VIDCLK_17_7344MHZ        => VIDCLK_17_7344MHZ,                                   -- 2x original MZ700 colour modulator clock.        
+        VIDCLK_PSEUDO            => VIDCLK_PSEUDO,                                       -- Clock to create pixel slicing to generate pseudo monochrome.
+
+        -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
+        -- Addres Bus
+        VADDR                    => VADDR,                                               -- Z80 Address bus, multiplexed with video address.
+
+        -- Data Bus
+        VDATA                    => VDATA,                                               -- Z80 Data bus from mainboard Colour Card CD connector..
+
+        -- Control signals.
+        VZ80_IORQn               => VZ80_IORQn,                                          -- IORQn to FPGA.
+        VZ80_RDn                 => VZ80_RDn,                                            -- RDn to FPGA.
+        VZ80_WRn                 => VZ80_WRn,                                            -- WRn to FPGA.
+        VWAITn                   => VWAITn,                                              -- WAIT signal to CPU when accessing video RAM when busy.
+
+        -- VGA signals.
+        VGA_R                    => VGA_R,                                               -- 16 level Red output.
+        VGA_G                    => VGA_G,                                               -- 16 level Green output.
+        VGA_B                    => VGA_B,                                               -- 16 level Blue output.
+        VGA_HS                   => VGA_HS,                                              -- Horizontal sync.
+        VGA_VS                   => VGA_VS,                                              -- Vertical sync.
+
+        -- Composite signals.
+        CSYNCn                   => CSYNCn,                                              -- Composite sync negative polarity.
+        CSYNC                    => CSYNC,                                               -- Comnposite sync.
+        VSRVIDEO_OUT             => VSRVIDEO_OUT,                                        -- Video out from 74LS165 on mainboard, pre-GATE.
+        VHBLNK_OUTn              => VHBLNK_OUTn,                                         -- Horizontal blanking.
+        VHSY_OUT                 => VHSY_OUT,                                            -- Horizontal Sync.
+        VSYNCH_OUT               => VSYNCH_OUT,                                          -- Veritcal Sync.
+        VVBLNK_OUTn              => VVBLNK_OUTn,                                         -- Vertical blanking.
+
+        -- Reset.
+        VRESETn                  => RESETn                                               -- Reset to FPGA.
+
+        -- Reserved.
+      --TBA                      => TBA                                                  -- Reserved signals.        
+    );
+
+    -- Process to reset the FPGA based on the external RESET trigger, PLL's being locked
+    -- and a counter to set minimum width.
+    --
+    FPGARESET: process(VRESETn, CLOCK_50, PLL_LOCKED, PLL_LOCKED2, PLL_LOCKED3, PLL_LOCKED4)
+    begin
+        if VRESETn = '0' then
+            RESET_COUNTER        <= (others => '1');
+            RESETn               <= '0';
+        elsif PLL_LOCKED = '1' and PLL_LOCKED2 = '1' and PLL_LOCKED3 = '1' and PLL_LOCKED4 = '1' then
+            if rising_edge(CLOCK_50) then
+                if RESET_COUNTER /= 0 then
+                    RESET_COUNTER <= RESET_COUNTER - 1;
+                else
+                    RESETn        <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+end architecture;

FPGA/VideoController_pkg.vhd

@@ -0,0 +1,209 @@
+---------------------------------------------------------------------------------------------------------
+--
+-- Name:            VideoController_pkg.vhd
+-- Created:         June 2020
+-- Author(s):       Philip Smart
+-- Description:     Sharp MZ80A Video Module v2.0 CPLD configuration file.
+--                                                     
+--                  This module contains parameters for the CPLD in v2.0 of the Sharp MZ80A Video Module
+--                  project.
+--
+-- Credits:         
+-- Copyright:       (c) 2018-20 Philip Smart <philip.smart@net2net.org>
+--
+-- History:         June 2020 - Initial creation.
+--
+---------------------------------------------------------------------------------------------------------
+-- This source file is free software: you can redistribute it and-or modify
+-- it under the terms of the GNU General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http:--www.gnu.org-licenses->.
+---------------------------------------------------------------------------------------------------------
+
+library ieee;
+library pkgs;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+package VideoController_pkg is
+
+    ------------------------------------------------------------ 
+    -- Constants
+    ------------------------------------------------------------ 
+
+    -- Potential logic state constants.
+    constant YES                      : std_logic := '1';
+    constant NO                       : std_logic := '0';
+    constant HI                       : std_logic := '1';
+    constant LO                       : std_logic := '0';
+    constant ONE                      : std_logic := '1';
+    constant ZERO                     : std_logic := '0';
+    constant HIZ                      : std_logic := 'Z';
+
+    -- Target hardware modes.
+    constant MODE_MZ80K               : integer   := 0;
+    constant MODE_MZ80C               : integer   := 1;
+    constant MODE_MZ1200              : integer   := 2;
+    constant MODE_MZ80A               : integer   := 3;
+    constant MODE_MZ700               : integer   := 4;
+    constant MODE_MZ800               : integer   := 5;
+    constant MODE_MZ80B               : integer   := 6;
+    constant MODE_MZ2000              : integer   := 7;
+
+    -- Memory management modes.
+    constant TZMM_ORIG                : integer   := 00;                     -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
+    constant TZMM_BOOT                : integer   := 01;                     -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
+    constant TZMM_TZFS                : integer   := 02;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
+    constant TZMM_TZFS2               : integer   := 03;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
+    constant TZMM_TZFS3               : integer   := 04;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
+    constant TZMM_TZFS4               : integer   := 05;                     -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
+    constant TZMM_CPM                 : integer   := 06;                     -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
+    constant TZMM_CPM2                : integer   := 07;                     -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
+                                                                             -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
+    constant TZMM_COMPAT              : integer   := 08;                     -- Compatiblilty monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
+    constant TZMM_MZ700_0             : integer   := 10;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
+    constant TZMM_MZ700_1             : integer   := 11;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
+    constant TZMM_MZ700_2             : integer   := 12;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
+    constant TZMM_MZ700_3             : integer   := 13;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
+    constant TZMM_MZ700_4             : integer   := 14;                     -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
+    constant TZMM_TZPU0               : integer   := 24;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
+    constant TZMM_TZPU1               : integer   := 25;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
+    constant TZMM_TZPU2               : integer   := 26;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
+    constant TZMM_TZPU3               : integer   := 27;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
+    constant TZMM_TZPU4               : integer   := 28;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
+    constant TZMM_TZPU5               : integer   := 29;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
+    constant TZMM_TZPU6               : integer   := 30;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
+    constant TZMM_TZPU7               : integer   := 31;                     -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
+
+
+    ------------------------------------------------------------ 
+    -- Configurable parameters.
+    ------------------------------------------------------------ 
+    -- Target hardware.
+    constant CPLD_HOST_HW             : integer  := MODE_MZ80A;
+
+    -- Target video hardware.
+    constant CPLD_HAS_FPGA_VIDEO      : std_logic := '1';
+
+    -- Version of hdl.
+    constant CPLD_VERSION             : integer   := 1;
+
+    -- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
+    --
+    constant USE_K64F_CTL_CLOCK       : integer   := 1;
+
+    ------------------------------------------------------------ 
+    -- Function prototypes
+    ------------------------------------------------------------ 
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer;
+
+    -- Function to reverse the order of the bits in a standard logic vector.
+    -- ie. 1010 becomes 0101
+    function reverse_vector(slv:std_logic_vector) return std_logic_vector; 
+
+    -- Function to convert an integer (0 or 1) into std_logic.
+    --
+    function to_std_logic(i : in integer) return std_logic;
+
+    -- Function to return the value of a bit as an integer for array indexing etc.
+    function bit_to_integer( s : std_logic ) return natural;     
+
+    ------------------------------------------------------------ 
+    -- Records
+    ------------------------------------------------------------ 
+
+    ------------------------------------------------------------ 
+    -- Components
+    ------------------------------------------------------------
+
+end VideoController_pkg;
+
+------------------------------------------------------------ 
+-- Function definitions.
+------------------------------------------------------------ 
+package body VideoController_pkg is
+    
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer is
+    begin
+        if a > b then
+            return a;
+        else
+            return b;
+        end if;
+        return a;
+    end function IntMax;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural is
+        variable tmp : positive     := 1;
+        variable log : natural      := 0;
+    begin
+        if arg = 1 then
+            return 0;
+        end if;
+
+        while arg > tmp loop
+            tmp := tmp * 2;
+            log := log + 1;
+        end loop;
+        return log;
+    end function;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer is
+        variable ticks         : real;
+        variable fracTicks     : real;
+    begin
+        ticks         := (Real(period) * Real(clock)) / 1000000000.0;
+        fracTicks     := ticks - CEIL(ticks);
+        if fracTicks > 0.0001 then
+            return Integer(CEIL(ticks + 1.0));
+        else
+            return Integer(CEIL(ticks));
+        end if;
+    end function;
+
+    function reverse_vector(slv:std_logic_vector) return std_logic_vector is 
+       variable target : std_logic_vector(slv'high downto slv'low); 
+    begin 
+      for idx in slv'high downto slv'low loop 
+        target(idx) := slv(slv'low + (slv'high-idx)); 
+      end loop; 
+      return target; 
+    end reverse_vector;
+
+    function to_std_logic(i : in integer) return std_logic is
+    begin
+      if i = 0 then
+        return '0';
+      end if;
+      return '1';
+    end function;
+
+    -- Function to return the value of a bit as an integer for array indexing etc.
+    function bit_to_integer( s : std_logic ) return natural is
+    begin
+        if s = '1' then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function;
+end package body;

FPGA/build/SFL.cmp

@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component SFL
+	PORT
+	(
+		noe_in		: IN STD_LOGIC 
+	);
+end component;

FPGA/build/SFL.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "Serial Flash Loader"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "SFL.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SFL.cmp"]

FPGA/build/SFL.vhd

@@ -0,0 +1,102 @@
+-- megafunction wizard: %Serial Flash Loader%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altserial_flash_loader 
+
+-- ============================================================
+-- File Name: SFL.vhd
+-- Megafunction Name(s):
+-- 			altserial_flash_loader
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY SFL IS
+	PORT
+	(
+		noe_in		: IN STD_LOGIC 
+	);
+END SFL;
+
+
+ARCHITECTURE SYN OF sfl IS
+
+
+
+
+	COMPONENT altserial_flash_loader
+	GENERIC (
+		enable_quad_spi_support		: NATURAL;
+		enable_shared_access		: STRING;
+		enhanced_mode		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING
+	);
+	PORT (
+			noe	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+
+	altserial_flash_loader_component : altserial_flash_loader
+	GENERIC MAP (
+		enable_quad_spi_support => 0,
+		enable_shared_access => "OFF",
+		enhanced_mode => 1,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altserial_flash_loader"
+	)
+	PORT MAP (
+		noe => noe_in
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
+-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
+-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
+-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf

FPGA/build/SFL_inst.vhd

@@ -0,0 +1,3 @@
+SFL_inst : SFL PORT MAP (
+		noe_in	 => noe_in_sig
+	);

FPGA/build/VideoController.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "16:29:32  June 24, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "VideoController"

FPGA/build/VideoController.qsf

@@ -0,0 +1,288 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		tranZPUterSW_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY VideoControllerFPGA
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32  JUNE 24, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+
+# Clocks.
+# =======
+#set_location_assignment PIN_22 -to CLOCK_50
+set_location_assignment PIN_129 -to CLOCK_50
+
+# Video Interface Address Bus
+# ===========================
+set_location_assignment PIN_80 -to VADDR[15]
+set_location_assignment PIN_83 -to VADDR[14]
+set_location_assignment PIN_120 -to VADDR[13]
+set_location_assignment PIN_121 -to VADDR[12]
+set_location_assignment PIN_125 -to VADDR[11]
+set_location_assignment PIN_132 -to VADDR[10]
+set_location_assignment PIN_133 -to VADDR[9]
+set_location_assignment PIN_135 -to VADDR[8]
+set_location_assignment PIN_136 -to VADDR[7]
+set_location_assignment PIN_137 -to VADDR[6]
+set_location_assignment PIN_141 -to VADDR[5]
+set_location_assignment PIN_142 -to VADDR[4]
+set_location_assignment PIN_143 -to VADDR[3]
+set_location_assignment PIN_144 -to VADDR[2]
+set_location_assignment PIN_7 -to VADDR[1]
+set_location_assignment PIN_4 -to VADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[0]
+
+# Video Data Bus
+# ==============
+set_location_assignment PIN_106 -to VDATA[7]
+set_location_assignment PIN_105 -to VDATA[6]
+set_location_assignment PIN_104 -to VDATA[5]
+set_location_assignment PIN_103 -to VDATA[4]
+set_location_assignment PIN_101 -to VDATA[3]
+set_location_assignment PIN_100 -to VDATA[2]
+set_location_assignment PIN_99 -to VDATA[1]
+set_location_assignment PIN_98 -to VDATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[0]
+
+# Video control signals.
+# ======================
+#set_location_assignment PIN_113 -to VCSn
+#set_location_assignment PIN_112 -to VGTn
+set_location_assignment PIN_115 -to VZ80_IORQn
+#set_location_assignment PIN_119 -to VMEM_CSn
+set_location_assignment PIN_114 -to VZ80_RDn
+set_location_assignment PIN_110 -to VRESETn
+#set_location_assignment PIN_28 -to VVRAM_CS_INn
+set_location_assignment PIN_111 -to VZ80_WRn
+set_location_assignment PIN_85 -to VWAITn
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCSn
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGTn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMEM_CSn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRESETn
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVRAM_CS_INn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn
+
+# VGA/RGB signals.
+# ================
+set_location_assignment PIN_46 -to VGA_R[0]
+set_location_assignment PIN_49 -to VGA_R[1]
+set_location_assignment PIN_50 -to VGA_R[2]
+set_location_assignment PIN_51 -to VGA_R[3]
+set_location_assignment PIN_39 -to VGA_G[0]
+set_location_assignment PIN_42 -to VGA_G[1]
+set_location_assignment PIN_43 -to VGA_G[2]
+set_location_assignment PIN_44 -to VGA_G[3]
+set_location_assignment PIN_30 -to VGA_B[0]
+set_location_assignment PIN_31 -to VGA_B[1]
+set_location_assignment PIN_32 -to VGA_B[2]
+set_location_assignment PIN_33 -to VGA_B[3]
+set_location_assignment PIN_59 -to VGA_HS
+set_location_assignment PIN_58 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+
+# Composite video signals.
+# ========================
+set_location_assignment PIN_64 -to CSYNCn
+set_location_assignment PIN_60 -to CSYNC
+set_location_assignment PIN_65 -to VSRVIDEO_OUT
+set_location_assignment PIN_66 -to VHBLNK_OUTn
+set_location_assignment PIN_67 -to VHSY_OUT
+set_location_assignment PIN_68 -to VSYNCH_OUT
+set_location_assignment PIN_69 -to VVBLNK_OUTn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CSYNCn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CSYNC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VSRVIDEO_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VHBLNK_OUTn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VHSY_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VSYNCH_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVBLNK_OUTn
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNCn
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSRVIDEO_OUT
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VHBLNK_OUTn
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VHSY_OUT
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNCH_OUT
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VVBLNK_OUTn
+
+
+# Mainboard video signals on the CN1 connector passed to the FPGA.
+# ================================================================
+#set_location_assignment PIN_71 -to VMB_HBLNKn
+#set_location_assignment PIN_72 -to VMB_LOAD
+#set_location_assignment PIN_76 -to VMB_SYNCH
+#set_location_assignment PIN_77 -to VMB_V_HBLNKn
+#set_location_assignment PIN_79 -to VMB_VIDEO
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_HBLNKn
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_LOAD
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_SYNCH
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_V_HBLNKn
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_VIDEO
+
+# Reserved.
+# =========
+#set_location_assignment PIN_86 -to TBA[1]
+#set_location_assignment PIN_87 -to TBA[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[0]
+
+# Files in project.
+# =================
+set_global_assignment -name VHDL_FILE ../VideoController_Toplevel.vhd
+#set_global_assignment -name QIP_FILE Clock_50to100.qip
+set_global_assignment -name QIP_FILE SFL.qip
+set_global_assignment -name QIP_FILE Video_Clock.qip
+set_global_assignment -name QIP_FILE Video_Clock_II.qip
+set_global_assignment -name QIP_FILE Video_Clock_III.qip
+set_global_assignment -name QIP_FILE Video_Clock_IV.qip
+set_global_assignment -name QIP_FILE vbuffer.qip
+set_global_assignment -name VHDL_FILE ../VideoController_pkg.vhd
+set_global_assignment -name VHDL_FILE ../VideoController.vhd
+set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
+set_global_assignment -name SDC_FILE VideoController_constraints.sdc
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

FPGA/build/VideoController_constraints.sdc

@@ -0,0 +1,267 @@
+## Generated SDC file "VideoController.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
+
+## DATE    "Fri Jul  3 00:11:58 2020"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
+create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+#derive_pll_clocks
+create_generated_clock -name {SYS_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {IF_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -phase 180.000 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}] 
+create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}] 
+create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}] 
+create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[4]}]
+create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}] 
+create_generated_clock -name {VIDCLK_PSEUDO} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 64 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {VCPLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -master_clock {CLOCK_50} [get_pins {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {VCPLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -master_clock {CLOCK_50} [get_pins {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CLOCK_50}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VRESETn}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VZ80_WRn}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VZ80_RDn}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VZ80_IORQn}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {VMEM_CSn}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[15]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[14]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[13]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[12]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[11]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[10]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[9]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[8]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[7]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[6]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[5]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[4]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[3]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[2]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[1]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VADDR[0]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[0]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[1]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[2]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[3]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[4]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[5]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[6]}]
+set_input_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VDATA[7]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {TBA[3]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {TBA[2]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {TBA[1]}]
+#set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {TBA[0]}]
+# Required for the Serial Flash Loader.
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {altera_reserved_tck}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {altera_reserved_tdi}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {altera_reserved_tms}]
+set_input_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[0]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[1]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[2]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[3]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[4]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[5]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[6]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VDATA[7]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  8.000 [get_ports {VWAITn}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_B[0]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_B[1]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_B[2]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_B[3]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_G[0]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_G[1]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_G[2]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_G[3]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_R[0]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_R[1]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_R[2]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_R[3]}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_VS}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VGA_HS}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {CSYNC}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {CSYNCn}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VSRVIDEO_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VHBLNK_OUTn}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VHSY_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VSYNCH_OUT}]
+set_output_delay -add_delay  -clock [get_clocks {SYS_CLK}]  1.000 [get_ports {VVBLNK_OUTn}]
+# Required for the Serial Flash Loader.
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
+set_output_delay -add_delay  -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {altera_reserved_tdo}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+# There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
+set_false_path  -from  [get_clocks {VIDCLK_8MHZ}]        -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_8_86719MHZ}]  -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_16MHZ}]       -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_17_7344MHZ}]  -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_25_175MHZ}]   -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_40MHZ}]       -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_65MHZ}]       -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
+set_false_path  -from  [get_clocks {VIDCLK_PSEUDO}]      -to  [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
+
+# Z80 clock has no relationship to the video frequencies, it is used only for latching data asynchronous to the FPGA clocks.
+set_false_path  -from  [get_clocks {IF_CLK}]             -to  [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
+
+# The system clock has no real relationship with the video frequencies, rendering and display. The only place they meet is in the dual port BRAM.
+set_false_path  -from  [get_clocks {SYS_CLK}]            -to  [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
+
+# Clock 50MHZ, the input oscillator is only used for the PLL input and as I/O input/output latch which is detached from the video block
+set_false_path  -from  [get_clocks {CLOCK_50}]           -to  [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
+
+# The Z80 data, address and control lines do not go to the video block (except the parameter update which is not critical) so set it as a false path so as not to consider.
+set_false_path  -from  [get_ports {VDATA[*]}]            -to  [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
+set_false_path  -from  [get_ports {VADDR[*]}]            -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
+set_false_path  -from  [get_ports {VZ80_WRn VZ80_RDn VZ80_IORQn}]            -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -setup -start 2
+
+set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {IF_CLK}] -hold -start 1
+set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {IF_CLK}] -setup -start 2
+set_multicycle_path -from [get_clocks {IF_CLK}] -to [get_clocks {SYS_CLK}] -hold -start 2
+set_multicycle_path -from [get_clocks {IF_CLK}] -to [get_clocks {SYS_CLK}] -setup -start 3
+
+# GPU control and run variables have at least 1 clock between them being setup and used.
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
+
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -setup -start 2
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -setup -start 2
+
+
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
+
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -hold -start 1
+set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -hold -start 1
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

FPGA/build/Video_Clock.cmp

@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component Video_Clock
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

FPGA/build/Video_Clock.ppf

@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="Video_Clock" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

FPGA/build/Video_Clock.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock.ppf"]

FPGA/build/Video_Clock.vhd

@@ -0,0 +1,490 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: Video_Clock.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY Video_Clock IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END Video_Clock;
+
+
+ARCHITECTURE SYN OF video_clock IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 12,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 25,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 8,
+		clk1_phase_shift => "31250",
+		clk2_divide_by => 25,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 8,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 25,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 16,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 5,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 8,
+		clk4_phase_shift => "0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=Video_Clock",
+		lpm_type => "altpll",
+		operation_mode => "NO_COMPENSATION",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "120.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "32.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "80.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "16.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "32.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "80.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_Video.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "31250"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

FPGA/build/Video_Clock_II.cmp

@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component Video_Clock_II
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

FPGA/build/Video_Clock_II.ppf

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="Video_Clock_II" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

FPGA/build/Video_Clock_II.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_II.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_II.ppf"]

FPGA/build/Video_Clock_II.vhd

@@ -0,0 +1,394 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: Video_Clock_II.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY Video_Clock_II IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END Video_Clock_II;
+
+
+ARCHITECTURE SYN OF video_clock_ii IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 13,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 5000,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 5051,
+		clk1_phase_shift => "0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_II",
+		lpm_type => "altpll",
+		operation_mode => "NO_COMPENSATION",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire5,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "130.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.509998"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "130.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.51000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5000"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5051"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_II_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

FPGA/build/Video_Clock_III.cmp

@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component Video_Clock_III
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

FPGA/build/Video_Clock_III.ppf

@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="Video_Clock_III" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

FPGA/build/Video_Clock_III.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_III.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_III.ppf"]

FPGA/build/Video_Clock_III.vhd

@@ -0,0 +1,365 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: Video_Clock_III.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY Video_Clock_III IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END Video_Clock_III;
+
+
+ARCHITECTURE SYN OF video_clock_iii IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	locked    <= sub_wire0;
+	sub_wire2    <= sub_wire1(0);
+	c0    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 25,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 64,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_III",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire4,
+		locked => sub_wire0,
+		clk => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "128.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "128.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "64"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_III_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

FPGA/build/Video_Clock_III_inst.vhd

@@ -0,0 +1,6 @@
+Video_Clock_III_inst : Video_Clock_III PORT MAP (
+		areset	 => areset_sig,
+		inclk0	 => inclk0_sig,
+		c0	 => c0_sig,
+		locked	 => locked_sig
+	);

FPGA/build/Video_Clock_II_inst.vhd

@@ -0,0 +1,7 @@
+Video_Clock_II_inst : Video_Clock_II PORT MAP (
+		areset	 => areset_sig,
+		inclk0	 => inclk0_sig,
+		c0	 => c0_sig,
+		c1	 => c1_sig,
+		locked	 => locked_sig
+	);

FPGA/build/Video_Clock_IV.cmp

@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component Video_Clock_IV
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

FPGA/build/Video_Clock_IV.ppf

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="Video_Clock_IV" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

FPGA/build/Video_Clock_IV.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Video_Clock_IV.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_IV.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Video_Clock_IV.ppf"]

FPGA/build/Video_Clock_IV.vhd

@@ -0,0 +1,397 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: Video_Clock_IV.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY Video_Clock_IV IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END Video_Clock_IV;
+
+
+ARCHITECTURE SYN OF video_clock_iv IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 15625,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 5542,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 250000,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 177343,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=Video_Clock_IV",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire5,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "17.734400"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "35.468601"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "17.73440000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "35.46860000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Video_Clock_II.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15625"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5542"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "250000"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "177343"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Video_Clock_IV_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

FPGA/build/Video_Clock_inst.vhd

@@ -0,0 +1,10 @@
+Video_Clock_inst : Video_Clock PORT MAP (
+		areset	 => areset_sig,
+		inclk0	 => inclk0_sig,
+		c0	 => c0_sig,
+		c1	 => c1_sig,
+		c2	 => c2_sig,
+		c3	 => c3_sig,
+		c4	 => c4_sig,
+		locked	 => locked_sig
+	);

FPGA/build/vbuffer.cmp

@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component vbuffer
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		wrfull		: OUT STD_LOGIC 
+	);
+end component;

FPGA/build/vbuffer.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "vbuffer.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vbuffer_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vbuffer.cmp"]

FPGA/build/vbuffer.vhd

@@ -0,0 +1,204 @@
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo 
+
+-- ============================================================
+-- File Name: vbuffer.vhd
+-- Megafunction Name(s):
+-- 			dcfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY vbuffer IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		wrfull		: OUT STD_LOGIC 
+	);
+END vbuffer;
+
+
+ARCHITECTURE SYN OF vbuffer IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+
+
+
+	COMPONENT dcfifo
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		read_aclr_synch		: STRING;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			rdclk	: IN STD_LOGIC ;
+			wrfull	: OUT STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdempty	: OUT STD_LOGIC ;
+			wrclk	: IN STD_LOGIC ;
+			wrreq	: IN STD_LOGIC ;
+			aclr	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdreq	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	wrfull    <= sub_wire0;
+	q    <= sub_wire1(7 DOWNTO 0);
+	rdempty    <= sub_wire2;
+
+	dcfifo_component : dcfifo
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 8192,
+		lpm_showahead => "ON",
+		lpm_type => "dcfifo",
+		lpm_width => 8,
+		lpm_widthu => 13,
+		overflow_checking => "OFF",
+		rdsync_delaypipe => 3,
+		read_aclr_synch => "OFF",
+		underflow_checking => "OFF",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 3
+	)
+	PORT MAP (
+		rdclk => rdclk,
+		wrclk => wrclk,
+		wrreq => wrreq,
+		aclr => aclr,
+		data => data,
+		rdreq => rdreq,
+		wrfull => sub_wire0,
+		q => sub_wire1,
+		rdempty => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "4096"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vbuffer_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf

FPGA/build/vbuffer_inst.vhd

@@ -0,0 +1,11 @@
+vbuffer_inst : vbuffer PORT MAP (
+		aclr	 => aclr_sig,
+		data	 => data_sig,
+		rdclk	 => rdclk_sig,
+		rdreq	 => rdreq_sig,
+		wrclk	 => wrclk_sig,
+		wrreq	 => wrreq_sig,
+		q	 => q_sig,
+		rdempty	 => rdempty_sig,
+		wrfull	 => wrfull_sig
+	);

docker/QuartusPrime/Dockerfile.13.0.1

@@ -0,0 +1,173 @@
+#########################################################################################################
+##
+## Name:            Dockerfile.13.0.1
+## Created:         June 2020
+## Author(s):       Philip Smart
+## Description:     A Docker build script to create an Ubuntu 16.04 OS with Quartus Prime 13.0.1
+##
+## Credits:         
+## Copyright:       (c) 2019 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2019   - Initial module written.
+##                  June 2020     - Need to use a CPLD MAX series device which is only supported in 
+##                                  Quartus 13.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+# Ubuntu 16.04 as the base.
+FROM ubuntu:xenial
+
+# Maintainer!
+MAINTAINER Philip Smart <philip.smart@net2net.org>
+
+# Set build time environment variables.
+ENV DEBIAN_FRONTEND=noninteractive
+
+# Set constants for the build, more simpler to adjust these than the script if you want to change Quartus version.
+# Uncomment one of the QUARTUS= arguments below depending on wether your using the LITE or STANDARD version of Quartus.
+ARG TARGET_DOWNLOAD_DIR=/tmp/
+ARG INSTALLATION_DIR=/opt/altera
+ARG ALTERA_DOWNLOAD_SITE=http://download.altera.com/akdlm/software/acdsinst
+ARG QUARTUS_VERSION_INSTALLER=/13.0sp1/232/ib_installers/
+#ARG QUARTUS_VERSION_UPDATE=/13.0.1/232/update/
+#ARG QUARTUS=QuartusSetup-13.0.1.232.run
+ARG QUARTUS=QuartusSetupWeb-13.0.1.232.run
+#ARG QUARTUS_UPDATE=QuartusSetup-13.0.1.232.run
+ARG QUARTUS_PROGRAMMER=QuartusProgrammerSetup-13.0.1.232.run
+ARG QUARTUS_HELP=QuartusHelpSetup-13.0.1.232.run
+ARG QUARTUS_LINUX_SUPPORT_BIN=linux-socfpga-13.02-RC10-bin.tar.gz
+ARG QUARTUS_LINUX_SUPPORT_SRC=linux-socfpga-13.02-RC10-src.bsx
+ARG QUARTUS_DEVICE_FILES="arria_web-13.0.1.232.qdz cyclonev-13.0.1.232.qdz cyclone_web-13.0.1.232.qdz cyclone-13.0.1.232.qdz max-13.0.1.232.qdz"
+
+# Base Ubuntu install, add necessary packages for Quartus, command line editting and web-browser.
+RUN dpkg --add-architecture i386
+RUN apt-get update 
+RUN apt-get install --no-install-recommends -y \
+                ca-certificates \
+                libstdc++6:i386 \
+                libc6:i386 \
+                libx11-dev:i386 \
+                libxext-dev:i386 \
+                libxau-dev:i386 \
+                libxdmcp-dev:i386 \
+                libfreetype6:i386 \
+                libxtst6:i386 \
+                libxi6:i386 \                
+                fontconfig:i386 \
+                expat:i386 \
+                lib32ncurses5-dev \
+                libc6:i386 \
+                libcrypto++9v5 \
+                libfontconfig1 \
+                libglib2.0-0 \
+                libncurses5:i386 \
+                libsm6 \
+                libsm6:i386 \
+                libssl-dev \
+                libstdc++6:i386 \
+                libxext6:i386 \
+                libxft2:i386 \
+                libxrender1 \
+                libzmq3-dev \
+                libxext6:i386 \
+                libxrender-dev:i386 \
+                locales \
+                make \
+                openjdk-8-jdk \
+                pkg-config \
+                unixodbc-dev \
+                wget \
+                xauth \
+                xvfb \
+		net-tools \
+                x11-apps \
+                aptitude \
+                vim \
+                sudo \
+                firefox
+
+# Setup environment defaults.
+RUN echo "en_US.UTF-8 UTF-8" >> /etc/locale.gen && locale-gen
+ENV LANG en_US.UTF-8
+ENV LANGUAGE en_US:en
+ENV LC_ALL en_US.UTF-8
+ENV EXEC_DIR ${INSTALLATION_DIR}
+
+#
+# UNCOMMENT PRODUCTION OR DEVELOPMENT ACCORDING TO REQUIREMENTS. 
+#
+
+# PRODUCTION CYCLE, fetch files from Altera as needed.
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS}
+#RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_UPDATE}"
+#RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_UPDATE}/${QUARTUS_UPDATE}
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_PROGRAMMER}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_PROGRAMMER}
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_HELP}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_HELP}
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_LINUX_SUPPORT_BIN}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_LINUX_SUPPORT_BIN}
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_LINUX_SUPPORT_SRC}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_LINUX_SUPPORT_SRC}
+RUN for DEVICE_FILE in ${QUARTUS_DEVICE_FILES}; \
+		do \
+		    echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${DEVICE_FILE}"; \
+		    wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${DEVICE_FILE}; \
+		done
+
+# DEVELOPMENT CYCLE, quartus files cached locally.
+#COPY ./files/13.0/*.qdz ${TARGET_DOWNLOAD_DIR}
+#COPY ./files/13.0/*.run ${TARGET_DOWNLOAD_DIR}
+
+# Install Quartus.
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS}
+#RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_UPDATE}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_PROGRAMMER}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_HELP}
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS}            --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+#RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_UPDATE}     --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_PROGRAMMER} --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_HELP}       --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+
+# Copy the license file, this would be a dummy for the Lite version or a genuine one for the Standard version coded to the host
+# MAC Address.
+COPY ./files/license.dat                ${INSTALLATION_DIR}/
+
+# Copy quartus config files to enable the license.
+COPY ./files/quartus2.*                 /root/.altera.quartus/
+COPY ./files/quartus_web_rules_file.txt /root/.altera.quartus/
+
+# Copy the Arrow USB Blaster and setup the udev rules to detect and mount USB-Blaster I and II devices.
+COPY ./files/libjtag_hw_arrow.so        ${INSTALLATION_DIR}/quartus/linux64/
+COPY ./files/70-usb.rules               /etc/udev/rules.d/
+
+# Setup necessary environment variables.
+RUN echo "export PATH=\$PATH:${INSTALLATION_DIR}/quartus/bin:${INSTALLATION_DIR}/qprogrammer/bin" >> /root/.bashrc
+RUN echo "export LM_LICENSE_FILE=${INSTALLATION_DIR}/license.dat" >> /root/.bashrc
+
+# Clean up, removing unnecessary installation files.
+RUN rm -rf ${TARGET_DOWNLOAD_DIR}/* ${INSTALLATION_DIR}/uninstall ${INSTALLATION_DIR}/logs/*
+
+# Add the current user into the image.
+ARG user_uid
+ARG user_gid
+ARG user_name
+RUN groupadd -g $user_uid $user_name
+RUN adduser --uid $user_uid --gid $user_gid --disabled-password --gecos $user_name --home /home/$user_name $user_name
+
+# Start Quartus
+CMD ${EXEC_DIR}/quartus/bin/quartus --64bit

docker/QuartusPrime/Dockerfile.13.1

@@ -0,0 +1,168 @@
+#########################################################################################################
+##
+## Name:            Dockerfile.13.1.1
+## Created:         June 2020
+## Author(s):       Philip Smart
+## Description:     A Docker build script to create an Ubuntu 16.04 OS with Quartus Prime 13.1
+##
+## Credits:         
+## Copyright:       (c) 2019 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2019   - Initial module written.
+##                  June 2020     - Need to use a CPLD MAX series device which is only supported in 
+##                                  Quartus 13.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+# Ubuntu 16.04 as the base.
+FROM ubuntu:xenial
+
+# Maintainer!
+MAINTAINER Philip Smart <philip.smart@net2net.org>
+
+# Set build time environment variables.
+ENV DEBIAN_FRONTEND=noninteractive
+
+# Set constants for the build, more simpler to adjust these than the script if you want to change Quartus version.
+# Uncomment one of the QUARTUS= arguments below depending on wether your using the LITE or STANDARD version of Quartus.
+ARG TARGET_DOWNLOAD_DIR=/tmp/
+ARG INSTALLATION_DIR=/opt/altera
+ARG ALTERA_DOWNLOAD_SITE=http://download.altera.com/akdlm/software/acdsinst
+ARG QUARTUS_VERSION_INSTALLER=/13.1/162/ib_installers/
+ARG QUARTUS_VERSION_UPDATE=/13.1.0/162/update/
+ARG QUARTUS=QuartusSetup-13.1.0.162.run
+#ARG QUARTUS=QuartusLiteSetup-13.1.0.162.run
+ARG QUARTUS_UPDATE=QuartusSetup-13.1.0.162.run
+ARG QUARTUS_PROGRAMMER=QuartusProgrammerSetup-13.1.0.162.run
+ARG QUARTUS_HELP=QuartusHelpSetup-13.1.0.162.run
+ARG QUARTUS_DEVICE_FILES="arria-13.1.0.162 arriav-13.1.0.162 arriavgz-13.1.0.162 arria_web-13.1.0.162 cyclone-13.1.0.162 cyclonev-13.1.0.162 cyclone_web-13.1.0.162 max-13.1.0.162 max-17.1.0.590 max_web-13.1.0.162 stratixv-13.1.0.162"
+
+
+# Base Ubuntu install, add necessary packages for Quartus, command line editting and web-browser.
+RUN dpkg --add-architecture i386
+RUN apt-get update 
+RUN apt-get install --no-install-recommends -y \
+                ca-certificates \
+                libstdc++6:i386 \
+                libc6:i386 \
+                libx11-dev:i386 \
+                libxext-dev:i386 \
+                libxau-dev:i386 \
+                libxdmcp-dev:i386 \
+                libfreetype6:i386 \
+                libxtst6:i386 \
+                libxi6:i386 \
+                fontconfig:i386 \
+                expat:i386 \
+                lib32ncurses5-dev \
+                libc6:i386 \
+                libcrypto++9v5 \
+                libfontconfig1 \
+                libglib2.0-0 \
+                libncurses5:i386 \
+                libsm6 \
+                libsm6:i386 \
+                libssl-dev \
+                libstdc++6:i386 \
+                libxext6:i386 \
+                libxft2:i386 \
+                libxrender1 \
+                libzmq3-dev \
+                libxext6:i386 \
+                libxrender-dev:i386 \
+                locales \
+                make \
+                openjdk-8-jdk \
+                pkg-config \
+                unixodbc-dev \
+                wget \
+                xauth \
+                xvfb \
+		net-tools \
+                x11-apps \
+                aptitude \
+                vim \
+                sudo \
+                firefox
+
+# Setup environment defaults.
+RUN echo "en_US.UTF-8 UTF-8" >> /etc/locale.gen && locale-gen
+ENV LANG en_US.UTF-8
+ENV LANGUAGE en_US:en
+ENV LC_ALL en_US.UTF-8
+ENV EXEC_DIR ${INSTALLATION_DIR}
+
+#
+# UNCOMMENT PRODUCTION OR DEVELOPMENT ACCORDING TO REQUIREMENTS. 
+#
+
+# PRODUCTION CYCLE, fetch files from Altera as needed.
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS}
+#RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_UPDATE}"
+#RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_UPDATE}/${QUARTUS_UPDATE}
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_PROGRAMMER}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_PROGRAMMER}
+RUN echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_HELP}"
+RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_HELP}
+RUN for DEVICE_FILE in ${QUARTUS_DEVICE_FILES}; \
+		do \
+		    echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${DEVICE_FILE}"; \
+		    wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${DEVICE_FILE}; \
+		done
+
+# DEVELOPMENT CYCLE, quartus files cached locally.
+#COPY ./files/13.1/*.qdz ${TARGET_DOWNLOAD_DIR}
+#COPY ./files/13.1/*.run ${TARGET_DOWNLOAD_DIR}
+
+# Install Quartus.
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS}
+#RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_UPDATE}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_PROGRAMMER}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_HELP}
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS}            --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+#RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_UPDATE}     --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_PROGRAMMER} --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_HELP}       --mode unattended --installdir ${INSTALLATION_DIR}/ #--accept_eula 1
+
+# Copy the license file, this would be a dummy for the Lite version or a genuine one for the Standard version coded to the host
+# MAC Address.
+COPY ./files/license.dat                ${INSTALLATION_DIR}/
+
+# Copy quartus config files to enable the license.
+COPY ./files/quartus2.*                 /root/.altera.quartus/
+COPY ./files/quartus_web_rules_file.txt /root/.altera.quartus/
+
+# Copy the Arrow USB Blaster and setup the udev rules to detect and mount USB-Blaster I and II devices.
+COPY ./files/libjtag_hw_arrow.so        ${INSTALLATION_DIR}/quartus/linux64/
+COPY ./files/70-usb.rules               /etc/udev/rules.d/
+
+# Setup necessary environment variables.
+RUN echo "export PATH=\$PATH:${INSTALLATION_DIR}/quartus/bin:${INSTALLATION_DIR}/qprogrammer/bin" >> /root/.bashrc
+RUN echo "export LM_LICENSE_FILE=${INSTALLATION_DIR}/license.dat" >> /root/.bashrc
+
+# Clean up, removing unnecessary installation files.
+RUN rm -rf ${TARGET_DOWNLOAD_DIR}/* ${INSTALLATION_DIR}/uninstall ${INSTALLATION_DIR}/logs/*
+
+# Add the current user into the image.
+ARG user_uid
+ARG user_gid
+ARG user_name
+RUN groupadd -g $user_uid $user_name
+RUN adduser --uid $user_uid --gid $user_gid --disabled-password --gecos $user_name --home /home/$user_name $user_name
+
+# Start Quartus
+CMD ${EXEC_DIR}/quartus/bin/quartus --64bit

docker/QuartusPrime/Dockerfile.17.1.1

@@ -0,0 +1,167 @@
+#########################################################################################################
+##
+## Name:            Dockerfile.17.1.1
+## Created:         August 2019
+## Author(s):       Philip Smart
+## Description:     A Docker build script to create an Ubuntu 16.04 OS with Quartus Prime 17.1.1
+##
+## Credits:         
+## Copyright:       (c) 2019 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2019   - Initial module written.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+
+# Ubuntu 16.04 as the base.
+FROM ubuntu:xenial
+
+# Maintainer!
+MAINTAINER Philip Smart <philip.smart@net2net.org>
+
+# Set build time environment variables.
+ENV DEBIAN_FRONTEND=noninteractive
+
+# Set constants for the build, more simpler to adjust these than the script if you want to change Quartus version.
+# Uncomment one of the QUARTUS= arguments below depending on wether your using the LITE or STANDARD version of Quartus.
+ARG TARGET_DOWNLOAD_DIR=/tmp/
+ARG INSTALLATION_DIR=/opt/altera
+ARG ALTERA_DOWNLOAD_SITE=http://download.altera.com/akdlm/software/acdsinst
+ARG QUARTUS_VERSION_INSTALLER=/17.1std/590/ib_installers/
+ARG QUARTUS_VERSION_UPDATE=/17.1std.1/593/update/
+ARG QUARTUS=QuartusSetup-17.1.0.590-linux.run
+#ARG QUARTUS=QuartusLiteSetup-17.1.0.590-linux.run
+ARG QUARTUS_UPDATE=QuartusSetup-17.1.1.593-linux.run
+ARG QUARTUS_PROGRAMMER=QuartusProgrammerSetup-17.1.0.590-linux.run
+ARG QUARTUS_HELP=QuartusHelpSetup-17.1.0.590-linux.run
+ARG QUARTUS_DEVICE_FILES="arria_lite-17.1.0.590.qdz cyclone10lp-17.1.0.590.qdz cyclone-17.1.0.590.qdz cyclonev-17.1.0.590.qdz max10-17.1.0.590.qdz max-17.1.0.590.qdz"
+
+# Base Ubuntu install, add necessary packages for Quartus, command line editting and web-browser.
+RUN dpkg --add-architecture i386
+RUN apt-get update 
+RUN apt-get install --no-install-recommends -y \
+                ca-certificates \
+                libstdc++6:i386 \
+                libc6:i386 \
+                libx11-dev:i386 \
+                libxext-dev:i386 \
+                libxau-dev:i386 \
+                libxdmcp-dev:i386 \
+                libfreetype6:i386 \
+                libxtst6:i386 \
+                libxi6:i386 \
+                fontconfig:i386 \
+                expat:i386 \
+                lib32ncurses5-dev \
+                libc6:i386 \
+                libcrypto++9v5 \
+                libfontconfig1 \
+                libglib2.0-0 \
+                libncurses5:i386 \
+                libsm6 \
+                libsm6:i386 \
+                libssl-dev \
+                libstdc++6:i386 \
+                libxext6:i386 \
+                libxft2:i386 \
+                libxrender1 \
+                libzmq3-dev \
+                libxext6:i386 \
+                libxrender-dev:i386 \
+                locales \
+                make \
+                openjdk-8-jdk \
+                pkg-config \
+                unixodbc-dev \
+                wget \
+                xauth \
+                xvfb \
+		net-tools \
+                x11-apps \
+                aptitude \
+                vim \
+                sudo \
+                firefox
+
+# Setup environment defaults.
+RUN echo "en_US.UTF-8 UTF-8" >> /etc/locale.gen && locale-gen
+ENV LANG en_US.UTF-8
+ENV LANGUAGE en_US:en
+ENV LC_ALL en_US.UTF-8
+ENV EXEC_DIR ${INSTALLATION_DIR}
+
+#
+# UNCOMMENT PRODUCTION OR DEVELOPMENT ACCORDING TO REQUIREMENTS. 
+#
+
+# PRODUCTION CYCLE, fetch files from Altera as needed.
+#RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS}
+#RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_UPDATE}/${QUARTUS_UPDATE}
+#RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_PROGRAMMER}
+#RUN wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${QUARTUS_HELP}
+#RUN for DEVICE_FILE in ${QUARTUS_DEVICE_FILES}; \
+#		do \
+#		    echo "Fetching ${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${DEVICE_FILE}"; \
+#		    wget -q --directory-prefix=${TARGET_DOWNLOAD_DIR} ${ALTERA_DOWNLOAD_SITE}/${QUARTUS_VERSION_INSTALLER}/${DEVICE_FILE}; \
+#		done
+
+# DEVELOPMENT CYCLE, quartus files cached locally.
+COPY ./files/17.1/*.qdz ${TARGET_DOWNLOAD_DIR}
+COPY ./files/17.1/*.run ${TARGET_DOWNLOAD_DIR}
+
+# Install Quartus.
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_UPDATE}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_PROGRAMMER}
+RUN chmod +x ${TARGET_DOWNLOAD_DIR}${QUARTUS_HELP}
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS}            --mode unattended --installdir ${INSTALLATION_DIR}/ --accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_UPDATE}     --mode unattended --installdir ${INSTALLATION_DIR}/ --accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_PROGRAMMER} --mode unattended --installdir ${INSTALLATION_DIR}/ --accept_eula 1
+RUN ${TARGET_DOWNLOAD_DIR}${QUARTUS_HELP}       --mode unattended --installdir ${INSTALLATION_DIR}/ --accept_eula 1
+
+# Copy the license file, this would be a dummy for the Lite version or a genuine one for the Standard version coded to the host
+# MAC Address.
+COPY ./files/license.dat                ${INSTALLATION_DIR}/
+
+# Copy quartus config files to enable the license.
+COPY ./files/quartus2.*                 /root/.altera.quartus/
+COPY ./files/quartus_web_rules_file.txt /root/.altera.quartus/
+
+# Copy the Arrow USB Blaster and setup the udev rules to detect and mount USB-Blaster I and II devices.
+COPY ./files/libjtag_hw_arrow.so        ${INSTALLATION_DIR}/quartus/linux64/
+COPY ./files/70-usb.rules               /etc/udev/rules.d/
+
+# Local upgrades.
+COPY local/17.1/license.dat             ${INSTALLATION_DIR}/
+COPY local/17.1/libsys_cpt.so           ${INSTALLATION_DIR}/quartus/linux64/
+COPY local/17.1/libgcl_afcq.so          ${INSTALLATION_DIR}/quartus/linux64/
+
+# Setup necessary environment variables.
+RUN echo "export PATH=\$PATH:${INSTALLATION_DIR}/quartus/bin:${INSTALLATION_DIR}/qprogrammer/bin" >> /root/.bashrc
+RUN echo "export LM_LICENSE_FILE=${INSTALLATION_DIR}/license.dat" >> /root/.bashrc
+
+# Clean up, removing unnecessary installation files.
+RUN rm -rf ${TARGET_DOWNLOAD_DIR}/* ${INSTALLATION_DIR}/uninstall ${INSTALLATION_DIR}/logs/*
+#
+# Add the current user into the image.
+ARG user_uid
+ARG user_gid
+ARG user_name
+RUN groupadd -g $user_uid $user_name
+RUN adduser --uid $user_uid --gid $user_gid --disabled-password --gecos $user_name --home /home/$user_name $user_name
+
+# Start Quartus
+CMD ${EXEC_DIR}/quartus/bin/quartus --64bit

docker/QuartusPrime/files/70-usb.rules

@@ -0,0 +1,13 @@
+===
+# USB-Blaster 
+SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster/%k" 
+SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6002", MODE="0666", SYMLINK+="usbblaster/%k" 
+SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6003", MODE="0666", SYMLINK+="usbblaster/%k" 
+ 
+# USB-Blaster II 
+SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="0666", SYMLINK+="usbblaster2/%k" 
+SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="0666", SYMLINK+="usbblaster2/%k" 
+=== 
+
+# Arrow-USB-Blaster
+SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="0666", SYMLINK+="usbblasterarrow/%k"

docker/QuartusPrime/files/license.dat

@@ -0,0 +1 @@
+# Place your license in this file.

docker/QuartusPrime/files/quartus2.ini

@@ -0,0 +1,4 @@
+
+[General 17.1]
+LICENSE_FILE = /opt/altera/license.dat
+WAIT_FOR_LICENSE = off

docker/QuartusPrime/files/quartus2.qreg

@@ -0,0 +1,172 @@
+[17.1]
+Registry_version=27
+Altera_Foundation_Class\quartusQuartus_Prime_17.1_Lite_EditionDialogGeometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\f\x17\0\0\x6\xb8\0\0\xe\xf5\0\0\a\xc8\0\0\f\x17\0\0\x6\xb8\0\0\xe\xf5\0\0\a\xc8\0\0\0\0\0\0)
+Toolbar\Large_icons=true
+Quartus_UI_Framework\startup_failed=No
+Messages\id_column_in_quartus_12_1_and_later=true
+General\Check_for_New_Info_Message_at_Startup=Yes
+General\Confirm_Before_Connect_to_Internet=No
+General\Current_Message_Release_Number=0
+General\TalkForward_Message_URL=
+General\quartusShow_welcome_screen=true
+General\quartusClose_welcome_screen_after_project_load=true
+General\Tooltip_enable=true
+General\Tooltip_interval=5
+General\Tooltip_hide_interval=1
+Chip_Viewer\Tooltip_enable=true
+Chip_Viewer\Tooltip_interval=5
+Chip_Viewer\Tooltip_hide_interval=1
+Logical_Floorplan\Tooltip_enable=true
+Logical_Floorplan\Tooltip_interval=5
+Logical_Floorplan\Tooltip_hide_interval=1
+Atom_Property_Editor\Tooltip_enable=true
+Atom_Property_Editor\Tooltip_interval=5
+Atom_Property_Editor\Tooltip_hide_interval=1
+RTL_Viewer\Tooltip_enable=true
+RTL_Viewer\Tooltip_Interval=5
+RTL_Viewer\Tooltip_Hide_Interval=1
+State_Machine_Viewer\Tooltip_enable=true
+State_Machine_Viewer\Tooltip_Interval=5
+State_Machine_Viewer\Tooltip_Hide_Interval=1
+Pin_Planner\Tooltip_enable=true
+Pin_Planner\Tooltip_interval=5
+Pin_Planner\Tooltip_hide_interval=1
+Altera_Foundation_Class\quartusOptionsDialogGeometry="@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\x3;\0\0\x1r\0\0\b\xb2\0\0\x4\x91\0\0\x3;\0\0\x1r\0\0\b\xb2\0\0\x4\x91\0\0\0\x2\0\0)"
+Altera_Foundation_Class\quartusSelect_FileFileDialogGeometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\b\x8a\0\0\x1y\0\0\v\x4\0\0\x3/\0\0\b\x8a\0\0\x1y\0\0\v\x4\0\0\x3/\0\0\0\x2\0\0)
+Quartus_UI_Framework\quartussld_bnlqmdiGeometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\x2p\0\0\0W\0\0\x6.\0\0\x2\xc4\0\0\x2p\0\0\0m\0\0\x6.\0\0\x2\xc4\0\0\0\x2\0\0)
+Quartus_UI_Framework\quartussld_bnlqmdiState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x3\xbf\0\0\x2\x1f\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\0&\0L\0\x65\0\x66\0t\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\x2\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0\x46\0\x65\0\x65\0\x64\0\x62\0\x61\0\x63\0k\x2\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0(\0R\0i\0g\0h\0t\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\x2\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0$\0T\0o\0p\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\0\x1\0\0\0*\0\x42\0o\0t\0t\0o\0m\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+Quartus_UI_Framework\quartussld_atcqmdiGeometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\xf7\0\0\0Z\0\0\x4\x16\0\0\x2\xc7\0\0\0\xf7\0\0\0p\0\0\x4\x16\0\0\x2\xc7\0\0\0\x2\0\0)
+Quartus_UI_Framework\quartussld_atcqmdiState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x3 \0\0\x2\x1f\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\0&\0L\0\x65\0\x66\0t\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\x2\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0\x46\0\x65\0\x65\0\x64\0\x62\0\x61\0\x63\0k\x2\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0(\0R\0i\0g\0h\0t\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\x2\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0$\0T\0o\0p\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\0\x1\0\0\0*\0\x42\0o\0t\0t\0o\0m\0 \0\x42\0u\0t\0t\0o\0n\0 \0T\0o\0o\0l\0\x62\0\x61\0r\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+Altera_Foundation_Class\quartusOpen_ProjectFileDialogGeometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\x2\xc9\0\0\x1\r\0\0\x5\x43\0\0\x2\xc3\0\0\x2\xc9\0\0\x1\r\0\0\x5\x43\0\0\x2\xc3\0\0\0\x2\0\0)
+Quartus_UI_Framework\quartusQuartus_Primedock_widget0=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget0Area=8
+Quartus_UI_Framework\quartusQuartus_Primedock_widget0Floating=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget0Pinned=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget0Minimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget0Closed=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget1=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget1Area=1
+Quartus_UI_Framework\quartusQuartus_Primedock_widget1Floating=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget1Pinned=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget1Minimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget1Closed=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget2=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget2Area=1
+Quartus_UI_Framework\quartusQuartus_Primedock_widget2Floating=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget2Pinned=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget2Minimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget2Closed=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget3=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget3Area=8
+Quartus_UI_Framework\quartusQuartus_Primedock_widget3Floating=false
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+Quartus_UI_Framework\quartusQuartus_Primedock_widget3Minimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget3Closed=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget4=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget4Area=1
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+Quartus_UI_Framework\quartusQuartus_Primedock_widget4Minimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widget4Closed=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget5=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widget5Area=1
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+Quartus_UI_Framework\quartusQuartus_Primedock_widget5Closed=false
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+Quartus_UI_Framework\current_project=
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+Quartus_UI_Framework\quartusQuartus_Primedock_widgetProject_Navigator=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetProject_NavigatorArea=1
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetProject_NavigatorFloating=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetProject_NavigatorPinned=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetProject_NavigatorMinimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetProject_NavigatorClosed=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTasks=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTasksArea=1
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTasksFloating=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTasksPinned=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTasksMinimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTasksClosed=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetIP_Catalog=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetIP_CatalogArea=2
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetIP_CatalogFloating=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetIP_CatalogPinned=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetIP_CatalogMinimized=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetIP_CatalogClosed=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetNode_Finder=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetNode_FinderArea=1
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetNode_FinderFloating=true
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+Quartus_UI_Framework\quartusQuartus_Primedock_widgetNode_FinderClosed=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTcl_Console=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTcl_ConsoleArea=8
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+Quartus_UI_Framework\quartusQuartus_Primedock_widgetTcl_ConsoleClosed=true
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetStatus=false
+Quartus_UI_Framework\quartusQuartus_Primedock_widgetStatusArea=1
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+Quartus_UI_Framework\quartusQuartus_Primedock_widgetStatusClosed=true
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+Quartus_UI_Framework\quartusQuartus_Primedock_widgetLogic_Lock_Regions_WindowArea=8
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+Task_Manager_Window\Task_Manager_File=tmwq_tasks_compile.tmf
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docker/QuartusPrime/run_quartus.sh

@@ -0,0 +1,69 @@
+#!/bin/bash -x
+#########################################################################################################
+##
+## Name:            run_quartus.sh
+## Created:         August 2019
+## Author(s):       Philip Smart
+## Description:     A shell script to start the Quartus Prime Docker image.
+##
+## Credits:         
+## Copyright:       (c) 2019 Philip Smart <philip.smart@net2net.org>
+##
+## History:         August 2019   - Initial module written.
+##
+#########################################################################################################
+## This source file is free software: you can redistribute it and#or modify
+## it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This source file is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#########################################################################################################
+
+# Configurable parameters. The MAC_ADDRESS is needed if you are using a licensed Quartus as it uses the hostid which is the mac address.
+# Set a default for the X-Display if the environment hasnt set it.
+#
+MAC_ADDR="02:50:dd:72:03:01"
+PROJECT_DIR_HOST=/srv/quartus
+PROJECT_DIR_IMAGE=/srv/quartus
+DISPLAY=${DISPLAY:-192.168.15.210:0}
+VERSION=$1
+
+if [ "${VERSION}" = "17.1.1" -o "X${VERSION}" = "X" ]; then
+    VERSION=17.1.1
+elif [ "${VERSION}" != "13.0.1" -a "${VERSION}" != "13.1" ]; then
+    echo "Unknown QuartusII version:$1"
+fi
+# In order to get X-Forwarding from the container, we need to update the X Authorities and bind the authorisation file inside the virtual machine.
+XSOCK=/tmp/.X11-unix
+XAUTH=/tmp/.docker.xauth
+NLIST=`xauth nlist $DISPLAY | sed -e 's/^..../ffff/'`
+if [ "${NLIST}" != "" ]; then
+    echo ${NLIST} | xauth -f $XAUTH nmerge -
+fi
+chmod 777 $XAUTH
+
+# Run the Ubuntu hosted Quartus Prime service.
+docker run --rm \
+		   --mac-address "${MAC_ADDR}" \
+		   --env DISPLAY=${DISPLAY} \
+		   --ipc=host \
+		   --env XAUTHORITY=${XAUTH} \
+		   --privileged \
+		   --volume /dev:/dev \
+		   --volume ${PROJECT_DIR_HOST}:${PROJECT_DIR_IMAGE} \
+		   --volume ${XAUTH}:${XAUTH} \
+		   --volume ${XSOCK}:${XSOCK} \
+		   --volume /sys:/sys:ro \
+		   --name quartus${VERSION} \
+		   quartus-ii-${VERSION} &
+
+# Bring up a terminal session for any local changes.
+sleep 5
+docker exec -it quartus${VERSION} bash

license.txt

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received.  You must make sure that they, too, receive
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+know their rights.
+
+  Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+  For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software.  For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
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+
+  Some devices are designed to deny users access to install or run
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+States should not allow patents to restrict development and use of
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+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+                       TERMS AND CONDITIONS
+
+  0. Definitions.
+
+  "This License" refers to version 3 of the GNU General Public License.
+
+  "Copyright" also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+  "The Program" refers to any copyrightable work licensed under this
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+  A "covered work" means either the unmodified Program or a work based
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+
+  To "propagate" a work means to do anything with it that, without
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+  To "convey" a work means any kind of propagation that enables other
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+feature that (1) displays an appropriate copyright notice, and (2)
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+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License.  If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+  1. Source Code.
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+  The "source code" for a work means the preferred form of the work
+for making modifications to it.  "Object code" means any non-source
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+produce the work, or an object code interpreter used to run it.
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+  The "Corresponding Source" for a work in object code form means all
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+programs which are used unmodified in performing those activities but
+which are not part of the work.  For example, Corresponding Source
+includes interface definition files associated with source files for
+the work, and the source code for shared libraries and dynamically
+linked subprograms that the work is specifically designed to require,
+such as by intimate data communication or control flow between those
+subprograms and other parts of the work.
+
+  The Corresponding Source need not include anything that users
+can regenerate automatically from other parts of the Corresponding
+Source.
+
+  The Corresponding Source for a work in source code form is that
+same work.
+
+  2. Basic Permissions.
+
+  All rights granted under this License are granted for the term of
+copyright on the Program, and are irrevocable provided the stated
+conditions are met.  This License explicitly affirms your unlimited
+permission to run the unmodified Program.  The output from running a
+covered work is covered by this License only if the output, given its
+content, constitutes a covered work.  This License acknowledges your
+rights of fair use or other equivalent, as provided by copyright law.
+
+  You may make, run and propagate covered works that you do not
+convey, without conditions so long as your license otherwise remains
+in force.  You may convey covered works to others for the sole purpose
+of having them make modifications exclusively for you, or provide you
+with facilities for running those works, provided that you comply with
+the terms of this License in conveying all material for which you do
+not control copyright.  Those thus making or running the covered works
+for you must do so exclusively on your behalf, under your direction
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+your copyrighted material outside their relationship with you.
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+  "Additional permissions" are terms that supplement the terms of this
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+                     END OF TERMS AND CONDITIONS
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+The hypothetical commands `show w' and `show c' should show the appropriate
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+
+  The GNU General Public License does not permit incorporating your program
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+<https://www.gnu.org/licenses/why-not-lgpl.html>.

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