Added schematics, kicad and pcb gerber files
This commit is contained in:
Philip Smart
@@ -131,7 +131,7 @@ architecture rtl of VideoController is
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-- H_DSP_START, H_DSP_END, H_DSP_WND_START, H_DSP_WND_END, V_DSP_START, V_DSP_END, V_DSP_WND_START, V_DSP_WND_END, H_LINE_END, V_LINE_END, MAX_COLUMNS, H_SYNC_START, H_SYNC_END, V_SYNC_START, V_SYNC_END, H_POLARITY, V_POLARITY, H_PX, V_PX
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( 0, 320, 0, 320, 0, 200, 0, 200, 511, 259, 40, 320 + 43, 320 + 43 + 45, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 0 MZ80K/C/1200/A machines have a monochrome 60Hz display with scan of 512 x 260 for a 320x200 viewable area.
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( 0, 640, 0, 640, 0, 200, 0, 200, 1023, 259, 80, 640 + 106, 640 + 106 + 90, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 1 MZ80K/C/1200/A machines with an adapted monochrome 60Hz display with scan of 1024 x 260 for a 640x200 viewable area.
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--( 0, 320, 0, 320, 0, 200, 0, 200, 567, 311, 40, 320 + 80, 320 + 80 + 40, 200 + 50, 200 + 50 + 3, 0, 0, 0, 0), -- 2 MZ80K/C/1200/A machines with MZ700 style colour @ 50Hz display with scan of 568 x 312 for a 320x200 viewable area.
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--( 0, 320, 0, 320, 0, 200, 0, 200, 567, 311, 40, 320 + 80, 320 + 80 + 40, 200 + 50, 200 + 50 + 3, 0, 0, 0, 0), -- 2 MZ80K/C/1200/A machines with MZ700 style colour @ 50Hz display with scan of 568 x 312 for a 320x200 viewable area.
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--( 0, 640, 0, 640, 0, 200, 0, 200, 1135, 311, 80, 640 + 160, 640 + 160 + 80, 200 + 50, 200 + 50 + 3, 0, 0, 0, 0), -- 3 MZ80K/C/1200/A machines with MZ700 style colour @ 50Hz display with scan of 1136 x 312 for a 640x200 viewable area.
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( 0, 320, 0, 320, 0, 200, 0, 200, 567, 259, 40, 320 + 80, 320 + 80 + 40, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 2 MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display with scan of 512 x 260 for a 320x200 viewable area.
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( 0, 640, 0, 640, 0, 200, 0, 200, 1135, 259, 80, 640 + 160, 640 + 160 + 80, 200 + 19, 200 + 19 + 4, 0, 0, 0, 0), -- 3 MZ80K/C/1200/A machines with MZ700 style colour @ 60Hz display with scan of 1024 x 260 for a 640x200 viewable area.
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@@ -238,6 +238,10 @@ architecture rtl of VideoController is
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signal MODE_CPLD_SWITCH : std_logic := '1'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the machine mode has changed. Flag is active for 1 clock cycle.
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signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register.
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signal DSP_PARAM_SEL : std_logic_vector(3 downto 0); -- Display parameter selection register.
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signal DSP_PARAM_DATA : unsigned(7 downto 0); -- Video parameter update data.
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signal DSP_PARAM_UPD : std_logic; -- Flag to indicate parameter update data is available.
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signal DSP_PARAM_ADDR : std_logic; -- Video parameter address to update.
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signal DSP_PARAM_CLR : std_logic; -- Flag to indicate parameter update data processed and can be cleared.
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signal PALETTE_PARAM_SEL : std_logic_vector(8 downto 0); -- Palette parameter selection register.
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signal PALETTE_DO_R : std_logic_vector(4 downto 0); -- Read Red palette output.
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signal PALETTE_DO_G : std_logic_vector(4 downto 0); -- Read Green palette output.
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@@ -306,6 +310,7 @@ architecture rtl of VideoController is
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signal GPU_COMMAND : std_logic_vector(7 downto 0); -- GPU command register.
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signal GPU_STATUS : std_logic_vector(7 downto 0); -- GPU Status register.
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signal GPU_STATE : GPUStateType; -- GPU FSM State.
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signal GPU_START_ADDR : std_logic_vector(13 downto 0); -- Address being worked on by the GPU.
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signal Z80_MA : std_logic_vector(11 downto 0); -- CPU Address Masked according to machine model.
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signal CS_INVERTn : std_logic; -- Chip Select to enable Inverse mode.
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signal CS_SCROLLn : std_logic; -- Chip Select to perform a hardware scroll.
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@@ -468,11 +473,12 @@ begin
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width_a => 5,
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widthad_b => 9,
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width_b => 5,
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outdata_reg_b => "UNREGISTERED"
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outdata_reg_a => "CLOCK0",
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outdata_reg_b => "CLOCK1"
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)
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PORT MAP (
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-- Port A used for CPU access.
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clock_a => VID_CLK,
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clock_a => SYS_CLK,
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clocken_a => '1',
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address_a => PALETTE_PARAM_SEL,
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data_a => VDATA(4 downto 0),
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@@ -494,11 +500,12 @@ begin
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width_a => 5,
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widthad_b => 9,
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width_b => 5,
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outdata_reg_b => "UNREGISTERED"
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outdata_reg_a => "CLOCK0",
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outdata_reg_b => "CLOCK1"
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)
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PORT MAP (
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-- Port A used for CPU access.
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clock_a => VID_CLK,
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clock_a => SYS_CLK,
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clocken_a => '1',
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address_a => PALETTE_PARAM_SEL,
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data_a => VDATA(4 downto 0),
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@@ -520,11 +527,12 @@ begin
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width_a => 5,
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widthad_b => 9,
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width_b => 5,
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outdata_reg_b => "UNREGISTERED"
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outdata_reg_a => "CLOCK0",
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outdata_reg_b => "CLOCK1"
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)
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PORT MAP (
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-- Port A used for CPU access.
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clock_a => VID_CLK,
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clock_a => SYS_CLK,
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clocken_a => '1',
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address_a => PALETTE_PARAM_SEL,
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data_a => VDATA(4 downto 0),
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@@ -551,11 +559,12 @@ begin
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width_a => 8,
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widthad_b => 11,
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width_b => 16,
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED"
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)
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PORT MAP (
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-- Port A used for CPU access.
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clock_a => not SYS_CLK,
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clock_a => SYS_CLK,
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clocken_a => '1',
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address_a => VRAM_ADDR(10 downto 0) & VRAM_ADDR(11),
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data_a => VRAM_DI,
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@@ -581,6 +590,7 @@ begin
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width_a => 8,
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widthad_b => 14,
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width_b => 8,
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED"
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)
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PORT MAP (
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@@ -611,6 +621,7 @@ begin
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width_a => 8,
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widthad_b => 14,
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width_b => 8,
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED"
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)
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PORT MAP (
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@@ -642,6 +653,7 @@ begin
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width_a => 8,
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widthad_b => 14,
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width_b => 8,
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED"
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)
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PORT MAP (
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@@ -671,7 +683,9 @@ begin
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widthad_a => 12,
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width_a => 8,
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widthad_b => 12,
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width_b => 8
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width_b => 8,
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED"
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)
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PORT MAP (
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clock_a => SYS_CLK,
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@@ -698,10 +712,11 @@ begin
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widthad_a => 12,
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width_a => 8,
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widthad_b => 12,
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width_b => 8
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width_b => 8,
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outdata_reg_a => "UNREGISTERED"
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)
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PORT MAP (
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clock_a => VID_CLK,
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clock_a => SYS_CLK,
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clocken_a => '1',
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address_a => CG_ADDR(11 downto 0),
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data_a => CGRAM_DI,
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@@ -1241,6 +1256,7 @@ begin
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VIDEOMODE <= 0;
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VIDEOMODE_RESET_TIMER <= (others => '1');
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VIDCLK_DIV <= '0';
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DSP_PARAM_CLR <= '0';
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elsif rising_edge(VID_CLK) then
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@@ -1315,91 +1331,93 @@ begin
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--
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elsif VIDCLK_DIV = '1' then
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-- Parameter update handshake. Clear the flag when the Z80 domain has cleared its flag.
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if DSP_PARAM_CLR = '1' and DSP_PARAM_UPD = '0' then
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DSP_PARAM_CLR <= '0';
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end if;
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-- Ability to adjust the video parameter registers to tune or override the default values from the lookup table. This can be useful in debugging,
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-- adjusting to a new monitor etc.
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--
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if CS_IO_DXXn = '0' and VZ80_WRn = '0' then
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-- The actual data is captured in the Z80 clock domain and passed/synchronised to this multi-clock domain via internal hand shaked registers.
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--
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if DSP_PARAM_UPD = '1' and DSP_PARAM_CLR = '0' then
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case VADDR(3 downto 0) is
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-- 0xD0 - Set the parameter number to update.
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when "0000" =>
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DSP_PARAM_SEL <= VDATA(3 downto 0);
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-- 0xD1 - Update the lower selected parameter byte.
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when "0001" =>
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if DSP_PARAM_ADDR = '0' then
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case DSP_PARAM_SEL is
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when "0000" =>
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H_DSP_START(7 downto 0) <= unsigned(VDATA);
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H_DSP_START(7 downto 0) <= DSP_PARAM_DATA;
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when "0001" =>
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H_DSP_END(7 downto 0) <= unsigned(VDATA);
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H_DSP_END(7 downto 0) <= DSP_PARAM_DATA;
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when "0010" =>
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H_DSP_WND_START(7 downto 0) <= unsigned(VDATA);
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H_DSP_WND_START(7 downto 0) <= DSP_PARAM_DATA;
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when "0011" =>
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H_DSP_WND_END(7 downto 0) <= unsigned(VDATA);
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H_DSP_WND_END(7 downto 0) <= DSP_PARAM_DATA;
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when "0100" =>
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V_DSP_START(7 downto 0) <= unsigned(VDATA);
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V_DSP_START(7 downto 0) <= DSP_PARAM_DATA;
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when "0101" =>
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V_DSP_END(7 downto 0) <= unsigned(VDATA);
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V_DSP_END(7 downto 0) <= DSP_PARAM_DATA;
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when "0110" =>
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V_DSP_WND_START(7 downto 0) <= unsigned(VDATA);
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V_DSP_WND_START(7 downto 0) <= DSP_PARAM_DATA;
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when "0111" =>
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V_DSP_WND_END(7 downto 0) <= unsigned(VDATA);
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V_DSP_WND_END(7 downto 0) <= DSP_PARAM_DATA;
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when "1000" =>
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H_LINE_END(7 downto 0) <= unsigned(VDATA);
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H_LINE_END(7 downto 0) <= DSP_PARAM_DATA;
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when "1001" =>
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V_LINE_END(7 downto 0) <= unsigned(VDATA);
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V_LINE_END(7 downto 0) <= DSP_PARAM_DATA;
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when "1010" =>
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MAX_COLUMN(7 downto 0) <= unsigned(VDATA);
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MAX_COLUMN(7 downto 0) <= DSP_PARAM_DATA;
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when "1011" =>
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H_SYNC_START(7 downto 0) <= unsigned(VDATA);
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H_SYNC_START(7 downto 0) <= DSP_PARAM_DATA;
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when "1100" =>
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H_SYNC_END(7 downto 0) <= unsigned(VDATA);
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H_SYNC_END(7 downto 0) <= DSP_PARAM_DATA;
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when "1101" =>
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V_SYNC_START(7 downto 0) <= unsigned(VDATA);
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V_SYNC_START(7 downto 0) <= DSP_PARAM_DATA;
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when "1110" =>
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V_SYNC_END(7 downto 0) <= unsigned(VDATA);
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V_SYNC_END(7 downto 0) <= DSP_PARAM_DATA;
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when "1111" =>
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H_PX(7 downto 0) <= unsigned(VDATA);
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H_PX(7 downto 0) <= DSP_PARAM_DATA;
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end case;
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else
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-- 0xD2 - Update the upper selected parameter byte.
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when "0010" =>
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case DSP_PARAM_SEL is
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when "0000" =>
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H_DSP_START(15 downto 8) <= unsigned(VDATA);
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H_DSP_START(15 downto 8) <= DSP_PARAM_DATA;
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when "0001" =>
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H_DSP_END(15 downto 8) <= unsigned(VDATA);
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H_DSP_END(15 downto 8) <= DSP_PARAM_DATA;
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when "0010" =>
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H_DSP_WND_START(15 downto 8) <= unsigned(VDATA);
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H_DSP_WND_START(15 downto 8) <= DSP_PARAM_DATA;
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when "0011" =>
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H_DSP_WND_END(15 downto 8) <= unsigned(VDATA);
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H_DSP_WND_END(15 downto 8) <= DSP_PARAM_DATA;
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when "0100" =>
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V_DSP_START(15 downto 8) <= unsigned(VDATA);
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V_DSP_START(15 downto 8) <= DSP_PARAM_DATA;
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when "0101" =>
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V_DSP_END(15 downto 8) <= unsigned(VDATA);
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V_DSP_END(15 downto 8) <= DSP_PARAM_DATA;
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when "0110" =>
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V_DSP_WND_START(15 downto 8) <= unsigned(VDATA);
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V_DSP_WND_START(15 downto 8) <= DSP_PARAM_DATA;
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when "0111" =>
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V_DSP_WND_END(15 downto 8) <= unsigned(VDATA);
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V_DSP_WND_END(15 downto 8) <= DSP_PARAM_DATA;
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when "1000" =>
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H_LINE_END(15 downto 8) <= unsigned(VDATA);
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H_LINE_END(15 downto 8) <= DSP_PARAM_DATA;
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when "1001" =>
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V_LINE_END(15 downto 8) <= unsigned(VDATA);
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V_LINE_END(15 downto 8) <= DSP_PARAM_DATA;
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when "1010" =>
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when "1011" =>
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H_SYNC_START(15 downto 8) <= unsigned(VDATA);
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H_SYNC_START(15 downto 8) <= DSP_PARAM_DATA;
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when "1100" =>
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H_SYNC_END(15 downto 8) <= unsigned(VDATA);
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H_SYNC_END(15 downto 8) <= DSP_PARAM_DATA;
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when "1101" =>
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V_SYNC_START(15 downto 8) <= unsigned(VDATA);
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V_SYNC_START(15 downto 8) <= DSP_PARAM_DATA;
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when "1110" =>
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V_SYNC_END(15 downto 8) <= unsigned(VDATA);
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V_SYNC_END(15 downto 8) <= DSP_PARAM_DATA;
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when "1111" =>
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V_PX(7 downto 0) <= unsigned(VDATA);
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V_PX(7 downto 0) <= DSP_PARAM_DATA;
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end case;
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when others =>
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end case;
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end if;
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-- Flag the data has been registered.
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DSP_PARAM_CLR <= '1';
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end if;
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-- Activate/deactivate signals according to pixel position.
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@@ -1627,8 +1645,7 @@ begin
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-- 0x82 = Parameterised Clear framebuffer screen. Parameters: start x [87:72], start y [71:56], end x [55:40], end y [39:24], R Filter [23:16], G Filter [15:8], B Filter [7:0] - R/G/B Filters are 8 pixel wide.
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-- Other commands.
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-- 0xFF = Immediate GPU reset, cancel current command and return to idle.
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GPU: process( VRESETn, IF_CLK, SYS_CLK )
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variable GPU_START_ADDR : std_logic_vector(13 downto 0); -- Current start address being worked on by the GPU.
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GPU: process( VRESETn, SYS_CLK )
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variable GPU_START_X : integer range 0 to 640; -- X starting location.
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variable GPU_START_Y : integer range 0 to 200; -- Y starting location.
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variable GPU_END_X : integer range 0 to 640; -- X ending location.
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@@ -1755,7 +1772,7 @@ begin
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GPU_STATE <= GPU_FB_Clear_Start;
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when GPU_FB_Clear_Start =>
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GPU_START_ADDR := std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14));
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GPU_START_ADDR <= std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14));
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GRAM_GPU_ADDR <= std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14));
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GRAM_GPU_DI_R <= GPU_FILTER_R;
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GRAM_GPU_DI_G <= GPU_FILTER_G;
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@@ -1782,7 +1799,7 @@ begin
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GPU_STATE <= GPU_FB_Clear_3;
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else
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GRAM_GPU_ADDR <= GPU_START_ADDR + 80;
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GPU_START_ADDR:= GPU_START_ADDR + 80;
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GPU_START_ADDR<= GPU_START_ADDR + 80;
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GPU_VAR_Y := GPU_VAR_Y + 1;
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GPU_STATE <= GPU_FB_Clear_1;
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end if;
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@@ -1857,10 +1874,10 @@ begin
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when GPU_VRAM_Clear_Start =>
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-- For modes with hardware scroll, add in the current offset so the visible part of the display is updated.
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if MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ700 = '1' then
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GPU_START_ADDR:= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14)) + (OFFSET_ADDR & "000");
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GPU_START_ADDR<= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14)) + (OFFSET_ADDR & "000");
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VRAM_GPU_ADDR <= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 13)) + (OFFSET_ADDR & "000");
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else
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GPU_START_ADDR:= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14));
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GPU_START_ADDR<= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14));
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VRAM_GPU_ADDR <= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 13));
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end if;
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GPU_VAR_Y := GPU_START_Y;
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@@ -1899,10 +1916,10 @@ begin
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-- Alternate between character ram and attribute ram, they differ by 0x800 bytes, ie; 0xD000:D7FF and 0xD800:0xDFFF
|
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if VRAM_GPU_ADDR < X"800" then
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VRAM_GPU_ADDR <= GPU_START_ADDR(12 downto 0) + X"800";
|
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GPU_START_ADDR := GPU_START_ADDR + X"800";
|
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GPU_START_ADDR <= GPU_START_ADDR + X"800";
|
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else
|
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VRAM_GPU_ADDR <= GPU_START_ADDR(12 downto 0) - X"800" + GPU_COLUMNS;
|
||||
GPU_START_ADDR := GPU_START_ADDR - X"800" + GPU_COLUMNS;
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GPU_START_ADDR <= GPU_START_ADDR - X"800" + GPU_COLUMNS;
|
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GPU_VAR_Y := GPU_VAR_Y + 1;
|
||||
|
||||
-- If we have filled to the set line, exit.
|
||||
@@ -2010,6 +2027,7 @@ begin
|
||||
CGRAM_WEn <= '1';
|
||||
GPU_PARAMS <= (others => '0');
|
||||
GPU_COMMAND <= (others => '0');
|
||||
DSP_PARAM_UPD <= '0';
|
||||
|
||||
elsif rising_edge(IF_CLK) then
|
||||
|
||||
@@ -2395,13 +2413,44 @@ begin
|
||||
|
||||
-- Set the mode switch event flag if the mode changes.
|
||||
if CPLD_CFG_DATA(2 downto 0) /= VDATA(2 downto 0) then
|
||||
MODE_CPLD_SWITCH <= '1';
|
||||
MODE_CPLD_SWITCH <= '1';
|
||||
end if;
|
||||
|
||||
-- Store the new value into the register, used for read operations.
|
||||
CPLD_CFG_DATA <= VDATA;
|
||||
CPLD_CFG_DATA <= VDATA;
|
||||
else
|
||||
MODE_CPLD_SWITCH <= '0';
|
||||
MODE_CPLD_SWITCH <= '0';
|
||||
end if;
|
||||
|
||||
-- Clear the parameter update flag if it has been actioned and the handshake has been set.
|
||||
if DSP_PARAM_UPD = '1' and DSP_PARAM_CLR = '1' then
|
||||
DSP_PARAM_UPD <= '0';
|
||||
end if;
|
||||
|
||||
-- Ability to adjust the video parameter registers to tune or override the default values from the lookup table. This can be useful in debugging,
|
||||
-- adjusting to a new monitor etc.
|
||||
--
|
||||
if CS_IO_DXXn = '0' and VZ80_WRn = '0' then
|
||||
|
||||
case VADDR(3 downto 0) is
|
||||
-- 0xD0 - Set the parameter number to update.
|
||||
when "0000" =>
|
||||
DSP_PARAM_SEL <= VDATA(3 downto 0);
|
||||
|
||||
-- 0xD1 - Update the lower selected parameter byte.
|
||||
when "0001" =>
|
||||
DSP_PARAM_DATA <= unsigned(VDATA);
|
||||
DSP_PARAM_ADDR <= '0';
|
||||
DSP_PARAM_UPD <= '1';
|
||||
|
||||
-- 0xD2 - Update the upper selected parameter byte.
|
||||
when "0010" =>
|
||||
DSP_PARAM_DATA <= unsigned(VDATA);
|
||||
DSP_PARAM_ADDR <= '1';
|
||||
DSP_PARAM_UPD <= '1';
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
@@ -38,14 +38,24 @@ set_time_format -unit ns -decimal_places 3
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
|
||||
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
derive_pll_clocks
|
||||
#create_generated_clock -name {vcpll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {vcpll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLOCK_50} [get_pins {vcpll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
#derive_pll_clocks
|
||||
create_generated_clock -name {SYS_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {IF_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -phase 180.000 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
|
||||
create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
|
||||
create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[4]}]
|
||||
create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
create_generated_clock -name {VIDCLK_PSEUDO} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 64 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {VCPLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -master_clock {CLOCK_50} [get_pins {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {VCPLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -master_clock {CLOCK_50} [get_pins {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
@@ -66,35 +76,35 @@ derive_clock_uncertainty
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VRESETn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
|
||||
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[10]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[9]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[8]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[7]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[6]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[5]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[4]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[3]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[2]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[1]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[0]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[15]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[14]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[13]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[12]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[11]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[10]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[9]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[8]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[7]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[6]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[5]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[4]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[3]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[2]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[1]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[0]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[0]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[1]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[2]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[3]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[4]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[5]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[6]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VDATA[7]}]
|
||||
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[3]}]
|
||||
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[2]}]
|
||||
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[1]}]
|
||||
@@ -110,36 +120,36 @@ set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SF
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_VS}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_HS}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNCn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSRVIDEO_OUT}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VHBLNK_OUTn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VHSY_OUT}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSYNCH_OUT}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVBLNK_OUTn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[4]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[5]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[6]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[7]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VWAITn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[1]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[2]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[3]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_VS}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_HS}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNCn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSRVIDEO_OUT}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VHBLNK_OUTn}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VHSY_OUT}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSYNCH_OUT}]
|
||||
set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VVBLNK_OUTn}]
|
||||
# Required for the Serial Flash Loader.
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
|
||||
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
|
||||
@@ -156,33 +166,87 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {a
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
set_false_path -from [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[4]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL1|altpll_component|auto_generated|pll1|clk[4]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
# There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
|
||||
set_false_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
set_false_path -from [get_clocks {VIDCLK_PSEUDO}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
|
||||
|
||||
# Z80 clock has no relationship to the video frequencies, it is used only for latching data asynchronous to the FPGA clocks.
|
||||
set_false_path -from [get_clocks {IF_CLK}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
|
||||
|
||||
# The system clock has no real relationship with the video frequencies, rendering and display. The only place they meet is in the dual port BRAM.
|
||||
set_false_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
|
||||
|
||||
# Clock 50MHZ, the input oscillator is only used for the PLL input and as I/O input/output latch which is detached from the video block
|
||||
set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
|
||||
|
||||
# The Z80 data, address and control lines do not go to the video block (except the parameter update which is not critical) so set it as a false path so as not to consider.
|
||||
set_false_path -from [get_ports {VDATA[*]}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
|
||||
set_false_path -from [get_ports {VADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
|
||||
set_false_path -from [get_ports {VZ80_WRn VZ80_RDn VZ80_IORQn}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -setup -start 2
|
||||
|
||||
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {IF_CLK}] -hold -start 1
|
||||
set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {IF_CLK}] -setup -start 2
|
||||
set_multicycle_path -from [get_clocks {IF_CLK}] -to [get_clocks {SYS_CLK}] -hold -start 2
|
||||
set_multicycle_path -from [get_clocks {IF_CLK}] -to [get_clocks {SYS_CLK}] -setup -start 3
|
||||
|
||||
# GPU control and run variables have at least 1 clock between them being setup and used.
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -setup -start 2
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -setup -start 2
|
||||
|
||||
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -hold -start 1
|
||||
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -hold -start 1
|
||||
|
||||
|
||||
#**************************************************************
|
||||
|
||||
BIN
pcb/v1_0/MZ80-80CLR_153mmX67mm_v1.zip
Normal file
BIN
pcb/v1_0/MZ80-80CLR_153mmX67mm_v1.zip
Normal file
Binary file not shown.
14
pcb/v2_0/MZ80-80CLR-B_Adhes.gbr
Normal file
14
pcb/v2_0/MZ80-80CLR-B_Adhes.gbr
Normal file
@@ -0,0 +1,14 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Glue,Bot*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
255
pcb/v2_0/MZ80-80CLR-B_CrtYd.gbr
Normal file
255
pcb/v2_0/MZ80-80CLR-B_CrtYd.gbr
Normal file
@@ -0,0 +1,255 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,User*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.050000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X115890000Y-77314000D02*
|
||||
X115890000Y-80674000D01*
|
||||
X117790000Y-77314000D02*
|
||||
X115890000Y-77314000D01*
|
||||
X117790000Y-80674000D02*
|
||||
X117790000Y-77314000D01*
|
||||
X115890000Y-80674000D02*
|
||||
X117790000Y-80674000D01*
|
||||
X119319000Y-77314000D02*
|
||||
X119319000Y-80674000D01*
|
||||
X121219000Y-77314000D02*
|
||||
X119319000Y-77314000D01*
|
||||
X121219000Y-80674000D02*
|
||||
X121219000Y-77314000D01*
|
||||
X119319000Y-80674000D02*
|
||||
X121219000Y-80674000D01*
|
||||
X122780000Y-72324000D02*
|
||||
X126140000Y-72324000D01*
|
||||
X122780000Y-70424000D02*
|
||||
X122780000Y-72324000D01*
|
||||
X126140000Y-70424000D02*
|
||||
X122780000Y-70424000D01*
|
||||
X126140000Y-72324000D02*
|
||||
X126140000Y-70424000D01*
|
||||
X113567000Y-77663000D02*
|
||||
X110207000Y-77663000D01*
|
||||
X113567000Y-79563000D02*
|
||||
X113567000Y-77663000D01*
|
||||
X110207000Y-79563000D02*
|
||||
X113567000Y-79563000D01*
|
||||
X110207000Y-77663000D02*
|
||||
X110207000Y-79563000D01*
|
||||
X122780000Y-75880000D02*
|
||||
X126140000Y-75880000D01*
|
||||
X122780000Y-73980000D02*
|
||||
X122780000Y-75880000D01*
|
||||
X126140000Y-73980000D02*
|
||||
X122780000Y-73980000D01*
|
||||
X126140000Y-75880000D02*
|
||||
X126140000Y-73980000D01*
|
||||
X114075000Y-72710000D02*
|
||||
X110715000Y-72710000D01*
|
||||
X114075000Y-74610000D02*
|
||||
X114075000Y-72710000D01*
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12272
pcb/v2_0/MZ80-80CLR-B_Cu.gbr
Normal file
12272
pcb/v2_0/MZ80-80CLR-B_Cu.gbr
Normal file
File diff suppressed because it is too large
Load Diff
255
pcb/v2_0/MZ80-80CLR-B_Fab.gbr
Normal file
255
pcb/v2_0/MZ80-80CLR-B_Fab.gbr
Normal file
@@ -0,0 +1,255 @@
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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
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X121628000Y-67075000D02*
|
||||
X123228000Y-67075000D01*
|
||||
X121628000Y-66275000D02*
|
||||
X121628000Y-67075000D01*
|
||||
X123228000Y-66275000D02*
|
||||
X121628000Y-66275000D01*
|
||||
X123228000Y-67075000D02*
|
||||
X123228000Y-66275000D01*
|
||||
X121628000Y-69107000D02*
|
||||
X123228000Y-69107000D01*
|
||||
X121628000Y-68307000D02*
|
||||
X121628000Y-69107000D01*
|
||||
X123228000Y-68307000D02*
|
||||
X121628000Y-68307000D01*
|
||||
X123228000Y-69107000D02*
|
||||
X123228000Y-68307000D01*
|
||||
X113322000Y-70466000D02*
|
||||
X111722000Y-70466000D01*
|
||||
X113322000Y-71266000D02*
|
||||
X113322000Y-70466000D01*
|
||||
X111722000Y-71266000D02*
|
||||
X113322000Y-71266000D01*
|
||||
X111722000Y-70466000D02*
|
||||
X111722000Y-71266000D01*
|
||||
X118510000Y-65875000D02*
|
||||
X117710000Y-65875000D01*
|
||||
X117710000Y-65875000D02*
|
||||
X117710000Y-67475000D01*
|
||||
X117710000Y-67475000D02*
|
||||
X118510000Y-67475000D01*
|
||||
X118510000Y-67475000D02*
|
||||
X118510000Y-65875000D01*
|
||||
X113322000Y-66275000D02*
|
||||
X111722000Y-66275000D01*
|
||||
X113322000Y-67075000D02*
|
||||
X113322000Y-66275000D01*
|
||||
X111722000Y-67075000D02*
|
||||
X113322000Y-67075000D01*
|
||||
X111722000Y-66275000D02*
|
||||
X111722000Y-67075000D01*
|
||||
X121755000Y-77235000D02*
|
||||
X123355000Y-77235000D01*
|
||||
X121755000Y-76435000D02*
|
||||
X121755000Y-77235000D01*
|
||||
X123355000Y-76435000D02*
|
||||
X121755000Y-76435000D01*
|
||||
X123355000Y-77235000D02*
|
||||
X123355000Y-76435000D01*
|
||||
X111360000Y-56350000D02*
|
||||
X111360000Y-57950000D01*
|
||||
X112160000Y-56350000D02*
|
||||
X111360000Y-56350000D01*
|
||||
X112160000Y-57950000D02*
|
||||
X112160000Y-56350000D01*
|
||||
X111360000Y-57950000D02*
|
||||
X112160000Y-57950000D01*
|
||||
X110128000Y-88303000D02*
|
||||
X110128000Y-86703000D01*
|
||||
X109328000Y-88303000D02*
|
||||
X110128000Y-88303000D01*
|
||||
X109328000Y-86703000D02*
|
||||
X109328000Y-88303000D01*
|
||||
X110128000Y-86703000D02*
|
||||
X109328000Y-86703000D01*
|
||||
X126257000Y-88303000D02*
|
||||
X126257000Y-86703000D01*
|
||||
X125457000Y-88303000D02*
|
||||
X126257000Y-88303000D01*
|
||||
X125457000Y-86703000D02*
|
||||
X125457000Y-88303000D01*
|
||||
X126257000Y-86703000D02*
|
||||
X125457000Y-86703000D01*
|
||||
X122155000Y-56350000D02*
|
||||
X122155000Y-57950000D01*
|
||||
X122955000Y-56350000D02*
|
||||
X122155000Y-56350000D01*
|
||||
X122955000Y-57950000D02*
|
||||
X122955000Y-56350000D01*
|
||||
X122155000Y-57950000D02*
|
||||
X122955000Y-57950000D01*
|
||||
M02*
|
||||
7997
pcb/v2_0/MZ80-80CLR-B_Mask.gbr
Normal file
7997
pcb/v2_0/MZ80-80CLR-B_Mask.gbr
Normal file
File diff suppressed because it is too large
Load Diff
4577
pcb/v2_0/MZ80-80CLR-B_Paste.gbr
Normal file
4577
pcb/v2_0/MZ80-80CLR-B_Paste.gbr
Normal file
File diff suppressed because it is too large
Load Diff
1941
pcb/v2_0/MZ80-80CLR-B_SilkS.gbr
Normal file
1941
pcb/v2_0/MZ80-80CLR-B_SilkS.gbr
Normal file
File diff suppressed because it is too large
Load Diff
13
pcb/v2_0/MZ80-80CLR-Cmts_User.gbr
Normal file
13
pcb/v2_0/MZ80-80CLR-Cmts_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,Comment*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
13
pcb/v2_0/MZ80-80CLR-Dwgs_User.gbr
Normal file
13
pcb/v2_0/MZ80-80CLR-Dwgs_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Drawing*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
13
pcb/v2_0/MZ80-80CLR-Eco1_User.gbr
Normal file
13
pcb/v2_0/MZ80-80CLR-Eco1_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,ECO1*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
13
pcb/v2_0/MZ80-80CLR-Eco2_User.gbr
Normal file
13
pcb/v2_0/MZ80-80CLR-Eco2_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,ECO2*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
27
pcb/v2_0/MZ80-80CLR-Edge_Cuts.gbr
Normal file
27
pcb/v2_0/MZ80-80CLR-Edge_Cuts.gbr
Normal file
@@ -0,0 +1,27 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Profile,NP*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.100000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X133985000Y-62230000D02*
|
||||
X142000000Y-62230000D01*
|
||||
X133985000Y-33000000D02*
|
||||
X133985000Y-62230000D01*
|
||||
X133985000Y-33000000D02*
|
||||
X70485000Y-33000000D01*
|
||||
X142000000Y-133000000D02*
|
||||
X142000000Y-62230000D01*
|
||||
X70485000Y-133000000D02*
|
||||
X142000000Y-133000000D01*
|
||||
X70485000Y-33000000D02*
|
||||
X70485000Y-133000000D01*
|
||||
M02*
|
||||
55
pcb/v2_0/MZ80-80CLR-F_Adhes.gbr
Normal file
55
pcb/v2_0/MZ80-80CLR-F_Adhes.gbr
Normal file
@@ -0,0 +1,55 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Glue,Top*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.100000*%
|
||||
%ADD11C,0.083333*%
|
||||
%ADD12C,0.116667*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X117471000Y-88392000D02*
|
||||
G75*
|
||||
G03X117471000Y-88392000I-250000J0D01*
|
||||
G01*
|
||||
D11*
|
||||
X117429333Y-88392000D02*
|
||||
G75*
|
||||
G03X117429333Y-88392000I-208333J0D01*
|
||||
G01*
|
||||
X117354333Y-88392000D02*
|
||||
G75*
|
||||
G03X117354333Y-88392000I-133333J0D01*
|
||||
G01*
|
||||
D12*
|
||||
X117279333Y-88392000D02*
|
||||
G75*
|
||||
G03X117279333Y-88392000I-58333J0D01*
|
||||
G01*
|
||||
D10*
|
||||
X74672000Y-72898000D02*
|
||||
G75*
|
||||
G03X74672000Y-72898000I-250000J0D01*
|
||||
G01*
|
||||
D11*
|
||||
X74630333Y-72898000D02*
|
||||
G75*
|
||||
G03X74630333Y-72898000I-208333J0D01*
|
||||
G01*
|
||||
X74555333Y-72898000D02*
|
||||
G75*
|
||||
G03X74555333Y-72898000I-133333J0D01*
|
||||
G01*
|
||||
D12*
|
||||
X74480333Y-72898000D02*
|
||||
G75*
|
||||
G03X74480333Y-72898000I-58333J0D01*
|
||||
G01*
|
||||
M02*
|
||||
503
pcb/v2_0/MZ80-80CLR-F_CrtYd.gbr
Normal file
503
pcb/v2_0/MZ80-80CLR-F_CrtYd.gbr
Normal file
@@ -0,0 +1,503 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,User*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:52*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.050000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X118647000Y-131923000D02*
|
||||
X118647000Y-121823000D01*
|
||||
X125447000Y-131923000D02*
|
||||
X125447000Y-121823000D01*
|
||||
X118647000Y-131923000D02*
|
||||
X125447000Y-131923000D01*
|
||||
X125447000Y-121823000D02*
|
||||
X118647000Y-121823000D01*
|
||||
X128298000Y-97233000D02*
|
||||
X131798000Y-97233000D01*
|
||||
X128298000Y-100633000D02*
|
||||
X128298000Y-97233000D01*
|
||||
X131798000Y-100633000D02*
|
||||
X128298000Y-100633000D01*
|
||||
X131798000Y-97233000D02*
|
||||
X131798000Y-100633000D01*
|
||||
X105948000Y-72014500D02*
|
||||
X105948000Y-81164500D01*
|
||||
X105948000Y-81164500D02*
|
||||
X107348000Y-81164500D01*
|
||||
X107348000Y-81164500D02*
|
||||
X107348000Y-82264500D01*
|
||||
X107348000Y-82264500D02*
|
||||
X108448000Y-82264500D01*
|
||||
X108448000Y-82264500D02*
|
||||
X108448000Y-83664500D01*
|
||||
X108448000Y-83664500D02*
|
||||
X117598000Y-83664500D01*
|
||||
X105948000Y-72014500D02*
|
||||
X105948000Y-62864500D01*
|
||||
X105948000Y-62864500D02*
|
||||
X107348000Y-62864500D01*
|
||||
X107348000Y-62864500D02*
|
||||
X107348000Y-61764500D01*
|
||||
X107348000Y-61764500D02*
|
||||
X108448000Y-61764500D01*
|
||||
X108448000Y-61764500D02*
|
||||
X108448000Y-60364500D01*
|
||||
X108448000Y-60364500D02*
|
||||
X117598000Y-60364500D01*
|
||||
X129248000Y-72014500D02*
|
||||
X129248000Y-81164500D01*
|
||||
X129248000Y-81164500D02*
|
||||
X127848000Y-81164500D01*
|
||||
X127848000Y-81164500D02*
|
||||
X127848000Y-82264500D01*
|
||||
X127848000Y-82264500D02*
|
||||
X126748000Y-82264500D01*
|
||||
X126748000Y-82264500D02*
|
||||
X126748000Y-83664500D01*
|
||||
X126748000Y-83664500D02*
|
||||
X117598000Y-83664500D01*
|
||||
X129248000Y-72014500D02*
|
||||
X129248000Y-62864500D01*
|
||||
X129248000Y-62864500D02*
|
||||
X127848000Y-62864500D01*
|
||||
X127848000Y-62864500D02*
|
||||
X127848000Y-61764500D01*
|
||||
X127848000Y-61764500D02*
|
||||
X126748000Y-61764500D01*
|
||||
X126748000Y-61764500D02*
|
||||
X126748000Y-60364500D01*
|
||||
X126748000Y-60364500D02*
|
||||
X117598000Y-60364500D01*
|
||||
X132550000Y-45742000D02*
|
||||
X106150000Y-45742000D01*
|
||||
X132550000Y-42192000D02*
|
||||
X132550000Y-45742000D01*
|
||||
X106150000Y-42192000D02*
|
||||
X132550000Y-42192000D01*
|
||||
X106150000Y-45742000D02*
|
||||
X106150000Y-42192000D01*
|
||||
X76201000Y-102648000D02*
|
||||
X79501000Y-102648000D01*
|
||||
X76201000Y-104108000D02*
|
||||
X76201000Y-102648000D01*
|
||||
X79501000Y-104108000D02*
|
||||
X76201000Y-104108000D01*
|
||||
X79501000Y-102648000D02*
|
||||
X79501000Y-104108000D01*
|
||||
X74251000Y-100412000D02*
|
||||
X81451000Y-100412000D01*
|
||||
X81451000Y-100412000D02*
|
||||
X81451000Y-91612000D01*
|
||||
X81451000Y-91612000D02*
|
||||
X74251000Y-91612000D01*
|
||||
X74251000Y-91612000D02*
|
||||
X74251000Y-100412000D01*
|
||||
X96780000Y-49056000D02*
|
||||
X87630000Y-49056000D01*
|
||||
X96780000Y-50456000D02*
|
||||
X96780000Y-49056000D01*
|
||||
X97880000Y-50456000D02*
|
||||
X96780000Y-50456000D01*
|
||||
X97880000Y-51556000D02*
|
||||
X97880000Y-50456000D01*
|
||||
X99280000Y-51556000D02*
|
||||
X97880000Y-51556000D01*
|
||||
X99280000Y-60706000D02*
|
||||
X99280000Y-51556000D01*
|
||||
X96780000Y-72356000D02*
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|
||||
M02*
|
||||
45550
pcb/v2_0/MZ80-80CLR-F_Cu.gbr
Normal file
45550
pcb/v2_0/MZ80-80CLR-F_Cu.gbr
Normal file
File diff suppressed because it is too large
Load Diff
642
pcb/v2_0/MZ80-80CLR-F_Fab.gbr
Normal file
642
pcb/v2_0/MZ80-80CLR-F_Fab.gbr
Normal file
@@ -0,0 +1,642 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
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G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
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||||
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||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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|
||||
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X73514000Y-121882000D02*
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X74314000Y-121882000D01*
|
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X73514000Y-123482000D02*
|
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X73514000Y-121882000D01*
|
||||
X74314000Y-123482000D02*
|
||||
X73514000Y-123482000D01*
|
||||
X114592000Y-103905000D02*
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X114592000Y-103105000D02*
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X114592000Y-103905000D01*
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|
||||
X114592000Y-103105000D01*
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|
||||
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|
||||
X110585238Y-50030095D01*
|
||||
M02*
|
||||
16209
pcb/v2_0/MZ80-80CLR-F_Mask.gbr
Normal file
16209
pcb/v2_0/MZ80-80CLR-F_Mask.gbr
Normal file
File diff suppressed because it is too large
Load Diff
29549
pcb/v2_0/MZ80-80CLR-F_Paste.gbr
Normal file
29549
pcb/v2_0/MZ80-80CLR-F_Paste.gbr
Normal file
File diff suppressed because it is too large
Load Diff
3238
pcb/v2_0/MZ80-80CLR-F_SilkS.gbr
Normal file
3238
pcb/v2_0/MZ80-80CLR-F_SilkS.gbr
Normal file
File diff suppressed because it is too large
Load Diff
13
pcb/v2_0/MZ80-80CLR-Margin.gbr
Normal file
13
pcb/v2_0/MZ80-80CLR-Margin.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
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||||
G04 #@! TF.CreationDate,2020-07-05T10:41:52+01:00*
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%MOMM*%
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G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
109
pcb/v2_0/MZ80-80CLR-NPTH-drl_map.gbr
Normal file
109
pcb/v2_0/MZ80-80CLR-NPTH-drl_map.gbr
Normal file
@@ -0,0 +1,109 @@
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||||
%FSLAX45Y45*%
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||||
G04 Gerber Fmt 4.5, Leading zero omitted, Abs format (unit mm)*
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G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-05 10:41:57*
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%MOMM*%
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|
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G04 APERTURE LIST*
|
||||
%ADD10C,0.100000*%
|
||||
%ADD11C,0.200000*%
|
||||
%ADD12C,0.300000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X13398500Y-6223000D02*
|
||||
X14200000Y-6223000D01*
|
||||
X13398500Y-3300000D02*
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|
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||||
D11*
|
||||
D12*
|
||||
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|
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|
||||
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|
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|
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|
||||
X8701357Y-13470714D01*
|
||||
X8701357Y-13770714D01*
|
||||
X8972786Y-13770714D02*
|
||||
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|
||||
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|
||||
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|
||||
X8872786Y-13570714D01*
|
||||
X8844214Y-13585000D01*
|
||||
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|
||||
X8944214Y-13770714D01*
|
||||
X8872786Y-13770714D01*
|
||||
X8844214Y-13756429D01*
|
||||
X8829928Y-13727857D01*
|
||||
X8829928Y-13699286D01*
|
||||
X8844214Y-13670714D01*
|
||||
X8872786Y-13656429D01*
|
||||
X8944214Y-13656429D01*
|
||||
X8972786Y-13642143D01*
|
||||
X9115643Y-13570714D02*
|
||||
X9115643Y-13870714D01*
|
||||
X9115643Y-13585000D02*
|
||||
X9144214Y-13570714D01*
|
||||
X9201357Y-13570714D01*
|
||||
X9229928Y-13585000D01*
|
||||
X9244214Y-13599286D01*
|
||||
X9258500Y-13627857D01*
|
||||
X9258500Y-13713571D01*
|
||||
X9244214Y-13742143D01*
|
||||
X9229928Y-13756429D01*
|
||||
X9201357Y-13770714D01*
|
||||
X9144214Y-13770714D01*
|
||||
X9115643Y-13756429D01*
|
||||
X9387071Y-13742143D02*
|
||||
X9401357Y-13756429D01*
|
||||
X9387071Y-13770714D01*
|
||||
X9372786Y-13756429D01*
|
||||
X9387071Y-13742143D01*
|
||||
X9387071Y-13770714D01*
|
||||
X9387071Y-13585000D02*
|
||||
X9401357Y-13599286D01*
|
||||
X9387071Y-13613571D01*
|
||||
X9372786Y-13599286D01*
|
||||
X9387071Y-13585000D01*
|
||||
X9387071Y-13613571D01*
|
||||
M02*
|
||||
13
pcb/v2_0/MZ80-80CLR-NPTH.drl
Normal file
13
pcb/v2_0/MZ80-80CLR-NPTH.drl
Normal file
@@ -0,0 +1,13 @@
|
||||
M48
|
||||
; DRILL file {KiCad (5.1.2-1)-1} date Sunday, 05 July 2020 at 10:41:56
|
||||
; FORMAT={-:-/ absolute / metric / decimal}
|
||||
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|
||||
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|
||||
; #@! TF.FileFunction,NonPlated,1,2,NPTH
|
||||
FMAT,2
|
||||
METRIC
|
||||
%
|
||||
G90
|
||||
G05
|
||||
T0
|
||||
M30
|
||||
2269
pcb/v2_0/MZ80-80CLR-PTH-drl_map.gbr
Normal file
2269
pcb/v2_0/MZ80-80CLR-PTH-drl_map.gbr
Normal file
File diff suppressed because it is too large
Load Diff
332
pcb/v2_0/MZ80-80CLR-PTH.drl
Normal file
332
pcb/v2_0/MZ80-80CLR-PTH.drl
Normal file
@@ -0,0 +1,332 @@
|
||||
M48
|
||||
; DRILL file {KiCad (5.1.2-1)-1} date Sunday, 05 July 2020 at 10:41:56
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
FMAT,2
|
||||
METRIC
|
||||
T1C0.400
|
||||
T2C0.800
|
||||
T3C1.000
|
||||
%
|
||||
G90
|
||||
G05
|
||||
T1
|
||||
X72.473Y-89.525
|
||||
X73.184Y-82.593
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
X75.949Y-87.612
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||||
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|
||||
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|
||||
X76.968Y-47.491
|
||||
X77.47Y-91.059
|
||||
X77.851Y-97.536
|
||||
X78.317Y-55.714
|
||||
X78.319Y-56.826
|
||||
X78.613Y-69.469
|
||||
X78.613Y-91.059
|
||||
X79.354Y-53.956
|
||||
X79.629Y-91.059
|
||||
X80.01Y-55.118
|
||||
X80.01Y-58.293
|
||||
X80.01Y-61.468
|
||||
X80.088Y-53.26
|
||||
X80.151Y-97.546
|
||||
X80.852Y-105.503
|
||||
X81.153Y-63.754
|
||||
X82.514Y-69.661
|
||||
X82.931Y-59.69
|
||||
X82.942Y-97.601
|
||||
X82.942Y-101.274
|
||||
X84.074Y-55.245
|
||||
X84.074Y-64.897
|
||||
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|
||||
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||||
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|
||||
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|
||||
X86.233Y-91.059
|
||||
X86.868Y-97.536
|
||||
X87.081Y-73.834
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||||
X87.249Y-91.059
|
||||
X87.503Y-64.77
|
||||
X87.88Y-51.396
|
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X88.392Y-91.059
|
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X89.386Y-59.731
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||||
X89.63Y-52.075
|
||||
X89.703Y-111.762
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||||
X90.297Y-56.515
|
||||
X90.379Y-72.723
|
||||
X90.424Y-67.564
|
||||
X90.795Y-46.339
|
||||
X91.186Y-57.912
|
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X91.186Y-61.595
|
||||
X91.313Y-53.594
|
||||
X91.567Y-64.897
|
||||
X91.824Y-98.935
|
||||
X91.824Y-101.346
|
||||
X91.918Y-73.313
|
||||
X92.146Y-83.545
|
||||
X92.38Y-70.017
|
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X92.49Y-48.702
|
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X92.723Y-68.186
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X92.964Y-53.594
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X93.372Y-47.321
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X93.535Y-69.608
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X93.98Y-56.515
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X93.98Y-62.611
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|
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X95.005Y-54.028
|
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X95.631Y-91.186
|
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X95.631Y-97.536
|
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X96.542Y-69.447
|
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X96.567Y-47.992
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X96.673Y-83.544
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X98.501Y-46.914
|
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X98.868Y-95.94
|
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X99.167Y-100.752
|
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|
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X99.659Y-47.247
|
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X100.639Y-79.909
|
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|
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X100.898Y-99.205
|
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|
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X101.469Y-81.295
|
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X101.469Y-85.855
|
||||
X101.526Y-91.843
|
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X101.526Y-96.941
|
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X101.72Y-98.087
|
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X102.151Y-49.745
|
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X102.169Y-83.891
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X109.927Y-84.123
|
||||
X110.109Y-73.66
|
||||
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|
||||
X110.617Y-66.675
|
||||
X110.617Y-70.866
|
||||
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|
||||
X110.754Y-84.685
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X113.03Y-89.662
|
||||
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|
||||
X114.006Y-84.127
|
||||
X114.413Y-54.313
|
||||
X114.702Y-52.858
|
||||
X114.808Y-59.817
|
||||
X114.808Y-79.883
|
||||
X114.934Y-81.199
|
||||
X115.364Y-95.082
|
||||
X115.413Y-84.599
|
||||
X115.443Y-67.691
|
||||
X115.522Y-99.958
|
||||
X115.697Y-80.518
|
||||
X115.803Y-97.085
|
||||
X116.097Y-85.6
|
||||
X116.332Y-63.5
|
||||
X116.832Y-42.543
|
||||
X116.986Y-52.74
|
||||
X117.585Y-85.635
|
||||
X118.603Y-85.099
|
||||
X118.648Y-93.21
|
||||
X118.811Y-53.607
|
||||
X119.253Y-65.659
|
||||
X119.761Y-88.519
|
||||
X120.79Y-85.198
|
||||
X121.031Y-65.659
|
||||
X121.412Y-67.691
|
||||
X121.468Y-86.002
|
||||
X121.539Y-80.391
|
||||
X121.617Y-84.077
|
||||
X121.666Y-69.85
|
||||
X121.666Y-74.93
|
||||
X121.92Y-65.659
|
||||
X122.381Y-64.596
|
||||
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|
||||
X122.555Y-77.851
|
||||
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|
||||
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|
||||
X123.589Y-65.804
|
||||
X123.922Y-86.494
|
||||
X124.133Y-96.868
|
||||
X124.218Y-57.708
|
||||
X124.333Y-66.675
|
||||
X124.333Y-68.707
|
||||
X124.46Y-76.835
|
||||
X125.299Y-78.536
|
||||
X125.349Y-59.817
|
||||
X126.111Y-84.201
|
||||
X126.229Y-57.076
|
||||
X126.492Y-81.153
|
||||
X126.619Y-68.326
|
||||
X126.619Y-71.374
|
||||
X126.619Y-75.946
|
||||
X126.619Y-78.994
|
||||
X127.411Y-52.918
|
||||
X128.264Y-86.58
|
||||
X128.469Y-54.708
|
||||
X128.595Y-92.897
|
||||
X128.918Y-61.778
|
||||
X129.404Y-57.376
|
||||
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|
||||
X130.414Y-57.341
|
||||
X130.981Y-47.416
|
||||
X131.57Y-52.908
|
||||
X137.464Y-78.994
|
||||
T2
|
||||
X131.064Y-35.497
|
||||
X131.064Y-37.497
|
||||
X131.064Y-39.497
|
||||
X76.48Y-115.03
|
||||
X76.48Y-130.27
|
||||
X79.02Y-115.03
|
||||
X79.02Y-130.27
|
||||
X81.56Y-115.03
|
||||
X81.56Y-130.27
|
||||
X84.1Y-115.03
|
||||
X84.1Y-130.27
|
||||
X86.64Y-115.03
|
||||
X86.64Y-130.27
|
||||
X89.18Y-115.03
|
||||
X89.18Y-130.27
|
||||
X91.72Y-115.03
|
||||
X91.72Y-130.27
|
||||
X94.26Y-115.03
|
||||
X94.26Y-130.27
|
||||
X96.8Y-115.03
|
||||
X96.8Y-130.27
|
||||
X99.34Y-115.03
|
||||
X99.34Y-130.27
|
||||
X101.88Y-115.03
|
||||
X101.88Y-130.27
|
||||
X104.42Y-115.03
|
||||
X104.42Y-130.27
|
||||
X106.96Y-115.03
|
||||
X106.96Y-130.27
|
||||
X109.5Y-115.03
|
||||
X109.5Y-130.27
|
||||
X110.1Y-91.61
|
||||
X110.1Y-106.85
|
||||
X112.64Y-91.61
|
||||
X112.64Y-106.85
|
||||
X115.18Y-91.61
|
||||
X115.18Y-106.85
|
||||
X117.72Y-91.61
|
||||
X117.72Y-106.85
|
||||
X120.26Y-91.61
|
||||
X120.26Y-106.85
|
||||
X122.8Y-91.61
|
||||
X122.8Y-106.85
|
||||
X125.34Y-91.61
|
||||
X125.34Y-106.85
|
||||
X127.88Y-91.61
|
||||
X127.88Y-106.85
|
||||
X130.42Y-91.61
|
||||
X130.42Y-106.85
|
||||
X132.96Y-91.61
|
||||
X132.96Y-106.85
|
||||
X135.5Y-91.61
|
||||
X135.5Y-106.85
|
||||
X138.04Y-91.61
|
||||
X138.04Y-106.85
|
||||
X75.184Y-77.089
|
||||
X75.184Y-84.709
|
||||
X92.964Y-77.089
|
||||
X92.964Y-84.709
|
||||
T3
|
||||
X84.963Y-36.195
|
||||
X84.963Y-38.735
|
||||
X87.503Y-36.195
|
||||
X87.503Y-38.735
|
||||
X90.043Y-36.195
|
||||
X90.043Y-38.735
|
||||
X92.583Y-36.195
|
||||
X92.583Y-38.735
|
||||
X95.123Y-36.195
|
||||
X95.123Y-38.735
|
||||
X97.663Y-36.195
|
||||
X97.663Y-38.735
|
||||
X100.203Y-36.195
|
||||
X100.203Y-38.735
|
||||
X102.743Y-36.195
|
||||
X102.743Y-38.735
|
||||
X105.283Y-36.195
|
||||
X105.283Y-38.735
|
||||
X107.823Y-36.195
|
||||
X107.823Y-38.735
|
||||
X110.363Y-36.195
|
||||
X110.363Y-38.735
|
||||
X112.903Y-36.195
|
||||
X112.903Y-38.735
|
||||
X115.443Y-36.195
|
||||
X115.443Y-38.735
|
||||
X117.983Y-36.195
|
||||
X117.983Y-38.735
|
||||
X120.523Y-36.195
|
||||
X120.523Y-38.735
|
||||
X123.063Y-36.195
|
||||
X123.063Y-38.735
|
||||
X125.603Y-36.195
|
||||
X125.603Y-38.735
|
||||
X107.95Y-49.022
|
||||
X107.95Y-51.562
|
||||
X110.49Y-49.022
|
||||
X110.49Y-51.562
|
||||
X113.03Y-49.022
|
||||
X113.03Y-51.562
|
||||
X120.65Y-48.895
|
||||
X120.65Y-51.435
|
||||
X123.19Y-48.895
|
||||
X123.19Y-51.435
|
||||
X125.73Y-48.895
|
||||
X125.73Y-51.435
|
||||
X128.27Y-48.895
|
||||
X128.27Y-51.435
|
||||
X130.81Y-48.895
|
||||
X130.81Y-51.435
|
||||
X107.95Y-43.942
|
||||
X110.49Y-43.942
|
||||
X113.03Y-43.942
|
||||
X115.57Y-43.942
|
||||
X118.11Y-43.942
|
||||
X120.65Y-43.942
|
||||
X123.19Y-43.942
|
||||
X125.73Y-43.942
|
||||
X128.27Y-43.942
|
||||
X130.81Y-43.942
|
||||
T0
|
||||
M30
|
||||
BIN
pcb/v2_0/MZ80-80CLR_100x71_v2_0_05072020.zip
Normal file
BIN
pcb/v2_0/MZ80-80CLR_100x71_v2_0_05072020.zip
Normal file
Binary file not shown.
14
pcb/v2_0a/MZ80-80CLR-B_Adhes.gbr
Normal file
14
pcb/v2_0a/MZ80-80CLR-B_Adhes.gbr
Normal file
@@ -0,0 +1,14 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
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|
||||
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|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
263
pcb/v2_0a/MZ80-80CLR-B_CrtYd.gbr
Normal file
263
pcb/v2_0a/MZ80-80CLR-B_CrtYd.gbr
Normal file
@@ -0,0 +1,263 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
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||||
X88919000Y-65113000D01*
|
||||
X88119000Y-66713000D02*
|
||||
X88919000Y-66713000D01*
|
||||
X82842000Y-58020000D02*
|
||||
X81242000Y-58020000D01*
|
||||
X82842000Y-58820000D02*
|
||||
X82842000Y-58020000D01*
|
||||
X81242000Y-58820000D02*
|
||||
X82842000Y-58820000D01*
|
||||
X81242000Y-58020000D02*
|
||||
X81242000Y-58820000D01*
|
||||
X91713000Y-56680000D02*
|
||||
X91713000Y-55080000D01*
|
||||
X90913000Y-56680000D02*
|
||||
X91713000Y-56680000D01*
|
||||
X90913000Y-55080000D02*
|
||||
X90913000Y-56680000D01*
|
||||
X91713000Y-55080000D02*
|
||||
X90913000Y-55080000D01*
|
||||
X93364000Y-56680000D02*
|
||||
X93364000Y-55080000D01*
|
||||
X92564000Y-56680000D02*
|
||||
X93364000Y-56680000D01*
|
||||
X92564000Y-55080000D02*
|
||||
X92564000Y-56680000D01*
|
||||
X93364000Y-55080000D02*
|
||||
X92564000Y-55080000D01*
|
||||
X91275000Y-59582000D02*
|
||||
X92875000Y-59582000D01*
|
||||
X91275000Y-58782000D02*
|
||||
X91275000Y-59582000D01*
|
||||
X92875000Y-58782000D02*
|
||||
X91275000Y-58782000D01*
|
||||
X92875000Y-59582000D02*
|
||||
X92875000Y-58782000D01*
|
||||
X86125000Y-56680000D02*
|
||||
X86125000Y-55080000D01*
|
||||
X85325000Y-56680000D02*
|
||||
X86125000Y-56680000D01*
|
||||
X85325000Y-55080000D02*
|
||||
X85325000Y-56680000D01*
|
||||
X86125000Y-55080000D02*
|
||||
X85325000Y-55080000D01*
|
||||
X90024000Y-65113000D02*
|
||||
X90024000Y-66713000D01*
|
||||
X90824000Y-65113000D02*
|
||||
X90024000Y-65113000D01*
|
||||
X90824000Y-66713000D02*
|
||||
X90824000Y-65113000D01*
|
||||
X90024000Y-66713000D02*
|
||||
X90824000Y-66713000D01*
|
||||
X91275000Y-63265000D02*
|
||||
X92875000Y-63265000D01*
|
||||
X91275000Y-62465000D02*
|
||||
X91275000Y-63265000D01*
|
||||
X92875000Y-62465000D02*
|
||||
X91275000Y-62465000D01*
|
||||
X92875000Y-63265000D02*
|
||||
X92875000Y-62465000D01*
|
||||
X82842000Y-54972000D02*
|
||||
X81242000Y-54972000D01*
|
||||
X82842000Y-55772000D02*
|
||||
X82842000Y-54972000D01*
|
||||
X81242000Y-55772000D02*
|
||||
X82842000Y-55772000D01*
|
||||
X81242000Y-54972000D02*
|
||||
X81242000Y-55772000D01*
|
||||
X111544000Y-76435000D02*
|
||||
X109944000Y-76435000D01*
|
||||
X111544000Y-77235000D02*
|
||||
X111544000Y-76435000D01*
|
||||
X109944000Y-77235000D02*
|
||||
X111544000Y-77235000D01*
|
||||
X109944000Y-76435000D02*
|
||||
X109944000Y-77235000D01*
|
||||
X118834000Y-67075000D02*
|
||||
X120434000Y-67075000D01*
|
||||
X118834000Y-66275000D02*
|
||||
X118834000Y-67075000D01*
|
||||
X120434000Y-66275000D02*
|
||||
X118834000Y-66275000D01*
|
||||
X120434000Y-67075000D02*
|
||||
X120434000Y-66275000D01*
|
||||
X118834000Y-69107000D02*
|
||||
X120434000Y-69107000D01*
|
||||
X118834000Y-68307000D02*
|
||||
X118834000Y-69107000D01*
|
||||
X120434000Y-68307000D02*
|
||||
X118834000Y-68307000D01*
|
||||
X120434000Y-69107000D02*
|
||||
X120434000Y-68307000D01*
|
||||
X110528000Y-70466000D02*
|
||||
X108928000Y-70466000D01*
|
||||
X110528000Y-71266000D02*
|
||||
X110528000Y-70466000D01*
|
||||
X108928000Y-71266000D02*
|
||||
X110528000Y-71266000D01*
|
||||
X108928000Y-70466000D02*
|
||||
X108928000Y-71266000D01*
|
||||
X115716000Y-65875000D02*
|
||||
X114916000Y-65875000D01*
|
||||
X114916000Y-65875000D02*
|
||||
X114916000Y-67475000D01*
|
||||
X114916000Y-67475000D02*
|
||||
X115716000Y-67475000D01*
|
||||
X115716000Y-67475000D02*
|
||||
X115716000Y-65875000D01*
|
||||
X110528000Y-66275000D02*
|
||||
X108928000Y-66275000D01*
|
||||
X110528000Y-67075000D02*
|
||||
X110528000Y-66275000D01*
|
||||
X108928000Y-67075000D02*
|
||||
X110528000Y-67075000D01*
|
||||
X108928000Y-66275000D02*
|
||||
X108928000Y-67075000D01*
|
||||
X118961000Y-77235000D02*
|
||||
X120561000Y-77235000D01*
|
||||
X118961000Y-76435000D02*
|
||||
X118961000Y-77235000D01*
|
||||
X120561000Y-76435000D02*
|
||||
X118961000Y-76435000D01*
|
||||
X120561000Y-77235000D02*
|
||||
X120561000Y-76435000D01*
|
||||
X108693000Y-57112000D02*
|
||||
X108693000Y-58712000D01*
|
||||
X109493000Y-57112000D02*
|
||||
X108693000Y-57112000D01*
|
||||
X109493000Y-58712000D02*
|
||||
X109493000Y-57112000D01*
|
||||
X108693000Y-58712000D02*
|
||||
X109493000Y-58712000D01*
|
||||
X107334000Y-88303000D02*
|
||||
X107334000Y-86703000D01*
|
||||
X106534000Y-88303000D02*
|
||||
X107334000Y-88303000D01*
|
||||
X106534000Y-86703000D02*
|
||||
X106534000Y-88303000D01*
|
||||
X107334000Y-86703000D02*
|
||||
X106534000Y-86703000D01*
|
||||
X122193000Y-88049000D02*
|
||||
X122193000Y-86449000D01*
|
||||
X121393000Y-88049000D02*
|
||||
X122193000Y-88049000D01*
|
||||
X121393000Y-86449000D02*
|
||||
X121393000Y-88049000D01*
|
||||
X122193000Y-86449000D02*
|
||||
X121393000Y-86449000D01*
|
||||
X122155000Y-57112000D02*
|
||||
X122155000Y-58712000D01*
|
||||
X122955000Y-57112000D02*
|
||||
X122155000Y-57112000D01*
|
||||
X122955000Y-58712000D02*
|
||||
X122955000Y-57112000D01*
|
||||
X122155000Y-58712000D02*
|
||||
X122955000Y-58712000D01*
|
||||
M02*
|
||||
8079
pcb/v2_0a/MZ80-80CLR-B_Mask.gbr
Normal file
8079
pcb/v2_0a/MZ80-80CLR-B_Mask.gbr
Normal file
File diff suppressed because it is too large
Load Diff
4730
pcb/v2_0a/MZ80-80CLR-B_Paste.gbr
Normal file
4730
pcb/v2_0a/MZ80-80CLR-B_Paste.gbr
Normal file
File diff suppressed because it is too large
Load Diff
1972
pcb/v2_0a/MZ80-80CLR-B_SilkS.gbr
Normal file
1972
pcb/v2_0a/MZ80-80CLR-B_SilkS.gbr
Normal file
File diff suppressed because it is too large
Load Diff
13
pcb/v2_0a/MZ80-80CLR-Cmts_User.gbr
Normal file
13
pcb/v2_0a/MZ80-80CLR-Cmts_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,Comment*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
13
pcb/v2_0a/MZ80-80CLR-Dwgs_User.gbr
Normal file
13
pcb/v2_0a/MZ80-80CLR-Dwgs_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Drawing*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
13
pcb/v2_0a/MZ80-80CLR-Eco1_User.gbr
Normal file
13
pcb/v2_0a/MZ80-80CLR-Eco1_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,ECO1*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
13
pcb/v2_0a/MZ80-80CLR-Eco2_User.gbr
Normal file
13
pcb/v2_0a/MZ80-80CLR-Eco2_User.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,ECO2*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
27
pcb/v2_0a/MZ80-80CLR-Edge_Cuts.gbr
Normal file
27
pcb/v2_0a/MZ80-80CLR-Edge_Cuts.gbr
Normal file
@@ -0,0 +1,27 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Profile,NP*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.100000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X133985000Y-62230000D02*
|
||||
X142000000Y-62230000D01*
|
||||
X133985000Y-33000000D02*
|
||||
X133985000Y-62230000D01*
|
||||
X133985000Y-33000000D02*
|
||||
X70485000Y-33000000D01*
|
||||
X142000000Y-133000000D02*
|
||||
X142000000Y-62230000D01*
|
||||
X70485000Y-133000000D02*
|
||||
X142000000Y-133000000D01*
|
||||
X70485000Y-33000000D02*
|
||||
X70485000Y-133000000D01*
|
||||
M02*
|
||||
55
pcb/v2_0a/MZ80-80CLR-F_Adhes.gbr
Normal file
55
pcb/v2_0a/MZ80-80CLR-F_Adhes.gbr
Normal file
@@ -0,0 +1,55 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Glue,Top*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.100000*%
|
||||
%ADD11C,0.083333*%
|
||||
%ADD12C,0.116667*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X117979000Y-86868000D02*
|
||||
G75*
|
||||
G03X117979000Y-86868000I-250000J0D01*
|
||||
G01*
|
||||
D11*
|
||||
X117937333Y-86868000D02*
|
||||
G75*
|
||||
G03X117937333Y-86868000I-208333J0D01*
|
||||
G01*
|
||||
X117862333Y-86868000D02*
|
||||
G75*
|
||||
G03X117862333Y-86868000I-133333J0D01*
|
||||
G01*
|
||||
D12*
|
||||
X117787333Y-86868000D02*
|
||||
G75*
|
||||
G03X117787333Y-86868000I-58333J0D01*
|
||||
G01*
|
||||
D10*
|
||||
X74037000Y-37592000D02*
|
||||
G75*
|
||||
G03X74037000Y-37592000I-250000J0D01*
|
||||
G01*
|
||||
D11*
|
||||
X73995333Y-37592000D02*
|
||||
G75*
|
||||
G03X73995333Y-37592000I-208333J0D01*
|
||||
G01*
|
||||
X73920333Y-37592000D02*
|
||||
G75*
|
||||
G03X73920333Y-37592000I-133333J0D01*
|
||||
G01*
|
||||
D12*
|
||||
X73845333Y-37592000D02*
|
||||
G75*
|
||||
G03X73845333Y-37592000I-58333J0D01*
|
||||
G01*
|
||||
M02*
|
||||
495
pcb/v2_0a/MZ80-80CLR-F_CrtYd.gbr
Normal file
495
pcb/v2_0a/MZ80-80CLR-F_CrtYd.gbr
Normal file
@@ -0,0 +1,495 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,User*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.050000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X118647000Y-131923000D02*
|
||||
X118647000Y-121823000D01*
|
||||
X125447000Y-131923000D02*
|
||||
X125447000Y-121823000D01*
|
||||
X118647000Y-131923000D02*
|
||||
X125447000Y-131923000D01*
|
||||
X125447000Y-121823000D02*
|
||||
X118647000Y-121823000D01*
|
||||
X128044000Y-97487000D02*
|
||||
X131544000Y-97487000D01*
|
||||
X128044000Y-100887000D02*
|
||||
X128044000Y-97487000D01*
|
||||
X131544000Y-100887000D02*
|
||||
X128044000Y-100887000D01*
|
||||
X131544000Y-97487000D02*
|
||||
X131544000Y-100887000D01*
|
||||
X106150000Y-42142000D02*
|
||||
X106150000Y-45742000D01*
|
||||
X132600000Y-42142000D02*
|
||||
X106150000Y-42142000D01*
|
||||
X132600000Y-45742000D02*
|
||||
X132600000Y-42142000D01*
|
||||
X106150000Y-45742000D02*
|
||||
X132600000Y-45742000D01*
|
||||
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48061
pcb/v2_0a/MZ80-80CLR-F_Cu.gbr
Normal file
48061
pcb/v2_0a/MZ80-80CLR-F_Cu.gbr
Normal file
File diff suppressed because it is too large
Load Diff
593
pcb/v2_0a/MZ80-80CLR-F_Fab.gbr
Normal file
593
pcb/v2_0a/MZ80-80CLR-F_Fab.gbr
Normal file
@@ -0,0 +1,593 @@
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||||
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||||
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||||
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||||
X98441000Y-50003000D01*
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
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||||
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||||
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|
||||
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|
||||
X78651000Y-102127000D01*
|
||||
D11*
|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
X131516380Y-37854142D02*
|
||||
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|
||||
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|
||||
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|
||||
X130611619Y-37330333D01*
|
||||
X130706857Y-37282714D01*
|
||||
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|
||||
X130944952Y-37330333D01*
|
||||
X130992571Y-37377952D01*
|
||||
X131040190Y-37473190D01*
|
||||
X131040190Y-37854142D01*
|
||||
X131516380Y-36330333D02*
|
||||
X131516380Y-36901761D01*
|
||||
X131516380Y-36616047D02*
|
||||
X130516380Y-36616047D01*
|
||||
X130659238Y-36711285D01*
|
||||
X130754476Y-36806523D01*
|
||||
X130802095Y-36901761D01*
|
||||
M02*
|
||||
16123
pcb/v2_0a/MZ80-80CLR-F_Mask.gbr
Normal file
16123
pcb/v2_0a/MZ80-80CLR-F_Mask.gbr
Normal file
File diff suppressed because it is too large
Load Diff
29397
pcb/v2_0a/MZ80-80CLR-F_Paste.gbr
Normal file
29397
pcb/v2_0a/MZ80-80CLR-F_Paste.gbr
Normal file
File diff suppressed because it is too large
Load Diff
8030
pcb/v2_0a/MZ80-80CLR-F_SilkS.gbr
Normal file
8030
pcb/v2_0a/MZ80-80CLR-F_SilkS.gbr
Normal file
File diff suppressed because it is too large
Load Diff
13
pcb/v2_0a/MZ80-80CLR-Margin.gbr
Normal file
13
pcb/v2_0a/MZ80-80CLR-Margin.gbr
Normal file
@@ -0,0 +1,13 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.2-1)-1*
|
||||
G04 #@! TF.CreationDate,2020-07-07T12:37:09+01:00*
|
||||
G04 #@! TF.ProjectId,MZ80-80CLR,4d5a3830-2d38-4304-934c-522e6b696361,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Other,User*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:37:09*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
109
pcb/v2_0a/MZ80-80CLR-NPTH-drl_map.gbr
Normal file
109
pcb/v2_0a/MZ80-80CLR-NPTH-drl_map.gbr
Normal file
@@ -0,0 +1,109 @@
|
||||
%FSLAX45Y45*%
|
||||
G04 Gerber Fmt 4.5, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW (5.1.2-1)-1) date 2020-07-07 12:36:55*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,0.100000*%
|
||||
%ADD11C,0.200000*%
|
||||
%ADD12C,0.300000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X13398500Y-6223000D02*
|
||||
X14200000Y-6223000D01*
|
||||
X13398500Y-3300000D02*
|
||||
X13398500Y-6223000D01*
|
||||
X13398500Y-3300000D02*
|
||||
X7048500Y-3300000D01*
|
||||
X14200000Y-13300000D02*
|
||||
X14200000Y-6223000D01*
|
||||
X7048500Y-13300000D02*
|
||||
X14200000Y-13300000D01*
|
||||
X7048500Y-3300000D02*
|
||||
X7048500Y-13300000D01*
|
||||
D11*
|
||||
D12*
|
||||
X7329928Y-13770714D02*
|
||||
X7329928Y-13470714D01*
|
||||
X7401357Y-13470714D01*
|
||||
X7444214Y-13485000D01*
|
||||
X7472786Y-13513571D01*
|
||||
X7487071Y-13542143D01*
|
||||
X7501357Y-13599286D01*
|
||||
X7501357Y-13642143D01*
|
||||
X7487071Y-13699286D01*
|
||||
X7472786Y-13727857D01*
|
||||
X7444214Y-13756429D01*
|
||||
X7401357Y-13770714D01*
|
||||
X7329928Y-13770714D01*
|
||||
X7629928Y-13770714D02*
|
||||
X7629928Y-13570714D01*
|
||||
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13
pcb/v2_0a/MZ80-80CLR-NPTH.drl
Normal file
13
pcb/v2_0a/MZ80-80CLR-NPTH.drl
Normal file
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M48
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||||
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||||
T0
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||||
M30
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2149
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2149
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pcb/v2_0a/MZ80-80CLR-PTH.drl
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Normal file
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||||
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||||
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||||
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|
||||
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|
||||
G90
|
||||
G05
|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
T2
|
||||
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|
||||
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|
||||
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|
||||
X79.02Y-130.27
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||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
X96.8Y-130.27
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
T3
|
||||
X107.95Y-49.149
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
M30
|
||||
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Normal file
BIN
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Normal file
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Normal file
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Normal file
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2958
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Normal file
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Normal file
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Normal file
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144
schematics/v1.0/Graphic.pretty/CycloneInside.kicad_mod
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144
schematics/v1.0/Graphic.pretty/CycloneInside.kicad_mod
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291
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291
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(fp_poly (pts (xy -0.045813 -2.921426) (xy -0.024497 -2.880847) (xy -0.009619 -2.814088) (xy -0.004270 -2.766284) (xy -0.001895 -2.717228) (xy -0.004963 -2.673459) (xy -0.015035 -2.625462) (xy -0.033673 -2.563719)
|
||||
(xy -0.041279 -2.540765) (xy -0.103875 -2.386905) (xy -0.180923 -2.256515) (xy -0.273357 -2.148291) (xy -0.382108 -2.060931) (xy -0.386715 -2.057915) (xy -0.429632 -2.031038) (xy -0.463523 -2.011662)
|
||||
(xy -0.481355 -2.003797) (xy -0.481696 -2.003778) (xy -0.493295 -2.015760) (xy -0.502573 -2.040521) (xy -0.508953 -2.096691) (xy -0.506531 -2.171537) (xy -0.496269 -2.257255) (xy -0.479126 -2.346041)
|
||||
(xy -0.456065 -2.430091) (xy -0.453733 -2.437151) (xy -0.402112 -2.573390) (xy -0.345580 -2.690439) (xy -0.285415 -2.786625) (xy -0.222894 -2.860276) (xy -0.159294 -2.909720) (xy -0.095894 -2.933285)
|
||||
(xy -0.073274 -2.935111) (xy -0.045813 -2.921426) )(layer F.SilkS) (width 0.010000)
|
||||
)
|
||||
(fp_poly (pts (xy 3.756222 -4.902438) (xy 3.805510 -4.878984) (xy 3.833175 -4.842154) (xy 3.838222 -4.813052) (xy 3.827101 -4.768900) (xy 3.793000 -4.738217) (xy 3.734814 -4.720245) (xy 3.696582 -4.715805)
|
||||
(xy 3.612445 -4.709719) (xy 3.612445 -4.910667) (xy 3.688153 -4.910667) (xy 3.756222 -4.902438) )(layer F.SilkS) (width 0.010000)
|
||||
)
|
||||
)
|
||||
1708
schematics/v1.0/MZ80-80CLR_v1.dsn
Normal file
1708
schematics/v1.0/MZ80-80CLR_v1.dsn
Normal file
File diff suppressed because it is too large
Load Diff
BIN
schematics/v1.0/MZ80-80CLR_v1.jpg
Normal file
BIN
schematics/v1.0/MZ80-80CLR_v1.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 167 KiB |
12935
schematics/v1.0/MZ80-80CLR_v1.kicad_pcb
Normal file
12935
schematics/v1.0/MZ80-80CLR_v1.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
43
schematics/v1.0/MZ80-80CLR_v1.pro
Normal file
43
schematics/v1.0/MZ80-80CLR_v1.pro
Normal file
@@ -0,0 +1,43 @@
|
||||
update=Wednesday, 08 April 2020 at 15:28:07
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=39
|
||||
ERC_TestSimilarLabels=1
|
||||
71
schematics/v1.0/MZ80-80CLR_v1.sch
Normal file
71
schematics/v1.0/MZ80-80CLR_v1.sch
Normal file
@@ -0,0 +1,71 @@
|
||||
EESchema Schematic File Version 4
|
||||
LIBS:MZ80-80CLR-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 3
|
||||
Title "Sharp MZ-80A 40/80 Column Colour Adapter"
|
||||
Date "2019-08-23"
|
||||
Rev "1.0"
|
||||
Comp ""
|
||||
Comment1 "display."
|
||||
Comment2 "specification to allow colour output and selectable 40/80 column"
|
||||
Comment3 "along with the colour board connector CN1 extends the MZ-80A"
|
||||
Comment4 "An add on board, located as an extender in sockets of IC20, 31 and 8"
|
||||
$EndDescr
|
||||
$Sheet
|
||||
S 950 800 2600 1800
|
||||
U 689FAE6F
|
||||
F0 "Colour" 39
|
||||
F1 "Colour.sch" 39
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1000 3250 2500 1750
|
||||
U 68A807E5
|
||||
F0 "40-80Column" 39
|
||||
F1 "40-80Column.sch" 39
|
||||
$EndSheet
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H3
|
||||
U 1 1 6B339D40
|
||||
P 1000 7150
|
||||
F 0 "H3" H 1100 7153 50 0000 L CNN
|
||||
F 1 "MountingHole_Pad" H 1100 7108 50 0001 L CNN
|
||||
F 2 "MountingHole:MountingHole_2.7mm_M2.5_ISO7380" H 1000 7150 50 0001 C CNN
|
||||
F 3 "~" H 1000 7150 50 0001 C CNN
|
||||
1 1000 7150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H4
|
||||
U 1 1 6B339F6D
|
||||
P 1350 7150
|
||||
F 0 "H4" H 1450 7153 50 0000 L CNN
|
||||
F 1 "MountingHole_Pad" H 1450 7108 50 0001 L CNN
|
||||
F 2 "MountingHole:MountingHole_2.7mm_M2.5_ISO7380" H 1350 7150 50 0001 C CNN
|
||||
F 3 "~" H 1350 7150 50 0001 C CNN
|
||||
1 1350 7150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDPWR #PWR01
|
||||
U 1 1 6BE70104
|
||||
P 1000 7450
|
||||
F 0 "#PWR01" H 1000 7250 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1004 7296 50 0000 C CNN
|
||||
F 2 "" H 1000 7400 50 0001 C CNN
|
||||
F 3 "" H 1000 7400 50 0001 C CNN
|
||||
1 1000 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1350 7400 1350 7250
|
||||
Wire Wire Line
|
||||
1000 7250 1000 7400
|
||||
Wire Wire Line
|
||||
1000 7400 1350 7400
|
||||
Wire Wire Line
|
||||
1000 7400 1000 7450
|
||||
Connection ~ 1000 7400
|
||||
$EndSCHEMATC
|
||||
6940
schematics/v1.0/MZ80-80CLR_v1.ses
Normal file
6940
schematics/v1.0/MZ80-80CLR_v1.ses
Normal file
File diff suppressed because it is too large
Load Diff
406
schematics/v2.0/40-80-Column_CG.sch
Normal file
406
schematics/v2.0/40-80-Column_CG.sch
Normal file
@@ -0,0 +1,406 @@
|
||||
EESchema Schematic File Version 4
|
||||
LIBS:MZ80-80CLR-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 6 6
|
||||
Title "MZ-80A 40/80 Column & CG Module"
|
||||
Date "2020-06-25"
|
||||
Rev "2.0"
|
||||
Comp ""
|
||||
Comment1 "to allow the selection of different character sets."
|
||||
Comment2 "columns. Additionally expand the character generation ROM"
|
||||
Comment3 "create the ability to programmatically switch between 40/80."
|
||||
Comment4 "Using original gate arrays with logic substituted with the CPLD"
|
||||
$EndDescr
|
||||
Entry Wire Line
|
||||
1300 650 1400 750
|
||||
Entry Wire Line
|
||||
1300 850 1400 950
|
||||
Entry Wire Line
|
||||
1300 950 1400 1050
|
||||
Entry Wire Line
|
||||
1300 1050 1400 1150
|
||||
Entry Wire Line
|
||||
1300 1150 1400 1250
|
||||
Entry Wire Line
|
||||
1300 1250 1400 1350
|
||||
Entry Wire Line
|
||||
1300 1350 1400 1450
|
||||
Entry Bus Bus
|
||||
1400 650 1500 550
|
||||
NoConn ~ 4000 2350
|
||||
NoConn ~ 4000 2250
|
||||
NoConn ~ 4000 1800
|
||||
Wire Wire Line
|
||||
4850 1100 4900 1100
|
||||
Wire Wire Line
|
||||
4850 2350 5100 2350
|
||||
Wire Wire Line
|
||||
4850 2550 5400 2550
|
||||
Wire Wire Line
|
||||
4850 2650 5350 2650
|
||||
$Comp
|
||||
L power:+5V #PWR048
|
||||
U 1 1 68ED3C76
|
||||
P 5400 2500
|
||||
F 0 "#PWR048" H 5400 2350 50 0001 C CNN
|
||||
F 1 "+5V" H 5415 2673 50 0000 C CNN
|
||||
F 2 "" H 5400 2500 50 0001 C CNN
|
||||
F 3 "" H 5400 2500 50 0001 C CNN
|
||||
1 5400 2500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 5400 2500
|
||||
$Comp
|
||||
L power:GNDPWR #PWR047
|
||||
U 1 1 68ED479B
|
||||
P 5350 2650
|
||||
F 0 "#PWR047" H 5350 2450 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 5354 2496 50 0000 C CNN
|
||||
F 2 "" H 5350 2600 50 0001 C CNN
|
||||
F 3 "" H 5350 2600 50 0001 C CNN
|
||||
1 5350 2650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 5350 2650
|
||||
$Comp
|
||||
L 74xx:74LS165_Socket SK3
|
||||
U 1 1 68F3B395
|
||||
P 2550 1850
|
||||
F 0 "SK3" H 2550 1650 50 0000 C CNN
|
||||
F 1 "IC8 Socket" H 2600 1550 50 0000 C CNN
|
||||
F 2 "Package_DIP:DIP-16_W7.62mm_Socket" H 2550 1850 50 0001 C CNN
|
||||
F 3 "http://www.ti.com/lit/gpn/sn74LS165" H 2550 1850 50 0001 C CNN
|
||||
1 2550 1850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2550 2900 2550 2850
|
||||
Wire Wire Line
|
||||
2550 900 2550 950
|
||||
$Comp
|
||||
L power:GNDPWR #PWR041
|
||||
U 1 1 690B70C3
|
||||
P 2550 2900
|
||||
F 0 "#PWR041" H 2550 2700 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 2554 2746 50 0000 C CNN
|
||||
F 2 "" H 2550 2850 50 0001 C CNN
|
||||
F 3 "" H 2550 2850 50 0001 C CNN
|
||||
1 2550 2900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR042
|
||||
U 1 1 690B76CC
|
||||
P 2550 900
|
||||
F 0 "#PWR042" H 2550 750 50 0001 C CNN
|
||||
F 1 "+5V" H 2565 1073 50 0000 C CNN
|
||||
F 2 "" H 2550 900 50 0001 C CNN
|
||||
F 3 "" H 2550 900 50 0001 C CNN
|
||||
1 2550 900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 2050 2250
|
||||
NoConn ~ 2050 2450
|
||||
$Comp
|
||||
L Device:C_Small C42
|
||||
U 1 1 694D8E82
|
||||
P 5500 2500
|
||||
F 0 "C42" V 5400 2450 50 0000 L CNN
|
||||
F 1 "100nF" V 5600 2450 31 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric_Pad1.05x0.95mm_HandSolder" H 5500 2500 50 0001 C CNN
|
||||
F 3 "~" H 5500 2500 50 0001 C CNN
|
||||
1 5500 2500
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5600 2500 5600 2650
|
||||
Wire Wire Line
|
||||
5400 2500 5400 2550
|
||||
Wire Wire Line
|
||||
5600 2650 5350 2650
|
||||
NoConn ~ 4000 2050
|
||||
NoConn ~ 4000 1300
|
||||
Entry Wire Line
|
||||
5000 550 5100 650
|
||||
Text Label 3650 650 3 31 ~ 0
|
||||
2MHZ_OUT
|
||||
Entry Wire Line
|
||||
3350 550 3450 650
|
||||
Entry Wire Line
|
||||
3450 550 3550 650
|
||||
Text Label 3450 650 3 31 ~ 0
|
||||
1MHZ_OUT
|
||||
Entry Wire Line
|
||||
4800 550 4900 650
|
||||
Text Label 3750 650 3 31 ~ 0
|
||||
31.5K_OUT
|
||||
Entry Wire Line
|
||||
3550 550 3650 650
|
||||
Entry Wire Line
|
||||
3650 550 3750 650
|
||||
Text Label 5100 650 3 31 ~ 0
|
||||
~VBLNK_OUT~
|
||||
Entry Wire Line
|
||||
4900 550 5000 650
|
||||
NoConn ~ 3050 1350
|
||||
Entry Wire Line
|
||||
3000 550 3100 650
|
||||
Text Label 3100 650 3 31 ~ 0
|
||||
SRVIDEO_OUT
|
||||
Wire Wire Line
|
||||
3100 650 3100 1250
|
||||
Wire Wire Line
|
||||
950 650 1300 650
|
||||
Text GLabel 900 1350 0 39 Input ~ 0
|
||||
~VBLNK_OUT~
|
||||
Text GLabel 900 850 0 39 Input ~ 0
|
||||
~HBLNK_OUT~
|
||||
Text GLabel 900 1450 0 39 Output ~ 0
|
||||
~VRAM_CS_IN~
|
||||
Text GLabel 800 1150 0 39 Input ~ 0
|
||||
HSY_OUT
|
||||
Text GLabel 950 650 0 39 Input ~ 0
|
||||
SRVIDEO_OUT
|
||||
Text GLabel 900 1250 0 39 Input ~ 0
|
||||
SYNCH_OUT
|
||||
Text GLabel 850 1050 0 39 Input ~ 0
|
||||
31.5K_OUT
|
||||
Text GLabel 850 950 0 39 Input ~ 0
|
||||
2MHZ_OUT
|
||||
Wire Wire Line
|
||||
3050 1250 3100 1250
|
||||
NoConn ~ 2050 2550
|
||||
NoConn ~ 2050 1250
|
||||
Text GLabel 950 3350 0 39 BiDi ~ 0
|
||||
VRAMD0[7..0]
|
||||
Entry Bus Bus
|
||||
3100 3450 3000 3350
|
||||
Entry Wire Line
|
||||
1300 750 1400 850
|
||||
Text GLabel 850 750 0 39 Input ~ 0
|
||||
1MHZ_OUT
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 76370325
|
||||
P 2250 3650
|
||||
AR Path="/76370325" Ref="#PWR?" Part="1"
|
||||
AR Path="/689FAE6F/76370325" Ref="#PWR?" Part="1"
|
||||
AR Path="/600002AE/76370325" Ref="#PWR?" Part="1"
|
||||
AR Path="/6E14A406/76370325" Ref="#PWR0102" Part="1"
|
||||
F 0 "#PWR0102" H 2250 3500 50 0001 C CNN
|
||||
F 1 "+5V" H 2250 3800 50 0000 C CNN
|
||||
F 2 "" H 2250 3650 50 0001 C CNN
|
||||
F 3 "" H 2250 3650 50 0001 C CNN
|
||||
1 2250 3650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDPWR #PWR039
|
||||
U 1 1 742271BF
|
||||
P 2250 5350
|
||||
F 0 "#PWR039" H 2250 5150 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 2254 5196 50 0000 C CNN
|
||||
F 2 "" H 2250 5300 50 0001 C CNN
|
||||
F 3 "" H 2250 5300 50 0001 C CNN
|
||||
1 2250 5350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L MZ80-80CLR-rescue:2016_Socket SK?
|
||||
U 1 1 66246898
|
||||
P 2250 4500
|
||||
AR Path="/66246898" Ref="SK?" Part="1"
|
||||
AR Path="/689FAE6F/66246898" Ref="SK?" Part="1"
|
||||
AR Path="/600002AE/66246898" Ref="SK?" Part="1"
|
||||
AR Path="/6E14A406/66246898" Ref="SK1" Part="1"
|
||||
F 0 "SK1" H 2250 4200 50 0000 C CNN
|
||||
F 1 "IC15 Socket" H 2250 4100 50 0000 C CNN
|
||||
F 2 "Package_DIP:DIP-24_W15.24mm_Socket" H 2250 4500 50 0001 C CNN
|
||||
F 3 "" H 2250 4500 50 0001 C CNN
|
||||
1 2250 4500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Entry Wire Line
|
||||
3000 4250 3100 4350
|
||||
Entry Wire Line
|
||||
3000 4350 3100 4450
|
||||
Entry Wire Line
|
||||
3000 4450 3100 4550
|
||||
Entry Wire Line
|
||||
3000 4550 3100 4650
|
||||
Text Label 2700 4250 0 31 ~ 0
|
||||
VRAMD4
|
||||
Text Label 2700 4350 0 31 ~ 0
|
||||
VRAMD5
|
||||
Text Label 2700 4450 0 31 ~ 0
|
||||
VRAMD6
|
||||
Text Label 2700 4550 0 31 ~ 0
|
||||
VRAMD7
|
||||
Entry Wire Line
|
||||
3000 3850 3100 3950
|
||||
Entry Wire Line
|
||||
3000 3950 3100 4050
|
||||
Entry Wire Line
|
||||
3000 4050 3100 4150
|
||||
Entry Wire Line
|
||||
3000 4150 3100 4250
|
||||
Text Label 2700 3850 0 31 ~ 0
|
||||
VRAMD0
|
||||
Text Label 2700 3950 0 31 ~ 0
|
||||
VRAMD1
|
||||
Text Label 2700 4050 0 31 ~ 0
|
||||
VRAMD2
|
||||
Text Label 2700 4150 0 31 ~ 0
|
||||
VRAMD3
|
||||
Wire Wire Line
|
||||
2650 3850 3000 3850
|
||||
Wire Wire Line
|
||||
2650 3950 3000 3950
|
||||
Wire Wire Line
|
||||
2650 4050 3000 4050
|
||||
Wire Wire Line
|
||||
2650 4150 3000 4150
|
||||
Wire Wire Line
|
||||
2650 4250 3000 4250
|
||||
Wire Wire Line
|
||||
2650 4350 3000 4350
|
||||
Wire Wire Line
|
||||
2650 4450 3000 4450
|
||||
Wire Wire Line
|
||||
2650 4550 3000 4550
|
||||
NoConn ~ 1850 5100
|
||||
NoConn ~ 2050 1350
|
||||
NoConn ~ 2050 1450
|
||||
NoConn ~ 2050 1550
|
||||
NoConn ~ 2050 1650
|
||||
NoConn ~ 2050 1750
|
||||
NoConn ~ 2050 1850
|
||||
NoConn ~ 2050 1950
|
||||
NoConn ~ 2050 2050
|
||||
Wire Bus Line
|
||||
950 3350 3000 3350
|
||||
NoConn ~ 1850 3800
|
||||
NoConn ~ 1850 3900
|
||||
NoConn ~ 1850 4000
|
||||
NoConn ~ 1850 4100
|
||||
NoConn ~ 1850 4200
|
||||
NoConn ~ 1850 4300
|
||||
NoConn ~ 1850 4400
|
||||
NoConn ~ 1850 4500
|
||||
NoConn ~ 1850 4600
|
||||
NoConn ~ 1850 4700
|
||||
NoConn ~ 1850 4800
|
||||
NoConn ~ 1850 5000
|
||||
NoConn ~ 4300 2950
|
||||
NoConn ~ 4400 2950
|
||||
NoConn ~ 4500 2950
|
||||
Wire Wire Line
|
||||
4000 2450 3950 2450
|
||||
Wire Wire Line
|
||||
3950 2450 3950 2550
|
||||
Wire Wire Line
|
||||
3950 2550 4000 2550
|
||||
Wire Wire Line
|
||||
3950 2550 3950 2650
|
||||
Wire Wire Line
|
||||
3950 2650 4000 2650
|
||||
Connection ~ 3950 2550
|
||||
Wire Wire Line
|
||||
3950 2650 3950 2700
|
||||
Connection ~ 3950 2650
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 5FB6960C
|
||||
P 3950 2700
|
||||
F 0 "#PWR?" H 3950 2500 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3954 2546 50 0000 C CNN
|
||||
F 2 "" H 3950 2650 50 0001 C CNN
|
||||
F 3 "" H 3950 2650 50 0001 C CNN
|
||||
1 3950 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Memory_RAM:MB14298_Socket SK4
|
||||
U 1 1 68A811B6
|
||||
P 4400 1950
|
||||
F 0 "SK4" H 4450 2450 39 0000 C CNN
|
||||
F 1 "IC20 Socket" H 4500 2350 39 0000 C CNN
|
||||
F 2 "Package_DIP:DIP-28_W15.24mm_Socket" H 4400 2950 39 0001 C CNN
|
||||
F 3 "" H 4400 2950 39 0001 C CNN
|
||||
1 4400 1950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 4000 1600
|
||||
NoConn ~ 4000 1500
|
||||
NoConn ~ 4000 1200
|
||||
NoConn ~ 4850 1850
|
||||
NoConn ~ 4850 1950
|
||||
NoConn ~ 4850 2050
|
||||
NoConn ~ 4850 2250
|
||||
NoConn ~ 4850 2450
|
||||
Wire Wire Line
|
||||
4900 1100 4900 650
|
||||
Wire Wire Line
|
||||
5000 1700 5000 650
|
||||
Wire Wire Line
|
||||
4850 1700 5000 1700
|
||||
Wire Wire Line
|
||||
5100 2350 5100 650
|
||||
Text Label 4900 650 3 31 ~ 0
|
||||
HSY_OUT
|
||||
Text Label 5000 650 3 31 ~ 0
|
||||
SYNCH_OUT
|
||||
Wire Wire Line
|
||||
3750 1100 3750 650
|
||||
Wire Wire Line
|
||||
3750 1100 4000 1100
|
||||
Wire Wire Line
|
||||
3650 1700 3650 650
|
||||
Wire Wire Line
|
||||
3650 1700 4000 1700
|
||||
Wire Wire Line
|
||||
3550 1950 3550 650
|
||||
Wire Wire Line
|
||||
3550 1950 4000 1950
|
||||
Text Label 3550 650 3 31 ~ 0
|
||||
~HBLNK_OUT~
|
||||
Wire Wire Line
|
||||
3450 2150 3450 650
|
||||
Wire Wire Line
|
||||
3450 2150 4000 2150
|
||||
Wire Wire Line
|
||||
1850 5200 1700 5200
|
||||
Wire Wire Line
|
||||
1700 5200 1700 650
|
||||
Entry Wire Line
|
||||
1600 550 1700 650
|
||||
Text Label 1700 650 3 31 ~ 0
|
||||
~VRAM_CS_IN~
|
||||
Wire Wire Line
|
||||
850 750 1300 750
|
||||
Wire Wire Line
|
||||
900 850 1300 850
|
||||
Wire Wire Line
|
||||
850 950 1300 950
|
||||
Wire Wire Line
|
||||
850 1050 1300 1050
|
||||
Wire Wire Line
|
||||
800 1150 1300 1150
|
||||
Wire Wire Line
|
||||
900 1250 1300 1250
|
||||
Wire Wire Line
|
||||
900 1350 1300 1350
|
||||
Wire Wire Line
|
||||
900 1450 1300 1450
|
||||
Entry Wire Line
|
||||
1300 1450 1400 1550
|
||||
Wire Bus Line
|
||||
1500 550 5000 550
|
||||
Wire Bus Line
|
||||
1400 650 1400 1550
|
||||
Wire Bus Line
|
||||
3100 3450 3100 4650
|
||||
$EndSCHEMATC
|
||||
1247
schematics/v2.0/40-80Column.sch
Normal file
1247
schematics/v2.0/40-80Column.sch
Normal file
File diff suppressed because it is too large
Load Diff
1247
schematics/v2.0/40-80Column_open.sch
Normal file
1247
schematics/v2.0/40-80Column_open.sch
Normal file
File diff suppressed because it is too large
Load Diff
2223
schematics/v2.0/CPLD.sch
Normal file
2223
schematics/v2.0/CPLD.sch
Normal file
File diff suppressed because it is too large
Load Diff
707
schematics/v2.0/Colour.sch
Normal file
707
schematics/v2.0/Colour.sch
Normal file
@@ -0,0 +1,707 @@
|
||||
EESchema Schematic File Version 4
|
||||
LIBS:MZ80-80CLR-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 3 6
|
||||
Title "MZ-80A Colour Output Module"
|
||||
Date "2020-06-25"
|
||||
Rev "2.0"
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 "by the FPGA based on the serialised video stream."
|
||||
Comment4 "Output circuits to an RGB/Composite monitor. The RGB is generated"
|
||||
$EndDescr
|
||||
Text Label 5650 3500 0 39 ~ 0
|
||||
Composite
|
||||
Wire Wire Line
|
||||
5250 4650 5300 4650
|
||||
Wire Wire Line
|
||||
4650 5200 4700 5200
|
||||
Wire Wire Line
|
||||
4800 4250 4950 4250
|
||||
Wire Wire Line
|
||||
4800 4250 4800 4050
|
||||
Connection ~ 4800 4250
|
||||
Wire Wire Line
|
||||
4650 4250 4800 4250
|
||||
Wire Wire Line
|
||||
4950 4250 4950 4350
|
||||
Wire Wire Line
|
||||
4650 4350 4650 4250
|
||||
Wire Wire Line
|
||||
4650 4550 4650 4600
|
||||
Wire Wire Line
|
||||
4950 5200 4900 5200
|
||||
Wire Wire Line
|
||||
4950 5100 4950 5200
|
||||
Wire Wire Line
|
||||
4950 4650 4950 4700
|
||||
Wire Wire Line
|
||||
4950 4650 5050 4650
|
||||
Connection ~ 4950 4650
|
||||
Wire Wire Line
|
||||
4950 4550 4950 4650
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6063CCC0
|
||||
P 5150 4650
|
||||
AR Path="/6063CCC0" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/6063CCC0" Ref="R22" Part="1"
|
||||
AR Path="/600002AE/6063CCC0" Ref="R?" Part="1"
|
||||
F 0 "R22" V 5250 4700 50 0000 R CNN
|
||||
F 1 "68R" V 5150 4700 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5150 4650 50 0001 C CNN
|
||||
F 3 "~" H 5150 4650 50 0001 C CNN
|
||||
1 5150 4650
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6063C63F
|
||||
P 4800 5200
|
||||
AR Path="/6063C63F" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/6063C63F" Ref="R20" Part="1"
|
||||
AR Path="/600002AE/6063C63F" Ref="R?" Part="1"
|
||||
F 0 "R20" V 4700 5250 50 0000 R CNN
|
||||
F 1 "220R" V 4800 5250 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4800 5200 50 0001 C CNN
|
||||
F 3 "~" H 4800 5200 50 0001 C CNN
|
||||
1 4800 5200
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 60600D5F
|
||||
P 4650 4450
|
||||
AR Path="/60600D5F" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/60600D5F" Ref="R19" Part="1"
|
||||
AR Path="/600002AE/60600D5F" Ref="R?" Part="1"
|
||||
F 0 "R19" H 4850 4400 50 0000 R CNN
|
||||
F 1 "1K" V 4650 4500 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4650 4450 50 0001 C CNN
|
||||
F 3 "~" H 4650 4450 50 0001 C CNN
|
||||
1 4650 4450
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 605FF538
|
||||
P 4950 4450
|
||||
AR Path="/605FF538" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/605FF538" Ref="R21" Part="1"
|
||||
AR Path="/600002AE/605FF538" Ref="R?" Part="1"
|
||||
F 0 "R21" H 5150 4400 50 0000 R CNN
|
||||
F 1 "68R" V 4950 4500 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4950 4450 50 0001 C CNN
|
||||
F 3 "~" H 4950 4450 50 0001 C CNN
|
||||
1 4950 4450
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Text Label 5650 3400 0 39 ~ 0
|
||||
CSYNC
|
||||
$Comp
|
||||
L Connector_Generic:Conn_01x10 J1
|
||||
U 1 1 5FA8230F
|
||||
P 5550 3000
|
||||
AR Path="/689FAE6F/5FA8230F" Ref="J1" Part="1"
|
||||
AR Path="/600002AE/5FA8230F" Ref="J?" Part="1"
|
||||
F 0 "J1" H 5500 2350 50 0000 L CNN
|
||||
F 1 "RGB" H 5450 2250 50 0000 L CNN
|
||||
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x10_P2.54mm_Vertical" H 5550 3000 50 0001 C CNN
|
||||
F 3 "~" H 5550 3000 50 0001 C CNN
|
||||
1 5550 3000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4550 4800 4650 4800
|
||||
Wire Wire Line
|
||||
4650 4600 4550 4600
|
||||
Connection ~ 4650 4600
|
||||
Wire Wire Line
|
||||
4650 4900 4650 4800
|
||||
Connection ~ 4650 4900
|
||||
Connection ~ 4650 5200
|
||||
Wire Wire Line
|
||||
4650 5200 4650 5000
|
||||
Wire Wire Line
|
||||
4550 5200 4650 5200
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 5F6ECB08
|
||||
P 4450 5000
|
||||
AR Path="/5F6ECB08" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/5F6ECB08" Ref="R17" Part="1"
|
||||
AR Path="/600002AE/5F6ECB08" Ref="R?" Part="1"
|
||||
F 0 "R17" V 4350 5050 50 0000 R CNN
|
||||
F 1 "1K" V 4450 5000 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4450 5000 50 0001 C CNN
|
||||
F 3 "~" H 4450 5000 50 0001 C CNN
|
||||
1 4450 5000
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 5F6EC67F
|
||||
P 4450 4600
|
||||
AR Path="/5F6EC67F" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/5F6EC67F" Ref="R15" Part="1"
|
||||
AR Path="/600002AE/5F6EC67F" Ref="R?" Part="1"
|
||||
F 0 "R15" V 4350 4650 50 0000 R CNN
|
||||
F 1 "3K9" V 4450 4650 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4450 4600 50 0001 C CNN
|
||||
F 3 "~" H 4450 4600 50 0001 C CNN
|
||||
1 4450 4600
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 5F6EB43F
|
||||
P 4450 4800
|
||||
AR Path="/5F6EB43F" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/5F6EB43F" Ref="R16" Part="1"
|
||||
AR Path="/600002AE/5F6EB43F" Ref="R?" Part="1"
|
||||
F 0 "R16" V 4350 4850 50 0000 R CNN
|
||||
F 1 "2K2" V 4450 4850 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4450 4800 50 0001 C CNN
|
||||
F 3 "~" H 4450 4800 50 0001 C CNN
|
||||
1 4450 4800
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Transistor_BJT:BC307 Q1
|
||||
U 1 1 5F6E5CFD
|
||||
P 4850 4900
|
||||
AR Path="/689FAE6F/5F6E5CFD" Ref="Q1" Part="1"
|
||||
AR Path="/600002AE/5F6E5CFD" Ref="Q?" Part="1"
|
||||
F 0 "Q1" H 4800 4650 50 0000 L CNN
|
||||
F 1 "BC309" H 4700 4750 50 0000 L CNN
|
||||
F 2 "Package_TO_SOT_THT:TO-92_Inline" H 5050 4825 50 0001 L CIN
|
||||
F 3 "http://www.onsemi.com/pub_link/Collateral/BC307-D.PDF" H 4850 4900 50 0001 L CNN
|
||||
1 4850 4900
|
||||
1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 68A6544E
|
||||
P 4950 2700
|
||||
AR Path="/68A6544E" Ref="#PWR?" Part="1"
|
||||
AR Path="/689FAE6F/68A6544E" Ref="#PWR017" Part="1"
|
||||
AR Path="/600002AE/68A6544E" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR017" H 4950 2500 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 5150 2650 50 0000 C CNN
|
||||
F 2 "" H 4950 2650 50 0001 C CNN
|
||||
F 3 "" H 4950 2650 50 0001 C CNN
|
||||
1 4950 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5350 2600 5350 2500
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 68A65426
|
||||
P 5350 2500
|
||||
AR Path="/68A65426" Ref="#PWR?" Part="1"
|
||||
AR Path="/689FAE6F/68A65426" Ref="#PWR018" Part="1"
|
||||
AR Path="/600002AE/68A65426" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR018" H 5350 2350 50 0001 C CNN
|
||||
F 1 "+5V" H 5365 2673 50 0000 C CNN
|
||||
F 2 "" H 5350 2500 50 0001 C CNN
|
||||
F 3 "" H 5350 2500 50 0001 C CNN
|
||||
1 5350 2500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 5650 3300 0 39 ~ 0
|
||||
~CSYNC~
|
||||
Text Label 5650 3200 0 39 ~ 0
|
||||
VS
|
||||
Text Label 5650 3100 0 39 ~ 0
|
||||
HS
|
||||
Text Label 5650 3000 0 39 ~ 0
|
||||
GREEN
|
||||
Text Label 5650 2900 0 39 ~ 0
|
||||
RED
|
||||
Text Label 5650 2800 0 39 ~ 0
|
||||
BLUE
|
||||
Text Label 5650 2700 0 39 ~ 0
|
||||
GND
|
||||
Text Label 5650 2600 0 39 ~ 0
|
||||
5V
|
||||
Text GLabel 2000 2450 0 39 Input ~ 0
|
||||
VGA_R[3..0]
|
||||
Text GLabel 2000 3200 0 39 Input ~ 0
|
||||
VGA_G[3..0]
|
||||
Text GLabel 2000 1700 0 39 Input ~ 0
|
||||
VGA_B[3..0]
|
||||
Text GLabel 1900 4000 0 39 Input ~ 0
|
||||
VGA_HS
|
||||
Text GLabel 1900 4100 0 39 Input ~ 0
|
||||
VGA_VS
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74A3EA3C
|
||||
P 3200 2650
|
||||
AR Path="/74A3EA3C" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74A3EA3C" Ref="R5" Part="1"
|
||||
AR Path="/600002AE/74A3EA3C" Ref="R?" Part="1"
|
||||
F 0 "R5" V 3150 2800 50 0000 C CNN
|
||||
F 1 "500R" V 3200 2650 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 2650 50 0001 C CNN
|
||||
F 3 "~" H 3200 2650 50 0001 C CNN
|
||||
1 3200 2650
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74A70F1C
|
||||
P 3200 2950
|
||||
AR Path="/74A70F1C" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74A70F1C" Ref="R7" Part="1"
|
||||
AR Path="/600002AE/74A70F1C" Ref="R?" Part="1"
|
||||
F 0 "R7" V 3150 3100 50 0000 C CNN
|
||||
F 1 "2K" V 3200 2950 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 2950 50 0001 C CNN
|
||||
F 3 "~" H 3200 2950 50 0001 C CNN
|
||||
1 3200 2950
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74A9DCF3
|
||||
P 3200 2800
|
||||
AR Path="/74A9DCF3" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74A9DCF3" Ref="R6" Part="1"
|
||||
AR Path="/600002AE/74A9DCF3" Ref="R?" Part="1"
|
||||
F 0 "R6" V 3150 2950 50 0000 C CNN
|
||||
F 1 "1K" V 3200 2800 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 2800 50 0001 C CNN
|
||||
F 3 "~" H 3200 2800 50 0001 C CNN
|
||||
1 3200 2800
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74ACA98C
|
||||
P 3200 3100
|
||||
AR Path="/74ACA98C" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74ACA98C" Ref="R8" Part="1"
|
||||
AR Path="/600002AE/74ACA98C" Ref="R?" Part="1"
|
||||
F 0 "R8" V 3150 3250 50 0000 C CNN
|
||||
F 1 "4K" V 3200 3100 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 3100 50 0001 C CNN
|
||||
F 3 "~" H 3200 3100 50 0001 C CNN
|
||||
1 3200 3100
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Entry Bus Bus
|
||||
2650 2450 2750 2550
|
||||
Wire Bus Line
|
||||
2000 2450 2650 2450
|
||||
Entry Wire Line
|
||||
2750 2550 2850 2650
|
||||
Entry Wire Line
|
||||
2750 2700 2850 2800
|
||||
Entry Wire Line
|
||||
2750 2850 2850 2950
|
||||
Entry Wire Line
|
||||
2750 3000 2850 3100
|
||||
Wire Wire Line
|
||||
2850 2650 3100 2650
|
||||
Wire Wire Line
|
||||
2850 2800 3100 2800
|
||||
Wire Wire Line
|
||||
2850 2950 3100 2950
|
||||
Wire Wire Line
|
||||
2850 3100 3100 3100
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F65B1E
|
||||
P 3200 3400
|
||||
AR Path="/74F65B1E" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F65B1E" Ref="R9" Part="1"
|
||||
AR Path="/600002AE/74F65B1E" Ref="R?" Part="1"
|
||||
F 0 "R9" V 3150 3550 50 0000 C CNN
|
||||
F 1 "500R" V 3200 3400 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 3400 50 0001 C CNN
|
||||
F 3 "~" H 3200 3400 50 0001 C CNN
|
||||
1 3200 3400
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F65B28
|
||||
P 3200 3700
|
||||
AR Path="/74F65B28" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F65B28" Ref="R11" Part="1"
|
||||
AR Path="/600002AE/74F65B28" Ref="R?" Part="1"
|
||||
F 0 "R11" V 3150 3850 50 0000 C CNN
|
||||
F 1 "2K" V 3200 3700 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 3700 50 0001 C CNN
|
||||
F 3 "~" H 3200 3700 50 0001 C CNN
|
||||
1 3200 3700
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F65B32
|
||||
P 3200 3550
|
||||
AR Path="/74F65B32" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F65B32" Ref="R10" Part="1"
|
||||
AR Path="/600002AE/74F65B32" Ref="R?" Part="1"
|
||||
F 0 "R10" V 3150 3700 50 0000 C CNN
|
||||
F 1 "1K" V 3200 3550 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 3550 50 0001 C CNN
|
||||
F 3 "~" H 3200 3550 50 0001 C CNN
|
||||
1 3200 3550
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F65B3C
|
||||
P 3200 3850
|
||||
AR Path="/74F65B3C" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F65B3C" Ref="R12" Part="1"
|
||||
AR Path="/600002AE/74F65B3C" Ref="R?" Part="1"
|
||||
F 0 "R12" V 3150 4000 50 0000 C CNN
|
||||
F 1 "4K" V 3200 3850 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 3850 50 0001 C CNN
|
||||
F 3 "~" H 3200 3850 50 0001 C CNN
|
||||
1 3200 3850
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Entry Bus Bus
|
||||
2650 3200 2750 3300
|
||||
Entry Wire Line
|
||||
2750 3300 2850 3400
|
||||
Entry Wire Line
|
||||
2750 3450 2850 3550
|
||||
Entry Wire Line
|
||||
2750 3600 2850 3700
|
||||
Entry Wire Line
|
||||
2750 3750 2850 3850
|
||||
Wire Wire Line
|
||||
2850 3400 3100 3400
|
||||
Wire Wire Line
|
||||
2850 3550 3100 3550
|
||||
Wire Wire Line
|
||||
2850 3700 3100 3700
|
||||
Wire Wire Line
|
||||
2850 3850 3100 3850
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F975F6
|
||||
P 3200 1900
|
||||
AR Path="/74F975F6" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F975F6" Ref="R1" Part="1"
|
||||
AR Path="/600002AE/74F975F6" Ref="R?" Part="1"
|
||||
F 0 "R1" V 3150 2050 50 0000 C CNN
|
||||
F 1 "500R" V 3200 1900 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 1900 50 0001 C CNN
|
||||
F 3 "~" H 3200 1900 50 0001 C CNN
|
||||
1 3200 1900
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F97600
|
||||
P 3200 2200
|
||||
AR Path="/74F97600" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F97600" Ref="R3" Part="1"
|
||||
AR Path="/600002AE/74F97600" Ref="R?" Part="1"
|
||||
F 0 "R3" V 3150 2350 50 0000 C CNN
|
||||
F 1 "2K" V 3200 2200 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 2200 50 0001 C CNN
|
||||
F 3 "~" H 3200 2200 50 0001 C CNN
|
||||
1 3200 2200
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F9760A
|
||||
P 3200 2050
|
||||
AR Path="/74F9760A" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F9760A" Ref="R2" Part="1"
|
||||
AR Path="/600002AE/74F9760A" Ref="R?" Part="1"
|
||||
F 0 "R2" V 3150 2200 50 0000 C CNN
|
||||
F 1 "1K" V 3200 2050 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 2050 50 0001 C CNN
|
||||
F 3 "~" H 3200 2050 50 0001 C CNN
|
||||
1 3200 2050
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 74F97614
|
||||
P 3200 2350
|
||||
AR Path="/74F97614" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/74F97614" Ref="R4" Part="1"
|
||||
AR Path="/600002AE/74F97614" Ref="R?" Part="1"
|
||||
F 0 "R4" V 3150 2500 50 0000 C CNN
|
||||
F 1 "4K" V 3200 2350 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 2350 50 0001 C CNN
|
||||
F 3 "~" H 3200 2350 50 0001 C CNN
|
||||
1 3200 2350
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Entry Bus Bus
|
||||
2650 1700 2750 1800
|
||||
Entry Wire Line
|
||||
2750 1800 2850 1900
|
||||
Entry Wire Line
|
||||
2750 1950 2850 2050
|
||||
Entry Wire Line
|
||||
2750 2100 2850 2200
|
||||
Entry Wire Line
|
||||
2750 2250 2850 2350
|
||||
Wire Wire Line
|
||||
2850 1900 3100 1900
|
||||
Wire Wire Line
|
||||
2850 2050 3100 2050
|
||||
Wire Wire Line
|
||||
2850 2200 3100 2200
|
||||
Wire Wire Line
|
||||
2850 2350 3100 2350
|
||||
Wire Bus Line
|
||||
2000 1700 2650 1700
|
||||
Wire Bus Line
|
||||
2000 3200 2650 3200
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 750ECD27
|
||||
P 3200 4000
|
||||
AR Path="/750ECD27" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/750ECD27" Ref="R13" Part="1"
|
||||
AR Path="/600002AE/750ECD27" Ref="R?" Part="1"
|
||||
F 0 "R13" V 3150 4150 50 0000 C CNN
|
||||
F 1 "120R" V 3200 4000 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 4000 50 0001 C CNN
|
||||
F 3 "~" H 3200 4000 50 0001 C CNN
|
||||
1 3200 4000
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 750F0A65
|
||||
P 3200 4100
|
||||
AR Path="/750F0A65" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/750F0A65" Ref="R14" Part="1"
|
||||
AR Path="/600002AE/750F0A65" Ref="R?" Part="1"
|
||||
F 0 "R14" V 3150 4250 50 0000 C CNN
|
||||
F 1 "120R" V 3200 4100 31 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3200 4100 50 0001 C CNN
|
||||
F 3 "~" H 3200 4100 50 0001 C CNN
|
||||
1 3200 4100
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1900 4000 3100 4000
|
||||
Wire Wire Line
|
||||
1900 4100 3100 4100
|
||||
Text Label 2850 2650 0 31 ~ 0
|
||||
VGA_R3
|
||||
Text Label 2850 2800 0 31 ~ 0
|
||||
VGA_R2
|
||||
Text Label 2850 2950 0 31 ~ 0
|
||||
VGA_R1
|
||||
Text Label 2850 3100 0 31 ~ 0
|
||||
VGA_R0
|
||||
Text Label 2850 3400 0 31 ~ 0
|
||||
VGA_G3
|
||||
Text Label 2850 3550 0 31 ~ 0
|
||||
VGA_G2
|
||||
Text Label 2850 3700 0 31 ~ 0
|
||||
VGA_G1
|
||||
Text Label 2850 3850 0 31 ~ 0
|
||||
VGA_G0
|
||||
Text Label 2850 1900 0 31 ~ 0
|
||||
VGA_B3
|
||||
Text Label 2850 2050 0 31 ~ 0
|
||||
VGA_B2
|
||||
Text Label 2850 2200 0 31 ~ 0
|
||||
VGA_B1
|
||||
Text Label 2850 2350 0 31 ~ 0
|
||||
VGA_B0
|
||||
Wire Wire Line
|
||||
3300 1900 3450 1900
|
||||
Wire Wire Line
|
||||
3450 1900 3450 2050
|
||||
Wire Wire Line
|
||||
3450 2350 3300 2350
|
||||
Wire Wire Line
|
||||
3300 2200 3450 2200
|
||||
Connection ~ 3450 2200
|
||||
Wire Wire Line
|
||||
3450 2200 3450 2350
|
||||
Wire Wire Line
|
||||
3300 2050 3450 2050
|
||||
Connection ~ 3450 2050
|
||||
Wire Wire Line
|
||||
3450 2050 3450 2200
|
||||
Wire Wire Line
|
||||
3300 2650 3450 2650
|
||||
Wire Wire Line
|
||||
3450 2650 3450 2800
|
||||
Wire Wire Line
|
||||
3450 3100 3300 3100
|
||||
Wire Wire Line
|
||||
3300 2950 3450 2950
|
||||
Connection ~ 3450 2950
|
||||
Wire Wire Line
|
||||
3450 2950 3450 3100
|
||||
Wire Wire Line
|
||||
3300 2800 3450 2800
|
||||
Connection ~ 3450 2800
|
||||
Wire Wire Line
|
||||
3450 2800 3450 2900
|
||||
Wire Wire Line
|
||||
3300 3400 3450 3400
|
||||
Wire Wire Line
|
||||
3450 3400 3450 3550
|
||||
Wire Wire Line
|
||||
3450 3850 3300 3850
|
||||
Wire Wire Line
|
||||
3300 3700 3450 3700
|
||||
Connection ~ 3450 3700
|
||||
Wire Wire Line
|
||||
3450 3700 3450 3850
|
||||
Wire Wire Line
|
||||
3300 3550 3450 3550
|
||||
Connection ~ 3450 3550
|
||||
Wire Wire Line
|
||||
3450 3550 3450 3700
|
||||
Wire Wire Line
|
||||
3850 2800 4300 2800
|
||||
Wire Wire Line
|
||||
3450 2900 4200 2900
|
||||
Connection ~ 3450 2900
|
||||
Wire Wire Line
|
||||
3450 2900 3450 2950
|
||||
Wire Wire Line
|
||||
3450 3400 3850 3400
|
||||
Wire Wire Line
|
||||
3850 3400 3850 3000
|
||||
Wire Wire Line
|
||||
3850 3000 4100 3000
|
||||
Connection ~ 3450 3400
|
||||
Wire Wire Line
|
||||
3450 2350 3850 2350
|
||||
Connection ~ 3450 2350
|
||||
Wire Wire Line
|
||||
3850 2350 3850 2800
|
||||
Wire Wire Line
|
||||
3300 4000 3950 4000
|
||||
Wire Wire Line
|
||||
3950 4000 3950 3100
|
||||
Wire Wire Line
|
||||
3950 3100 5350 3100
|
||||
Wire Wire Line
|
||||
3300 4100 4050 4100
|
||||
Wire Wire Line
|
||||
4050 4100 4050 3200
|
||||
Wire Wire Line
|
||||
4050 3200 5350 3200
|
||||
Wire Wire Line
|
||||
5350 2700 4950 2700
|
||||
Connection ~ 4650 4800
|
||||
Wire Wire Line
|
||||
4650 4800 4650 4600
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 75924817
|
||||
P 4450 5200
|
||||
AR Path="/75924817" Ref="R?" Part="1"
|
||||
AR Path="/689FAE6F/75924817" Ref="R18" Part="1"
|
||||
AR Path="/600002AE/75924817" Ref="R?" Part="1"
|
||||
F 0 "R18" V 4350 5250 50 0000 R CNN
|
||||
F 1 "1K" V 4450 5200 31 0000 R CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4450 5200 50 0001 C CNN
|
||||
F 3 "~" H 4450 5200 50 0001 C CNN
|
||||
1 4450 5200
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4550 5000 4650 5000
|
||||
Connection ~ 4650 5000
|
||||
Wire Wire Line
|
||||
4650 5000 4650 4900
|
||||
Wire Wire Line
|
||||
4300 4600 4300 2800
|
||||
Wire Wire Line
|
||||
4300 4600 4350 4600
|
||||
Connection ~ 4300 2800
|
||||
Wire Wire Line
|
||||
4300 2800 5350 2800
|
||||
Wire Wire Line
|
||||
4200 4800 4200 2900
|
||||
Wire Wire Line
|
||||
4200 4800 4350 4800
|
||||
Connection ~ 4200 2900
|
||||
Wire Wire Line
|
||||
4200 2900 5350 2900
|
||||
Wire Wire Line
|
||||
4100 5000 4100 3000
|
||||
Wire Wire Line
|
||||
4100 5000 4350 5000
|
||||
Connection ~ 4100 3000
|
||||
Wire Wire Line
|
||||
4100 3000 5350 3000
|
||||
Text GLabel 1850 4450 0 39 Input ~ 0
|
||||
~CSYNC~
|
||||
Wire Wire Line
|
||||
1850 5200 3600 5200
|
||||
Text GLabel 1850 5200 0 39 Input ~ 0
|
||||
CSYNC
|
||||
$Comp
|
||||
L Jumper:Jumper_3_Bridged12 JP1
|
||||
U 1 1 7595AC8F
|
||||
P 3850 4800
|
||||
F 0 "JP1" V 3896 4867 50 0000 L CNN
|
||||
F 1 "Jumper_3_Bridged12" V 3805 4867 50 0000 L CNN
|
||||
F 2 "Connector_PinHeader_2.00mm:PinHeader_1x03_P2.00mm_Vertical" H 3850 4800 50 0001 C CNN
|
||||
F 3 "~" H 3850 4800 50 0001 C CNN
|
||||
1 3850 4800
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1850 4450 3850 4450
|
||||
Wire Wire Line
|
||||
3850 4450 3850 4550
|
||||
Wire Wire Line
|
||||
3850 5050 3850 5200
|
||||
Wire Wire Line
|
||||
4000 4800 4000 5200
|
||||
Wire Wire Line
|
||||
4000 5200 4350 5200
|
||||
Wire Wire Line
|
||||
5300 4650 5300 3500
|
||||
Wire Wire Line
|
||||
5300 3500 5350 3500
|
||||
Wire Wire Line
|
||||
4400 4150 4400 3300
|
||||
Wire Wire Line
|
||||
4400 3300 5350 3300
|
||||
Wire Wire Line
|
||||
3850 4450 3850 4150
|
||||
Connection ~ 3850 4450
|
||||
Wire Wire Line
|
||||
3850 4150 4400 4150
|
||||
Wire Wire Line
|
||||
3600 5200 3600 4250
|
||||
Wire Wire Line
|
||||
3600 4250 4500 4250
|
||||
Wire Wire Line
|
||||
4500 4250 4500 3400
|
||||
Wire Wire Line
|
||||
4500 3400 5350 3400
|
||||
Connection ~ 3600 5200
|
||||
Wire Wire Line
|
||||
3600 5200 3850 5200
|
||||
Wire Bus Line
|
||||
2750 2550 2750 3000
|
||||
Wire Bus Line
|
||||
2750 3300 2750 3750
|
||||
Wire Bus Line
|
||||
2750 1800 2750 2250
|
||||
$EndSCHEMATC
|
||||
2128
schematics/v2.0/FPGACPLD.sch
Normal file
2128
schematics/v2.0/FPGACPLD.sch
Normal file
File diff suppressed because it is too large
Load Diff
567
schematics/v2.0/FPGACPLDProgramming.sch
Normal file
567
schematics/v2.0/FPGACPLDProgramming.sch
Normal file
@@ -0,0 +1,567 @@
|
||||
EESchema Schematic File Version 4
|
||||
LIBS:MZ80-80CLR-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 4 6
|
||||
Title "FPGA and CPLD Support Circuits."
|
||||
Date "2020-06-27"
|
||||
Rev "2.0"
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 "FPGA and CPLD Programming and support circuits."
|
||||
$EndDescr
|
||||
$Comp
|
||||
L epm7128slc84:EP3C25E144C8N U3
|
||||
U 2 1 6D244DB7
|
||||
P 2400 2000
|
||||
F 0 "U3" H 2300 2800 50 0000 C CNN
|
||||
F 1 "EP3C25E144C8N" H 2400 1050 50 0000 C CNN
|
||||
F 2 "Package_QFP:EQFP-144-1EP_20x20mm_P0.5mm_EP6.61x5.615mm" H 3100 200 50 0001 L CNN
|
||||
F 3 "https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf" H 4050 1200 50 0001 C CNN
|
||||
2 2400 2000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L epm7128slc84:EPCS16 U6
|
||||
U 1 1 6D24AB29
|
||||
P 2350 3900
|
||||
F 0 "U6" H 2350 3900 39 0000 C CNN
|
||||
F 1 "EPCS16" H 2350 3800 39 0000 C CNN
|
||||
F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 2350 3900 39 0001 C CNN
|
||||
F 3 "" H 2350 3900 39 0001 C CNN
|
||||
1 2350 3900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDPWR #PWR025
|
||||
U 1 1 6D254BE6
|
||||
P 2350 4350
|
||||
F 0 "#PWR025" H 2350 4150 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 2500 4350 50 0000 C CNN
|
||||
F 2 "" H 2350 4300 50 0001 C CNN
|
||||
F 3 "" H 2350 4300 50 0001 C CNN
|
||||
1 2350 4350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2200 3450 2200 3400
|
||||
Wire Wire Line
|
||||
2200 3400 2350 3400
|
||||
Wire Wire Line
|
||||
2500 3400 2500 3450
|
||||
Wire Wire Line
|
||||
2350 3400 2350 3450
|
||||
Connection ~ 2350 3400
|
||||
Wire Wire Line
|
||||
2350 3400 2500 3400
|
||||
$Comp
|
||||
L Device:C C37
|
||||
U 1 1 6D256B48
|
||||
P 3050 3550
|
||||
F 0 "C37" H 3165 3596 50 0000 L CNN
|
||||
F 1 "100nF" H 3165 3505 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric_Pad1.05x0.95mm_HandSolder" H 3088 3400 50 0001 C CNN
|
||||
F 3 "~" H 3050 3550 50 0001 C CNN
|
||||
1 3050 3550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2500 3400 3050 3400
|
||||
Connection ~ 2500 3400
|
||||
$Comp
|
||||
L power:GNDPWR #PWR026
|
||||
U 1 1 6D257DA1
|
||||
P 3050 3700
|
||||
F 0 "#PWR026" H 3050 3500 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3200 3700 50 0000 C CNN
|
||||
F 2 "" H 3050 3650 50 0001 C CNN
|
||||
F 3 "" H 3050 3650 50 0001 C CNN
|
||||
1 3050 3700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3450 3850 3450 2250
|
||||
Wire Wire Line
|
||||
3450 2250 3000 2250
|
||||
Wire Wire Line
|
||||
2750 3850 3450 3850
|
||||
Wire Wire Line
|
||||
3500 3950 3500 2350
|
||||
Wire Wire Line
|
||||
3500 2350 3000 2350
|
||||
Wire Wire Line
|
||||
2750 3950 3500 3950
|
||||
Wire Wire Line
|
||||
1950 3950 1850 3950
|
||||
Wire Wire Line
|
||||
1850 3950 1850 4550
|
||||
Wire Wire Line
|
||||
1850 4550 3550 4550
|
||||
Wire Wire Line
|
||||
3550 4550 3550 2150
|
||||
Wire Wire Line
|
||||
3550 2150 3000 2150
|
||||
Wire Wire Line
|
||||
1950 3850 1800 3850
|
||||
Wire Wire Line
|
||||
1800 3850 1800 4600
|
||||
Wire Wire Line
|
||||
1800 4600 3600 4600
|
||||
Wire Wire Line
|
||||
3600 4600 3600 2450
|
||||
Wire Wire Line
|
||||
3600 2450 3000 2450
|
||||
Wire Wire Line
|
||||
3000 1800 3750 1800
|
||||
$Comp
|
||||
L Device:R_Small R23
|
||||
U 1 1 6D26CD8E
|
||||
P 3300 1000
|
||||
F 0 "R23" H 3350 1050 50 0000 L CNN
|
||||
F 1 "10K" H 3350 950 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3300 1000 50 0001 C CNN
|
||||
F 3 "~" H 3300 1000 50 0001 C CNN
|
||||
1 3300 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R24
|
||||
U 1 1 6D26E25E
|
||||
P 3550 1000
|
||||
F 0 "R24" H 3600 1050 50 0000 L CNN
|
||||
F 1 "10K" H 3600 950 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3550 1000 50 0001 C CNN
|
||||
F 3 "~" H 3550 1000 50 0001 C CNN
|
||||
1 3550 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R25
|
||||
U 1 1 6D26EE17
|
||||
P 3800 1000
|
||||
F 0 "R25" H 3850 1050 50 0000 L CNN
|
||||
F 1 "10K" H 3850 950 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 3800 1000 50 0001 C CNN
|
||||
F 3 "~" H 3800 1000 50 0001 C CNN
|
||||
1 3800 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3300 1100 3300 1250
|
||||
Wire Wire Line
|
||||
3300 1250 3000 1250
|
||||
Wire Wire Line
|
||||
3550 1100 3550 1350
|
||||
Wire Wire Line
|
||||
3550 1350 3000 1350
|
||||
Wire Wire Line
|
||||
3800 1100 3800 1550
|
||||
Wire Wire Line
|
||||
3800 1550 3000 1550
|
||||
$Comp
|
||||
L power:GNDPWR #PWR028
|
||||
U 1 1 6D2718E1
|
||||
P 3200 1450
|
||||
F 0 "#PWR028" H 3200 1250 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3350 1450 50 0000 C CNN
|
||||
F 2 "" H 3200 1400 50 0001 C CNN
|
||||
F 3 "" H 3200 1400 50 0001 C CNN
|
||||
1 3200 1450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3000 1450 3200 1450
|
||||
$Comp
|
||||
L Device:R_Small R26
|
||||
U 1 1 6D27313A
|
||||
P 4550 3150
|
||||
F 0 "R26" H 4600 3200 50 0000 L CNN
|
||||
F 1 "10K" H 4600 3100 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4550 3150 50 0001 C CNN
|
||||
F 3 "~" H 4550 3150 50 0001 C CNN
|
||||
1 4550 3150
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R27
|
||||
U 1 1 6D27430F
|
||||
P 4400 4100
|
||||
F 0 "R27" H 4450 4150 50 0000 L CNN
|
||||
F 1 "1K" H 4450 4050 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4400 4100 50 0001 C CNN
|
||||
F 3 "~" H 4400 4100 50 0001 C CNN
|
||||
1 4400 4100
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4550 3250 4550 3650
|
||||
Wire Wire Line
|
||||
3300 900 3300 850
|
||||
Wire Wire Line
|
||||
3300 850 3550 850
|
||||
Wire Wire Line
|
||||
3550 850 3550 900
|
||||
Wire Wire Line
|
||||
3550 850 3800 850
|
||||
Wire Wire Line
|
||||
3800 850 3800 900
|
||||
Connection ~ 3550 850
|
||||
Wire Wire Line
|
||||
4550 3050 4550 3000
|
||||
$Comp
|
||||
L power:+3.3V #PWR030
|
||||
U 1 1 6D27A094
|
||||
P 3550 850
|
||||
F 0 "#PWR030" H 3550 700 50 0001 C CNN
|
||||
F 1 "+3.3V" H 3565 1023 50 0000 C CNN
|
||||
F 2 "" H 3550 850 50 0001 C CNN
|
||||
F 3 "" H 3550 850 50 0001 C CNN
|
||||
1 3550 850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Oscillator:ASE-xxxMHz X1
|
||||
U 1 1 6D27DA45
|
||||
P 950 1350
|
||||
F 0 "X1" H 1200 1300 50 0000 L CNN
|
||||
F 1 "ASE-50MHz" H 1200 1200 50 0000 L CNN
|
||||
F 2 "Oscillator:Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm" H 1650 1000 50 0001 C CNN
|
||||
F 3 "http://www.abracon.com/Oscillators/ASV.pdf" H 850 1350 50 0001 C CNN
|
||||
1 950 1350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1250 1350 1800 1350
|
||||
$Comp
|
||||
L power:GNDPWR #PWR023
|
||||
U 1 1 6D27FEA8
|
||||
P 950 1650
|
||||
F 0 "#PWR023" H 950 1450 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1100 1650 50 0000 C CNN
|
||||
F 2 "" H 950 1600 50 0001 C CNN
|
||||
F 3 "" H 950 1600 50 0001 C CNN
|
||||
1 950 1650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR022
|
||||
U 1 1 6D280F33
|
||||
P 950 900
|
||||
F 0 "#PWR022" H 950 750 50 0001 C CNN
|
||||
F 1 "+3.3V" H 965 1073 50 0000 C CNN
|
||||
F 2 "" H 950 900 50 0001 C CNN
|
||||
F 3 "" H 950 900 50 0001 C CNN
|
||||
1 950 900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 650 1350
|
||||
$Comp
|
||||
L Device:C C36
|
||||
U 1 1 6D283FE9
|
||||
P 1300 1050
|
||||
F 0 "C36" H 1415 1096 50 0000 L CNN
|
||||
F 1 "100nF" H 1415 1005 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric_Pad1.05x0.95mm_HandSolder" H 1338 900 50 0001 C CNN
|
||||
F 3 "~" H 1300 1050 50 0001 C CNN
|
||||
1 1300 1050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
950 900 1300 900
|
||||
$Comp
|
||||
L power:GNDPWR #PWR024
|
||||
U 1 1 6D283FF4
|
||||
P 1300 1200
|
||||
F 0 "#PWR024" H 1300 1000 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1450 1200 50 0000 C CNN
|
||||
F 2 "" H 1300 1150 50 0001 C CNN
|
||||
F 3 "" H 1300 1150 50 0001 C CNN
|
||||
1 1300 1200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
950 900 950 1050
|
||||
Connection ~ 950 900
|
||||
NoConn ~ 1800 1450
|
||||
NoConn ~ 1800 1550
|
||||
NoConn ~ 1800 1650
|
||||
NoConn ~ 1800 1750
|
||||
NoConn ~ 1800 1850
|
||||
NoConn ~ 1800 1950
|
||||
NoConn ~ 1800 2050
|
||||
NoConn ~ 1800 2150
|
||||
NoConn ~ 1800 2250
|
||||
NoConn ~ 1800 2350
|
||||
NoConn ~ 1800 2450
|
||||
NoConn ~ 1800 2550
|
||||
NoConn ~ 1800 2650
|
||||
NoConn ~ 1800 2750
|
||||
Wire Wire Line
|
||||
3000 2600 3100 2600
|
||||
Wire Wire Line
|
||||
3100 2800 3000 2800
|
||||
$Comp
|
||||
L power:GNDPWR #PWR027
|
||||
U 1 1 6D2A5329
|
||||
P 3100 2950
|
||||
F 0 "#PWR027" H 3100 2750 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3250 2950 50 0000 C CNN
|
||||
F 2 "" H 3100 2900 50 0001 C CNN
|
||||
F 3 "" H 3100 2900 50 0001 C CNN
|
||||
1 3100 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3100 2600 3100 2800
|
||||
Wire Wire Line
|
||||
3100 2800 3100 2950
|
||||
Connection ~ 3100 2800
|
||||
$Comp
|
||||
L power:+2V5 #PWR029
|
||||
U 1 1 6D2A86F7
|
||||
P 3200 2700
|
||||
F 0 "#PWR029" H 3200 2550 50 0001 C CNN
|
||||
F 1 "+2V5" H 3215 2873 50 0000 C CNN
|
||||
F 2 "" H 3200 2700 50 0001 C CNN
|
||||
F 3 "" H 3200 2700 50 0001 C CNN
|
||||
1 3200 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3000 2700 3200 2700
|
||||
$Comp
|
||||
L Switch:SW_Push SW1
|
||||
U 1 1 6D2AF935
|
||||
P 4250 1350
|
||||
F 0 "SW1" H 4250 1635 50 0000 C CNN
|
||||
F 1 "CONFIG" H 4250 1544 50 0000 C CNN
|
||||
F 2 "Button_Switch_SMD:SW_SPST_B3S-1000" H 4250 1550 50 0001 C CNN
|
||||
F 3 "~" H 4250 1550 50 0001 C CNN
|
||||
1 4250 1350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 3550 1350
|
||||
Wire Wire Line
|
||||
3550 1350 4050 1350
|
||||
Text GLabel 800 4950 0 39 Input ~ 0
|
||||
~RESET~
|
||||
$Comp
|
||||
L Oscillator:ASE-xxxMHz X2
|
||||
U 1 1 6F9BB54A
|
||||
P 950 5750
|
||||
F 0 "X2" H 1200 5700 50 0000 L CNN
|
||||
F 1 "ASE-16MHz" H 1200 5600 50 0000 L CNN
|
||||
F 2 "Oscillator:Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm" H 1650 5400 50 0001 C CNN
|
||||
F 3 "http://www.abracon.com/Oscillators/ASV.pdf" H 850 5750 50 0001 C CNN
|
||||
1 950 5750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1250 5750 1800 5750
|
||||
$Comp
|
||||
L power:GNDPWR #PWR035
|
||||
U 1 1 6F9BB551
|
||||
P 950 6050
|
||||
F 0 "#PWR035" H 950 5850 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1100 6050 50 0000 C CNN
|
||||
F 2 "" H 950 6000 50 0001 C CNN
|
||||
F 3 "" H 950 6000 50 0001 C CNN
|
||||
1 950 6050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR034
|
||||
U 1 1 6F9BB557
|
||||
P 950 5300
|
||||
F 0 "#PWR034" H 950 5150 50 0001 C CNN
|
||||
F 1 "+3.3V" H 965 5473 50 0000 C CNN
|
||||
F 2 "" H 950 5300 50 0001 C CNN
|
||||
F 3 "" H 950 5300 50 0001 C CNN
|
||||
1 950 5300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 650 5750
|
||||
$Comp
|
||||
L Device:C C38
|
||||
U 1 1 6F9BB55E
|
||||
P 1300 5450
|
||||
F 0 "C38" H 1415 5496 50 0000 L CNN
|
||||
F 1 "100nF" H 1415 5405 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric_Pad1.05x0.95mm_HandSolder" H 1338 5300 50 0001 C CNN
|
||||
F 3 "~" H 1300 5450 50 0001 C CNN
|
||||
1 1300 5450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
950 5300 1300 5300
|
||||
$Comp
|
||||
L power:GNDPWR #PWR036
|
||||
U 1 1 6F9BB565
|
||||
P 1300 5600
|
||||
F 0 "#PWR036" H 1300 5400 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1450 5600 50 0000 C CNN
|
||||
F 2 "" H 1300 5550 50 0001 C CNN
|
||||
F 3 "" H 1300 5550 50 0001 C CNN
|
||||
1 1300 5600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
950 5300 950 5450
|
||||
Connection ~ 950 5300
|
||||
$Comp
|
||||
L Connector_Generic:Conn_02x05_Odd_Even J5
|
||||
U 1 1 6F9F2008
|
||||
P 4900 3650
|
||||
F 0 "J5" H 4950 4067 50 0000 C CNN
|
||||
F 1 "JTAG" H 4950 3976 50 0000 C CNN
|
||||
F 2 "Connector_PinSocket_2.54mm:PinSocket_2x05_P2.54mm_Vertical" H 4900 3650 50 0001 C CNN
|
||||
F 3 "~" H 4900 3650 50 0001 C CNN
|
||||
1 4900 3650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 4700 3750
|
||||
NoConn ~ 5200 3750
|
||||
NoConn ~ 5200 3650
|
||||
Wire Wire Line
|
||||
5200 3450 5300 3450
|
||||
Wire Wire Line
|
||||
5300 3850 5200 3850
|
||||
$Comp
|
||||
L power:GNDPWR #PWR037
|
||||
U 1 1 6F9F2017
|
||||
P 5300 4300
|
||||
F 0 "#PWR037" H 5300 4100 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 5450 4300 50 0000 C CNN
|
||||
F 2 "" H 5300 4250 50 0001 C CNN
|
||||
F 3 "" H 5300 4250 50 0001 C CNN
|
||||
1 5300 4300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 5300 3850
|
||||
Wire Wire Line
|
||||
5200 3550 5500 3550
|
||||
Wire Wire Line
|
||||
5500 3550 5500 3000
|
||||
Wire Wire Line
|
||||
3200 5650 3750 5650
|
||||
$Comp
|
||||
L power:+3.3V #PWR038
|
||||
U 1 1 6FA01A74
|
||||
P 5500 2950
|
||||
F 0 "#PWR038" H 5500 2800 50 0001 C CNN
|
||||
F 1 "+3.3V" H 5515 3123 50 0000 C CNN
|
||||
F 2 "" H 5500 2950 50 0001 C CNN
|
||||
F 3 "" H 5500 2950 50 0001 C CNN
|
||||
1 5500 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
800 4950 1700 4950
|
||||
Wire Wire Line
|
||||
1700 4950 1700 5650
|
||||
Wire Wire Line
|
||||
1700 5650 1800 5650
|
||||
NoConn ~ 1800 5850
|
||||
NoConn ~ 1800 5950
|
||||
$Comp
|
||||
L power:+3.3V #PWR0101
|
||||
U 1 1 762F7371
|
||||
P 2350 3400
|
||||
F 0 "#PWR0101" H 2350 3250 50 0001 C CNN
|
||||
F 1 "+3.3V" H 2365 3573 50 0000 C CNN
|
||||
F 2 "" H 2350 3400 50 0001 C CNN
|
||||
F 3 "" H 2350 3400 50 0001 C CNN
|
||||
1 2350 3400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4550 3650 4700 3650
|
||||
$Comp
|
||||
L epm7128slc84:EPM7512AEQFP144-3 U5
|
||||
U 2 1 6F9A374D
|
||||
P 2500 5800
|
||||
F 0 "U5" H 2500 6100 50 0000 C CNN
|
||||
F 1 "EPM7512AEQFP144-3" H 2500 5400 50 0000 C CNN
|
||||
F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 3350 2900 50 0001 L CNN
|
||||
F 3 "https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf" H 2500 5800 50 0001 C CNN
|
||||
2 2500 5800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5300 3450 5300 3850
|
||||
$Comp
|
||||
L power:GNDPWR #PWR0103
|
||||
U 1 1 5F753790
|
||||
P 4600 1450
|
||||
F 0 "#PWR0103" H 4600 1250 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 4600 1300 50 0000 C CNN
|
||||
F 2 "" H 4600 1400 50 0001 C CNN
|
||||
F 3 "" H 4600 1400 50 0001 C CNN
|
||||
1 4600 1450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4600 1450 4600 1350
|
||||
Wire Wire Line
|
||||
4600 1350 4450 1350
|
||||
Wire Wire Line
|
||||
3200 5750 3650 5750
|
||||
Wire Wire Line
|
||||
3650 5750 3650 1700
|
||||
Wire Wire Line
|
||||
3650 1700 3000 1700
|
||||
Wire Wire Line
|
||||
3000 1900 3700 1900
|
||||
Wire Wire Line
|
||||
3700 1900 3700 3650
|
||||
Wire Wire Line
|
||||
3700 5850 3200 5850
|
||||
Wire Wire Line
|
||||
3750 1800 3750 3450
|
||||
Wire Wire Line
|
||||
4700 3450 4400 3450
|
||||
Connection ~ 3750 3450
|
||||
Wire Wire Line
|
||||
3750 3450 3750 5650
|
||||
Wire Wire Line
|
||||
4700 3550 3950 3550
|
||||
Wire Wire Line
|
||||
3950 3550 3950 2000
|
||||
Wire Wire Line
|
||||
3950 2000 3000 2000
|
||||
Wire Wire Line
|
||||
3950 3850 3950 5950
|
||||
Wire Wire Line
|
||||
3950 5950 3200 5950
|
||||
Wire Wire Line
|
||||
4550 3650 3700 3650
|
||||
Connection ~ 4550 3650
|
||||
Connection ~ 3700 3650
|
||||
Wire Wire Line
|
||||
3700 3650 3700 5850
|
||||
Wire Wire Line
|
||||
3950 3850 4700 3850
|
||||
Wire Wire Line
|
||||
4400 4000 4400 3450
|
||||
Connection ~ 4400 3450
|
||||
Wire Wire Line
|
||||
4400 3450 3750 3450
|
||||
Wire Wire Line
|
||||
4400 4200 4400 4250
|
||||
Wire Wire Line
|
||||
4400 4250 5300 4250
|
||||
Wire Wire Line
|
||||
5300 4250 5300 4300
|
||||
Wire Wire Line
|
||||
5300 3850 5300 4250
|
||||
Connection ~ 5300 4250
|
||||
Wire Wire Line
|
||||
4550 3000 5500 3000
|
||||
Connection ~ 5500 3000
|
||||
Wire Wire Line
|
||||
5500 3000 5500 2950
|
||||
$EndSCHEMATC
|
||||
650
schematics/v2.0/FPGAProgramming.sch
Normal file
650
schematics/v2.0/FPGAProgramming.sch
Normal file
@@ -0,0 +1,650 @@
|
||||
EESchema Schematic File Version 4
|
||||
LIBS:MZ80-80CLR-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 5 6
|
||||
Title "FPGA Support Circuits."
|
||||
Date "2020-06-27"
|
||||
Rev "2.0"
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 "FPGA Programming and support circuits."
|
||||
$EndDescr
|
||||
$Comp
|
||||
L epm7128slc84:EP3C25E144C8N U?
|
||||
U 2 1 6D244DB7
|
||||
P 2400 2000
|
||||
F 0 "U?" H 2300 2800 50 0000 C CNN
|
||||
F 1 "EP3C25E144C8N" H 2400 1050 50 0000 C CNN
|
||||
F 2 "Package_QFP" H 3100 200 50 0001 L CNN
|
||||
F 3 "https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf" H 4050 1200 50 0001 C CNN
|
||||
2 2400 2000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector_Generic:Conn_02x05_Odd_Even J?
|
||||
U 1 1 6D2483D3
|
||||
P 5000 1900
|
||||
F 0 "J?" H 5050 2317 50 0000 C CNN
|
||||
F 1 "JTAG FPGA" H 5050 2226 50 0000 C CNN
|
||||
F 2 "" H 5000 1900 50 0001 C CNN
|
||||
F 3 "~" H 5000 1900 50 0001 C CNN
|
||||
1 5000 1900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L epm7128slc84:EPCS16 U?
|
||||
U 1 1 6D24AB29
|
||||
P 2350 3900
|
||||
F 0 "U?" H 2350 3900 39 0000 C CNN
|
||||
F 1 "EPCS16" H 2350 3800 39 0000 C CNN
|
||||
F 2 "" H 2350 3900 39 0001 C CNN
|
||||
F 3 "" H 2350 3900 39 0001 C CNN
|
||||
1 2350 3900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D254BE6
|
||||
P 2350 4350
|
||||
F 0 "#PWR?" H 2350 4150 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 2500 4350 50 0000 C CNN
|
||||
F 2 "" H 2350 4300 50 0001 C CNN
|
||||
F 3 "" H 2350 4300 50 0001 C CNN
|
||||
1 2350 4350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2200 3450 2200 3400
|
||||
Wire Wire Line
|
||||
2200 3400 2350 3400
|
||||
Wire Wire Line
|
||||
2500 3400 2500 3450
|
||||
Wire Wire Line
|
||||
2350 3400 2350 3450
|
||||
Connection ~ 2350 3400
|
||||
Wire Wire Line
|
||||
2350 3400 2500 3400
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6D256B48
|
||||
P 3050 3550
|
||||
F 0 "C?" H 3165 3596 50 0000 L CNN
|
||||
F 1 "100nF" H 3165 3505 50 0000 L CNN
|
||||
F 2 "" H 3088 3400 50 0001 C CNN
|
||||
F 3 "~" H 3050 3550 50 0001 C CNN
|
||||
1 3050 3550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2500 3400 3050 3400
|
||||
Connection ~ 2500 3400
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D257DA1
|
||||
P 3050 3700
|
||||
F 0 "#PWR?" H 3050 3500 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3200 3700 50 0000 C CNN
|
||||
F 2 "" H 3050 3650 50 0001 C CNN
|
||||
F 3 "" H 3050 3650 50 0001 C CNN
|
||||
1 3050 3700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3450 3850 3450 2250
|
||||
Wire Wire Line
|
||||
3450 2250 3000 2250
|
||||
Wire Wire Line
|
||||
2750 3850 3450 3850
|
||||
Wire Wire Line
|
||||
3500 3950 3500 2350
|
||||
Wire Wire Line
|
||||
3500 2350 3000 2350
|
||||
Wire Wire Line
|
||||
2750 3950 3500 3950
|
||||
Wire Wire Line
|
||||
1950 3950 1850 3950
|
||||
Wire Wire Line
|
||||
1850 3950 1850 4550
|
||||
Wire Wire Line
|
||||
1850 4550 3550 4550
|
||||
Wire Wire Line
|
||||
3550 4550 3550 2150
|
||||
Wire Wire Line
|
||||
3550 2150 3000 2150
|
||||
Wire Wire Line
|
||||
1950 3850 1800 3850
|
||||
Wire Wire Line
|
||||
1800 3850 1800 4600
|
||||
Wire Wire Line
|
||||
1800 4600 3600 4600
|
||||
Wire Wire Line
|
||||
3600 4600 3600 2450
|
||||
Wire Wire Line
|
||||
3600 2450 3000 2450
|
||||
Wire Wire Line
|
||||
3000 1800 4100 1800
|
||||
Wire Wire Line
|
||||
4100 1800 4100 1700
|
||||
Wire Wire Line
|
||||
4100 1700 4800 1700
|
||||
Wire Wire Line
|
||||
3000 2000 4150 2000
|
||||
Wire Wire Line
|
||||
4150 2000 4150 1800
|
||||
Wire Wire Line
|
||||
4150 1800 4800 1800
|
||||
Wire Wire Line
|
||||
3000 1900 4300 1900
|
||||
Wire Wire Line
|
||||
3000 1700 4050 1700
|
||||
Wire Wire Line
|
||||
4050 1700 4050 2100
|
||||
Wire Wire Line
|
||||
4050 2100 4800 2100
|
||||
NoConn ~ 4800 2000
|
||||
NoConn ~ 5300 2000
|
||||
NoConn ~ 5300 1900
|
||||
Wire Wire Line
|
||||
5300 1700 5400 1700
|
||||
Wire Wire Line
|
||||
5400 1700 5400 2100
|
||||
Wire Wire Line
|
||||
5400 2100 5300 2100
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D269E93
|
||||
P 5400 2200
|
||||
F 0 "#PWR?" H 5400 2000 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 5550 2200 50 0000 C CNN
|
||||
F 2 "" H 5400 2150 50 0001 C CNN
|
||||
F 3 "" H 5400 2150 50 0001 C CNN
|
||||
1 5400 2200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5400 2200 5400 2100
|
||||
Connection ~ 5400 2100
|
||||
Wire Wire Line
|
||||
5300 1800 5600 1800
|
||||
Wire Wire Line
|
||||
5600 1800 5600 1750
|
||||
$Comp
|
||||
L power:+2V5 #PWR?
|
||||
U 1 1 6D26C04E
|
||||
P 5600 1750
|
||||
F 0 "#PWR?" H 5600 1600 50 0001 C CNN
|
||||
F 1 "+2V5" H 5615 1923 50 0000 C CNN
|
||||
F 2 "" H 5600 1750 50 0001 C CNN
|
||||
F 3 "" H 5600 1750 50 0001 C CNN
|
||||
1 5600 1750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6D26CD8E
|
||||
P 3300 1000
|
||||
F 0 "R?" H 3350 1050 50 0000 L CNN
|
||||
F 1 "10K" H 3350 950 50 0000 L CNN
|
||||
F 2 "" H 3300 1000 50 0001 C CNN
|
||||
F 3 "~" H 3300 1000 50 0001 C CNN
|
||||
1 3300 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6D26E25E
|
||||
P 3550 1000
|
||||
F 0 "R?" H 3600 1050 50 0000 L CNN
|
||||
F 1 "10K" H 3600 950 50 0000 L CNN
|
||||
F 2 "" H 3550 1000 50 0001 C CNN
|
||||
F 3 "~" H 3550 1000 50 0001 C CNN
|
||||
1 3550 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6D26EE17
|
||||
P 3800 1000
|
||||
F 0 "R?" H 3850 1050 50 0000 L CNN
|
||||
F 1 "10K" H 3850 950 50 0000 L CNN
|
||||
F 2 "" H 3800 1000 50 0001 C CNN
|
||||
F 3 "~" H 3800 1000 50 0001 C CNN
|
||||
1 3800 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3300 1100 3300 1250
|
||||
Wire Wire Line
|
||||
3300 1250 3000 1250
|
||||
Wire Wire Line
|
||||
3550 1100 3550 1350
|
||||
Wire Wire Line
|
||||
3550 1350 3000 1350
|
||||
Wire Wire Line
|
||||
3800 1100 3800 1550
|
||||
Wire Wire Line
|
||||
3800 1550 3000 1550
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D2718E1
|
||||
P 3200 1450
|
||||
F 0 "#PWR?" H 3200 1250 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3350 1450 50 0000 C CNN
|
||||
F 2 "" H 3200 1400 50 0001 C CNN
|
||||
F 3 "" H 3200 1400 50 0001 C CNN
|
||||
1 3200 1450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3000 1450 3200 1450
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6D27313A
|
||||
P 4050 1000
|
||||
F 0 "R?" H 4100 1050 50 0000 L CNN
|
||||
F 1 "10K" H 4100 950 50 0000 L CNN
|
||||
F 2 "" H 4050 1000 50 0001 C CNN
|
||||
F 3 "~" H 4050 1000 50 0001 C CNN
|
||||
1 4050 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6D27430F
|
||||
P 4300 1000
|
||||
F 0 "R?" H 4350 1050 50 0000 L CNN
|
||||
F 1 "10K" H 4350 950 50 0000 L CNN
|
||||
F 2 "" H 4300 1000 50 0001 C CNN
|
||||
F 3 "~" H 4300 1000 50 0001 C CNN
|
||||
1 4300 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4050 1100 4050 1700
|
||||
Connection ~ 4050 1700
|
||||
Wire Wire Line
|
||||
4300 1100 4300 1900
|
||||
Connection ~ 4300 1900
|
||||
Wire Wire Line
|
||||
4300 1900 4800 1900
|
||||
Wire Wire Line
|
||||
3300 900 3300 850
|
||||
Wire Wire Line
|
||||
3300 850 3550 850
|
||||
Wire Wire Line
|
||||
3550 850 3550 900
|
||||
Wire Wire Line
|
||||
3550 850 3800 850
|
||||
Wire Wire Line
|
||||
3800 850 3800 900
|
||||
Connection ~ 3550 850
|
||||
Wire Wire Line
|
||||
4050 900 4050 850
|
||||
Wire Wire Line
|
||||
4050 850 4200 850
|
||||
Wire Wire Line
|
||||
4300 850 4300 900
|
||||
$Comp
|
||||
L power:+2V5 #PWR?
|
||||
U 1 1 6D27950E
|
||||
P 4200 850
|
||||
F 0 "#PWR?" H 4200 700 50 0001 C CNN
|
||||
F 1 "+2V5" H 4215 1023 50 0000 C CNN
|
||||
F 2 "" H 4200 850 50 0001 C CNN
|
||||
F 3 "" H 4200 850 50 0001 C CNN
|
||||
1 4200 850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 4200 850
|
||||
Wire Wire Line
|
||||
4200 850 4300 850
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 6D27A094
|
||||
P 3550 850
|
||||
F 0 "#PWR?" H 3550 700 50 0001 C CNN
|
||||
F 1 "+3.3V" H 3565 1023 50 0000 C CNN
|
||||
F 2 "" H 3550 850 50 0001 C CNN
|
||||
F 3 "" H 3550 850 50 0001 C CNN
|
||||
1 3550 850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Oscillator:ASE-xxxMHz X?
|
||||
U 1 1 6D27DA45
|
||||
P 950 1350
|
||||
F 0 "X?" H 1200 1300 50 0000 L CNN
|
||||
F 1 "ASE-50MHz" H 1200 1200 50 0000 L CNN
|
||||
F 2 "Oscillator:Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm" H 1650 1000 50 0001 C CNN
|
||||
F 3 "http://www.abracon.com/Oscillators/ASV.pdf" H 850 1350 50 0001 C CNN
|
||||
1 950 1350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1250 1350 1800 1350
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D27FEA8
|
||||
P 950 1650
|
||||
F 0 "#PWR?" H 950 1450 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1100 1650 50 0000 C CNN
|
||||
F 2 "" H 950 1600 50 0001 C CNN
|
||||
F 3 "" H 950 1600 50 0001 C CNN
|
||||
1 950 1650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 6D280F33
|
||||
P 950 900
|
||||
F 0 "#PWR?" H 950 750 50 0001 C CNN
|
||||
F 1 "+3.3V" H 965 1073 50 0000 C CNN
|
||||
F 2 "" H 950 900 50 0001 C CNN
|
||||
F 3 "" H 950 900 50 0001 C CNN
|
||||
1 950 900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 650 1350
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6D283FE9
|
||||
P 1300 1050
|
||||
F 0 "C?" H 1415 1096 50 0000 L CNN
|
||||
F 1 "100nF" H 1415 1005 50 0000 L CNN
|
||||
F 2 "" H 1338 900 50 0001 C CNN
|
||||
F 3 "~" H 1300 1050 50 0001 C CNN
|
||||
1 1300 1050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
950 900 1300 900
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D283FF4
|
||||
P 1300 1200
|
||||
F 0 "#PWR?" H 1300 1000 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 1450 1200 50 0000 C CNN
|
||||
F 2 "" H 1300 1150 50 0001 C CNN
|
||||
F 3 "" H 1300 1150 50 0001 C CNN
|
||||
1 1300 1200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
950 900 950 1050
|
||||
Connection ~ 950 900
|
||||
NoConn ~ 1800 1450
|
||||
NoConn ~ 1800 1550
|
||||
NoConn ~ 1800 1650
|
||||
NoConn ~ 1800 1750
|
||||
NoConn ~ 1800 1850
|
||||
NoConn ~ 1800 1950
|
||||
NoConn ~ 1800 2050
|
||||
NoConn ~ 1800 2150
|
||||
NoConn ~ 1800 2250
|
||||
NoConn ~ 1800 2350
|
||||
NoConn ~ 1800 2450
|
||||
NoConn ~ 1800 2550
|
||||
NoConn ~ 1800 2650
|
||||
NoConn ~ 1800 2750
|
||||
Wire Wire Line
|
||||
3000 2600 3100 2600
|
||||
Wire Wire Line
|
||||
3100 2800 3000 2800
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6D2A5329
|
||||
P 3100 2950
|
||||
F 0 "#PWR?" H 3100 2750 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 3250 2950 50 0000 C CNN
|
||||
F 2 "" H 3100 2900 50 0001 C CNN
|
||||
F 3 "" H 3100 2900 50 0001 C CNN
|
||||
1 3100 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3100 2600 3100 2800
|
||||
Wire Wire Line
|
||||
3100 2800 3100 2950
|
||||
Connection ~ 3100 2800
|
||||
$Comp
|
||||
L power:+2V5 #PWR?
|
||||
U 1 1 6D2A86F7
|
||||
P 3200 2700
|
||||
F 0 "#PWR?" H 3200 2550 50 0001 C CNN
|
||||
F 1 "+2V5" H 3215 2873 50 0000 C CNN
|
||||
F 2 "" H 3200 2700 50 0001 C CNN
|
||||
F 3 "" H 3200 2700 50 0001 C CNN
|
||||
1 3200 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3000 2700 3200 2700
|
||||
$Comp
|
||||
L Switch:SW_Push SW?
|
||||
U 1 1 6D2AF935
|
||||
P 5050 1350
|
||||
F 0 "SW?" H 5050 1635 50 0000 C CNN
|
||||
F 1 "CONFIG" H 5050 1544 50 0000 C CNN
|
||||
F 2 "" H 5050 1550 50 0001 C CNN
|
||||
F 3 "~" H 5050 1550 50 0001 C CNN
|
||||
1 5050 1350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 3550 1350
|
||||
Wire Wire Line
|
||||
5400 1350 5400 1700
|
||||
Connection ~ 5400 1700
|
||||
$Comp
|
||||
L Switch:SW_Push SW?
|
||||
U 1 1 6DC834D5
|
||||
P 1550 5550
|
||||
F 0 "SW?" H 1550 5835 50 0000 C CNN
|
||||
F 1 "RESET" H 1550 5744 50 0000 C CNN
|
||||
F 2 "" H 1550 5750 50 0001 C CNN
|
||||
F 3 "~" H 1550 5750 50 0001 C CNN
|
||||
1 1550 5550
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3550 1350 4850 1350
|
||||
Wire Wire Line
|
||||
5250 1350 5400 1350
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6DC931C7
|
||||
P 1350 5300
|
||||
F 0 "R?" H 1400 5350 50 0000 L CNN
|
||||
F 1 "10K" H 1400 5250 50 0000 L CNN
|
||||
F 2 "" H 1350 5300 50 0001 C CNN
|
||||
F 3 "~" H 1350 5300 50 0001 C CNN
|
||||
1 1350 5300
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1350 5150 1350 5200
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 6DC931D5
|
||||
P 1350 5150
|
||||
F 0 "#PWR?" H 1350 5000 50 0001 C CNN
|
||||
F 1 "+3.3V" H 1365 5323 50 0000 C CNN
|
||||
F 2 "" H 1350 5150 50 0001 C CNN
|
||||
F 3 "" H 1350 5150 50 0001 C CNN
|
||||
1 1350 5150
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
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||||
U 1 1 6DC95D7E
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||||
P 1350 5850
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||||
F 0 "C?" H 1465 5896 50 0000 L CNN
|
||||
F 1 "100nF" H 1465 5805 50 0000 L CNN
|
||||
F 2 "" H 1388 5700 50 0001 C CNN
|
||||
F 3 "~" H 1350 5850 50 0001 C CNN
|
||||
1 1350 5850
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1350 5400 1350 5550
|
||||
Connection ~ 1350 5550
|
||||
Wire Wire Line
|
||||
1350 5550 1350 5700
|
||||
Wire Wire Line
|
||||
1350 6000 1800 6000
|
||||
Wire Wire Line
|
||||
1800 6000 1800 5550
|
||||
Wire Wire Line
|
||||
1800 5550 1750 5550
|
||||
Text GLabel 7300 1200 0 39 Input ~ 0
|
||||
~RESET~
|
||||
Wire Wire Line
|
||||
750 5550 1350 5550
|
||||
$Comp
|
||||
L epm7128slc84:EPM7512AEQFP144-3 U?
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||||
U 2 1 6F9A374D
|
||||
P 8200 1800
|
||||
F 0 "U?" H 8200 2100 50 0000 C CNN
|
||||
F 1 "EPM7512AEQFP144-3" H 8200 1400 50 0000 C CNN
|
||||
F 2 "Package_QFP" H 9050 -1100 50 0001 L CNN
|
||||
F 3 "https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf" H 8200 1800 50 0001 C CNN
|
||||
2 8200 1800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Oscillator:ASE-xxxMHz X?
|
||||
U 1 1 6F9BB54A
|
||||
P 6300 1750
|
||||
F 0 "X?" H 6550 1700 50 0000 L CNN
|
||||
F 1 "ASE-16MHz" H 6550 1600 50 0000 L CNN
|
||||
F 2 "Oscillator:Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm" H 7000 1400 50 0001 C CNN
|
||||
F 3 "http://www.abracon.com/Oscillators/ASV.pdf" H 6200 1750 50 0001 C CNN
|
||||
1 6300 1750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6600 1750 7500 1750
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6F9BB551
|
||||
P 6300 2050
|
||||
F 0 "#PWR?" H 6300 1850 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 6450 2050 50 0000 C CNN
|
||||
F 2 "" H 6300 2000 50 0001 C CNN
|
||||
F 3 "" H 6300 2000 50 0001 C CNN
|
||||
1 6300 2050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 6F9BB557
|
||||
P 6300 1300
|
||||
F 0 "#PWR?" H 6300 1150 50 0001 C CNN
|
||||
F 1 "+3.3V" H 6315 1473 50 0000 C CNN
|
||||
F 2 "" H 6300 1300 50 0001 C CNN
|
||||
F 3 "" H 6300 1300 50 0001 C CNN
|
||||
1 6300 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 6000 1750
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6F9BB55E
|
||||
P 6650 1450
|
||||
F 0 "C?" H 6765 1496 50 0000 L CNN
|
||||
F 1 "100nF" H 6765 1405 50 0000 L CNN
|
||||
F 2 "" H 6688 1300 50 0001 C CNN
|
||||
F 3 "~" H 6650 1450 50 0001 C CNN
|
||||
1 6650 1450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6300 1300 6650 1300
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6F9BB565
|
||||
P 6650 1600
|
||||
F 0 "#PWR?" H 6650 1400 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 6800 1600 50 0000 C CNN
|
||||
F 2 "" H 6650 1550 50 0001 C CNN
|
||||
F 3 "" H 6650 1550 50 0001 C CNN
|
||||
1 6650 1600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6300 1300 6300 1450
|
||||
Connection ~ 6300 1300
|
||||
$Comp
|
||||
L Connector_Generic:Conn_02x05_Odd_Even J?
|
||||
U 1 1 6F9F2008
|
||||
P 9850 1850
|
||||
F 0 "J?" H 9900 2267 50 0000 C CNN
|
||||
F 1 "JTAG CPLD" H 9900 2176 50 0000 C CNN
|
||||
F 2 "" H 9850 1850 50 0001 C CNN
|
||||
F 3 "~" H 9850 1850 50 0001 C CNN
|
||||
1 9850 1850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 9650 1950
|
||||
NoConn ~ 10150 1950
|
||||
NoConn ~ 10150 1850
|
||||
Wire Wire Line
|
||||
10150 1650 10250 1650
|
||||
Wire Wire Line
|
||||
10250 1650 10250 2050
|
||||
Wire Wire Line
|
||||
10250 2050 10150 2050
|
||||
$Comp
|
||||
L power:GNDPWR #PWR?
|
||||
U 1 1 6F9F2017
|
||||
P 10250 2150
|
||||
F 0 "#PWR?" H 10250 1950 50 0001 C CNN
|
||||
F 1 "GNDPWR" H 10400 2150 50 0000 C CNN
|
||||
F 2 "" H 10250 2100 50 0001 C CNN
|
||||
F 3 "" H 10250 2100 50 0001 C CNN
|
||||
1 10250 2150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
10250 2150 10250 2050
|
||||
Connection ~ 10250 2050
|
||||
Wire Wire Line
|
||||
10150 1750 10450 1750
|
||||
Wire Wire Line
|
||||
10450 1750 10450 1700
|
||||
Wire Wire Line
|
||||
8900 1650 9650 1650
|
||||
Wire Wire Line
|
||||
9050 2050 9050 1950
|
||||
Wire Wire Line
|
||||
9050 1950 8900 1950
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 6FA01A74
|
||||
P 10450 1700
|
||||
F 0 "#PWR?" H 10450 1550 50 0001 C CNN
|
||||
F 1 "+3.3V" H 10465 1873 50 0000 C CNN
|
||||
F 2 "" H 10450 1700 50 0001 C CNN
|
||||
F 3 "" H 10450 1700 50 0001 C CNN
|
||||
1 10450 1700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
8900 1750 9650 1750
|
||||
Wire Wire Line
|
||||
8900 1850 9650 1850
|
||||
Wire Wire Line
|
||||
9050 2050 9650 2050
|
||||
Wire Wire Line
|
||||
7300 1200 7400 1200
|
||||
Wire Wire Line
|
||||
7400 1200 7400 1650
|
||||
Wire Wire Line
|
||||
7400 1650 7500 1650
|
||||
NoConn ~ 7500 1850
|
||||
NoConn ~ 7500 1950
|
||||
$EndSCHEMATC
|
||||
1303
schematics/v2.0/FPGAVideoModule.sch
Normal file
1303
schematics/v2.0/FPGAVideoModule.sch
Normal file
File diff suppressed because it is too large
Load Diff
38
schematics/v2.0/Graphic.pretty/Argo.kicad_mod
Normal file
38
schematics/v2.0/Graphic.pretty/Argo.kicad_mod
Normal file
@@ -0,0 +1,38 @@
|
||||
(module LOGO (layer F.Cu)
|
||||
(at 0 0)
|
||||
(fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
|
||||
(effects (font (thickness 0.3)))
|
||||
)
|
||||
(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
|
||||
(effects (font (thickness 0.3)))
|
||||
)
|
||||
(fp_poly (pts (xy -0.196711 -1.697674) (xy -0.119057 -1.509220) (xy -0.123862 -1.374646) (xy -0.129716 -1.236468) (xy -0.097802 -1.005898) (xy -0.040397 -0.733497) (xy 0.030224 -0.469826) (xy 0.101784 -0.265448)
|
||||
(xy 0.162008 -0.170922) (xy 0.168777 -0.169333) (xy 0.297274 -0.239711) (xy 0.418671 -0.402675) (xy 0.473805 -0.550333) (xy 0.846667 -0.550333) (xy 0.889000 -0.508000) (xy 0.931334 -0.550333)
|
||||
(xy 0.889000 -0.592666) (xy 0.846667 -0.550333) (xy 0.473805 -0.550333) (xy 0.487114 -0.585975) (xy 0.485719 -0.668727) (xy 0.495617 -0.762000) (xy 0.677334 -0.762000) (xy 0.706220 -0.679534)
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(xy 1.185334 -0.714670) (xy 1.125197 -0.786282) (xy 1.087585 -0.812418) (xy 1.029648 -0.822397) (xy 0.799138 -0.822397) (xy 0.797621 -0.840019) (xy 0.766997 -0.846666) (xy 0.680779 -0.785206)
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(xy 0.677334 -0.762000) (xy 0.495617 -0.762000) (xy 0.505644 -0.856480) (xy 0.624365 -1.028153) (xy 0.791038 -1.128901) (xy 0.910773 -1.127241) (xy 1.170170 -0.981838) (xy 1.285822 -0.795551)
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|
||||
(xy 0.586867 0.846667) (xy 0.575880 0.909525) (xy 0.641139 1.063944) (xy 0.658515 1.095201) (xy 0.726206 1.266176) (xy 0.733212 1.398144) (xy 0.690360 1.450964) (xy 0.608475 1.384498)
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||||
(xy 0.336440 1.480789) (xy 0.300627 1.592584) (xy 0.263738 1.608667) (xy 0.168533 1.544953) (xy 0.050119 1.397000) (xy -0.082394 1.252472) (xy -0.214153 1.185741) (xy -0.301843 1.204755)
|
||||
(xy -0.302145 1.317462) (xy -0.295986 1.333500) (xy -0.227278 1.587595) (xy -0.271288 1.731367) (xy -0.305906 1.750912) (xy -0.399063 1.705438) (xy -0.497227 1.549604) (xy -0.503121 1.535778)
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||||
(xy -0.611474 1.370919) (xy -0.752758 1.261874) (xy -0.885274 1.222116) (xy -0.967321 1.265117) (xy -0.963085 1.387172) (xy -0.903244 1.650363) (xy -0.936925 1.795537) (xy -1.025706 1.842257)
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(xy -0.184310 0.138355) (xy -0.197555 0.112889) (xy -0.298035 0.102756) (xy -0.310444 0.112889) (xy -1.622443 0.112889) (xy -1.601404 0.059914) (xy -1.499755 0.016846) (xy -1.292184 0.038596)
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(xy -1.281169 0.040446) (xy -1.009246 0.053143) (xy -0.960053 0.028222) (xy -0.056444 0.028222) (xy -0.044822 0.078557) (xy 0.000000 0.084667) (xy 0.069690 0.053689) (xy 0.056445 0.028222)
|
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(xy -0.044035 0.018089) (xy -0.056444 0.028222) (xy -0.960053 0.028222) (xy -0.894251 -0.005113) (xy 0.315397 -0.005113) (xy 0.423832 -0.037049) (xy 0.604454 -0.162045) (xy 0.724868 -0.293695)
|
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(xy 0.740159 -0.388329) (xy 0.738268 -0.390389) (xy 0.643174 -0.379791) (xy 0.489029 -0.271038) (xy 0.443859 -0.228343) (xy 0.315472 -0.071602) (xy 0.315397 -0.005113) (xy -0.894251 -0.005113)
|
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(xy -0.872412 -0.016176) (xy -0.787661 -0.169333) (xy -0.423333 -0.169333) (xy -0.358904 -0.087127) (xy -0.338666 -0.084666) (xy -0.256460 -0.149096) (xy -0.254000 -0.169333) (xy -0.318429 -0.251540)
|
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(xy -0.338666 -0.254000) (xy -0.420873 -0.189571) (xy -0.423333 -0.169333) (xy -0.787661 -0.169333) (xy -0.776919 -0.188745) (xy -0.751219 -0.254000) (xy -0.592666 -0.254000) (xy -0.561688 -0.184310)
|
||||
(xy -0.536222 -0.197555) (xy -0.526089 -0.298035) (xy -0.536222 -0.310444) (xy -0.586556 -0.298822) (xy -0.592666 -0.254000) (xy -0.751219 -0.254000) (xy -0.701200 -0.381000) (xy -0.338666 -0.381000)
|
||||
(xy -0.296333 -0.338666) (xy -0.254000 -0.381000) (xy -0.296333 -0.423333) (xy -0.338666 -0.381000) (xy -0.701200 -0.381000) (xy -0.671894 -0.455408) (xy -0.668608 -0.465666) (xy -0.169333 -0.465666)
|
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(xy -0.127000 -0.423333) (xy -0.084666 -0.465666) (xy -0.127000 -0.508000) (xy -0.169333 -0.465666) (xy -0.668608 -0.465666) (xy -0.627916 -0.592666) (xy -0.338666 -0.592666) (xy -0.307688 -0.522976)
|
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(xy -0.282222 -0.536222) (xy -0.272089 -0.636702) (xy -0.282222 -0.649111) (xy -0.332556 -0.637489) (xy -0.338666 -0.592666) (xy -0.627916 -0.592666) (xy -0.573639 -0.762062) (xy -0.498454 -1.054600)
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(xy -0.462643 -1.278920) (xy -0.467437 -1.360244) (xy -0.468878 -1.556926) (xy -0.420620 -1.698403) (xy -0.323859 -1.879202) (xy -0.196711 -1.697674) )(layer F.SilkS) (width 0.010000)
|
||||
)
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(fp_poly (pts (xy 1.664232 -1.400084) (xy 1.647878 -1.266812) (xy 1.641503 -1.256210) (xy 1.591774 -1.076543) (xy 1.594935 -0.994833) (xy 1.571229 -0.873555) (xy 1.460270 -0.869531) (xy 1.291925 -0.977713)
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|
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)
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)
|
||||
144
schematics/v2.0/Graphic.pretty/CycloneInside.kicad_mod
Normal file
144
schematics/v2.0/Graphic.pretty/CycloneInside.kicad_mod
Normal file
@@ -0,0 +1,144 @@
|
||||
(module LOGO (layer F.Cu)
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||||
(at 0 0)
|
||||
(fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
|
||||
(effects (font (thickness 0.3)))
|
||||
)
|
||||
(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
|
||||
(effects (font (thickness 0.3)))
|
||||
)
|
||||
(fp_poly (pts (xy 20.320000 11.430000) (xy -20.320000 11.430000) (xy -20.320000 2.328333) (xy -7.664854 2.328333) (xy -7.664517 3.169628) (xy -7.663551 3.894108) (xy -7.662009 4.495699) (xy -7.659949 4.968330)
|
||||
(xy -7.657424 5.305929) (xy -7.654491 5.502422) (xy -7.651204 5.551739) (xy -7.647618 5.447805) (xy -7.643790 5.184550) (xy -7.641203 4.925728) (xy -7.635603 4.092708) (xy -7.632362 3.153739)
|
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(xy -7.631479 2.166748) (xy -7.632954 1.189663) (xy -7.636787 0.280410) (xy -7.641222 -0.323606) (xy -7.642993 -0.484984) (xy -6.771487 -0.484984) (xy -6.771474 0.052156) (xy -6.770845 1.138488)
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291
schematics/v2.0/Graphic.pretty/IntelInside.kicad_mod
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291
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||||
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||||
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||||
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1248
schematics/v2.0/MZ80-80CLR-cache.lib
Normal file
1248
schematics/v2.0/MZ80-80CLR-cache.lib
Normal file
File diff suppressed because it is too large
Load Diff
3
schematics/v2.0/MZ80-80CLR-rescue.dcm
Normal file
3
schematics/v2.0/MZ80-80CLR-rescue.dcm
Normal file
@@ -0,0 +1,3 @@
|
||||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
#End Doc Library
|
||||
237
schematics/v2.0/MZ80-80CLR-rescue.lib
Normal file
237
schematics/v2.0/MZ80-80CLR-rescue.lib
Normal file
@@ -0,0 +1,237 @@
|
||||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# 2016_Socket
|
||||
#
|
||||
DEF 2016_Socket U 0 10 Y Y 1 F N
|
||||
F0 "U" 0 250 50 H V C CNN
|
||||
F1 "2016_Socket" 450 -850 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -250 750 250 -750 0 1 0 f
|
||||
X GND 12 0 -850 94 U 50 50 0 0 w
|
||||
X Vcc 24 0 850 94 D 50 50 0 0 w
|
||||
X A7 1 -400 0 157 R 50 50 1 1 P
|
||||
X D1 10 400 550 157 L 50 50 1 1 B
|
||||
X D2 11 400 450 157 L 50 50 1 1 B
|
||||
X D3 13 400 350 157 L 50 50 1 1 B
|
||||
X D4 14 400 250 157 L 50 50 1 1 B
|
||||
X D5 15 400 150 157 L 50 50 1 1 B
|
||||
X D6 16 400 50 157 L 50 50 1 1 B
|
||||
X D7 17 400 -50 157 L 50 50 1 1 B
|
||||
X ~CS~ 18 -400 -700 157 R 50 50 1 1 P
|
||||
X A10 19 -400 -300 157 R 50 50 1 1 P
|
||||
X A6 2 -400 100 157 R 50 50 1 1 P
|
||||
X ~OE~ 20 -400 -600 157 R 50 50 1 1 I
|
||||
X ~WE~ 21 -400 -500 157 R 50 50 1 1 I
|
||||
X A9 22 -400 -200 157 R 50 50 1 1 P
|
||||
X A8 23 -400 -100 157 R 50 50 1 1 P
|
||||
X A5 3 -400 200 157 R 50 50 1 1 P
|
||||
X A4 4 -400 300 157 R 50 50 1 1 P
|
||||
X A3 5 -400 400 157 R 50 50 1 1 P
|
||||
X A2 6 -400 500 157 R 50 50 1 1 P
|
||||
X A1 7 -400 600 157 R 50 50 1 1 P
|
||||
X A0 8 -400 700 157 R 50 50 1 1 P
|
||||
X D0 9 400 650 157 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 2732_Socket
|
||||
#
|
||||
DEF 2732_Socket U 0 10 Y Y 1 F N
|
||||
F0 "U" 0 250 50 H V C CNN
|
||||
F1 "2732_Socket" 450 -850 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -250 750 250 -750 0 1 0 f
|
||||
X GND 12 0 -800 50 U 50 50 0 0 P
|
||||
X Vcc 24 0 800 50 D 50 50 0 0 P
|
||||
X A7 1 -400 0 157 R 50 50 1 1 P
|
||||
X Q1 10 400 550 157 L 50 50 1 1 P
|
||||
X Q2 11 400 450 157 L 50 50 1 1 P
|
||||
X Q3 13 400 350 157 L 50 50 1 1 P
|
||||
X Q4 14 400 250 157 L 50 50 1 1 P
|
||||
X Q5 15 400 150 157 L 50 50 1 1 P
|
||||
X Q6 16 400 50 157 L 50 50 1 1 P
|
||||
X Q7 17 400 -50 157 L 50 50 1 1 P
|
||||
X ~E 18 -400 -700 157 R 50 50 1 1 P
|
||||
X A10 19 -400 -300 157 R 50 50 1 1 P
|
||||
X A6 2 -400 100 157 R 50 50 1 1 P
|
||||
X ~G 20 -400 -600 157 R 50 50 1 1 P
|
||||
X A11 21 -400 -400 157 R 50 50 1 1 P
|
||||
X A9 22 -400 -200 157 R 50 50 1 1 P
|
||||
X A8 23 -400 -100 157 R 50 50 1 1 P
|
||||
X A5 3 -400 200 157 R 50 50 1 1 P
|
||||
X A4 4 -400 300 157 R 50 50 1 1 P
|
||||
X A3 5 -400 400 157 R 50 50 1 1 P
|
||||
X A2 6 -400 500 157 R 50 50 1 1 P
|
||||
X A1 7 -400 600 157 R 50 50 1 1 P
|
||||
X A0 8 -400 700 157 R 50 50 1 1 P
|
||||
X Q0 9 400 650 157 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# EP3C25E144C8N-1-epm7128slc84
|
||||
#
|
||||
DEF EP3C25E144C8N-1-epm7128slc84 U 0 40 Y Y 3 L N
|
||||
F0 "U" 800 200 50 H V L CNN
|
||||
F1 "EP3C25E144C8N-1-epm7128slc84" 800 -2350 50 H V L CNN
|
||||
F2 "Package_QFP" 800 -2250 50 H I L CNN
|
||||
F3 "" 1650 -800 50 H I C CNN
|
||||
$FPLIST
|
||||
*QFP*P0.5mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -550 1750 600 -1650 1 1 10 f
|
||||
S -400 850 400 -900 2 1 10 f
|
||||
S -700 1800 700 -2150 3 1 10 f
|
||||
X IO_B1_10 10 850 -700 254 L 50 50 1 1 B
|
||||
X IO_B6_100 100 -800 -200 254 R 50 50 1 1 B
|
||||
X IO_B6_101 101 -800 -300 254 R 50 50 1 1 B
|
||||
X IO_B6_103 103 -800 -400 243 R 50 50 1 1 B
|
||||
X IO_B6_104 104 -800 -500 254 R 50 50 1 1 B
|
||||
X IO_B6_105 105 -800 -600 254 R 50 50 1 1 B
|
||||
X IO_B6_106 106 -800 -700 246 R 50 50 1 1 B
|
||||
X IO_B1_11 11 -800 -800 254 R 50 50 1 1 B
|
||||
X IO_B7_110 110 850 -300 247 L 50 50 1 1 B
|
||||
X IO_B7_111 111 850 -200 248 L 50 50 1 1 B
|
||||
X IO_B7_112 112 850 -100 249 L 50 50 1 1 B
|
||||
X IO_B7_113 113 850 0 250 L 50 50 1 1 B
|
||||
X IO_B7_114 114 850 100 251 L 50 50 1 1 B
|
||||
X IO_B7_115 115 850 200 252 L 50 50 1 1 B
|
||||
X IO_B7_119 119 850 300 253 L 50 50 1 1 B
|
||||
X IO_B7_120 120 -800 300 254 R 50 50 1 1 B
|
||||
X IO_B7_121 121 -800 400 255 R 50 50 1 1 B
|
||||
X IO_B7_125 125 -800 500 256 R 50 50 1 1 B
|
||||
X IO_B8_132 132 -800 600 257 R 50 50 1 1 B
|
||||
X IO_B8_133 133 -800 700 258 R 50 50 1 1 B
|
||||
X IO_B8_135 135 -800 800 259 R 50 50 1 1 B
|
||||
X IO_B8_136 136 -800 900 260 R 50 50 1 1 B
|
||||
X IO_B8_137 137 -800 1000 261 R 50 50 1 1 B
|
||||
X IO_B8_141 141 -800 1100 254 R 50 50 1 1 B
|
||||
X IO_B8_142 142 -800 1200 254 R 50 50 1 1 B
|
||||
X IO_B8_143 143 -800 1300 254 R 50 50 1 1 B
|
||||
X IO_B8_144 144 -800 1400 254 R 50 50 1 1 B
|
||||
X IO_B2_28 28 850 -800 254 L 50 50 1 1 B
|
||||
X IO_B2_30 30 850 800 254 L 50 50 1 1 B
|
||||
X IO_B2_31 31 850 700 254 L 50 50 1 1 B
|
||||
X IO_B2_32 32 850 600 254 L 50 50 1 1 B
|
||||
X IO_B2_33 33 850 500 254 L 50 50 1 1 B
|
||||
X IO_B3_39 39 850 1200 254 L 50 50 1 1 B
|
||||
X IO_B1_4 4 -800 1600 254 R 50 50 1 1 B
|
||||
X IO_B3_42 42 850 1100 254 L 50 50 1 1 B
|
||||
X IO_B3_43 43 850 1000 254 L 50 50 1 1 B
|
||||
X IO_B3_44 44 850 900 254 L 50 50 1 1 B
|
||||
X IO_B3_46 46 850 1600 254 L 50 50 1 1 B
|
||||
X IO_B3_49 49 850 1500 254 L 50 50 1 1 B
|
||||
X IO_B3_50 50 850 1400 254 L 50 50 1 1 B
|
||||
X IO_B3_51 51 850 1300 254 L 50 50 1 1 B
|
||||
X IO_B4_58 58 850 -500 254 L 50 50 1 1 B
|
||||
X IO_B4_59 59 850 -400 254 L 50 50 1 1 B
|
||||
X IO_B4_60 60 850 -600 254 L 50 50 1 1 B
|
||||
X IO_B4_64 64 850 400 254 L 50 50 1 1 B
|
||||
X IO_B4_65 65 -800 -900 254 R 50 50 1 1 B
|
||||
X IO_B4_66 66 -800 -1000 254 R 50 50 1 1 B
|
||||
X IO_B4_67 67 -800 -1100 254 R 50 50 1 1 B
|
||||
X IO_B4_68 68 -800 -1200 254 R 50 50 1 1 B
|
||||
X IO_B4_69 69 -800 -1300 254 R 50 50 1 1 B
|
||||
X IO_B1_7 7 -800 1500 254 R 50 50 1 1 B
|
||||
X IO_B4_71 71 850 -900 254 L 50 50 1 1 B
|
||||
X IO_B4_72 72 850 -1000 254 L 50 50 1 1 B
|
||||
X IO_B5_76 76 850 -1100 254 L 50 50 1 1 B
|
||||
X IO_B5_77 77 850 -1200 254 L 50 50 1 1 B
|
||||
X IO_B5_79 79 850 -1300 254 L 50 50 1 1 B
|
||||
X IO_B5_80 80 -800 100 254 R 50 50 1 1 B
|
||||
X IO_B5_83 83 -800 200 254 R 50 50 1 1 B
|
||||
X IO_B5_85 85 850 -1400 254 L 50 50 1 1 B
|
||||
X IO_B5_86 86 -800 -1500 254 R 50 50 1 1 B
|
||||
X IO_B5_87 87 -800 -1400 254 R 50 50 1 1 B
|
||||
X IO_B6_98 98 -800 0 254 R 50 50 1 1 B
|
||||
X IO_B6_99 99 -800 -100 254 R 50 50 1 1 B
|
||||
X DCLK 12 600 -250 206 L 50 50 2 1 B
|
||||
X CLK8 126 -600 -50 200 R 50 50 2 1 I
|
||||
X CLK9 127 -600 -150 200 R 50 50 2 1 I
|
||||
X CLK10 128 -600 -250 200 R 50 50 2 1 I
|
||||
X CLK11 129 -600 -350 200 R 50 50 2 1 I
|
||||
X DATA0 13 600 -150 206 L 50 50 2 1 B
|
||||
X nCONFIG 14 600 650 200 L 50 50 2 1 I
|
||||
X TDI 15 600 300 200 L 50 50 2 1 I
|
||||
X TCK 16 600 200 200 L 50 50 2 1 I
|
||||
X TMS 18 600 100 200 L 50 50 2 1 I
|
||||
X TDO 20 600 0 200 L 50 50 2 1 I
|
||||
X nCE 21 600 550 200 L 50 50 2 1 I
|
||||
X CLK0 22 -600 750 200 R 50 50 2 1 I
|
||||
X CLK1 23 -600 650 200 R 50 50 2 1 I
|
||||
X CLK2 24 -600 550 200 R 50 50 2 1 I
|
||||
X CLK3 25 -600 450 200 R 50 50 2 1 I
|
||||
X CLK15 52 -600 -750 200 R 50 50 2 1 I
|
||||
X CLK14 53 -600 -650 200 R 50 50 2 1 I
|
||||
X CLK13 54 -600 -550 200 R 50 50 2 1 I
|
||||
X CLK12 55 -600 -450 200 R 50 50 2 1 I
|
||||
X ASDO 6 600 -350 201 L 50 50 2 1 B
|
||||
X nCS0 8 600 -450 203 L 50 50 2 1 B
|
||||
X CLK7 88 -600 50 200 R 50 50 2 1 I
|
||||
X CLK6 89 -600 150 200 R 50 50 2 1 I
|
||||
X nSTATUS 9 600 750 200 L 50 50 2 1 I
|
||||
X CLK5 90 -600 250 200 R 50 50 2 1 I
|
||||
X CLK4 91 -600 350 200 R 50 50 2 1 I
|
||||
X CONF_DONE 92 600 450 200 L 50 50 2 1 I
|
||||
X MSEL0 94 600 -600 200 L 50 50 2 1 I
|
||||
X MSEL1 96 600 -700 200 L 50 50 2 1 I
|
||||
X MSEL2 97 600 -800 200 L 50 50 2 1 I
|
||||
X VCCD_PLL3 1 900 -1450 200 L 50 50 3 1 W
|
||||
X VCCINT10 102 900 -600 200 L 50 50 3 1 W
|
||||
X VCCA2 107 900 -1800 200 L 50 50 3 1 W
|
||||
X GNDA2 108 -900 1350 200 R 50 50 3 1 W
|
||||
X VCCD_PLL2 109 900 -1350 200 L 50 50 3 1 W
|
||||
X VCCINT11 116 900 -700 200 L 50 50 3 1 W
|
||||
X VCCIO7 117 900 850 200 L 50 50 3 1 W
|
||||
X GND9 118 -900 100 200 R 50 50 3 1 W
|
||||
X VCCIO7 122 900 750 200 L 50 50 3 1 W
|
||||
X GND10 123 -900 0 200 R 50 50 3 1 W
|
||||
X VCCINT12 124 900 -800 200 L 50 50 3 1 W
|
||||
X VCCIO8 130 900 650 200 L 50 50 3 1 W
|
||||
X GND11 131 -900 -100 200 R 50 50 3 1 W
|
||||
X VCCINT13 134 900 -900 200 L 50 50 3 1 W
|
||||
X VCCINT14 138 900 -1000 200 L 50 50 3 1 W
|
||||
X VCCIO8 139 900 550 200 L 50 50 3 1 W
|
||||
X GND12 140 -900 -200 200 R 50 50 3 1 W
|
||||
X VCCIO1 17 900 1650 200 L 50 50 3 1 W
|
||||
X GND1 19 -900 900 200 R 50 50 3 1 W
|
||||
X GNDA3 2 -900 1250 200 R 50 50 3 1 W
|
||||
X VCCIO2 26 900 1550 200 L 50 50 3 1 W
|
||||
X GND2 27 -900 800 200 R 50 50 3 1 W
|
||||
X VCCINT2 29 900 200 200 L 50 50 3 1 W
|
||||
X VCCA3 3 900 -1900 200 L 50 50 3 1 W
|
||||
X VCCINT3 34 900 100 200 L 50 50 3 1 W
|
||||
X VCCA1 35 900 -1700 200 L 50 50 3 1 W
|
||||
X GNDA1 36 -900 1450 200 R 50 50 3 1 W
|
||||
X VCCD_PLL1 37 900 -1250 200 L 50 50 3 1 W
|
||||
X VCCINT4 38 900 0 200 L 50 50 3 1 W
|
||||
X VCCIO3 40 900 1450 200 L 50 50 3 1 W
|
||||
X GND3 41 -900 700 200 R 50 50 3 1 W
|
||||
X VCCINT5 45 900 -100 200 L 50 50 3 1 W
|
||||
X VCCIO3 47 900 1350 200 L 50 50 3 1 W
|
||||
X GND4 48 -900 600 200 R 50 50 3 1 W
|
||||
X VCCINT1 5 900 300 200 L 50 50 3 1 W
|
||||
X VCCIO4 56 900 1250 200 L 50 50 3 1 W
|
||||
X GND5 57 -900 500 200 R 50 50 3 1 W
|
||||
X VCCINT6 61 900 -200 200 L 50 50 3 1 W
|
||||
X VCCIO4 62 900 1150 200 L 50 50 3 1 W
|
||||
X GND6 63 -900 400 200 R 50 50 3 1 W
|
||||
X VCCINT7 70 900 -300 200 L 50 50 3 1 W
|
||||
X VCCD_PLL4 73 900 -1550 200 L 50 50 3 1 W
|
||||
X GNDA4 74 -900 1150 200 R 50 50 3 1 W
|
||||
X VCCA4 75 900 -2000 200 L 50 50 3 1 W
|
||||
X VCCINT8 78 900 -400 200 L 50 50 3 1 W
|
||||
X VCCIO5 81 900 1050 200 L 50 50 3 1 W
|
||||
X GND7 82 -900 300 200 R 50 50 3 1 W
|
||||
X VCCINT9 84 900 -500 200 L 50 50 3 1 W
|
||||
X VCCIO6 93 900 950 200 L 50 50 3 1 W
|
||||
X GND8 95 -900 200 200 R 50 50 3 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
BIN
schematics/v2.0/MZ80-80CLR.jpg
Normal file
BIN
schematics/v2.0/MZ80-80CLR.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 167 KiB |
10370
schematics/v2.0/MZ80-80CLR.kicad_pcb
Normal file
10370
schematics/v2.0/MZ80-80CLR.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
259
schematics/v2.0/MZ80-80CLR.pro
Normal file
259
schematics/v2.0/MZ80-80CLR.pro
Normal file
@@ -0,0 +1,259 @@
|
||||
update=Friday, 11 September 2020 at 19:18:42
|
||||
version=1
|
||||
last_client=kicad
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=0
|
||||
MinTrackWidth=0.1524
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.254
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.1524
|
||||
TrackWidth3=0.254
|
||||
TrackWidth4=0.381
|
||||
TrackWidth5=0.508
|
||||
TrackWidth6=0.8128
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
ViaDiameter2=0.4826
|
||||
ViaDrill2=0.3302
|
||||
ViaDiameter3=0.5
|
||||
ViaDrill3=0.4
|
||||
ViaDiameter4=1.905
|
||||
ViaDrill4=0.254
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=39
|
||||
ERC_TestSimilarLabels=1
|
||||
112
schematics/v2.0/MZ80-80CLR.rules
Normal file
112
schematics/v2.0/MZ80-80CLR.rules
Normal file
@@ -0,0 +1,112 @@
|
||||
|
||||
(rules PCB MZ80-80CLR
|
||||
(snap_angle
|
||||
fortyfive_degree
|
||||
)
|
||||
(autoroute_settings
|
||||
(fanout off)
|
||||
(eu.mihosoft.freerouting.autoroute on)
|
||||
(postroute on)
|
||||
(vias on)
|
||||
(via_costs 50)
|
||||
(plane_via_costs 5)
|
||||
(start_ripup_costs 100)
|
||||
(start_pass_no 10444)
|
||||
(layer_rule F.Cu
|
||||
(active on)
|
||||
(preferred_direction vertical)
|
||||
(preferred_direction_trace_costs 1.0)
|
||||
(against_preferred_direction_trace_costs 2.4)
|
||||
)
|
||||
(layer_rule B.Cu
|
||||
(active on)
|
||||
(preferred_direction horizontal)
|
||||
(preferred_direction_trace_costs 1.0)
|
||||
(against_preferred_direction_trace_costs 1.7)
|
||||
)
|
||||
)
|
||||
(rule
|
||||
(width 152.4)
|
||||
(clear 200.2)
|
||||
(clear 125.0 (type smd_to_turn_gap))
|
||||
(clear 50.0 (type smd_smd))
|
||||
)
|
||||
(padstack "Via[0-1]_800:400_um"
|
||||
(shape
|
||||
(circle F.Cu 800.0 0.0 0.0)
|
||||
)
|
||||
(shape
|
||||
(circle B.Cu 800.0 0.0 0.0)
|
||||
)
|
||||
(attach off)
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um" "Via[0-1]_800:400_um" default
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-kicad_default" "Via[0-1]_800:400_um" "kicad_default"
|
||||
)
|
||||
(via_rule
|
||||
default "Via[0-1]_800:400_um"
|
||||
)
|
||||
(via_rule
|
||||
"kicad_default" "Via[0-1]_800:400_um-kicad_default"
|
||||
)
|
||||
(class default
|
||||
(clearance_class default)
|
||||
(via_rule default)
|
||||
(rule
|
||||
(width 152.4)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class "kicad_default"
|
||||
"Net-(SK1-Pad21)" "Net-(SK2-Pad1)" "Net-(SK3-Pad13)" "Net-(SK3-Pad12)" "Net-(SK3-Pad6)" "Net-(SK3-Pad5)" "Net-(SK3-Pad15)" "Net-(U3-Pad13)"
|
||||
"Net-(U3-Pad12)" "Net-(JP1-Pad2)" "Net-(Q1-Pad3)" "Net-(Q1-Pad2)" CSYNC ~CSYNC~ "/FPGA and CPLD Module/A13" "/FPGA and CPLD Module/~IORQ~"
|
||||
"/FPGA and CPLD Module/A12" "/FPGA and CPLD Module/~MEM_CS~" "/FPGA and CPLD Module/A11" "/FPGA and CPLD Module/A10" "/FPGA and CPLD Module/A9" "/FPGA and CPLD Module/A8" "/FPGA and CPLD Module/A7" "/FPGA and CPLD Module/A6"
|
||||
"/FPGA and CPLD Module/A5" "/FPGA and CPLD Module/A4" "/FPGA and CPLD Module/A3" "/FPGA and CPLD Module/A2" "/FPGA and CPLD Module/A1" "/FPGA and CPLD Module/A0" "Net-(J4-Pad7)" "Net-(J4-Pad6)"
|
||||
"Net-(J4-Pad5)" "Net-(J4-Pad3)" "Net-(Q1-Pad1)" "VGA_B3" "VGA_B2" "VGA_B1" "VGA_B0" "VGA_R3"
|
||||
"VGA_R2" "VGA_R1" "VGA_R0" "VGA_G3" "VGA_G2" "VGA_G1" "VGA_G0" "VGA_HS"
|
||||
"VGA_VS" "Net-(SK1-Pad20)" "1MHZ_OUT" "2MHZ_OUT" "Net-(U3-Pad129)" "Net-(U3-Pad128)" "Net-(U3-Pad127)" "Net-(U3-Pad126)"
|
||||
"/FPGA and CPLD Module/~VMEM_CS~" "/FPGA and CPLD Module/~VIORQ~" "/FPGA and CPLD Module/~VRD~" "Net-(U3-Pad91)" "Net-(U3-Pad90)" "Net-(U3-Pad89)" "/FPGA and CPLD Module/~VCS~" "/FPGA and CPLD Module/~VGT~"
|
||||
"/FPGA and CPLD Module/~VWR~" "/FPGA and CPLD Module/~VRESET~" "Net-(U3-Pad55)" "Net-(U3-Pad54)" "Net-(U3-Pad53)" "Net-(U3-Pad52)" "Net-(U3-Pad25)" "Net-(U3-Pad24)"
|
||||
"Net-(U3-Pad23)" "Net-(U3-Pad22)" "Net-(U3-Pad8)" "Net-(U3-Pad6)" "Net-(U5-Pad128)" "Net-(U5-Pad126)" "SRVIDEO_OUT" "Net-(X1-Pad1)"
|
||||
"Net-(X2-Pad1)" "Net-(U3-Pad15)" "/FPGA and CPLD Module/~RESET~" "/FPGA and CPLD Module/~RD~" "/FPGA and CPLD Module/~CS~" "/FPGA and CPLD Module/~MB_HBLNK~" "/FPGA and CPLD Module/~GT~" "/FPGA and CPLD Module/MB_SYNCH"
|
||||
"/FPGA and CPLD Module/~WR~" "/FPGA and CPLD Module/~MB_V-HBLNK~" "/FPGA and CPLD Module/MB_VIDEO" "/FPGA and CPLD Module/MB_LOAD" "/FPGA and CPLD Module/D7" "/FPGA and CPLD Module/D6" "/FPGA and CPLD Module/D5" "/FPGA and CPLD Module/D4"
|
||||
"/FPGA and CPLD Module/D3" "/FPGA and CPLD Module/D2" "/FPGA and CPLD Module/D1" "/FPGA and CPLD Module/D0" "Net-(J3-Pad9)" "Net-(J3-Pad8)" "Net-(J3-Pad7)" "Net-(J3-Pad6)"
|
||||
"Net-(J3-Pad5)" "Net-(J3-Pad3)" "Net-(J3-Pad1)" "Net-(J4-Pad10)" "Net-(J4-Pad4)" "Net-(R1-Pad2)" "Net-(R2-Pad2)" "Net-(R3-Pad2)"
|
||||
"Net-(SK1-Pad23)" VRAMD2 "Net-(SK1-Pad22)" VRAMD1 VRAMD0 "Net-(SK1-Pad8)" "Net-(SK1-Pad19)" "Net-(SK1-Pad7)"
|
||||
"~VRAM_CS_IN~" "Net-(SK1-Pad6)" VRAMD7 "Net-(SK1-Pad5)" VRAMD6 "Net-(SK1-Pad4)" VRAMD5 "Net-(SK1-Pad3)"
|
||||
VRAMD4 "Net-(SK1-Pad2)" VRAMD3 "Net-(SK1-Pad1)" "Net-(SK3-Pad27)" "Net-(SK3-Pad26)" "31.5K_OUT" "Net-(SK3-Pad24)"
|
||||
"SYNCH_OUT" "Net-(SK3-Pad23)" "Net-(SK3-Pad9)" "Net-(SK3-Pad22)" "~VBLNK_OUT~" "HSY_OUT" "Net-(SK3-Pad20)" "Net-(SK3-Pad18)"
|
||||
"Net-(SK3-Pad17)" "Net-(SK3-Pad16)" "~HBLNK_OUT~" "/FPGA and CPLD Module/VDATA6" "/FPGA and CPLD Module/VDATA7" "/FPGA and CPLD Module/VDATA5" "/FPGA and CPLD Module/VDATA4" "/FPGA and CPLD Module/VDATA3"
|
||||
"/FPGA and CPLD Module/VDATA2" "/FPGA and CPLD Module/VDATA1" "/FPGA and CPLD Module/VDATA0" "/FPGA and CPLD Module/VADDR13" "/FPGA and CPLD Module/VADDR12" "/FPGA and CPLD Module/VADDR11" "/FPGA and CPLD Module/VADDR10" "/FPGA and CPLD Module/VADDR9"
|
||||
"/FPGA and CPLD Module/VADDR8" "/FPGA and CPLD Module/VADDR7" "/FPGA and CPLD Module/VADDR6" "/FPGA and CPLD Module/VADDR5" "/FPGA and CPLD Module/VADDR4" "/FPGA and CPLD Module/VADDR3" "/FPGA and CPLD Module/VADDR2" "/FPGA and CPLD Module/VADDR1"
|
||||
"/FPGA and CPLD Module/VADDR0" "Net-(U3-Pad88)" "Net-(U5-Pad143)" "Net-(U5-Pad142)" "Net-(U5-Pad141)" "Net-(U5-Pad140)" "Net-(U5-Pad139)" "Net-(U5-Pad138)"
|
||||
"Net-(U5-Pad137)" "Net-(U5-Pad136)" "Net-(U5-Pad134)" "Net-(U5-Pad133)" "Net-(U5-Pad132)" "Net-(U5-Pad131)" "Net-(U5-Pad26)" "Net-(U5-Pad25)"
|
||||
"Net-(U3-Pad11)" "Net-(U5-Pad5)" "/FPGA and CPLD Module/~VVRAM_CS_IN~" "/FPGA and CPLD Module/TBA2" "/FPGA and CPLD Module/TBA1" "/FPGA and CPLD Module/TBA0" "/FPGA and CPLD Module/TBA4" "/FPGA and CPLD Module/TBA3"
|
||||
"/FPGA and CPLD Module/TBA5" "/FPGA and CPLD Module/TBA6" "/FPGA and CPLD Module/TBA7" "/FPGA and CPLD Module/TBA8" "/FPGA and CPLD Module/TBA9" "Net-(SK2-Pad16)" "/FPGA and CPLD Module/VSRVIDEO_OUT" "/FPGA and CPLD Module/~VHBLNK_OUT~"
|
||||
"/FPGA and CPLD Module/VHSY_OUT" "/FPGA and CPLD Module/VSYNCH_OUT" "Net-(J2-Pad30)" "/FPGA and CPLD Module/~VVBLNK_OUT~" "Net-(SK1-Pad24)" "Net-(U3-Pad28)" "Net-(U5-Pad82)"
|
||||
(clearance_class "kicad_default")
|
||||
(via_rule kicad_default)
|
||||
(rule
|
||||
(width 152.4)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class power
|
||||
GNDPWR +5V +2V5 +3V3 +1V2
|
||||
(clearance_class default)
|
||||
(via_rule default)
|
||||
(rule
|
||||
(width 254.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
)
|
||||
35
schematics/v2.0/MZ80-80CLR.sch
Normal file
35
schematics/v2.0/MZ80-80CLR.sch
Normal file
@@ -0,0 +1,35 @@
|
||||
EESchema Schematic File Version 4
|
||||
LIBS:MZ80-80CLR-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 4
|
||||
Title "Sharp MZ-80A Video Module"
|
||||
Date "2020-07-07"
|
||||
Rev "2.0a"
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 "40/80 column colour output and MZ80B graphics capability."
|
||||
Comment3 "the colour board connector CN1 extends the MZ-80A specification to allow "
|
||||
Comment4 "An add on board, located as an extender in sockets of IC20, 15 and 8 along with"
|
||||
$EndDescr
|
||||
$Sheet
|
||||
S 7600 900 2500 1750
|
||||
U 68A807E5
|
||||
F0 "Power Supply" 39
|
||||
F1 "PowerSupply.sch" 39
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 4300 850 2600 1800
|
||||
U 600002AE
|
||||
F0 "FPGA and CPLD Module" 39
|
||||
F1 "FPGACPLD.sch" 39
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1050 850 2600 1800
|
||||
U 6E14A406
|
||||
F0 "Video Interface and VGA Output" 39
|
||||
F1 "VideoInterfaceAndVGA.sch" 39
|
||||
$EndSheet
|
||||
$EndSCHEMATC
|
||||
BIN
schematics/v2.0/MZ80-80CLR_v2_0_BS.jpg
Normal file
BIN
schematics/v2.0/MZ80-80CLR_v2_0_BS.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 187 KiB |
BIN
schematics/v2.0/MZ80-80CLR_v2_0_TS.jpg
Normal file
BIN
schematics/v2.0/MZ80-80CLR_v2_0_TS.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 228 KiB |
BIN
schematics/v2.0/MZ80-80CLR_v2_0a_BS.png
Normal file
BIN
schematics/v2.0/MZ80-80CLR_v2_0a_BS.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1.3 MiB |
BIN
schematics/v2.0/MZ80-80CLR_v2_0a_TS.png
Normal file
BIN
schematics/v2.0/MZ80-80CLR_v2_0a_TS.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1.9 MiB |
1495
schematics/v2.0/PowerSupply.sch
Normal file
1495
schematics/v2.0/PowerSupply.sch
Normal file
File diff suppressed because it is too large
Load Diff
1171
schematics/v2.0/VideoInterfaceAndVGA.sch
Normal file
1171
schematics/v2.0/VideoInterfaceAndVGA.sch
Normal file
File diff suppressed because it is too large
Load Diff
1197
schematics/v2.0/VideoModule.sch
Normal file
1197
schematics/v2.0/VideoModule.sch
Normal file
File diff suppressed because it is too large
Load Diff
235
schematics/v2.0/gui_defaults.par
Normal file
235
schematics/v2.0/gui_defaults.par
Normal file
@@ -0,0 +1,235 @@
|
||||
|
||||
(gui_defaults
|
||||
(windows
|
||||
(board_frame
|
||||
visible
|
||||
(bounds
|
||||
120 23 1150 896
|
||||
)
|
||||
)
|
||||
(color_manager
|
||||
not_visible
|
||||
(bounds
|
||||
0 600 1110 126
|
||||
)
|
||||
)
|
||||
(layer_visibility
|
||||
not_visible
|
||||
(bounds
|
||||
0 450 354 185
|
||||
)
|
||||
)
|
||||
(object_visibility
|
||||
not_visible
|
||||
(bounds
|
||||
0 514 370 536
|
||||
)
|
||||
)
|
||||
(display_miscellanious
|
||||
not_visible
|
||||
(bounds
|
||||
0 350 336 342
|
||||
)
|
||||
)
|
||||
(snapshots
|
||||
not_visible
|
||||
(bounds
|
||||
0 250 214 267
|
||||
)
|
||||
)
|
||||
(select_parameter
|
||||
visible
|
||||
(bounds
|
||||
0 23 356 464
|
||||
)
|
||||
)
|
||||
(route_parameter
|
||||
not_visible
|
||||
(bounds
|
||||
0 100 356 567
|
||||
)
|
||||
)
|
||||
(manual_rules
|
||||
not_visible
|
||||
(bounds
|
||||
0 23 356 205
|
||||
)
|
||||
)
|
||||
(route_details
|
||||
not_visible
|
||||
(bounds
|
||||
0 23 356 248
|
||||
)
|
||||
)
|
||||
(move_parameter
|
||||
not_visible
|
||||
(bounds
|
||||
0 50 412 146
|
||||
)
|
||||
)
|
||||
(clearance_matrix
|
||||
not_visible
|
||||
(bounds
|
||||
0 150 560 272
|
||||
)
|
||||
)
|
||||
(via_rules
|
||||
not_visible
|
||||
(bounds
|
||||
50 150 496 459
|
||||
)
|
||||
)
|
||||
(edit_vias
|
||||
not_visible
|
||||
(bounds
|
||||
100 150 404 113
|
||||
)
|
||||
)
|
||||
(edit_net_rules
|
||||
not_visible
|
||||
(bounds
|
||||
100 200 904 113
|
||||
)
|
||||
)
|
||||
(assign_net_rules
|
||||
not_visible
|
||||
(bounds
|
||||
100 250 219 362
|
||||
)
|
||||
)
|
||||
(padstack_info
|
||||
not_visible
|
||||
(bounds
|
||||
100 30 0 0
|
||||
)
|
||||
)
|
||||
(package_info
|
||||
not_visible
|
||||
(bounds
|
||||
200 30 0 0
|
||||
)
|
||||
)
|
||||
(component_info
|
||||
not_visible
|
||||
(bounds
|
||||
300 30 0 0
|
||||
)
|
||||
)
|
||||
(net_info
|
||||
not_visible
|
||||
(bounds
|
||||
350 30 0 0
|
||||
)
|
||||
)
|
||||
(incompletes_info
|
||||
not_visible
|
||||
(bounds
|
||||
400 30 0 0
|
||||
)
|
||||
)
|
||||
(violations_info
|
||||
not_visible
|
||||
(bounds
|
||||
500 30 0 0
|
||||
)
|
||||
)
|
||||
)
|
||||
(colors
|
||||
(background
|
||||
0 0 0
|
||||
)
|
||||
(hilight 0.8
|
||||
255 255 255
|
||||
)
|
||||
(incompletes 1.0
|
||||
255 255 255
|
||||
)
|
||||
(outline
|
||||
100 150 255
|
||||
)
|
||||
(component_front
|
||||
0 0 255
|
||||
)
|
||||
(component_back
|
||||
255 0 0
|
||||
)
|
||||
(violations
|
||||
255 0 255
|
||||
)
|
||||
(length_matching 0.1
|
||||
0 255 0
|
||||
)
|
||||
(traces 0.8
|
||||
255 0 0
|
||||
0 0 255
|
||||
)
|
||||
(fixed_traces 0.8
|
||||
255 0 0
|
||||
0 0 255
|
||||
)
|
||||
(vias 0.83
|
||||
200 200 0
|
||||
200 200 0
|
||||
)
|
||||
(fixed_vias 0.83
|
||||
200 200 0
|
||||
200 200 0
|
||||
)
|
||||
(pins 0.78
|
||||
150 50 0
|
||||
160 80 0
|
||||
)
|
||||
(conduction 0.2
|
||||
0 150 0
|
||||
100 100 0
|
||||
)
|
||||
(keepout 0.2
|
||||
0 110 110
|
||||
0 100 160
|
||||
)
|
||||
(via_keepout 0.2
|
||||
100 100 100
|
||||
100 100 100
|
||||
)
|
||||
)
|
||||
(parameter
|
||||
(selection_layers
|
||||
all_visible
|
||||
)
|
||||
(selectable_items
|
||||
TRACES VIAS PINS FIXED UNFIXED
|
||||
)
|
||||
(via_snap_to_smd_center
|
||||
on
|
||||
)
|
||||
(route_mode
|
||||
dynamic
|
||||
)
|
||||
(shove_enabled
|
||||
on
|
||||
)
|
||||
(drag_components_enabled
|
||||
on
|
||||
)
|
||||
(hilight_routing_obstacle
|
||||
off
|
||||
)
|
||||
(pull_tight_region
|
||||
2147483647
|
||||
)
|
||||
(pull_tight_accuracy
|
||||
500
|
||||
)
|
||||
(clearance_compensation
|
||||
off
|
||||
)
|
||||
(ignore_conduction_areas
|
||||
on
|
||||
)
|
||||
(automatic_layer_dimming
|
||||
0.7
|
||||
)
|
||||
(deselected_snapshot_attributes
|
||||
)
|
||||
)
|
||||
)
|
||||
Reference in New Issue
Block a user