268 lines
23 KiB
Tcl
268 lines
23 KiB
Tcl
## Generated SDC file "VideoController.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
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## DATE "Fri Jul 3 00:11:58 2020"
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##
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## DEVICE "EP3C25E144C8"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
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create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#derive_pll_clocks
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create_generated_clock -name {SYS_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[0]}]
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create_generated_clock -name {IF_CLK} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -phase 180.000 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[1]}]
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create_generated_clock -name {VIDCLK_8MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[2]}]
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create_generated_clock -name {VIDCLK_16MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[3]}]
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create_generated_clock -name {VIDCLK_40MHZ} -source [get_pins {VCPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL1|altpll_component|auto_generated|pll1|clk[4]}]
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create_generated_clock -name {VIDCLK_65MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 5 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[0]}]
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create_generated_clock -name {VIDCLK_25_175MHZ} -source [get_pins {VCPLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 91 -divide_by 90 -master_clock {CLOCK_50} [get_pins {VCPLL2|altpll_component|auto_generated|pll1|clk[1]}]
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create_generated_clock -name {VIDCLK_PSEUDO} -source [get_pins {VCPLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 64 -divide_by 25 -master_clock {CLOCK_50} [get_pins {VCPLL3|altpll_component|auto_generated|pll1|clk[0]}]
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create_generated_clock -name {VIDCLK_8_86719MHZ} -source [get_pins {VCPLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 324 -master_clock {CLOCK_50} [get_pins {VCPLL4|altpll_component|auto_generated|pll1|clk[0]}]
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create_generated_clock -name {VIDCLK_17_7344MHZ} -source [get_pins {VCPLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 115 -divide_by 162 -master_clock {CLOCK_50} [get_pins {VCPLL4|altpll_component|auto_generated|pll1|clk[1]}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VRESETn}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_WRn}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_RDn}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VZ80_IORQn}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[15]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[14]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[13]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[12]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[11]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[10]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[9]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[8]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[7]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[6]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[5]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[4]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[3]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[2]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[1]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VADDR[0]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[0]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[1]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[2]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[3]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[4]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[5]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[6]}]
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set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VDATA[7]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[3]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[2]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[1]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[0]}]
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# Required for the Serial Flash Loader.
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tck}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdi}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tms}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[0]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[1]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[2]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[3]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[4]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[5]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[6]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VDATA[7]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 8.000 [get_ports {VWAITn}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[0]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[1]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[2]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B[3]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[0]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[1]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[2]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G[3]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[0]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[1]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[2]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R[3]}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_VS}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_HS}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNC}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {CSYNCn}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSRVIDEO_OUT}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VHBLNK_OUTn}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VHSY_OUT}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VSYNCH_OUT}]
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set_output_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VVBLNK_OUTn}]
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# Required for the Serial Flash Loader.
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdo}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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# There is no relationship between the different video frequencies, only one is used at a time and they are switched through synchronised D-Type flip flops.
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set_false_path -from [get_clocks {VIDCLK_8MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_8_86719MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_17_7344MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_16MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_17_7344MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_25_175MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_40MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_65MHZ}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
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set_false_path -from [get_clocks {VIDCLK_PSEUDO}] -to [get_clocks {CLOCK_50 VIDCLK_PSEUDO VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_65MHZ VIDCLK_25_175MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ IF_CLK}]
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# Z80 clock has no relationship to the video frequencies, it is used only for latching data asynchronous to the FPGA clocks.
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set_false_path -from [get_clocks {IF_CLK}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
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# The system clock has no real relationship with the video frequencies, rendering and display. The only place they meet is in the dual port BRAM.
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set_false_path -from [get_clocks {SYS_CLK}] -to [get_clocks {CLOCK_50 VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
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# Clock 50MHZ, the input oscillator is only used for the PLL input and as I/O input/output latch which is detached from the video block
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set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ VIDCLK_PSEUDO}]
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# The Z80 data, address and control lines do not go to the video block (except the parameter update which is not critical) so set it as a false path so as not to consider.
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set_false_path -from [get_ports {VDATA[*]}] -to [get_clocks {VIDCLK_8MHZ VIDCLK_16MHZ VIDCLK_40MHZ VIDCLK_25_175MHZ VIDCLK_65MHZ VIDCLK_8_86719MHZ VIDCLK_17_7344MHZ}]
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set_false_path -from [get_ports {VADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
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set_false_path -from [get_ports {VZ80_WRn VZ80_RDn VZ80_IORQn}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -hold -start 1
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|DSP_PARAM_SEL[*]}] -to [get_ports {VDATA[*]}] -setup -start 2
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set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {IF_CLK}] -hold -start 1
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set_multicycle_path -from [get_clocks {SYS_CLK}] -to [get_clocks {IF_CLK}] -setup -start 2
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set_multicycle_path -from [get_clocks {IF_CLK}] -to [get_clocks {SYS_CLK}] -hold -start 2
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set_multicycle_path -from [get_clocks {IF_CLK}] -to [get_clocks {SYS_CLK}] -setup -start 3
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# GPU control and run variables have at least 1 clock between them being setup and used.
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -setup -start 2
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
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set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_Y[*]}] -to [get_registers {VideoController:vcToplevel|GRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|\GPU:GPU_VAR_Y[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|GPU_STATE.*}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_END_X[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
|
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_START_Y[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|GPU_START_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|\GPU:GPU_COLUMNS[*]}] -to [get_registers {VideoController:vcToplevel|VRAM_GPU_ADDR[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_MAPPED_DATA[*]}] -hold -start 1
|
|
set_multicycle_path -from [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -to [get_registers {VideoController:vcToplevel|XFER_DST_ADDR[*]}] -hold -start 1
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#**************************************************************
|
|
# Set Maximum Delay
|
|
#**************************************************************
|
|
|
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|
|
|
|
#**************************************************************
|
|
# Set Minimum Delay
|
|
#**************************************************************
|
|
|
|
|
|
|
|
#**************************************************************
|
|
# Set Input Transition
|
|
#**************************************************************
|
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|