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WIP Video Module v2

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This commit is contained in:
Philip Smart
2020-07-04 17:34:46 +01:00
parent cd629622f2
commit 0831b416bb
18 changed files with 3532 additions and 0 deletions
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CPLD/.VideoInterface.vhd.swp
CPLD/.VideoInterface_Toplevel.vhd.swp
CPLD/.VideoInterface_pkg.vhd.swp
CPLD/build/.VideoInterface.qsf.swp
CPLD/build/VideoInterface.csv
CPLD/build/VideoInterface.qsf.bak
CPLD/build/db/
CPLD/build/incremental_db/
CPLD/build/old/
CPLD/build/output_files/
CPLD/build/simulation/
FPGA/.VideoController.vhd.swp
FPGA/.VideoController_Toplevel.vhd.swp
FPGA/.VideoController_pkg.vhd.swp
FPGA/build/.VideoController.qsf.swp
FPGA/build/.qsys_edit/
FPGA/build/Clock_50to100.cnx
FPGA/build/Clock_50to100.cnxerr
FPGA/build/PLLJ_PLLSPE_INFO.txt
FPGA/build/VideoController.out.sdc
FPGA/build/VideoController.srf
FPGA/build/VideoController_assignment_defaults.qdf
FPGA/build/db/
FPGA/build/incremental_db/
FPGA/build/old/
FPGA/build/output_files/
FPGA/build/simulation/
FPGA/build/test.bsf
FPGA/build/test.cmp
FPGA/build/test.html
FPGA/build/test.qsys
FPGA/build/test.sopcinfo
FPGA/build/test/
FPGA/build/test_generation.rpt
FPGA/build/test_generation_1.rpt
FPGA/devices/
FPGA/functions.vhd
schematics/MZ80-80CLR/

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---------------------------------------------------------------------------------------------------------
--
-- Name: VideoInterface.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: MZ80A Video Module v2.0 CPLD logic definition file.
-- This module contains the definition of the logic used in v2.0 of the Sharp MZ80A
-- Video Module. The design uses a CPLD for glue logic and voltage translation and a
-- Cyclone III to realise the video circuitry.
-- The sizing of the CPLD is probably overkill but like most developments, more is better
-- until the design is finalised as it gives you more options.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.VideoInterface_pkg.all;
entity VideoInterface is
--generic (
--);
port (
-- Primary video clock.
VID_CLK : in std_logic; -- 16MHz base clock for video timing and gate clocking.
-- Z80 Address and Data. Address is muxed with video addressing, not direct.
A : in std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
D : inout std_logic_vector(7 downto 0); -- Z80 Data bus, from the Colour Card CN! connector.
-- Z80 Control signals.
WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector.
RDn : in std_logic; -- Z80 Read signal from the Colour Card CN! connector.
RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board.
IORQn : in std_logic; -- Z80 IORQ signal from the tranZPUter board.
-- Video and Mainboard signals.
SRVIDEO_OUT : out std_logic; -- Shift Register 74LS165 Video Output onto mainboard.
CLK_31_5K_OUT : out std_logic; -- 31.5KHz time base for the 8253 on mainboard. Signal was from the MB14298.
CLK_1MHZ_OUT : out std_logic; -- 1MHZ video timing clock output to mainboard. Signal was from the MB14298.
CLK_2MHZ_OUT : out std_logic; -- 2MHZ main CPU clock output to mainboard. Signal was from the MB14298.
HBLNK_OUTn : out std_logic; -- Horizontal Blanking output. Signal was from the MB14298.
HSY_OUT : out std_logic; -- Horizontal sync output. Signal was from the MB14298.
SYNCH_OUT : out std_logic; -- Vertical sync output. Signal was from the MB14298.
VBLNK_OUTn : out std_logic; -- Vertical blanking output. Signal was from the MB14298.
MB_HBLNKn : in std_logic; -- Mainboard Horizontal Blanking from the Colour Card CN! connector.
MB_SYNCH : in std_logic; -- Mainboard Vertical sync from the Colour Card CN! connector.
MB_V_HBLNKn : in std_logic; -- Mainboard combined vertical/horizontal sync from the Colour Card CN! connector.
MB_VIDEO : in std_logic; -- Mainboard Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
MB_LOAD : in std_logic; -- Mainboard shift register load signal from the Colour Card CN! connector.
VRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
GTn : in std_logic; -- GATE signal from the Colour Card CN! connector.
CSn : in std_logic; -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
MEM_CSn : in std_logic; -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
VADDR : out std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address.
VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector..
VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals.
VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn : out std_logic; -- IORQn to FPGA.
VRDn : out std_logic; -- RDn to FPGA.
VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn : out std_logic; -- Video Gate (GTn)
VWRn : out std_logic; -- WRn to FPGA.
VRESETn : out std_logic; -- Reset to FPGA.
--
VSRVIDEO_OUT : in std_logic; -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn : in std_logic; -- Horizontal blanking.
VHSY_OUT : in std_logic; -- Horizontal Sync.
VSYNCH_OUT : in std_logic; -- Veritcal Sync.
VVBLNK_OUTn : in std_logic; -- Vertical blanking.
-- Reserved.
TBA : in std_logic_vector(9 downto 0) -- Reserved signals.
-- JTAG / ISP
--TCK : in std_logic;
--TDI : in std_logic;
--TDO : out std_logic;
--TMS : in std_logic
);
end entity;
architecture rtl of VideoInterface is
-- Clock generation wires.
signal CLK2Mi : std_logic; -- 2MHz used for the CPU main frequency.
signal CLK1Mi : std_logic; -- 1MHz used for video timing.
signal CLK31500i : std_logic; -- 8253 Clock base frequency used for RTC,
function to_std_logic(L: boolean) return std_logic is
begin
if L then
return('1');
else
return('0');
end if;
end function to_std_logic;
begin
--
-- Instantiation
--
-- Voltage translation. The FPGA is max 3.3v tolerant (as are nearly all FPGA's) so the 5V signals from the mainboard would have to go through a diode clamp
-- or converter. Given the pricing of the MAX7000 series chips it is easier and cheaper to use a CPLD to perform the voltage translation as they are 5V tolerant
-- and the mainboard accepts 3.3V output voltages.
--
VADDR <= A;
VRESETn <= RESETn;
VIORQn <= IORQn;
VRDn <= RDn;
VWRn <= WRn;
VGTn <= GTn;
VCSn <= CSn;
VMEM_CSn <= MEM_CSn;
VVRAM_CS_INn <= VRAM_CS_INn;
-- Data bus is muxed between the Z80 data bus and VRAMD which is the gated data bus after the video buffers.
VDATA <= VRAMD when WRn = '0' and VRAM_CS_INn = '0'
else
D when WRn = '0' and VRAM_CS_INn = '1'
else (others => 'Z');
D <= VRAMD when RDn = '0' and VRAM_CS_INn = '0'
else
VDATA when RDn = '0' and VRAM_CS_INn = '1'
else (others => 'Z');
VRAMD <= VDATA when RDn = '0' and VRAM_CS_INn = '0'
else (others => 'Z');
SRVIDEO_OUT <= '1';
HBLNK_OUTn <= '1';
HSY_OUT <= '1';
SYNCH_OUT <= '1';
VBLNK_OUTn <= '1';
-- Process to subdivide the video clock into the frequencies required by the main board.
-- This logic was originally performed by the MB14298 Gate Array on the mainboard.
--
process(RESETn, VID_CLK, CLK2Mi, CLK1Mi, CLK31500i)
variable counter2Mi : unsigned(4 downto 0); -- Binary divider to create 2Mi clock.
variable counter1Mi : unsigned(5 downto 0); -- Binary divider to create 1Mi clock.
variable counter31500i : unsigned(10 downto 0); -- Binary divider to create 31500i clock.
begin
if RESETn = '0' then
counter2Mi := (others => '0');
counter1Mi := (others => '0');
counter31500i := (others => '0');
CLK2Mi <= '0';
CLK1Mi <= '0';
CLK31500i <= '0';
elsif rising_edge(VID_CLK) then
-- 2000000Hz
if counter2Mi = 0 or counter2Mi = 8 then
CLK2Mi <= not CLK2Mi;
if counter2Mi = 8 then
counter2Mi := (others => '0');
else
counter2Mi := counter2Mi + 1;
end if;
else
counter2Mi := counter2Mi + 1;
end if;
-- 1000000Hz
if counter1Mi = 0 or counter1Mi = 8 then
CLK1Mi <= not CLK1Mi;
if counter1Mi = 8 then
counter1Mi := (others => '0');
else
counter1Mi := counter1Mi + 1;
end if;
else
counter1Mi := counter1Mi + 1;
end if;
-- 31500Hz
if counter31500i = 0 or counter31500i = 255 then
CLK31500i <= not CLK31500i;
if counter31500i = 255 then
counter31500i := (others => '0');
else
counter31500i := counter31500i + 1;
end if;
else
counter31500i := counter31500i + 1;
end if;
end if;
CLK_31_5K_OUT <= CLK31500i;
CLK_1MHZ_OUT <= CLK1Mi;
CLK_2MHZ_OUT <= CLK2Mi;
end process;
end architecture;

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---------------------------------------------------------------------------------------------------------
--
-- Name: VideoInterface_Toplevel.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: MZ80A Video Module CPLD Top Level module.
--
-- This module contains the basic pin definition of the CPLD<->logic<-->FPGA needed in
-- the project.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.VideoInterface_pkg.all;
library altera;
use altera.altera_syn_attributes.all;
entity VideoInterfaceCPLD is
port (
-- Primary video clock.
VID_CLK : in std_logic; -- 16MHz base clock for video timing and gate clocking.
-- Z80 Address and Data. Address is muxed with video addressing, not direct.
A : in std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
D : inout std_logic_vector(7 downto 0); -- Z80 Data bus, from the Colour Card CN! connector.
-- Z80 Control signals.
WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector.
RDn : in std_logic; -- Z80 Read signal from the Colour Card CN! connector.
RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board.
IORQn : in std_logic; -- Z80 IORQ signal from the tranZPUter board.
-- Video and Mainboard signals.
SRVIDEO_OUT : out std_logic; -- Shift Register 74LS165 Video Output onto mainboard.
CLK_31_5K_OUT : out std_logic; -- 31.5KHz time base for the 8253 on mainboard. Signal was from the MB14298.
CLK_1MHZ_OUT : out std_logic; -- 1MHZ video timing clock output to mainboard. Signal was from the MB14298.
CLK_2MHZ_OUT : out std_logic; -- 2MHZ main CPU clock output to mainboard. Signal was from the MB14298.
HBLNK_OUTn : out std_logic; -- Horizontal Blanking output. Signal was from the MB14298.
HSY_OUT : out std_logic; -- Horizontal sync output. Signal was from the MB14298.
SYNCH_OUT : out std_logic; -- Vertical sync output. Signal was from the MB14298.
VBLNK_OUTn : out std_logic; -- Vertical blanking output. Signal was from the MB14298.
MB_HBLNKn : in std_logic; -- Mainboard Horizontal Blanking from the Colour Card CN! connector.
MB_SYNCH : in std_logic; -- Mainboard Vertical sync from the Colour Card CN! connector.
MB_V_HBLNKn : in std_logic; -- Mainboard combined vertical/horizontal sync from the Colour Card CN! connector.
MB_VIDEO : in std_logic; -- Mainboard Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
MB_LOAD : in std_logic; -- Mainboard shift register load signal from the Colour Card CN! connector.
VRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
GTn : in std_logic; -- GATE signal from the Colour Card CN! connector.
CSn : in std_logic; -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
MEM_CSn : in std_logic; -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
VADDR : out std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address.
VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector..
VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals.
VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn : out std_logic; -- IORQn to FPGA.
VRDn : out std_logic; -- RDn to FPGA.
VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn : out std_logic; -- Video Gate (GTn)
VWRn : out std_logic; -- WRn to FPGA.
VRESETn : out std_logic; -- Reset to FPGA.
--
VSRVIDEO_OUT : in std_logic; -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn : in std_logic; -- Horizontal blanking.
VHSY_OUT : in std_logic; -- Horizontal Sync.
VSYNCH_OUT : in std_logic; -- Veritcal Sync.
VVBLNK_OUTn : in std_logic; -- Vertical blanking.
-- Reserved.
TBA : in std_logic_vector(9 downto 0) -- Reserved signals.
-- JTAG / ISP
--TCK : in std_logic;
--TDI : in std_logic;
--TDO : out std_logic;
--TMS : in std_logic
);
END entity;
architecture rtl of VideoInterfaceCPLD is
begin
myVirtualToplevel : entity work.VideoInterface
--generic map
--(
--)
port map
(
-- Primary video clock.
VID_CLK => VID_CLK, -- 16MHz base clock for video timing and gate clocking.
-- Z80 Address and Data. Address is muxed with video addressing, not direct.
A => A, -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
D => D, -- Z80 Data bus, from the Colour Card CN! connector.
-- Z80 Control signals.
WRn => WRn, -- Z80 Write signal from the Colour Card CN! connector.
RDn => RDn, -- Z80 Read signal from the Colour Card CN! connector.
RESETn => RESETn, -- Z80 RESET signal from the tranZPUter board.
IORQn => IORQn, -- Z80 IORQ signal from the tranZPUter board.
-- Video and Mainboard signals.
SRVIDEO_OUT => SRVIDEO_OUT, -- Shift Register 74LS165 Video Output onto mainboard.
CLK_31_5K_OUT => CLK_31_5K_OUT, -- 31.5KHz time base for the 8253 on mainboard. Signal was from the MB14298.
CLK_1MHZ_OUT => CLK_1MHZ_OUT, -- 1MHZ video timing clock output to mainboard. Signal was from the MB14298.
CLK_2MHZ_OUT => CLK_2MHZ_OUT, -- 2MHZ main CPU clock output to mainboard. Signal was from the MB14298.
HBLNK_OUTn => HBLNK_OUTn, -- Horizontal Blanking output. Signal was from the MB14298.
HSY_OUT => HSY_OUT, -- Horizontal sync output. Signal was from the MB14298.
SYNCH_OUT => SYNCH_OUT, -- Vertical sync output. Signal was from the MB14298.
VBLNK_OUTn => VBLNK_OUTn, -- Vertical blanking output. Signal was from the MB14298.
MB_HBLNKn => MB_HBLNKn, -- Mainboard Horizontal Blanking from the Colour Card CN! connector.
MB_SYNCH => MB_SYNCH, -- Mainboard Vertical sync from the Colour Card CN! connector.
MB_V_HBLNKn => MB_V_HBLNKn, -- Mainboard combined vertical/horizontal sync from the Colour Card CN! connector.
MB_VIDEO => MB_VIDEO, -- Mainboard Video (74LS165 output combined with GATE) from the Colour Card CN! connector.
MB_LOAD => MB_LOAD, -- Mainboard shift register load signal from the Colour Card CN! connector.
VRAM_CS_INn => VRAM_CS_INn, -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
GTn => GTn, -- GATE signal from the Colour Card CN! connector.
CSn => CSn, -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
MEM_CSn => MEM_CSn, -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
VADDR => VADDR, -- Z80 Address bus, multiplexed with video address.
VDATA => VDATA, -- Z80 Data bus from mainboard Colour Card CD connector..
VRAMD => VRAMD, -- Z80 Data bus from the VRAM chip, gated according to state signals.
VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA.
VVRAM_CS_INn => VVRAM_CS_INn, -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn => VIORQn, -- IORQn to FPGA.
VRDn => VRDn, -- RDn to FPGA.
VCSn => VCSn, -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn => VGTn, -- Video Gate (GTn)
VWRn => VWRn, -- WRn to FPGA.
VRESETn => VRESETn, -- Reset to FPGA.
VSRVIDEO_OUT => VSRVIDEO_OUT, -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn => VHBLNK_OUTn, -- Horizontal blanking.
VHSY_OUT => VHSY_OUT, -- Horizontal Sync.
VSYNCH_OUT => VSYNCH_OUT, -- Veritcal Sync.
VVBLNK_OUTn => VVBLNK_OUTn, -- Vertical blanking.
-- Reserved.
TBA => TBA -- Reserved signals.
);
end architecture;

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---------------------------------------------------------------------------------------------------------
--
-- Name: VideoInterface_pkg.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ80A Video Module v2.0 CPLD configuration file.
--
-- This module contains parameters for the CPLD in v2.0 of the Sharp MZ80A Video Module
-- project.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package VideoInterface_pkg is
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
end VideoInterface_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body VideoInterface_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then
return 0;
end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer is
variable ticks : real;
variable fracTicks : real;
begin
ticks := (Real(period) * Real(clock)) / 1000000000.0;
fracTicks := ticks - CEIL(ticks);
if fracTicks > 0.0001 then
return Integer(CEIL(ticks + 1.0));
else
return Integer(CEIL(ticks));
end if;
end function;
end package body;

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "16:29:32 June 24, 2020"
# Revisions
PROJECT_REVISION = "VideoInterface"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# tranZPUterSW_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000AE
set_global_assignment -name DEVICE "EPM7512AETC144-7"
set_global_assignment -name TOP_LEVEL_ENTITY VideoInterfaceCPLD
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
# Global clocks.
# ==============
set_location_assignment PIN_125 -to VID_CLK
# Z80 Address Bus
# ===============
set_location_assignment PIN_87 -to A[13]
set_location_assignment PIN_88 -to A[12]
set_location_assignment PIN_90 -to A[11]
set_location_assignment PIN_111 -to A[10]
set_location_assignment PIN_112 -to A[9]
set_location_assignment PIN_113 -to A[8]
set_location_assignment PIN_114 -to A[7]
set_location_assignment PIN_116 -to A[6]
set_location_assignment PIN_117 -to A[5]
set_location_assignment PIN_118 -to A[4]
set_location_assignment PIN_119 -to A[3]
set_location_assignment PIN_120 -to A[2]
set_location_assignment PIN_121 -to A[1]
set_location_assignment PIN_122 -to A[0]
# Video Interface Address Bus
# ===========================
set_location_assignment PIN_42 -to VADDR[13]
set_location_assignment PIN_41 -to VADDR[12]
set_location_assignment PIN_40 -to VADDR[11]
set_location_assignment PIN_39 -to VADDR[10]
set_location_assignment PIN_38 -to VADDR[9]
set_location_assignment PIN_37 -to VADDR[8]
set_location_assignment PIN_36 -to VADDR[7]
set_location_assignment PIN_35 -to VADDR[6]
set_location_assignment PIN_34 -to VADDR[5]
set_location_assignment PIN_32 -to VADDR[4]
set_location_assignment PIN_31 -to VADDR[3]
set_location_assignment PIN_30 -to VADDR[2]
set_location_assignment PIN_29 -to VADDR[1]
set_location_assignment PIN_28 -to VADDR[0]
# Clock outputs.
# ==============
set_location_assignment PIN_7 -to CLK_1MHZ_OUT
set_location_assignment PIN_10 -to CLK_2MHZ_OUT
set_location_assignment PIN_9 -to CLK_31_5K_OUT
# Z80 control signals
# ===================
set_location_assignment PIN_92 -to CSn
set_location_assignment PIN_94 -to GTn
set_location_assignment PIN_83 -to IORQn
set_location_assignment PIN_82 -to MEM_CSn
set_location_assignment PIN_86 -to RESETn
set_location_assignment PIN_127 -to GCLRn
set_location_assignment PIN_91 -to RDn
set_location_assignment PIN_97 -to WRn
set_location_assignment PIN_12 -to VRAM_CS_INn
# Z80 Data Bus
# ============
set_location_assignment PIN_101 -to D[7]
set_location_assignment PIN_102 -to D[6]
set_location_assignment PIN_103 -to D[5]
set_location_assignment PIN_106 -to D[4]
set_location_assignment PIN_107 -to D[3]
set_location_assignment PIN_108 -to D[2]
set_location_assignment PIN_109 -to D[1]
set_location_assignment PIN_110 -to D[0]
# Video Data Bus
# ==============
set_location_assignment PIN_53 -to VDATA[7]
set_location_assignment PIN_54 -to VDATA[6]
set_location_assignment PIN_55 -to VDATA[5]
set_location_assignment PIN_56 -to VDATA[4]
set_location_assignment PIN_60 -to VDATA[3]
set_location_assignment PIN_61 -to VDATA[2]
set_location_assignment PIN_62 -to VDATA[1]
set_location_assignment PIN_63 -to VDATA[0]
# VRAM Data Bus
# =============
set_location_assignment PIN_18 -to VRAMD[7]
set_location_assignment PIN_19 -to VRAMD[6]
set_location_assignment PIN_21 -to VRAMD[5]
set_location_assignment PIN_22 -to VRAMD[4]
set_location_assignment PIN_23 -to VRAMD[3]
set_location_assignment PIN_16 -to VRAMD[2]
set_location_assignment PIN_14 -to VRAMD[1]
set_location_assignment PIN_15 -to VRAMD[0]
# Mainboard video signals on the CN1 connector.
# =============================================
set_location_assignment PIN_93 -to MB_HBLNKn
set_location_assignment PIN_100 -to MB_LOAD
set_location_assignment PIN_96 -to MB_SYNCH
set_location_assignment PIN_98 -to MB_V_HBLNKn
set_location_assignment PIN_99 -to MB_VIDEO
# Generated video signals.
# ========================
set_location_assignment PIN_1 -to HBLNK_OUTn
set_location_assignment PIN_2 -to HSY_OUT
set_location_assignment PIN_11 -to SRVIDEO_OUT
set_location_assignment PIN_8 -to SYNCH_OUT
set_location_assignment PIN_6 -to VBLNK_OUTn
# FPGA Generated video signals.
# =============================
set_location_assignment PIN_77 -to VHBLNK_OUTn
set_location_assignment PIN_80 -to VHSY_OUT
set_location_assignment PIN_84 -to VSRVIDEO_OUT
set_location_assignment PIN_79 -to VSYNCH_OUT
set_location_assignment PIN_78 -to VVBLNK_OUTn
# Video control signals.
# ======================
set_location_assignment PIN_46 -to VCSn
set_location_assignment PIN_47 -to VGTn
set_location_assignment PIN_44 -to VIORQn
set_location_assignment PIN_43 -to VMEM_CSn
set_location_assignment PIN_45 -to VRDn
set_location_assignment PIN_49 -to VRESETn
set_location_assignment PIN_27 -to VVRAM_CS_INn
set_location_assignment PIN_48 -to VWRn
# Reserved.
# =========
set_location_assignment PIN_75 -to TBA[9]
set_location_assignment PIN_74 -to TBA[8]
set_location_assignment PIN_72 -to TBA[7]
set_location_assignment PIN_71 -to TBA[6]
set_location_assignment PIN_70 -to TBA[5]
set_location_assignment PIN_69 -to TBA[4]
set_location_assignment PIN_68 -to TBA[3]
set_location_assignment PIN_67 -to TBA[2]
set_location_assignment PIN_66 -to TBA[1]
set_location_assignment PIN_65 -to TBA[0]
set_global_assignment -name VHDL_FILE ../VideoInterface_Toplevel.vhd
set_global_assignment -name VHDL_FILE ../VideoInterface_pkg.vhd
set_global_assignment -name VHDL_FILE ../VideoInterface.vhd
set_global_assignment -name SDC_FILE VideoInterface_constraints.sdc

5
CPLD/build/VideoInterface.srf Normal file
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{ "" "" "" "Found combinational loop of 2 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Macrocell buffer inserted after node \"Z80_BUSACKn\"" { } { } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 5 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}

107
CPLD/build/VideoInterface_constraints.sdc Normal file
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## Generated SDC file "cpld7512.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
## DATE "Wed Jul 1 12:17:36 2020"
##
## DEVICE "EPM7512AETC144-7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {VID_CLK} -period 62.500 -waveform { 0.000 31.250 } [get_ports { VID_CLK }]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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FPGA/VideoController.vhd Normal file
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FPGA/VideoController_Toplevel.vhd Normal file
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---------------------------------------------------------------------------------------------------------
--
-- Name: VideoController_Toplevel.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: MZ80A Video Module FPGA Top Level module.
--
-- This module contains the definition of the video controller used in v2.0 of the Sharp MZ80A
-- Video Module. The controller emulates the video logic of the Sharp MZ80A, MZ-700 and
-- MZ80B including pixel graphics.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.VideoController_pkg.all;
library altera;
use altera.altera_syn_attributes.all;
entity VideoControllerCPLD is
port (
-- Primary and video clocks.
CLOCK_50 : in std_logic; -- 50MHz main FPGA clock.
CLOCK_16 : in std_logic; -- 16MHz base clock for video timing and gate clocking.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Addres Bus
VADDR : in std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address.
-- Data Bus
VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector..
-- Control signals.
VMEM_CSn : in std_logic; -- Extended memory select to FPGA.
VVRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn : in std_logic; -- IORQn to FPGA.
VRDn : in std_logic; -- RDn to FPGA.
VCSn : in std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn : in std_logic; -- Video Gate (GTn)
VWRn : in std_logic; -- WRn to FPGA.
VRESETn : in std_logic; -- Reset to FPGA.
-- VGA signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
VGA_G : out std_logic_vector(3 downto 0); -- 16 level Green output.
VGA_B : out std_logic_vector(3 downto 0); -- 16 level Blue output.
VGA_HS : out std_logic; -- Horizontal sync.
VGA_VS : out std_logic; -- Vertical sync.
-- Composite signals.
CSYNCn : out std_logic; -- Composite sync negative polarity.
CSYNC : out std_logic; -- Comnposite sync.
VSRVIDEO_OUT : out std_logic; -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn : out std_logic; -- Horizontal blanking.
VHSY_OUT : out std_logic; -- Horizontal Sync.
VSYNCH_OUT : out std_logic; -- Veritcal Sync.
VVBLNK_OUTn : out std_logic; -- Vertical blanking.
-- Reserved.
TBA : in std_logic_vector(9 downto 0) -- Reserved signal paths to the CPLD.
-- JTAG / ISP
--TCK : in std_logic;
--TDI : in std_logic;
--TDO : out std_logic;
--TMS : in std_logic
);
END entity;
architecture rtl of VideoControllerCPLD is
signal SYS_CLK : std_logic;
signal PLL_LOCKED : std_logic;
begin
vcpll : entity work.Clock_50to100
port map
(
inclk0 => CLOCK_50,
c0 => SYS_CLK,
locked => PLL_LOCKED
);
vcToplevel : entity work.VideoController
--generic map
--(
--)
port map
(
-- Primary and video clocks.
SYS_CLK => SYS_CLK, -- 50MHz main FPGA clock.
VID_CLK => CLOCK_16, -- 16MHz base clock for video timing and gate clocking.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Addres Bus
VADDR => VADDR, -- Z80 Address bus, multiplexed with video address.
-- Data Bus
VDATA => VDATA, -- Z80 Data bus from mainboard Colour Card CD connector..
-- Control signals.
VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA.
VVRAM_CS_INn => VVRAM_CS_INn, -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn => VIORQn, -- IORQn to FPGA.
VRDn => VRDn, -- RDn to FPGA.
VCSn => VCSn, -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn => VGTn, -- Video Gate (GTn)
VWRn => VWRn, -- WRn to FPGA.
VRESETn => VRESETn, -- Reset to FPGA.
-- VGA signals.
VGA_R => VGA_R, -- 16 level Red output.
VGA_G => VGA_G, -- 16 level Green output.
VGA_B => VGA_B, -- 16 level Blue output.
VGA_HS => VGA_HS, -- Horizontal sync.
VGA_VS => VGA_VS, -- Vertical sync.
-- Composite signals.
CSYNCn => CSYNCn, -- Composite sync negative polarity.
CSYNC => CSYNC, -- Comnposite sync.
VSRVIDEO_OUT => VSRVIDEO_OUT, -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn => VHBLNK_OUTn, -- Horizontal blanking.
VHSY_OUT => VHSY_OUT, -- Horizontal Sync.
VSYNCH_OUT => VSYNCH_OUT, -- Veritcal Sync.
VVBLNK_OUTn => VVBLNK_OUTn, -- Vertical blanking.
-- Reserved.
TBA => TBA -- Reserved signals.
);
end architecture;

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FPGA/VideoController_pkg.vhd Normal file
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---------------------------------------------------------------------------------------------------------
--
-- Name: VideoController_pkg.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ80A Video Module v2.0 CPLD configuration file.
--
-- This module contains parameters for the CPLD in v2.0 of the Sharp MZ80A Video Module
-- project.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package VideoController_pkg is
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
end VideoController_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body VideoController_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then
return 0;
end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer is
variable ticks : real;
variable fracTicks : real;
begin
ticks := (Real(period) * Real(clock)) / 1000000000.0;
fracTicks := ticks - CEIL(ticks);
if fracTicks > 0.0001 then
return Integer(CEIL(ticks + 1.0));
else
return Integer(CEIL(ticks));
end if;
end function;
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
end package body;

25
FPGA/build/Clock_50to100.cmp Normal file
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--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Clock_50to100
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

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FPGA/build/Clock_50to100.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone II" variation_name="Clock_50to100" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

5
FPGA/build/Clock_50to100.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_50to100.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.ppf"]

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FPGA/build/Clock_50to100.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clock_50to100.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Clock_50to100 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clock_50to100;
ARCHITECTURE SYN OF clock_50to100 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0 ps",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

30
FPGA/build/VideoController.qpf Normal file
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@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "16:29:32 June 24, 2020"
# Revisions
PROJECT_REVISION = "VideoController"

266
FPGA/build/VideoController.qsf Normal file
View File

@@ -0,0 +1,266 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# tranZPUterSW_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY VideoControllerCPLD
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
# Clocks.
# =======
set_location_assignment PIN_22 -to CLOCK_50
set_location_assignment PIN_23 -to CLOCK_16
# Video Interface Address Bus
# ===========================
set_location_assignment PIN_120 -to VADDR[13]
set_location_assignment PIN_121 -to VADDR[12]
set_location_assignment PIN_125 -to VADDR[11]
set_location_assignment PIN_132 -to VADDR[10]
set_location_assignment PIN_133 -to VADDR[9]
set_location_assignment PIN_135 -to VADDR[8]
set_location_assignment PIN_136 -to VADDR[7]
set_location_assignment PIN_137 -to VADDR[6]
set_location_assignment PIN_141 -to VADDR[5]
set_location_assignment PIN_142 -to VADDR[4]
set_location_assignment PIN_143 -to VADDR[3]
set_location_assignment PIN_144 -to VADDR[2]
set_location_assignment PIN_7 -to VADDR[1]
set_location_assignment PIN_4 -to VADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[0]
# Video Data Bus
# ==============
set_location_assignment PIN_106 -to VDATA[7]
set_location_assignment PIN_105 -to VDATA[6]
set_location_assignment PIN_104 -to VDATA[5]
set_location_assignment PIN_103 -to VDATA[4]
set_location_assignment PIN_101 -to VDATA[3]
set_location_assignment PIN_100 -to VDATA[2]
set_location_assignment PIN_99 -to VDATA[1]
set_location_assignment PIN_98 -to VDATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[0]
# Video control signals.
# ======================
set_location_assignment PIN_113 -to VCSn
set_location_assignment PIN_112 -to VGTn
set_location_assignment PIN_115 -to VIORQn
set_location_assignment PIN_119 -to VMEM_CSn
set_location_assignment PIN_114 -to VRDn
set_location_assignment PIN_110 -to VRESETn
set_location_assignment PIN_28 -to VVRAM_CS_INn
set_location_assignment PIN_111 -to VWRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCSn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMEM_CSn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRESETn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVRAM_CS_INn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWRn
# VGA/RGB signals.
# ================
set_location_assignment PIN_46 -to VGA_R[0]
set_location_assignment PIN_49 -to VGA_R[1]
set_location_assignment PIN_50 -to VGA_R[2]
set_location_assignment PIN_51 -to VGA_R[3]
set_location_assignment PIN_39 -to VGA_G[0]
set_location_assignment PIN_42 -to VGA_G[1]
set_location_assignment PIN_43 -to VGA_G[2]
set_location_assignment PIN_44 -to VGA_G[3]
set_location_assignment PIN_30 -to VGA_B[0]
set_location_assignment PIN_31 -to VGA_B[1]
set_location_assignment PIN_32 -to VGA_B[2]
set_location_assignment PIN_33 -to VGA_B[3]
set_location_assignment PIN_59 -to VGA_HS
set_location_assignment PIN_58 -to VGA_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
# Composite video signals.
# ========================
set_location_assignment PIN_64 -to CSYNCn
set_location_assignment PIN_60 -to CSYNC
set_location_assignment PIN_65 -to VSRVIDEO_OUT
set_location_assignment PIN_66 -to VHBLNK_OUTn
set_location_assignment PIN_67 -to VHSY_OUT
set_location_assignment PIN_68 -to VSYNCH_OUT
set_location_assignment PIN_69 -to VVBLNK_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VSRVIDEO_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VHBLNK_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VHSY_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VSYNCH_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVBLNK_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNCn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSRVIDEO_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VHBLNK_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VHSY_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNCH_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VVBLNK_OUTn
# Reserved.
# =========
set_location_assignment PIN_71 -to TBA[9]
set_location_assignment PIN_72 -to TBA[8]
set_location_assignment PIN_76 -to TBA[7]
set_location_assignment PIN_77 -to TBA[6]
set_location_assignment PIN_79 -to TBA[5]
set_location_assignment PIN_80 -to TBA[4]
set_location_assignment PIN_83 -to TBA[3]
set_location_assignment PIN_85 -to TBA[2]
set_location_assignment PIN_86 -to TBA[1]
set_location_assignment PIN_87 -to TBA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[0]
# Files in project.
# =================
set_global_assignment -name VHDL_FILE ../VideoController_Toplevel.vhd
set_global_assignment -name QIP_FILE Clock_50to100.qip
set_global_assignment -name VHDL_FILE ../VideoController_pkg.vhd
set_global_assignment -name VHDL_FILE ../VideoController.vhd
set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
set_global_assignment -name SDC_FILE VideoController_constraints.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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FPGA/build/VideoController_constraints.sdc Normal file
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## Generated SDC file "VideoController.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports { CLOCK_50 }]
create_clock -name {CLOCK_16} -period 62.500 -waveform { 0.000 31.250 } [get_ports {CLOCK_16}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {vcpll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {vcpll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLOCK_50} [get_pins {vcpll|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_16}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_16}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_16}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_16}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_16}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_16}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_16}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {vcpll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_16}] -hold 0.080
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************