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New video module developments

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This commit is contained in:
Philip Smart
2020-11-02 01:19:20 +00:00
parent ba31018942
commit 82a4166db1
23 changed files with 4191 additions and 800 deletions
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.gitignore vendored
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@@ -62,3 +62,4 @@ CPLD/VideoInterface.vhd.16mhz
CPLD/VideoInterface_Toplevel.vhd.16mhz
FPGA/build/core
FPGA/vidsav
CPLD/build/VideoInterface.qws

420
CPLD/VideoInterface.vhd
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@@ -45,14 +45,13 @@ entity VideoInterface is
CLOCK_50 : in std_logic; -- 50Hz base clock for system board, video timing and gate clocking.
-- Z80 Address and Data. Address is muxed with video addressing, not direct.
-- A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
D : inout std_logic_vector(7 downto 0); -- Z80 Data bus, from the Colour Card CN! connector.
-- Z80 Control signals.
-- WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector.
WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector.
RDn : in std_logic; -- Z80 Read signal from the Colour Card CN! connector.
RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board.
-- IORQn : in std_logic; -- Z80 IORQ signal from the tranZPUter board.
-- Video and Mainboard signals.
SRVIDEO_OUT : out std_logic; -- Shift Register 74LS165 Video Output onto mainboard.
@@ -71,21 +70,20 @@ entity VideoInterface is
VRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
GTn : in std_logic; -- GATE signal from the Colour Card CN! connector.
CSn : in std_logic; -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
-- MEM_CSn : in std_logic; -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board.
OUTCLK : out std_logic; -- CPU signal serialiser clock.
INDATA : in std_logic_vector(3 downto 0); -- Incoming serialised CPU signals.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
VADDR : out std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address.
VADDR : out std_logic_vector(15 downto 0); -- Z80 Address bus, multiplexed with video address.
VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector..
VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals.
VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
--VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn : out std_logic; -- IORQn to FPGA.
VRDn : out std_logic; -- RDn to FPGA.
VZ80_IORQn : out std_logic; -- IORQn to FPGA.
VZ80_RDn : out std_logic; -- Z80_RDn from tranZPUter to FPGA.
VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn : out std_logic; -- Video Gate (GTn)
VWRn : out std_logic; -- WRn to FPGA.
VZ80_WRn : out std_logic; -- WRn to FPGA.
--
VSRVIDEO_OUT : in std_logic; -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn : in std_logic; -- Horizontal blanking.
@@ -118,21 +116,53 @@ architecture rtl of VideoInterface is
signal CLK31500i : std_logic; -- 8253 Clock base frequency used for RTC,
signal ENASERCLK : std_logic; -- Enable serializer clock.
signal IORQn : std_logic;
signal MEM_CSn : std_logic;
signal S_IORQn : std_logic; -- Serialiser signal - IORQn
signal S_VIDEO_RDn : std_logic; -- Serialiser signal - Video FPGA RDn
signal S_VIDEO_WRn : std_logic; -- Serialiser signal - Video FPGA WRn
signal INBUF : std_logic_vector(11 downto 0);
signal RCV_CYCLE : integer range 0 to 1;
signal INCOUNT : integer range 0 to 3;
signal VA : std_logic_vector(14 downto 0);
signal CS_LAST_LEVEL : std_logic_vector(1 downto 0); -- Register to store the previous chip select level for edge detection.
signal CS_IO_FXX_n : std_logic; -- Chip select for block F0:FF
signal CS_CPLD_CTRL_n : std_logic; -- Chip select for the CPLD Control Register at 0xF0
signal VA : std_logic_vector(15 downto 0);
signal MODE_MZ80A : std_logic := '1'; -- The System board is running in MZ80A mode.
signal MODE_MZ700 : std_logic := '0'; -- The System board is running in MZ700 mode.
signal MODE_MZ80B : std_logic := '0'; -- The System board is running in MZ80B mode.
signal MODE_CUSTOM : std_logic := '0'; -- The System board is running in custom mode.
signal CPLD_CTRL_REG : std_logic_vector(7 downto 0); -- Current value of the CPLD control register.
-- CPLD configuration signals.
signal MODE_CPLD_MZ80K : std_logic;
signal MODE_CPLD_MZ80C : std_logic;
signal MODE_CPLD_MZ1200 : std_logic;
signal MODE_CPLD_MZ80A : std_logic;
signal MODE_CPLD_MZ700 : std_logic;
signal MODE_CPLD_MZ800 : std_logic;
signal MODE_CPLD_MZ80B : std_logic;
signal MODE_CPLD_MZ2000 : std_logic;
signal MODE_CPLD_SWITCH : std_logic;
signal MODE_CPLD_MB_VIDEOn : std_logic; -- Mainboard video, 0 = enabled, 1 = disabled.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register.
-- IO Decode signals.
signal CS_IO_6XXn : std_logic; -- IO decode for the 0x60-0x6f region used by the CPLD.
signal CS_IO_EXXn : std_logic; -- Chip select for block E0:EF
signal CS_IO_FXXn : std_logic; -- Chip select for block F0:FF
signal CS_CPLD_CFGn : std_logic; -- Select to set the CPLD configuration register.
signal CS_FB_VMn : std_logic; -- Chip Select for the Video Mode register.
signal CS_FB_PAGEn : std_logic; -- Chip Select for the Page select register.
signal CS_80B_PIOn : std_logic; -- Chip select for MZ80B PIO when in MZ80B mode.
signal CS_LAST_LEVEL : std_logic_vector(4 downto 0); -- Register to store the previous chip select level for edge detection.
signal CS_DXXXn : std_logic; -- Chip select range for the VRAM/ARAM.
signal CS_EXXXn : std_logic; -- Chip select range for the memory mapped I/O.
signal CS_DVRAMn : std_logic; -- Chip select for the Video RAM.
signal CS_DARAMn : std_logic; -- Chip select for the Attribute RAM.
-- Video module signal mirrors.
signal MODE_VIDEO_MZ80A : std_logic := '1'; -- The machine is running in MZ80A mode.
signal MODE_VIDEO_MZ700 : std_logic := '0'; -- The machine is running in MZ700 mode.
signal MODE_VIDEO_MZ800 : std_logic := '0'; -- The machine is running in MZ800 mode.
signal MODE_VIDEO_MZ80B : std_logic := '0'; -- The machine is running in MZ80B mode.
signal MODE_VIDEO_MZ80K : std_logic := '0'; -- The machine is running in MZ80K mode.
signal MODE_VIDEO_MZ80C : std_logic := '0'; -- The machine is running in MZ80C mode.
signal MODE_VIDEO_MZ1200 : std_logic := '0'; -- The machine is running in MZ1200 mode.
signal MODE_VIDEO_MZ2000 : std_logic := '0'; -- The machine is running in MZ2000 mode.
signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable.
signal GRAM_MZ80B_ENABLE : std_logic; -- MZ80B Graphics memory enabled flag.
signal MZ80B_VRAM_HI_ADDR : std_logic; -- Video RAM located at D000:FFFF when high.
signal MZ80B_VRAM_LO_ADDR : std_logic; -- Video RAM located at 5000:7FFF when high.
function to_std_logic(L: boolean) return std_logic is
begin
@@ -144,108 +174,64 @@ architecture rtl of VideoInterface is
end function to_std_logic;
begin
--
-- Instantiation
--
-- Voltage translation. The FPGA is max 3.3v tolerant (as are nearly all FPGA's) so the 5V signals from the mainboard would have to go through a diode clamp
-- or converter. Given the pricing of the MAX7000 series chips it is easier and cheaper to use a CPLD to perform the voltage translation as they are 5V tolerant
-- and the mainboard accepts 3.3V output voltages.
--
VADDR <= VA(13 downto 0);
-- Data bus is muxed between the Z80 data bus and VRAMD which is the gated data bus after the video buffers.
-- The write signal WRn from the motherboard is actually a gated Write for the Video and Attribute RAM. The logic has been updated in the tranZPUter to
-- combine MEM_CSn with Z80 RD/WR such that use of RDn = 0 for read and RDn = 1 for write works as intended for all memory/IO operations.
--
VDATA <= D when RDn = '1' and MEM_CSn = '0' -- All memory write data sent to FPGA in region D000:FFFF
else
D when RDn = '1' and IORQn = '0' -- All I/O write data sent to FPGA.
else
(others => 'Z');
D <= VDATA when RDn = '0' and MEM_CSn = '0' and VA(13 downto 11) = "011" -- D800:DFFF via data bus.
else
VDATA when RDn = '0' and IORQn = '0' and ((VA(7 downto 4) = "1111" and VA(3 downto 0) > 3 and VA(3 downto 0) < 14) or VA(7 downto 5) = "000") -- I/O region F4:FD or 00:1F
else
CPLD_CTRL_REG when CS_CPLD_CTRL_n = '0' and RDn = '0' -- CPLD Control register at 0xF0
else
(others => 'Z');
VRAMD <= VDATA when RDn = '0' and MEM_CSn = '0' and VA(13 downto 11) = "010" -- D000:D7FF via IC16 74LS245.
else
(others => 'Z');
VIORQn <= IORQn;
VRDn <= RDn;
VWRn <= '0' when RDn = '1' and (MEM_CSn = '0' or IORQn = '0')
else '1';
VGTn <= GTn;
VCSn <= CSn;
VMEM_CSn <= MEM_CSn;
VVRAM_CS_INn <= VRAM_CS_INn;
--
-- CPU / RAM signals and selects.
--
CS_IO_FXX_n <= '0' when IORQn = '0' and VA(7 downto 4) = "1111"
else '1';
-- CPLD Control Register, 0xF0
CS_CPLD_CTRL_n <= '0' when CS_IO_FXX_n = '0' and VA(3 downto 0) = "0000"
else '1';
-- A tranZPUter signal serializer. Signals required by the Video Module but not accessible physically (without hardware hacks) are captured and serialised by the tranZPUter
-- as a set of 4 x 4 blocks, clocked by the video interace CPLD, As the mainboard can not run faster than 4MHz, a 24MHz serialiser clock should be sufficient to bring the
-- as a set of x 4 blocks, clocked by the video interace CPLD, As the mainboard can not run faster than 4MHz, a 24MHz serialiser clock should be sufficient to bring the
-- signals across but can be increased as necessary.
-- Reset synchronises the Video Module CPLD with the tranZPUter CPLD and the signals are sent during valid mainboard accesses. During tranZPUter accesses, both
-- IORQn and MEM_CSn are sent as 0, an invalid state, to indicate the signals are not valid.
-- S_VIDEO_RDn and S_VIDEO_WRn are sent as 0, an invalid state, to indicate the signals are not valid.
--
SIGNALSERIALIZER: process(RESETn, CLK24Mi, ENASERCLK)
SIGNALSERIALIZER: process(RESETn, CLK16Mi, ENASERCLK)
variable RCV_CYCLE : integer range 0 to 1;
begin
-- Each reset the FPGA and CPLD are in sync, set the signals to the starting level ready to commence serialization.
if RESETn = '0' then
ENASERCLK <= '0';
RCV_CYCLE <= 0;
INCOUNT <= 3;
RCV_CYCLE := 0;
INCOUNT <= 1;
INBUF <= "000000000000";
VA <= (others => '0');
IORQn <= '1';
MEM_CSn <= '1';
VA(15 downto 11) <= (others => '0');
S_IORQn <= '1';
S_VIDEO_RDn <= '1';
S_VIDEO_WRn <= '1';
elsif falling_edge(CLK24Mi) then
elsif falling_edge(CLK16Mi) then
case RCV_CYCLE is
-- Cycle starts by enabling the clock which the tranZPUter sees the rising edge and captures the 16 signals and places the
-- first block of 4 onto the mux-bus.
when 0 =>
ENASERCLK <= '1';
RCV_CYCLE <= 1;
RCV_CYCLE := 1;
-- Each clock period, a block of signals are placed on the bus with sufficient time for the signals to settle and to capture them.
when 1 =>
if INCOUNT > 0 then
INBUF(7 downto 0) <= INBUF(11 downto 4);
INBUF(11 downto 8) <= INDATA;
INBUF(3 downto 0) <= INDATA; --INBUF(7 downto 4);
--INBUF(7 downto 4) <= INDATA;
INCOUNT <= INCOUNT - 1;
else
-- If MEM_CSn and IORQn are both zero it indicates an invalid data set so dont act on it.
-- If S_VIDEO_WRn and S_VIDEO_RDn are both zero it indicates an invalid data set so dont act on it.
--
if INDATA(3 downto 2) /= "00" then
VA(13 downto 0) <= INDATA(1 downto 0) & INBUF(11 downto 0);
MEM_CSn <= INDATA(2);
IORQn <= INDATA(3);
if INDATA(3 downto 1) /= "000" then
VA(15 downto 11) <= INDATA(0) & INBUF(3 downto 0);
S_VIDEO_RDn <= INDATA(1);
S_VIDEO_WRn <= INDATA(2);
S_IORQn <= INDATA(3);
else
VA(13 downto 0) <= (others => '0');
MEM_CSn <= '1';
IORQn <= '1';
VA(15 downto 11) <= (others => '0');
S_VIDEO_RDn <= '1';
S_VIDEO_WRn <= '1';
S_IORQn <= '1';
end if;
INCOUNT <= 3;
INCOUNT <= 1;
end if;
RCV_CYCLE <= 1;
RCV_CYCLE := 1;
end case;
end if;
-- Enable the clock directly onto the bus clock line when data required.
if ENASERCLK = '1' then
OUTCLK <= CLK24Mi;
OUTCLK <= CLK16Mi;
else
OUTCLK <= '0';
end if;
@@ -311,7 +297,7 @@ begin
-- The 48MHz clock is used to create the base system clocks, 16MHz being the original machine base clock along with 4, 2 and 1MHz.
-- This logic was originally performed by the MB14298 Gate Array on the mainboard.
--
SYSCLOCKS: process(RESETn, CLOCK_48, CLK24Mi, CLK4_8Mi, CLK4Mi, CLK3_54Mi, CLK2Mi, CLK1Mi, CLK31500i, MODE_MZ80A, MODE_MZ80B, MODE_MZ700, MODE_CUSTOM)
SYSCLOCKS: process(RESETn, CLOCK_48, CLK24Mi, CLK4_8Mi, CLK4Mi, CLK3_54Mi, CLK2Mi, CLK1Mi, CLK31500i, CPLD_CFG_DATA)
variable counter24Mi : unsigned(1 downto 0); -- Binary divider to create 24Mi clock.
variable counter16Mi : unsigned(1 downto 0); -- Binary divider to create 16Mi clock.
variable counter4_8Mi : unsigned(2 downto 0); -- Binary divider to create 4_8Mi clock.
@@ -397,17 +383,22 @@ begin
--
CLK_31_5K_OUT <= CLK31500i;
CLK_1MHZ_OUT <= CLK1Mi;
if MODE_MZ80A = '1' then
CLK_2MHZ_OUT <= CLK2Mi;
elsif MODE_MZ80B = '1' then
CLK_2MHZ_OUT <= CLK4Mi;
elsif MODE_MZ700 = '1' then
CLK_2MHZ_OUT <= CLK3_54Mi;
elsif MODE_CUSTOM = '1' then
CLK_2MHZ_OUT <= CLK4_8Mi;
else -- Additional modes go here.
CLK_2MHZ_OUT <= CLK2Mi;
end if;
case to_integer(unsigned(CPLD_CFG_DATA(6 downto 4))) is
when MODE_FREQ_MZ80A =>
CLK_2MHZ_OUT <= CLK2Mi;
when MODE_FREQ_MZ80B =>
CLK_2MHZ_OUT <= CLK4Mi;
when MODE_FREQ_MZ700 =>
CLK_2MHZ_OUT <= CLK3_54Mi;
when MODE_FREQ_CUSTOM =>
CLK_2MHZ_OUT <= CLK4_8Mi;
when others =>
CLK_2MHZ_OUT <= CLK2Mi;
end case;
end process;
-- Process to subdivide the main 50MHz clock to obtain the MZ700 frequencies.
@@ -432,54 +423,205 @@ begin
end if;
end process;
-- Control Registers.
-- Control Registers - This mirrors the Video Module control registers as we need to know when video memory is to be mapped into main memory.
--
-- I/O Port:
-- 0xF0 - [2;0] = Mainboard/CPU clock.
-- 000 = Sharp MZ80A 2MHz System Clock.
-- 001 = Sharp MZ80B 4MHz System Clock.
-- 010 = Sharp MZ700 3.54MHz System Clock.
-- 011 -111 = Reserved, defaults to 2MHz System Clock.
CTRLREGISTERS: process(RESETn, CLK16Mi)
-- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF8->.
-- 0xF8=<val> sets the mode that of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000.
-- 0xFD=<val> memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue.
--
CTRLREGISTERS: process( RESETn, CLK16Mi, GRAM_PAGE_ENABLE, MZ80B_VRAM_HI_ADDR, MZ80B_VRAM_LO_ADDR )
begin
-- Ensure default values at reset.
if RESETn = '0' then
MODE_MZ80A <= '1';
MODE_MZ80B <= '0';
MODE_MZ700 <= '0';
MODE_CUSTOM <= '0';
CPLD_CTRL_REG <= "00000000";
MODE_VIDEO_MZ80A <= '0';
MODE_VIDEO_MZ700 <= '1';
MODE_VIDEO_MZ800 <= '0';
MODE_VIDEO_MZ80B <= '0';
MODE_VIDEO_MZ80K <= '0';
MODE_VIDEO_MZ80C <= '0';
MODE_VIDEO_MZ1200 <= '0';
MODE_VIDEO_MZ2000 <= '0';
GRAM_PAGE_ENABLE <= "00";
MZ80B_VRAM_HI_ADDR <= '0';
MZ80B_VRAM_LO_ADDR <= '0';
MODE_CPLD_SWITCH <= '0';
CPLD_CFG_DATA <= "00000011";
elsif rising_edge(CLK16Mi) then
-- Write to the CPLD Control Register?
if CS_CPLD_CTRL_n = '0' and CS_LAST_LEVEL(0) = '1' and RDn = '1' then
CPLD_CTRL_REG <= D;
MODE_MZ80A <= '0';
MODE_MZ80B <= '0';
MODE_MZ700 <= '0';
MODE_CUSTOM <= '0';
-- Write to config register.
-- CPLD Configuration register.
--
-- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
-- by host software such as RFS.
--
-- [2:0] - Mode/emulated machine.
-- 000 = MZ-80K
-- 001 = MZ-80C
-- 010 = MZ-1200
-- 011 = MZ-80A
-- 100 = MZ-700
-- 101 = MZ-800
-- 110 = MZ-80B
-- 111 = MZ-2000
-- [3] - Mainboard Video - 1 = Enable, 0 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
-- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
-- [6:4] = Mainboard/CPU clock.
-- 000 = Sharp MZ80A 2MHz System Clock.
-- 001 = Sharp MZ80B 4MHz System Clock.
-- 010 = Sharp MZ700 3.54MHz System Clock.
-- 011 -111 = Reserved, defaults to 2MHz System Clock.
--
if(CS_CPLD_CFGn = '0' and CS_LAST_LEVEL(0) = '1' and S_VIDEO_WRn = '0') then
-- Bits 2:0 select the system clock which drives the mainboard/CPU.
-- Set the mode switch event flag if the mode changes.
if CPLD_CFG_DATA(2 downto 0) /= D(2 downto 0) then
MODE_CPLD_SWITCH <= '1';
end if;
-- Store the new value into the register, used for read operations.
CPLD_CFG_DATA <= D;
else
MODE_CPLD_SWITCH <= '0';
end if;
-- Setup the video mode.
if CS_FB_VMn = '0' and CS_LAST_LEVEL(1) = '1' and S_VIDEO_WRn = '0' then
MODE_VIDEO_MZ80K <= '0';
MODE_VIDEO_MZ80C <= '0';
MODE_VIDEO_MZ1200 <= '0';
MODE_VIDEO_MZ80A <= '0';
MODE_VIDEO_MZ700 <= '0';
MODE_VIDEO_MZ800 <= '0';
MODE_VIDEO_MZ80B <= '0';
MODE_VIDEO_MZ2000 <= '0';
-- Bits [2:0] define the machine compatibility.
--
case D(2 downto 0) is
when "000" =>
MODE_MZ80A <= '1';
when "001" =>
MODE_MZ80B <= '1';
when "010" =>
MODE_MZ700 <= '1';
when "011" =>
MODE_CUSTOM <= '1';
case to_integer(unsigned(D(2 downto 0))) is
when MODE_MZ80K =>
MODE_VIDEO_MZ80K <= '1';
when MODE_MZ80C =>
MODE_VIDEO_MZ80C <= '1';
when MODE_MZ1200 =>
MODE_VIDEO_MZ1200 <= '1';
when MODE_MZ80A =>
MODE_VIDEO_MZ80A <= '1';
when MODE_MZ700 =>
MODE_VIDEO_MZ700 <= '1';
when MODE_MZ800 =>
MODE_VIDEO_MZ800 <= '1';
when MODE_MZ80B =>
MODE_VIDEO_MZ80B <= '1';
when MODE_MZ2000 =>
MODE_VIDEO_MZ2000 <= '1';
when others =>
MODE_MZ80A <= '1';
end case;
end if;
-- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and CS_LAST_LEVEL(2) = '1' then
GRAM_PAGE_ENABLE <= D(1 downto 0);
end if;
-- MZ80B Z80 PIO.
if CS_80B_PIOn = '0' and CS_LAST_LEVEL(3) = '1' and MODE_VIDEO_MZ80B = '1' and S_VIDEO_WRn = '0' then
-- Write to PIO A.
-- 7 = Assigns addresses $DOOO-$FFFF to V-RAM.
-- 6 = Assigns addresses $5000-$7FFF to V-RAM.
-- 5 = Changes screen to 80-character mode (L: 40-character mode).
if VA(1 downto 0) = "00" then
MZ80B_VRAM_HI_ADDR <= D(7);
MZ80B_VRAM_LO_ADDR <= D(6);
end if;
end if;
-- Remember the previous level so we can detect the edge transition. As the clock of this process is not necessarily running at the clock of the CPU
-- this step is important to guarantee transaction integrity.
CS_LAST_LEVEL <= '0' & CS_IO_FXX_n;
CS_LAST_LEVEL <= '0' & CS_80B_PIOn & CS_FB_PAGEn & CS_FB_VMn & CS_CPLD_CFGn;
end if;
-- MZ80B Graphics RAM is enabled whenever one of the two control lines goes active.
GRAM_MZ80B_ENABLE <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR;
end process;
-- Voltage translation. The FPGA is max 3.3v tolerant (as are nearly all FPGA's) so the 5V signals from the mainboard would have to go through a diode clamp
-- or converter. Given the pricing of the MAX7000 series chips it is easier and cheaper to use a CPLD to perform the voltage translation as they are 5V tolerant
-- and the mainboard accepts 3.3V output voltages.
--
VADDR <= VA(15 downto 11) & A(10 downto 0);
-- Data bus is muxed between the Z80 data bus and VRAMD which is the gated data bus after the video buffers.
-- The write signal WRn from the motherboard is actually a gated Write with video memory or I/O select. The read signal RDn from the motherboard is a gated Read with video memory or I/O select.
-- The logic has been updated in the tranZPUter to combine the Video Select with Z80 RD/WR such that use of S_VIDEO_RDn = 0 for read and S_VIDEO_WRn = 0 for write works as intended for all memory/IO operations. To
-- differentiate between memory and access, I/O operations use S_IORQn = 0.
--
VDATA <= D when S_VIDEO_WRn = '0' -- All memory write data sent to FPGA in region C000:FFFF
else
(others => 'Z');
D <= VDATA when S_VIDEO_RDn = '0' and CS_EXXXn = '1' -- C000:FFFF or FPGA IO Registers via data bus.
else
(others => 'Z');
VRAMD <= (others => 'Z');
VA(10 downto 0) <= A(10 downto 0); -- Lower 11 address bits taken from address bus.
VZ80_IORQn <= S_IORQn;
VZ80_WRn <= S_VIDEO_WRn; -- Write based on Z80_WRn and Video FPGA select signal from tranZPUter.
VZ80_RDn <= S_VIDEO_RDn; -- Read signal based on Z80_RDn and Video FPGA select from tranZPUter.
VGTn <= GTn;
VCSn <= CSn;
VVRAM_CS_INn <= VRAM_CS_INn;
-- Standard access to VRAM/ARAM.
CS_DXXXn <= '0' when S_IORQn = '1' and VA(15 downto 12) = "1101"
else '1';
CS_DVRAMn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11010"
else '1';
CS_DARAMn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11011"
else '1';
CS_EXXXn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11100" and GRAM_PAGE_ENABLE = "00" and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
else '1';
--
-- CPU / RAM signals and selects.
--
CS_IO_6XXn <= '0' when S_IORQn = '0' and VA(7 downto 4) = "0110"
else '1';
CS_IO_EXXn <= '0' when S_IORQn = '0' and VA(7 downto 4) = "1110"
else '1';
CS_IO_FXXn <= '0' when S_IORQn = '0' and VA(7 downto 4) = "1111"
else '1';
CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and VA(3 downto 0) = "1110" -- IO 6E
else '1';
-- 0xF8 set the video mode. [2:0] = mode, 000 = MZ80A, 001 = MZ-700, 010 = MZ-80B, 011 = MZ-800, 111 = Pixel graphics.
CS_FB_VMn <= '0' when CS_IO_FXXn = '0' and VA(3 downto 0) = "1000"
else '1';
-- 0xFD set the Video memory page in block C000:FFFF bit 0, set the CGROM upload access in bit 7.
CS_FB_PAGEn <= '0' when CS_IO_FXXn = '0' and VA(3 downto 0) = "1101"
else '1';
-- MZ80B/MZ2000 I/O Registers E0-EB,
CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and VA(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1'
else '1';
-- Set the mainboard video state, 0 = enabled, 1 = disabled.
MODE_CPLD_MB_VIDEOn <= CPLD_CFG_DATA(3);
-- Set CPLD mode flag according to value given in config 2:0
MODE_CPLD_MZ80K <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80K
else '0';
MODE_CPLD_MZ80C <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80C
else '0';
MODE_CPLD_MZ1200 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ1200
else '0';
MODE_CPLD_MZ80A <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80A
else '0';
MODE_CPLD_MZ700 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ700
else '0';
MODE_CPLD_MZ800 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ800
else '0';
MODE_CPLD_MZ80B <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80B
else '0';
MODE_CPLD_MZ2000 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ2000
else '0';
end architecture;

28
CPLD/VideoInterface_Toplevel.vhd
View File

@@ -41,15 +41,14 @@ entity VideoInterfaceCPLD is
CLOCK_50 : in std_logic; -- 50MHz base clock for system board, video timing and gate clocking.
-- Z80 Address and Data. Address is muxed with video addressing, not direct.
-- A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
D : inout std_logic_vector(7 downto 0); -- Z80 Data bus, from the Colour Card CN! connector.
-- Z80 Control signals.
-- WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector.
WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector.
RDn : in std_logic; -- Z80 Read signal from the Colour Card CN! connector.
RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board.
MB_RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board.
-- IORQn : in std_logic; -- Z80 IORQ signal from the tranZPUter board.
-- Video and Mainboard signals.
SRVIDEO_OUT : out std_logic; -- Shift Register 74LS165 Video Output onto mainboard.
@@ -68,21 +67,20 @@ entity VideoInterfaceCPLD is
VRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
GTn : in std_logic; -- GATE signal from the Colour Card CN! connector.
CSn : in std_logic; -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector.
-- MEM_CSn : in std_logic; -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board.
OUTCLK : out std_logic; -- CPU signal serialiser clock.
INDATA : in std_logic_vector(3 downto 0); -- Incoming serialised CPU signals.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
VADDR : out std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address.
VADDR : out std_logic_vector(15 downto 0); -- Z80 Address bus, multiplexed with video address.
VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector..
VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals.
VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
--VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
VZ80_IORQn : out std_logic; -- IORQn to FPGA.
VZ80_RDn : out std_logic; -- RDn to FPGA.
VZ80_WRn : out std_logic; -- WRn to FPGA.
VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn : out std_logic; -- IORQn to FPGA.
VRDn : out std_logic; -- RDn to FPGA.
VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn : out std_logic; -- Video Gate (GTn)
VWRn : out std_logic; -- WRn to FPGA.
VRESETn : out std_logic; -- Reset to FPGA.
--
VSRVIDEO_OUT : in std_logic; -- Video out from 74LS165 on mainboard, pre-GATE.
@@ -119,11 +117,11 @@ begin
CLOCK_50 => CLOCK_50, -- 50MHz base clock for system board, video timing and gate clocking.
-- Z80 Address and Data. Address is muxed with video addressing, not direct.
-- A => A, -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
A => A, -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board.
D => D, -- Z80 Data bus, from the Colour Card CN! connector.
-- Z80 Control signals.
-- WRn => WRn, -- Z80 Write signal from the Colour Card CN! connector.
WRn => WRn, -- Z80 Write signal from the Colour Card CN! connector.
RDn => RDn, -- Z80 Read signal from the Colour Card CN! connector.
RESETn => CPLDRESETn, -- Z80 RESET signal from the tranZPUter board.
-- IORQn => IORQn, -- Z80 IORQ signal from the tranZPUter board.
@@ -153,13 +151,13 @@ begin
VADDR => VADDR, -- Z80 Address bus, multiplexed with video address.
VDATA => VDATA, -- Z80 Data bus from mainboard Colour Card CD connector..
VRAMD => VRAMD, -- Z80 Data bus from the VRAM chip, gated according to state signals.
VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA.
--VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA.
VZ80_IORQn => VZ80_IORQn, -- IORQn to FPGA.
VZ80_RDn => VZ80_RDn, -- RDn to FPGA.
VZ80_WRn => VZ80_WRn, -- WRn to FPGA.
VVRAM_CS_INn => VVRAM_CS_INn, -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VIORQn => VIORQn, -- IORQn to FPGA.
VRDn => VRDn, -- RDn to FPGA.
VCSn => VCSn, -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn => VGTn, -- Video Gate (GTn)
VWRn => VWRn, -- WRn to FPGA.
VSRVIDEO_OUT => VSRVIDEO_OUT, -- Video out from 74LS165 on mainboard, pre-GATE.
VHBLNK_OUTn => VHBLNK_OUTn, -- Horizontal blanking.

93
CPLD/VideoInterface_pkg.vhd
View File

@@ -35,17 +35,6 @@ use ieee.numeric_std.all;
use ieee.math_real.all;
package VideoInterface_pkg is
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
------------------------------------------------------------
-- Constants
@@ -60,6 +49,78 @@ package VideoInterface_pkg is
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Target hardware modes.
constant MODE_MZ80K : integer := 0;
constant MODE_MZ80C : integer := 1;
constant MODE_MZ1200 : integer := 2;
constant MODE_MZ80A : integer := 3;
constant MODE_MZ700 : integer := 4;
constant MODE_MZ800 : integer := 5;
constant MODE_MZ80B : integer := 6;
constant MODE_MZ2000 : integer := 7;
-- Target Bus frequency modes.
constant MODE_FREQ_MZ80A : integer := 0;
constant MODE_FREQ_MZ80B : integer := 1;
constant MODE_FREQ_MZ700 : integer := 2;
constant MODE_FREQ_CUSTOM : integer := 7;
-- Memory management modes.
constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
-- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_COMPAT : integer := 08; -- Compatible monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ80A;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
-- Find the number of bits required to represent an integer.
function log2ceil(arg : positive) return natural;
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural;
------------------------------------------------------------
-- Records
@@ -117,4 +178,14 @@ package body VideoInterface_pkg is
end if;
end function;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
end package body;

36
CPLD/build/VideoInterface.qsf
View File

@@ -63,21 +63,23 @@ set_location_assignment PIN_125 -to CLOCK_50
#set_location_assignment PIN_90 -to A[13]
#set_location_assignment PIN_88 -to A[12]
#set_location_assignment PIN_87 -to A[11]
#set_location_assignment PIN_98 -to A[10]
#set_location_assignment PIN_101 -to A[9]
#set_location_assignment PIN_103 -to A[8]
#set_location_assignment PIN_106 -to A[7]
#set_location_assignment PIN_108 -to A[6]
#set_location_assignment PIN_110 -to A[5]
#set_location_assignment PIN_112 -to A[4]
#set_location_assignment PIN_114 -to A[3]
#set_location_assignment PIN_117 -to A[2]
#set_location_assignment PIN_119 -to A[1]
#set_location_assignment PIN_121 -to A[0]
set_location_assignment PIN_98 -to A[10]
set_location_assignment PIN_101 -to A[9]
set_location_assignment PIN_103 -to A[8]
set_location_assignment PIN_106 -to A[7]
set_location_assignment PIN_108 -to A[6]
set_location_assignment PIN_110 -to A[5]
set_location_assignment PIN_112 -to A[4]
set_location_assignment PIN_114 -to A[3]
set_location_assignment PIN_117 -to A[2]
set_location_assignment PIN_119 -to A[1]
set_location_assignment PIN_121 -to A[0]
# Video Interface Address Bus
# ===========================
set_location_assignment PIN_69 -to VADDR[15]
set_location_assignment PIN_68 -to VADDR[14]
set_location_assignment PIN_42 -to VADDR[13]
set_location_assignment PIN_41 -to VADDR[12]
set_location_assignment PIN_40 -to VADDR[11]
@@ -108,7 +110,7 @@ set_location_assignment PIN_93 -to GTn
set_location_assignment PIN_86 -to MB_RESETn
set_location_assignment PIN_127 -to RESETn
set_location_assignment PIN_91 -to RDn
#set_location_assignment PIN_96 -to WRn
set_location_assignment PIN_96 -to WRn
set_location_assignment PIN_16 -to VRAM_CS_INn
set_location_assignment PIN_90 -to INDATA[3]
@@ -186,17 +188,15 @@ set_location_assignment PIN_77 -to VVBLNK_OUTn
# ======================
set_location_assignment PIN_46 -to VCSn
set_location_assignment PIN_47 -to VGTn
set_location_assignment PIN_44 -to VIORQn
set_location_assignment PIN_43 -to VMEM_CSn
set_location_assignment PIN_45 -to VRDn
set_location_assignment PIN_44 -to VZ80_IORQn
#set_location_assignment PIN_43 -to VMEM_CSn
set_location_assignment PIN_45 -to VZ80_RDn
set_location_assignment PIN_49 -to VRESETn
set_location_assignment PIN_27 -to VVRAM_CS_INn
set_location_assignment PIN_48 -to VWRn
set_location_assignment PIN_48 -to VZ80_WRn
# Reserved.
# =========
#set_location_assignment PIN_69 -to TBA[4]
#set_location_assignment PIN_68 -to TBA[3]
#set_location_assignment PIN_67 -to TBA[2]
#set_location_assignment PIN_66 -to TBA[1]
#set_location_assignment PIN_65 -to TBA[0]

33
CPLD/build/VideoInterface.srf
View File

@@ -2,5 +2,38 @@
{ "" "" "" "Macrocell buffer inserted after node \"Z80_BUSACKn\"" { } { } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 5 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(127): object \"MODE_CPLD_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(157): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(153): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(158): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(136): object \"MODE_CPLD_MB_VIDEOn\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(134): object \"MODE_CPLD_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(133): object \"MODE_CPLD_MZ80B\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(132): object \"MODE_CPLD_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(131): object \"MODE_CPLD_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(130): object \"MODE_CPLD_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(129): object \"MODE_CPLD_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(135): object \"MODE_CPLD_SWITCH\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(128): object \"MODE_CPLD_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"GRAM_PAGE_ENABLE\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MZ80B_VRAM_HI_ADDR\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(162): object \"MZ80B_VRAM_LO_ADDR\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(150): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(151): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(158): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""}

37
CPLD/build/VideoInterface_constraints.sdc
View File

@@ -45,6 +45,7 @@ create_clock -name {CLOCK_50} -period 20.00 -waveform { 0.000 10.00 } [get_ports
# Create Generated Clock
#**************************************************************
create_clock -name {VideoInterface:myVirtualToplevel|CLK16Mi} -period 62.5 [get_keepers {VideoInterface:myVirtualToplevel|CLK16Mi}]
create_clock -name {VideoInterface:myVirtualToplevel|CLK24Mi} -period 41.667 [get_keepers {VideoInterface:myVirtualToplevel|CLK24Mi}]
#**************************************************************
@@ -67,24 +68,24 @@ set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CL
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[13]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[12]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[11]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[10]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[9]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[8]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[7]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[6]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[5]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[4]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[3]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[2]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[1]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[0]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[10]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[9]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[8]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[7]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[6]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[5]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[4]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[3]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[2]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[1]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[0]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {IORQn}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MEM_CSn}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {GTn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RESETn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RDn}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[3]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[2]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[1]}]
@@ -138,6 +139,8 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}]
@@ -152,7 +155,6 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[7]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
@@ -161,6 +163,7 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[7]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[6]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[5]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[4]}]
@@ -175,12 +178,12 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {S
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VBLNK_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VCSn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIORQn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRDn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
#set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVRAM_CS_INn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWRn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_HBLNKn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_LOAD}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_SYNCH}]

1826
FPGA/VideoController.vhd
View File

File diff suppressed because it is too large Load Diff

27
FPGA/VideoController_Toplevel.vhd
View File

@@ -42,17 +42,15 @@ entity VideoControllerFPGA is
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Addres Bus
VADDR : in std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address.
VADDR : in std_logic_vector(15 downto 0); -- Z80 Address bus, multiplexed with video address.
-- Data Bus
VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector..
-- Control signals.
VMEM_CSn : in std_logic; -- Extended memory select to FPGA.
VIORQn : in std_logic; -- IORQn to FPGA.
VRDn : in std_logic; -- RDn to FPGA.
VWRn : in std_logic; -- WRn to FPGA.
VRESETn : in std_logic; -- Reset to FPGA.
VZ80_IORQn : in std_logic; -- IORQn to FPGA.
VZ80_RDn : in std_logic; -- RDn to FPGA.
VZ80_WRn : in std_logic; -- WRn to FPGA.
-- VGA signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
@@ -68,8 +66,10 @@ entity VideoControllerFPGA is
VHBLNK_OUTn : out std_logic; -- Horizontal blanking.
VHSY_OUT : out std_logic; -- Horizontal Sync.
VSYNCH_OUT : out std_logic; -- Veritcal Sync.
VVBLNK_OUTn : out std_logic -- Vertical blanking.
VVBLNK_OUTn : out std_logic; -- Vertical blanking.
-- Reset.
VRESETn : in std_logic -- Reset to FPGA.
-- Reserved.
--TBA : in std_logic_vector(4 downto 0) -- Reserved signal paths to the CPLD.
);
@@ -147,11 +147,9 @@ begin
VDATA => VDATA, -- Z80 Data bus from mainboard Colour Card CD connector..
-- Control signals.
VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA.
VIORQn => VIORQn, -- IORQn to FPGA.
VRDn => VRDn, -- RDn to FPGA.
VWRn => VWRn, -- WRn to FPGA.
VRESETn => RESETn, -- Reset to FPGA.
VZ80_IORQn => VZ80_IORQn, -- IORQn to FPGA.
VZ80_RDn => VZ80_RDn, -- RDn to FPGA.
VZ80_WRn => VZ80_WRn, -- WRn to FPGA.
-- VGA signals.
VGA_R => VGA_R, -- 16 level Red output.
@@ -167,7 +165,10 @@ begin
VHBLNK_OUTn => VHBLNK_OUTn, -- Horizontal blanking.
VHSY_OUT => VHSY_OUT, -- Horizontal Sync.
VSYNCH_OUT => VSYNCH_OUT, -- Veritcal Sync.
VVBLNK_OUTn => VVBLNK_OUTn -- Vertical blanking.
VVBLNK_OUTn => VVBLNK_OUTn, -- Vertical blanking.
-- Reset.
VRESETn => RESETn -- Reset to FPGA.
-- Reserved.
--TBA => TBA -- Reserved signals.

90
FPGA/VideoController_pkg.vhd
View File

@@ -35,6 +35,72 @@ use ieee.numeric_std.all;
use ieee.math_real.all;
package VideoController_pkg is
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Target hardware modes.
constant MODE_MZ80K : integer := 0;
constant MODE_MZ80C : integer := 1;
constant MODE_MZ1200 : integer := 2;
constant MODE_MZ80A : integer := 3;
constant MODE_MZ700 : integer := 4;
constant MODE_MZ800 : integer := 5;
constant MODE_MZ80B : integer := 6;
constant MODE_MZ2000 : integer := 7;
-- Memory management modes.
constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
-- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_COMPAT : integer := 08; -- Compatiblilty monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ80A;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
@@ -55,19 +121,8 @@ package VideoController_pkg is
--
function to_std_logic(i : in integer) return std_logic;
------------------------------------------------------------
-- Constants
------------------------------------------------------------
-- Potential logic state constants.
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural;
------------------------------------------------------------
-- Records
@@ -142,4 +197,13 @@ package body VideoController_pkg is
return '1';
end function;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
end package body;

47
FPGA/build/VideoController.qsf
View File

@@ -86,6 +86,8 @@ set_location_assignment PIN_129 -to CLOCK_50
# Video Interface Address Bus
# ===========================
set_location_assignment PIN_80 -to VADDR[15]
set_location_assignment PIN_83 -to VADDR[14]
set_location_assignment PIN_120 -to VADDR[13]
set_location_assignment PIN_121 -to VADDR[12]
set_location_assignment PIN_125 -to VADDR[11]
@@ -100,6 +102,8 @@ set_location_assignment PIN_143 -to VADDR[3]
set_location_assignment PIN_144 -to VADDR[2]
set_location_assignment PIN_7 -to VADDR[1]
set_location_assignment PIN_4 -to VADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[11]
@@ -146,20 +150,20 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[0
# ======================
#set_location_assignment PIN_113 -to VCSn
#set_location_assignment PIN_112 -to VGTn
set_location_assignment PIN_115 -to VIORQn
set_location_assignment PIN_119 -to VMEM_CSn
set_location_assignment PIN_114 -to VRDn
set_location_assignment PIN_115 -to VZ80_IORQn
#set_location_assignment PIN_119 -to VMEM_CSn
set_location_assignment PIN_114 -to VZ80_RDn
set_location_assignment PIN_110 -to VRESETn
#set_location_assignment PIN_28 -to VVRAM_CS_INn
set_location_assignment PIN_111 -to VWRn
set_location_assignment PIN_111 -to VZ80_WRn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCSn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMEM_CSn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMEM_CSn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRESETn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVRAM_CS_INn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
# VGA/RGB signals.
# ================
@@ -230,23 +234,27 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VHSY_OU
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNCH_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VVBLNK_OUTn
# Mainboard video signals on the CN1 connector passed to the FPGA.
# ================================================================
set_location_assignment PIN_71 -to VMB_HBLNKn
set_location_assignment PIN_72 -to VMB_LOAD
set_location_assignment PIN_76 -to VMB_SYNCH
set_location_assignment PIN_77 -to VMB_V_HBLNKn
set_location_assignment PIN_79 -to VMB_VIDEO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_HBLNKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_LOAD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_SYNCH
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_V_HBLNKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_VIDEO
# Reserved.
# =========
#set_location_assignment PIN_71 -to TBA[9]
#set_location_assignment PIN_72 -to TBA[8]
#set_location_assignment PIN_76 -to TBA[7]
#set_location_assignment PIN_77 -to TBA[6]
#set_location_assignment PIN_79 -to TBA[5]
#set_location_assignment PIN_80 -to TBA[4]
#set_location_assignment PIN_83 -to TBA[3]
#set_location_assignment PIN_85 -to TBA[2]
#set_location_assignment PIN_86 -to TBA[1]
#set_location_assignment PIN_87 -to TBA[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[9]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[8]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[7]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[6]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[5]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[4]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[3]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[2]
@@ -271,4 +279,7 @@ set_global_assignment -name SDC_FILE VideoController_constraints.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

10
FPGA/build/VideoController_constraints.sdc
View File

@@ -67,10 +67,12 @@ derive_clock_uncertainty
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIORQn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}]

1382
software/mif/COLOURBOARD_CG.mif Normal file
View File

File diff suppressed because it is too large Load Diff

182
software/mif/MZ700_cgrom.mif Normal file
View File

@@ -0,0 +1,182 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 4096;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00;
0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00;
0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00;
0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00;
0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00;
0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00;
00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00;
00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00;
00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00;
00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00;
0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00;
0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00;
0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00;
0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10;
0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF;
0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10;
01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00;
01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F;
01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF;
01F8: 03 03 03 03 03 03 03 03 10 08 08 04 08 08 10 00 08 1C 3E 7F 7F 1C 3E 00;
0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00;
0228: 00 00 10 20 7F 20 10 00 1C 1C 6B 7F 6B 08 1C 00 00 3C 7E 7E 7E 7E 3C 00;
0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF;
0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF;
0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00;
0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00;
02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80;
02B8: 70 18 0C 06 0C 18 70 00 00 08 08 08 2A 1C 08 00 00 40 20 10 08 04 02 00;
02D0: 00 00 04 02 7F 02 04 00 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08;
02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08;
0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00;
0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00;
0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00;
0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00;
0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00;
0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00;
03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00;
03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02;
03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 18 18 18 18 18 18 18 00;
0408: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00;
0420: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00;
0438: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00;
0450: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00;
0468: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00;
0480: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00;
0498: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 46 3A 00;
04B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00;
04C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 24 00 38 04 3C 44 3A 00;
04E0: 00 00 00 01 02 04 08 10 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00;
04F8: 00 00 00 80 40 20 10 08 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00;
0510: 44 44 44 44 44 44 44 44 44 FF 44 44 44 FF 44 44 20 10 08 00 00 00 00 00;
0528: 00 00 00 32 4C 00 00 00 AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0;
0540: 03 0C 30 C0 00 00 00 00 C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00;
0558: 00 22 00 22 22 26 1A 00 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00;
0570: 42 18 24 42 7E 42 42 00 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80;
0588: 01 06 18 20 20 40 40 80 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
05A0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80;
05B8: 01 01 02 02 02 04 04 08 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03;
05D0: 00 00 00 00 01 06 38 C0 08 10 20 40 80 00 00 00 08 10 10 20 10 10 08 00;
05E8: 08 08 08 08 FF 08 08 08 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7E 00;
0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF;
0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF;
0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00;
0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00;
0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C;
0678: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05;
0690: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55;
06A8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55;
06C0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01;
06D8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08;
06F0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00;
0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02;
0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 11 22 44 88 11 22 44 88;
0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23;
0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80;
0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04;
0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70;
07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07;
07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77 00 00 00 00 00 00 00 00;
0808: 7C C6 BA BA 82 BA AA EE FC 86 BA 84 BA BA 86 FC 7E C2 BE A0 A0 BE C2 7E;
0820: F8 8C B6 AA AA B6 8C F8 FE 82 BE 88 88 BE 82 FE FE 82 BE 88 B8 A0 A0 E0;
0838: 7E 82 BE A0 AE BA 82 7E EE AA BA 82 BA AA AA EE FE 82 EE 28 28 EE 82 FE;
0850: 1F 11 1B 0A EA BA C6 7C E6 AA B4 88 88 B4 AA E6 E0 A0 A0 A0 A0 BE 82 FE;
0868: FE 82 AA AA BA AA AA EE EE 9A 8A A2 B2 AA AA EE 7C C6 BA AA AA BA C6 7C;
0880: FC 86 BA BA 86 BC A0 E0 7C C6 BA BA AA B2 C2 7C FC 86 BA BA 84 B4 AA E6;
0898: 7E C2 BE C4 7A FA 86 FC FE 82 EE 28 28 28 28 38 EE AA AA AA AA BA C6 7C;
08B0: EE AA AA AA AA 54 28 10 EE AA AA BA AA AA 82 FE C6 AA 54 28 28 54 AA C6;
08C8: EE AA 92 44 28 28 28 38 FE 82 FA 14 28 5E 82 FE 00 40 A0 90 FF 7E 00 00;
08E0: 00 02 05 09 FF 7E 00 00 00 7C D6 7C 38 54 92 00 92 54 38 FE 38 54 92 00;
08F8: 00 00 38 54 FE 00 00 00 7C 82 B2 AA AA 9A 82 7C 38 48 68 28 28 6C 44 7C;
0910: 7C 82 BA CA 14 2E 42 FE FC 82 FA 22 22 FA 82 FC 0C 14 24 54 B6 82 F6 1C;
0928: FE 82 BE 84 7A FA 86 FC 7E 82 BE BC 82 BA 82 7C FE 82 FA 14 28 50 50 70;
0940: 7C 82 BA 7C 82 BA 82 7C 7C 82 BA 82 7A FA 82 FC F8 88 BE AA FA 22 3E 00;
0958: 1F 11 7D 55 5F 44 7C 00 3C 5A FF E7 7E 24 42 81 3C 5A FF E7 7E 24 24 66;
0970: 08 1C 2A 7F 77 3E 36 63 08 1C 2A 7F 77 3E 36 14 41 A2 3C 5A 7E FF 42 63;
0988: 82 45 3C 5A 7E FF 42 C6 00 5A BD 99 24 42 24 00 81 A5 5A 18 18 24 C3 00;
09A0: 00 24 7E BD 7E 24 24 E7 24 7E BD 7E 24 42 42 C3 3C 5A FF AB D5 FF DD 89;
09B8: 3C 5A FF AB D5 FF 77 22 3C 42 A5 81 99 81 D5 AA 3C 42 A5 81 99 81 AB 55;
09D0: 42 42 66 E7 FF FF 7E 3C 1C FE 3F 0F 0F 3F FE 1C 3C 7E FF FF E7 66 42 42;
09E8: 38 7F FC F0 F0 FC 7F 38 3C 7E FF FF FF FF 7E 3C 10 38 28 28 28 7C FE D6;
0A00: 00 03 07 7E C7 7E 07 03 6B 7F 3E 14 14 14 1C 08 00 C0 E0 7E E3 7E E0 C0;
0A18: 3C 0C 3C 18 3C 76 76 46 3C 24 3C 18 3C 5A 5A 7E 3C 30 3C 18 3C 6E 6E 62;
0A30: 7E 7E 24 24 24 24 24 6C 7E 7E 24 24 24 24 24 66 7E 7E 24 24 24 24 24 36;
0A48: 22 63 F7 B7 FF 7E 3C 3C 38 6C FF 3F 0F 3F FC 38 3C 3C 7E FF ED EF C6 44;
0A60: 1C 36 FF FC F0 FC 3F 1E 3C 7E FF BF FF 7E 3C 3C 3C 3C 7E FF FD FF 7E 3C;
0A78: 1C 36 FF FF FF FF 3E 1C 38 6C FF FF FF FF 7C 38 18 3C 3C 3C 3C 18 3C 3C;
0A90: 00 00 7B FF FF 7B 00 00 3C 3C 18 3C 3C 3C 3C 18 00 00 DE FF FF DE 00 00;
0AA8: 20 60 20 20 30 28 3C 3C 00 40 FF 0B 07 03 00 00 3C 3C 14 0C 04 04 06 04;
0AC0: 00 02 FF D0 E0 C0 00 00 10 10 38 7C 92 10 10 38 00 08 10 31 FF 31 10 08;
0AD8: 38 10 10 92 7C 38 10 10 00 10 08 8C FF 8C 08 10 00 78 60 50 48 04 02 00;
0AF0: 00 02 04 48 50 60 78 00 00 40 20 12 0A 06 1E 00 00 1E 06 0A 12 20 40 00;
0B08: 18 7E 7E FF C3 81 81 81 1F 78 70 F0 F0 70 78 1F 81 81 81 C3 FF 7E 7E 18;
0B20: F8 1E 0E 0F 0F 0E 1E F8 BF A1 AD A5 A5 BD 81 FF FF 81 BD A5 85 FD 01 FF;
0B38: FF 81 BD A5 A5 B5 85 FD FF 80 BF A1 A5 BD 81 FF 00 18 00 3C 00 7E 00 FF;
0B50: 01 05 15 55 55 15 05 01 FF 00 7E 00 3C 00 18 00 80 A0 A8 AA AA A8 A0 80;
0B68: 00 08 1C 3E 00 08 1C 3E 00 00 11 33 77 33 11 00 00 3E 1C 08 00 3E 1C 08;
0B80: 00 00 44 66 77 66 44 00 00 00 E7 A5 E7 00 00 00 10 38 54 10 10 54 38 10;
0B98: 00 00 24 42 FF 42 24 00 7F 41 22 1C 08 08 08 7F 55 55 55 55 55 55 55 55;
0BB0: FF 00 FF 00 FF 00 FF 00 A5 42 A5 00 00 A5 42 A5 24 42 81 00 00 81 42 24;
0BC8: FF 80 9F A0 A0 A0 A0 A0 FF 01 E5 11 15 11 15 11 00 00 00 FF A0 AF A0 FF;
0BE0: 00 00 00 FF 41 41 55 FF A0 9F 80 FF 30 30 30 78 11 E1 01 FF 0C 0C 0C 1E;
0BF8: 80 AA 80 95 80 8F 80 FF 01 A9 01 51 01 E1 01 FF 3C 42 AB D5 10 10 14 08;
0C10: 00 00 18 24 24 18 00 00 00 18 24 42 42 24 18 00 3C 42 81 81 81 81 42 3C;
0C28: 00 00 00 18 18 00 00 00 00 00 3C 3C 3C 3C 00 00 00 7E 7E 7E 7E 7E 7E 00;
0C40: 3C 42 9D A1 A1 9D 42 3C FF FF FF E7 E7 FF FF FF FF FF C3 C3 C3 C3 FF FF;
0C58: FF 81 81 81 81 81 81 FF 20 30 20 20 FF 7E 3C 00 3C 42 81 FF FF 81 42 3C;
0C70: 3C 5A 99 99 99 99 5A 3C 3C 5A 99 FF FF 99 5A 3C 00 28 FE AA FE 54 38 10;
0C88: 0F 30 40 4E 8A 8E 80 81 F0 0C 02 72 51 71 01 81 0F 30 40 40 8E 80 80 81;
0CA0: F0 0C 02 02 71 01 01 81 81 80 88 84 43 40 30 0F 81 01 11 21 C2 02 0C F0;
0CB8: 81 80 80 87 40 40 30 0F 81 01 01 E1 02 02 0C F0 81 80 83 84 43 40 30 0F;
0CD0: 81 01 C1 21 C2 02 0C F0 81 80 87 88 48 40 30 0F 81 01 E1 11 12 02 0C F0;
0CE8: 08 10 54 FE FE FE FE 7C 00 06 08 10 30 78 78 30 00 52 34 06 60 2C 4A 00;
0D00: 91 52 00 03 C0 00 4A 89 80 C0 E0 F0 FF FF FF FF 00 00 01 02 FF C3 C3 FF;
0D18: 00 00 80 40 FF C3 C3 FF 00 C0 20 10 FC FE FF FC 01 03 07 0F FF FF FF FF;
0D30: 02 14 28 08 14 14 08 00 00 FE 42 20 10 20 42 FE 00 03 04 08 3F 7F FF 3F;
0D48: 00 20 10 10 10 28 48 86 00 3C 42 42 42 24 A5 E7 00 44 82 82 92 6C 00 00;
0D60: 00 00 6C 92 92 6C 00 00 00 02 6C 90 90 6E 00 00 00 1E 10 50 50 B0 10 00;
0D78: 00 00 10 00 7C 00 10 00 00 F1 5B 55 55 51 51 00 FF 89 91 C5 A3 89 91 FF;
0D90: FF C3 A5 99 99 A5 C3 FF 00 92 54 38 EE 38 54 92 FF 99 99 FF FF 99 99 FF;
0DA8: 92 54 38 10 10 10 10 10 38 10 38 10 38 10 38 10 00 00 00 AA FF AA 00 00;
0DC0: 00 10 10 7C 10 10 00 7C 7E 42 7E 42 7E 42 7E 42 00 FF 55 55 55 55 FF 00;
0DD8: 00 00 00 C0 B0 8C 83 FF 00 00 00 03 0D 31 C1 FF 00 00 00 00 3C 7E FF FF;
0DF0: FF FF 7E 3C 00 00 00 00 C0 E0 F0 F0 F0 F0 E0 C0;
0E00: 03 07 0F 0F 0F 0F 07 03 03 0C 3F 3F FF 7F 37 1F C0 30 B8 DC EE F6 FB FB;
0E18: 0E 0E 0A 04 01 01 03 0F 7A 74 F4 F4 F4 FA FD FD 04 4E E4 46 6F 7F 60 3F;
0E30: 20 72 27 62 F6 FE 06 FC 3B 31 1B 1F 10 1F 0F 07 DC 8C D8 F8 08 F8 F0 E0;
0E48: 01 03 07 06 0E 3E 70 30 80 C0 E0 60 70 7C 0E 0C 1E 0E 06 07 03 37 7F 8B;
0E60: 78 70 60 E0 C0 EC FE D1 01 33 7B 59 8C DF 7F 3F 80 CC DE 9A 31 FB FE FC;
0E78: 3F 1F 1F 0F 0F 7F 00 FF FC F8 F8 F0 F0 FE 00 FF 00 01 02 04 02 01 1F 1F;
0E90: 00 80 40 20 40 80 F8 F8 02 02 02 02 1F 20 7F 00 40 40 40 40 F8 04 FE 00;
0EA8: 73 73 73 7F 3F 1F 0F 0F CE CE CE FE FC F8 F0 F0 0F 0F 0F 18 7F 40 7F FF;
0EC0: F0 F0 F0 18 FE 02 FE FF F8 44 42 21 21 42 44 F8 FF 05 07 00 00 07 05 FF;
0ED8: FC 86 82 81 81 82 86 FC 00 00 80 40 7F 80 00 00 00 00 00 00 FF 01 01 01;
0EF0: 01 01 01 01 FF 00 00 00 FF 80 80 80 80 00 00 00 00 00 00 00 80 80 80 FF;
0F08: 00 08 0C 0A F9 0A 0C 08 00 08 0C 3A E9 3A 0C 08 1F 28 48 FE 88 88 8F 00;
0F20: 40 C0 40 E6 09 02 04 0F 40 C0 40 E2 06 0A 1F 02 40 C0 40 EF 01 07 01 0F;
0F38: 40 A0 20 4F E1 07 01 0F C0 60 18 06 18 60 80 FE 01 06 18 60 18 06 01 7F;
0F50: 00 01 06 1D 2A 2A 2A 1F 1B 8F 65 11 C9 A9 B1 F3 4C F7 F0 18 07 02 3E FE;
0F68: 7F 9F 31 41 81 81 F9 FD 88 02 40 00 88 41 00 91 40 01 88 00 40 04 80 11;
0F80: 00 30 58 FD FF 79 30 00 00 0C 1A BF FF 9E 0C 00 00 30 58 FD 3F F9 30 00;
0F98: 00 0C 1A BF FC 9F 0C 00 10 28 68 BC FC 78 10 38 BA EE AA 38 38 BA FE BA;
0FB0: BA FE BA 38 38 AA EE BA 00 E7 42 FF 9F FF 42 E7 00 E7 42 FF F9 FF 42 E7;
0FC8: 00 00 FC 1C 7F 63 3E 00 00 00 3F 38 FE C6 7C 00 FF 81 A5 81 81 A5 81 FF;
0FE0: E7 81 81 00 00 81 81 E7 00 04 08 FE 10 FE 20 40 18 24 24 20 10 10 10 10;
0FF8: 08 08 08 08 04 24 24 18;
END;

182
software/mif/MZ700_cgrom_jp.mif Normal file
View File

@@ -0,0 +1,182 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 4096;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00;
0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00;
0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00;
0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00;
0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00;
0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00;
00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00;
00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00;
00D8: 08 08 08 08 FF 08 08 08 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00;
00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00;
0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00;
0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00;
0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00;
0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10;
0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF;
0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10;
01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00;
01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F;
01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF;
01F8: 03 03 03 03 03 03 03 03 00 00 08 04 FE 04 08 00 08 1C 3E 7F 7F 1C 3E 00;
0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00;
0228: 00 00 10 20 7F 20 10 00 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00;
0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF;
0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF;
0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00;
0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00;
02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80;
02B8: 70 18 0C 06 0C 18 70 00 A0 50 A0 50 A0 50 A0 50 00 40 20 10 08 04 02 00;
02D0: AA 55 AA 55 AA 55 AA 55 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08;
02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08;
0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00;
0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 3C 08 00 00 62 64 08 10 26 46 00;
0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00;
0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00;
0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00;
0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00;
03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00;
03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02;
03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 00 08 08 08 2A 1C 08 00;
0408: 04 38 08 3E 08 08 10 00 00 3E 02 02 02 02 3E 00 00 22 22 12 02 04 18 00;
0420: 00 30 02 32 02 04 38 00 02 04 08 18 28 08 08 00 00 08 04 22 22 22 22 00;
0438: 08 3E 08 3E 08 08 08 00 00 1E 12 22 02 04 18 00 00 1C 00 00 00 00 3E 00;
0450: 00 3E 02 02 14 08 04 00 04 04 04 04 04 08 10 00 24 24 24 24 04 08 10 00;
0468: 00 3E 10 3E 10 10 0E 00 00 1C 00 1C 00 3C 02 00 1C 00 3E 02 02 04 08 00;
0480: 10 3E 12 14 10 10 0E 00 00 1E 12 2A 06 04 18 00 00 3E 02 04 08 14 22 00;
0498: 10 10 10 18 14 10 10 00 10 3E 12 12 12 12 24 00 08 08 3E 08 08 10 20 00;
04B0: 20 20 3E 20 20 20 1E 00 1C 00 3E 08 08 08 10 00 14 3E 14 14 04 08 10 00;
04C8: 00 30 00 02 02 04 38 00 00 2A 2A 2A 02 04 08 00 00 3E 22 22 22 22 3E 00;
04E0: 10 1E 24 04 04 04 08 00 1E 10 10 10 00 00 00 00 00 00 3E 02 0C 08 10 00;
04F8: 00 00 10 3E 12 14 10 00 00 3E 22 22 02 04 08 00 00 3E 02 14 08 14 20 00;
0510: 00 3E 02 02 02 04 18 00 3E 02 0A 0C 08 08 10 00 08 3E 22 22 02 04 08 00;
0528: 00 3E 08 08 08 08 3E 00 04 3E 04 0C 14 24 04 00 10 10 3E 12 14 10 10 00;
0540: 00 1C 04 04 04 04 3E 00 00 3E 02 3E 02 02 3E 00 08 3E 08 08 2A 2A 08 00;
0558: 00 10 28 04 02 02 00 00 00 20 20 22 24 28 30 00 00 02 02 14 08 14 20 00;
0570: 00 08 28 28 2A 2A 2C 00 08 3E 04 08 1C 2A 08 00 00 08 10 20 22 3E 02 00;
0588: 00 00 00 08 08 08 78 00 00 00 04 08 18 28 08 00 00 00 00 1C 04 04 3E 00;
05A0: 00 3E 02 3E 02 04 08 00 00 00 00 00 40 20 10 00 00 00 08 3E 22 02 0C 00;
05B8: 00 00 3C 04 3C 04 3C 00 70 50 70 00 00 00 00 00 00 00 00 00 00 00 20 00;
05D0: 00 00 00 3E 08 08 3E 00 00 00 00 2A 2A 02 0C 00 10 48 20 00 00 00 00 00;
05E8: 00 00 00 00 70 50 70 00 00 00 04 3E 0C 14 24 00 00 00 00 1C 00 00 00 00;
0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF;
0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BB BB BB 83 BB BB BB FF;
0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00;
0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00;
0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C;
0678: 3C 42 81 A5 81 99 42 3C 3E 22 22 3E 22 22 3E 00 3E 22 3E 22 3E 22 42 00;
0690: 08 2A 2A 08 14 22 41 00 08 09 3A 0C 1C 2A 49 00 08 08 3E 08 1C 2A 49 00;
06A8: 08 14 3E 49 3E 1C 7F 00 00 08 08 3E 08 08 7F 00 08 48 7E 48 3E 08 7F 00;
06C0: 20 3E 48 3C 28 7E 08 00 04 7E 54 7F 52 7F 0A 00 08 14 22 7F 12 12 24 00;
06D8: 38 12 7F 17 3B 52 14 00 7F 49 49 7F 41 41 41 00 22 14 3E 08 3E 08 08 00;
06F0: 0C 12 10 38 10 10 3E 00 00 C0 C8 54 54 55 22 00;
0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02;
0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00;
0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23;
0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80;
0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04;
0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70;
07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07;
07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77 00 00 00 00 00 00 00 00;
0808: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00;
0820: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00;
0838: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00;
0850: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00;
0868: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00;
0880: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00;
0898: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 42 3C 00;
08B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00;
08C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 08 08 08 08 FF 08 08 08;
08E0: 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00 08 08 08 08 0F 08 08 08;
08F8: 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00 08 18 28 08 08 08 3E 00;
0910: 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00 04 0C 14 24 7E 04 04 00;
0928: 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00 7E 42 04 08 10 10 10 00;
0940: 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00 00 00 00 7E 00 00 00 00;
0958: 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
0970: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10 00 FF 00 00 00 00 00 00;
0988: 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 FF;
09A0: 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10 FF FF 00 00 00 00 00 00;
09B8: C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00 04 04 04 04 04 04 04 04;
09D0: 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F 00 00 00 00 00 00 00 FF;
09E8: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF 03 03 03 03 03 03 03 03;
0A00: 00 00 08 04 FE 04 08 00 08 1C 3E 7F 7F 1C 3E 00 FF 7F 3F 1F 0F 07 03 01;
0A18: FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00 00 00 10 20 7F 20 10 00;
0A30: 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00 00 3C 42 42 42 42 3C 00;
0A48: 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF 00 00 00 00 03 04 08 08;
0A60: 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF 01 03 07 0F 1F 3F 7F FF;
0A78: 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00 0E 18 30 60 30 18 0E 00;
0A90: 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00 3C 04 04 04 04 04 3C 00;
0AA8: 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80 70 18 0C 06 0C 18 70 00;
0AC0: A0 50 A0 50 A0 50 A0 50 00 40 20 10 08 04 02 00 AA 55 AA 55 AA 55 AA 55;
0AD8: F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08 00 00 00 00 F8 08 08 08;
0AF0: 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08 00 00 01 3E 54 14 14 00;
0B08: 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00 24 24 7E 24 7E 24 24 00;
0B20: 08 1E 28 1C 0A 3C 08 00 00 62 64 08 10 26 46 00 30 48 48 30 4A 44 3A 00;
0B38: 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
0B50: 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00 0F 0F 0F 0F F0 F0 F0 F0;
0B68: 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00 08 08 04 03 00 00 00 00;
0B80: FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80 FF 80 80 80 80 80 80 80;
0B98: FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00 20 20 20 20 20 20 20 20;
0BB0: 04 08 11 22 44 88 10 20 20 10 88 44 22 11 08 04 00 00 00 00 FF 00 00 00;
0BC8: 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00 F0 F0 F0 F0 F0 F0 F0 F0;
0BE0: 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02 00 00 00 00 00 FF FF FF;
0BF8: 07 07 07 07 07 07 07 07 00 08 08 08 2A 1C 08 00 10 FE 20 7C 02 02 FC 00;
0C10: 00 FC 02 00 00 80 7E 00 3C 08 10 7E 08 10 0C 00 40 40 40 40 44 44 38 00;
0C28: 84 82 82 82 82 90 60 00 84 9E 84 84 9C A6 5C 00 10 7E 08 7E 04 02 60 18;
0C40: 0C 18 30 60 30 18 0C 00 9E 80 80 80 80 90 DE 00 10 7E 10 7E 10 70 9C 72;
0C58: 38 54 92 92 92 92 64 00 44 44 44 64 04 08 10 00 20 F8 20 F8 22 22 1C 00;
0C70: 70 10 14 7E 94 94 64 00 60 00 9C A2 C2 82 1C 00 44 44 FE 44 58 40 3E 00;
0C88: 20 FC 40 5E 80 A0 BE 00 08 FE 08 38 48 38 08 10 20 22 2C 30 40 80 7E 00;
0CA0: 22 F9 25 24 24 24 48 00 20 FA 41 44 9C A6 1C 00 E0 26 45 84 84 88 70 00;
0CB8: FE 04 08 10 10 08 04 00 20 FE 10 08 44 20 18 00 10 20 20 70 48 88 86 00;
0CD0: 80 7C 02 02 02 04 18 00 7C 08 10 2C 42 02 24 18 84 BE 84 84 84 84 48 00;
0CE8: 1E 10 10 10 00 00 00 00 00 20 70 20 78 94 68 00 00 00 58 E4 28 20 10 00;
0D00: 20 E4 2A 32 62 A2 24 00 04 44 7C 4A B2 97 66 00 38 00 10 4A 4A 8A 30 00;
0D18: 20 FC 20 7C AA 92 64 00 18 00 3C 42 02 04 08 00 10 00 7C 08 10 28 46 00;
0D30: 20 FD 21 7C A2 A2 64 00 48 4C 32 E2 24 10 10 08 08 9C AA CA CA 8C 18 00;
0D48: 08 0E 08 08 78 8E 78 00 9E 84 9E 84 9C A6 DC 00 00 20 50 88 04 02 02 00;
0D60: 20 E6 2C 34 64 A4 22 00 04 44 7C 4A B2 92 64 00 7C 08 10 3C 42 1A 24 18;
0D78: 20 E4 2A 32 66 AB 26 00 20 FD 21 60 A0 62 3E 00 00 00 00 00 08 08 08 78;
0D90: 00 00 48 44 44 44 20 00 00 00 10 B8 D4 98 30 00 10 FE 20 74 B8 48 7E 00;
0DA8: 00 00 00 00 00 40 20 10 00 20 00 78 04 04 08 00 00 00 20 38 20 78 60 00;
0DC0: 70 50 70 00 00 00 00 00 00 00 00 00 00 00 20 00 00 20 00 78 10 30 4C 00;
0DD8: 00 00 00 F8 04 04 18 00 20 90 40 00 00 00 00 00 00 00 00 00 00 70 50 70;
0DF0: 00 20 74 20 78 A4 68 00 00 00 00 1C 00 00 00 00;
0E00: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF;
0E18: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BB BB BB 83 BB BB BB FF;
0E30: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00;
0E48: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00;
0E60: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C;
0E78: 3C 42 81 A5 81 99 42 3C 3E 22 22 3E 22 22 3E 00 3E 22 3E 22 3E 22 42 00;
0E90: 08 2A 2A 08 14 22 41 00 08 09 3A 0C 1C 2A 49 00 08 08 3E 08 1C 2A 49 00;
0EA8: 08 14 3E 49 3E 1C 7F 00 00 08 08 3E 08 08 7F 00 08 48 7E 48 3E 08 7F 00;
0EC0: 20 3E 48 3C 28 7E 08 00 04 7E 54 7F 52 7F 0A 00 08 14 22 7F 12 12 24 00;
0ED8: 38 12 7F 17 3B 52 14 00 7F 49 49 7F 41 41 41 00 22 14 3E 08 3E 08 08 00;
0EF0: 0C 12 10 38 10 10 3E 00 00 C0 C8 54 54 55 22 00 00 00 00 00 00 02 FF 02;
0F08: 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02 00 00 20 50 88 05 02 00;
0F20: 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00 00 70 88 44 23 20 40 80;
0F38: 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23 88 90 A0 C0 C0 A8 98 B8;
0F50: A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80 00 00 24 24 E7 24 24 00;
0F68: 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04 55 AA 55 AA 55 AA 55 AA;
0F80: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00 00 07 07 07 00 00 00 00;
0F98: 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
0FB0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70 00 00 00 00 00 07 07 07;
0FC8: 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
0FE0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77 00 07 07 07 00 77 77 77;
0FF8: 00 77 77 77 00 77 77 77;
END;

96
software/mif/MZ80B.mif Normal file
View File

@@ -0,0 +1,96 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 2048;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 18 04 3E 03 D3 E3 3E 82 D3 E3 3E 0F D3 E9 3E CF D3 EB 3E FF D3 EB 3E 58;
0018: D3 E2 3E 12 D3 E0 AF D3 F4 31 E0 FF 21 00 D0 3E B3 D3 E8 36 00 23 7C B5;
0030: 20 F9 3E 13 D3 E8 AF 32 EC FF 32 E6 FF CD 4B 00 CB 5F 28 27 CB 47 CA EF;
0048: 05 18 0C 06 14 DB E8 E6 F0 B0 D3 E8 DB EA C9 CD 5F 00 CA 3C 03 18 0C 3E;
0060: A5 47 D3 D9 CD D6 05 DB D9 B8 C9 CD B5 01 CD 1D 02 CD CE 01 CD AE 00 38;
0078: 17 CD 30 02 21 01 CF 1E 10 0E 10 CD 39 02 3A 00 CF FE 01 20 11 CD CF 00;
0090: F5 CD 1D 02 CD 0B 02 F1 DA 5F 05 C3 02 00 21 26 03 1E 0A 0E 0F CD 46 02;
00A8: CD B5 01 37 18 E2 F3 16 04 01 80 00 21 00 CF CD 86 01 38 0E CD 52 01 38;
00C0: 09 CD DB 00 38 04 CB 5A 28 03 CD B5 01 FB C9 F3 16 08 ED 4B 12 CF 21 00;
00D8: 80 18 DC D5 C5 E5 26 02 CD 7A 01 38 38 28 F9 54 21 00 00 22 E0 FF E1 C1;
00F0: C5 E5 CD 32 01 38 26 77 23 0B 78 B1 20 F4 2A E0 FF CD 32 01 38 17 5F CD;
0108: 32 01 38 11 BD 20 04 7B BC 28 0A 15 28 03 62 18 C7 CD 3F 02 37 E1 C1 D1;
0120: C9 DB E1 2F 07 D8 07 30 F8 DB E1 2F 07 D8 07 38 F8 C9 E5 21 00 08 CD 7A;
0138: 01 38 15 28 0A E5 2A E0 FF 23 22 E0 FF E1 37 CB 15 25 20 EA CD 21 01 7D;
0150: E1 C9 E5 21 14 14 CB 5A 20 01 29 22 E2 FF 2A E2 FF CD 7A 01 38 EA 28 F6;
0168: 25 20 F6 CD 7A 01 38 E0 20 EC 2D 20 F6 CD 21 01 18 D6 CD 21 01 D8 CD 29;
0180: 02 DB E1 E6 40 C9 D5 C5 E5 DB E1 E6 20 28 1F 21 8B 02 1E 0A 0E 0E CD 46;
0198: 02 CD C2 01 DB EA 2F 07 38 0F DB E1 E6 20 20 F4 CD CE 01 CD 23 02 CD D9;
01B0: 01 E1 C1 D1 C9 3E 0D D3 E3 3E 1A D3 E0 CD 1D 02 18 2D 3E 08 D3 E3 CD 1D;
01C8: 02 3E 09 D3 E3 C9 21 6F 02 1E 04 0E 1C CD 46 02 C9 CD F4 01 CD 1D 02 3E;
01E0: 16 D3 E0 18 0A CD 1D 02 CD EF 01 3E 13 D3 E0 3E 12 D3 E0 C9 3E 12 D3 E0;
01F8: CD 1D 02 3E 0B D3 E3 CD 1D 02 3E 0A D3 E3 C9 3E 10 18 EB CD 07 02 18 D5;
0210: F5 AF 3D 20 FD 0B 78 B1 20 F7 F1 C1 C9 C5 01 E9 00 18 ED C5 01 0F 06 18;
0228: E7 3E 31 3D C2 2B 02 C9 21 61 02 1E 00 0E 0E 18 0D 3E 93 D3 E8 18 17 21;
0240: 99 02 1E 0A 0E 0D 3E 93 D3 E8 D9 21 00 D0 36 00 23 7C B5 20 F9 D9 AF 47;
0258: 16 D0 ED B0 3E 13 D3 E8 C9 49 50 4C 20 69 73 20 6C 6F 61 64 69 6E 67 49;
0270: 50 4C 20 69 73 20 6C 6F 6F 6B 69 6E 67 20 66 6F 72 20 61 20 70 72 6F 67;
0288: 72 61 6D 4D 61 6B 65 20 72 65 61 64 79 20 43 4D 54 4C 6F 61 64 69 6E 67;
02A0: 20 65 72 72 6F 72 4D 61 6B 65 20 72 65 61 64 79 20 46 44 50 72 65 73 73;
02B8: 20 46 20 6F 72 20 43 46 3A 46 6C 6F 70 70 79 20 64 69 73 6B 65 74 74 65;
02D0: 43 3A 43 61 73 73 65 74 74 65 20 74 61 70 65 44 72 69 76 65 20 4E 6F 3F;
02E8: 20 28 31 2D 34 29 54 68 69 73 20 64 69 73 6B 65 74 74 65 20 69 73 20 6E;
0300: 6F 74 20 6D 61 73 74 65 72 50 72 65 73 73 69 6E 67 20 53 20 6B 65 79 20;
0318: 73 74 61 72 74 73 20 74 68 65 20 43 4D 54 46 69 6C 65 20 6D 6F 64 65 20;
0330: 65 72 72 6F 72 01 49 50 4C 50 52 4F DD 21 00 CF AF 32 1E CF 32 1F CF FD;
0348: 21 E0 FF 21 00 01 FD 75 02 FD 74 03 CD 7A 04 21 00 CF 11 35 03 06 06 4E;
0360: 1A B9 C2 4A 05 23 13 10 F6 CD 30 02 21 07 CF 1E 10 0E 0A CD 39 02 DD 21;
0378: 00 80 2A 14 CF FD 75 02 FD 74 03 CD 7A 04 CD F3 03 C3 02 00 21 A6 02 1E;
0390: 0A 0E 0D CD 46 02 C3 59 05 3A E6 FF 0F D4 CC 03 3A EC FF F6 84 D3 DC AF;
03A8: CD E4 05 21 00 00 2B 7C B5 28 D9 DB D8 2F 07 38 F5 3A EC FF 4F 21 E7 FF;
03C0: 06 00 09 CB 46 C0 CD 09 04 CB C6 C9 3E 80 D3 DC 06 0A 21 19 3C 2B 7D B4;
03D8: 20 FB 10 F6 3E 01 32 E6 FF C9 3E 1B 2F D3 D8 CD 21 04 CD E4 05 DB D8 2F;
03F0: E6 99 C9 CD DD 05 AF D3 DC 32 E7 FF 32 E8 FF 32 E9 FF 32 EA FF 32 E6 FF;
0408: C9 E5 3E 0B 2F D3 D8 CD 21 04 CD E4 05 DB D8 2F E6 85 EE 04 E1 C8 C3 56;
0420: 05 D5 E5 CD D6 05 1E 07 21 00 00 2B 7C B5 28 09 DB D8 2F 0F 38 F5 E1 D1;
0438: C9 1D 20 EC C3 56 05 06 00 11 10 00 2A 1E CF AF ED 52 38 03 04 18 F9 19;
0450: 60 2C FD 74 04 FD 75 05 3A EC FF FE 04 30 18 FD 7E 04 FE 46 30 11 FD 7E;
0468: 05 B7 28 0B FE 11 30 07 FD 7E 02 FD B6 03 C0 C3 56 05 F3 CD 3F 04 3E 0A;
0480: 32 EB FF CD 99 03 FD 56 03 FD 7E 02 B7 28 01 14 FD 7E 05 FD 77 01 FD 7E;
0498: 04 FD 77 00 DD E5 E1 CB 3F 2F D3 DB 30 04 3E 01 18 02 3E 00 2F D3 DD CD;
04B0: E2 03 20 6A 0E DB FD 7E 00 CB 3F 2F D3 D9 FD 7E 01 2F D3 DA D9 21 F7 04;
04C8: E5 D9 3E 94 2F D3 D8 CD 2D 05 06 00 DB D8 0F D8 0F 38 F9 ED A2 20 F5 FD;
04E0: 34 01 FD 7E 01 FE 11 28 05 15 20 E6 18 01 15 3E D8 2F D3 D8 CD 21 04 DB;
04F8: D8 2F E6 FF 20 20 D9 E1 D9 FD 7E 01 FE 11 20 08 3E 01 FD 77 01 FD 34 00;
0510: 7A B7 20 05 3E 80 D3 DC C9 FD 7E 00 18 81 3A EB FF 3D 32 EB FF 28 2F CD;
0528: 09 04 C3 83 04 D5 E5 CD D6 05 1E 08 21 00 00 2B 7C B5 28 09 DB D8 2F 0F;
0540: 30 F5 E1 D1 C9 1D 20 EC 18 0C 21 EE 02 1E 07 0E 1B CD 46 02 18 03 CD 3F;
0558: 02 CD F3 03 31 E0 FF CD 5F 00 20 47 21 B3 02 1E 5A 0E 0C CD 39 02 1E AB;
0570: 0E 11 CD 39 02 1E D3 0E 0F CD 39 02 CD 4B 00 CB 5F CA 6B 00 CB 77 28 02;
0588: 18 F2 21 DF 02 1E 0A 0E 0F CD 46 02 16 12 CD C1 05 30 09 16 18 CD C1 05;
05A0: 30 02 18 F0 78 32 EC FF C3 3C 03 21 09 03 1E 54 0E 1D CD 39 02 06 06 CD;
05B8: 4D 00 CB 5F CA 6B 00 18 F6 DB E8 E6 F0 B2 D3 E8 DB EA 06 00 0E 04 0F 0F;
05D0: D0 04 0D 20 FA C9 D5 11 0D 00 C3 E8 05 D5 11 82 00 C3 E8 05 D5 11 2C 1A;
05E8: 1B 7B B2 20 FB D1 C9 21 00 80 DD 21 F8 05 18 1A DB F9 FE 00 C2 57 00 DD;
0600: 21 05 06 18 0D DB F9 77 23 7D B4 20 F6 D3 F8 C3 02 00 7C D3 F8 7D D3 F9;
0618: 16 04 15 20 FD DD E9 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0630: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0648: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0660: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0678: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0690: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
06A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
06C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
06D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
06F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0700: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0718: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0730: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0748: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0760: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0778: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
0790: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
07A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
07C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
07D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
07F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF;
END;

96
software/mif/MZ80K2E_Jap_cgrom.mif Normal file
View File

@@ -0,0 +1,96 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 2048;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00;
0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00;
0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00;
0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00;
0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00;
0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00;
00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00;
00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00;
00D8: 08 08 08 08 FF 08 08 08 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00;
00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00;
0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00;
0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00;
0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00;
0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10;
0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF;
0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10;
01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00;
01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F;
01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF;
01F8: 03 03 03 03 03 03 03 03 00 00 00 00 00 00 00 00 08 1C 3E 7F 7F 1C 3E 00;
0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00;
0228: 00 00 10 20 7F 20 10 00 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00;
0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF;
0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF;
0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00;
0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00;
02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80;
02B8: 70 18 0C 06 0C 18 70 00 A0 50 A0 50 A0 50 A0 50 00 40 20 10 08 04 02 00;
02D0: AA 55 AA 55 AA 55 AA 55 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08;
02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08;
0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00;
0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00;
0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00;
0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00;
0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00;
0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00;
03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00;
03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02;
03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 00 00 00 00 00 00 00 00;
0408: 04 38 08 3E 08 08 10 00 00 3E 02 02 02 02 3E 00 00 22 22 12 02 04 18 00;
0420: 00 30 02 32 02 04 38 00 02 04 08 18 28 08 08 00 00 08 04 22 22 22 22 00;
0438: 08 3E 08 3E 08 08 08 00 00 1E 12 22 02 04 18 00 00 1C 00 00 00 00 3E 00;
0450: 00 3E 02 02 14 08 04 00 04 04 04 04 04 08 10 00 24 24 24 24 04 08 10 00;
0468: 00 3E 10 3E 10 10 0E 00 00 1C 00 1C 00 3C 02 00 1C 00 3E 02 02 04 08 00;
0480: 10 3E 12 14 10 10 0E 00 00 1E 12 2A 06 04 18 00 00 3E 02 04 08 14 22 00;
0498: 10 10 10 18 14 10 10 00 10 3E 12 12 12 12 24 00 08 08 3E 08 08 10 20 00;
04B0: 20 20 3E 20 20 20 1E 00 1C 00 3E 08 08 08 10 00 14 3E 14 14 04 08 10 00;
04C8: 00 30 00 02 02 04 38 00 00 2A 2A 2A 02 04 08 00 00 3E 22 22 22 22 3E 00;
04E0: 10 1E 24 04 04 04 08 00 1E 10 10 10 00 00 00 00 00 00 3E 02 0C 08 10 00;
04F8: 00 00 10 3E 12 14 10 00 00 3E 22 22 02 04 08 00 00 3E 02 14 08 14 20 00;
0510: 00 3E 02 02 02 04 18 00 3E 02 0A 0C 08 08 10 00 08 3E 22 22 02 04 08 00;
0528: 00 3E 08 08 08 08 3E 00 04 3E 04 0C 14 24 04 00 10 10 3E 12 14 10 10 00;
0540: 00 1C 04 04 04 04 3E 00 00 3E 02 3E 02 02 3E 00 08 3E 08 08 2A 2A 08 00;
0558: 00 10 28 04 02 02 00 00 00 20 20 22 24 28 30 00 00 02 02 14 08 14 20 00;
0570: 00 08 28 28 2A 2A 2C 00 08 3E 04 08 1C 2A 08 00 00 08 10 20 22 3E 02 00;
0588: 00 00 00 08 08 08 78 00 00 00 04 08 18 28 08 00 00 00 00 1C 04 04 3E 00;
05A0: 00 3E 02 3E 02 04 08 00 00 00 00 00 40 20 10 00 00 00 08 3E 22 02 0C 00;
05B8: 00 00 3C 04 3C 04 3C 00 70 50 70 00 00 00 00 00 00 00 00 00 00 00 20 00;
05D0: 00 00 00 3E 08 08 3E 00 00 00 00 2A 2A 02 0C 00 10 48 20 00 00 00 00 00;
05E8: 00 00 00 00 70 50 70 00 00 00 04 3E 0C 14 24 00 00 00 00 1C 00 00 00 00;
0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF;
0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BB BB BB 81 BB BB BB FF;
0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00;
0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00;
0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C;
0678: 3C 42 81 A5 81 99 42 3C 3E 22 22 3E 22 22 3E 00 3E 22 3E 22 3E 22 42 00;
0690: 08 2A 2A 08 14 22 41 00 08 09 3A 0C 1C 2A 49 00 08 08 3E 08 1C 2A 49 00;
06A8: 08 14 3E 49 3E 1C 7F 00 00 08 08 3E 08 08 7F 00 08 48 7E 48 3E 08 7F 00;
06C0: 20 3E 48 3C 28 7E 08 00 04 7E 54 7F 52 7F 0A 00 08 14 22 7F 12 12 24 00;
06D8: 38 12 7F 17 3B 52 14 00 7F 49 49 7F 41 41 41 00 22 14 3E 08 3E 08 08 00;
06F0: 0C 12 10 38 10 10 3E 00 00 C0 C8 54 54 55 22 00;
0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02;
0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00;
0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23;
0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80;
0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04;
0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70;
07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07;
07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
END;

96
software/mif/MZ80K_cgrom.mif Normal file
View File

@@ -0,0 +1,96 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 2048;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00;
0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00;
0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00;
0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00;
0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00;
0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00;
00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00;
00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00;
00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00;
00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00;
0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00;
0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00;
0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00;
0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10;
0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF;
0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10;
01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00;
01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F;
01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF;
01F8: 03 03 03 03 03 03 03 03 00 00 00 00 00 00 00 00 08 1C 3E 7F 7F 1C 3E 00;
0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00;
0228: 00 00 10 20 7F 20 10 00 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00;
0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF;
0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF;
0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00;
0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00;
02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80;
02B8: 70 18 0C 06 0C 18 70 00 00 08 08 08 2A 1C 08 00 00 40 20 10 08 04 02 00;
02D0: 00 00 04 02 7F 02 04 00 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08;
02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08;
0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00;
0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00;
0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00;
0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00;
0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00;
0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00;
03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00;
03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02;
03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 00 00 00 00 00 00 00 00;
0408: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00;
0420: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00;
0438: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00;
0450: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00;
0468: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00;
0480: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00;
0498: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 42 3C 00;
04B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00;
04C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 24 00 38 04 3C 44 3A 00;
04E0: 00 00 00 01 02 04 08 10 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00;
04F8: 00 00 00 80 40 20 10 08 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00;
0510: 44 44 44 44 44 44 44 44 44 FF 44 44 44 FF 44 44 22 44 88 11 22 44 88 11;
0528: 88 44 22 11 88 44 22 11 AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0;
0540: 03 0C 30 C0 00 00 00 00 C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00;
0558: 00 22 00 22 22 22 1C 00 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00;
0570: 42 18 24 42 7E 42 42 00 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80;
0588: 01 06 18 20 20 40 40 80 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
05A0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80;
05B8: 01 01 02 02 02 04 04 08 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03;
05D0: 00 00 00 00 01 06 38 C0 08 10 20 40 80 00 00 00 22 14 3E 08 3E 08 08 00;
05E8: 08 08 08 08 FF 08 08 08 24 24 24 24 C3 81 42 3C 00 3C 7A A9 A9 7A 3C 00;
0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF;
0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF;
0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00;
0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00;
0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF 67 7E 3C;
0678: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05;
0690: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55;
06A8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55;
06C0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01;
06D8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08;
06F0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00;
0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02;
0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00;
0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 49 F1 49 25 23;
0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80;
0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04;
0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70;
07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07;
07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
END;

96
software/mif/MZFONT.mif Normal file
View File

@@ -0,0 +1,96 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 2048;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 1C 14 14 77 22 14 08 00 08 14 22 77 14 14 1C 00;
0018: 08 0C 7A 41 7A 0C 08 00 08 18 2F 41 2F 18 08 00 77 55 5D 41 5D 55 77 00;
0030: 1E 21 4F 50 4F 21 1E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0048: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0078: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00A8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00D8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00F0: 00 00 00 00 00 00 00 00 AA 55 AA 55 AA 55 AA 55 00 00 00 00 00 00 00 00;
0108: 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00 24 24 7E 24 7E 24 24 00;
0120: 08 1E 28 1C 0A 3C 08 00 00 62 64 08 10 26 46 00 30 48 48 30 4A 44 3A 00;
0138: 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
0150: 08 2A 1C 3E 1C 2A 08 00 00 08 08 3E 08 08 00 00 00 00 00 00 00 08 08 10;
0168: 00 00 00 7E 00 00 00 00 00 00 00 00 00 18 18 00 00 02 04 08 10 20 40 00;
0180: 3C 42 46 5A 62 42 3C 00 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00;
0198: 3C 42 02 3C 02 42 3C 00 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00;
01B0: 1C 20 40 7C 42 42 3C 00 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00;
01C8: 3C 42 42 3E 02 04 38 00 00 00 08 00 00 08 00 00 00 00 08 00 00 08 08 10;
01E0: 0E 18 30 60 30 18 0E 00 00 00 7E 00 7E 00 00 00 70 18 0C 06 0C 18 70 00;
01F8: 3C 42 02 0C 10 00 10 00 1C 22 4A 56 4C 20 1E 00 18 24 42 7E 42 42 42 00;
0210: 7C 22 22 3C 22 22 7C 00 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00;
0228: 7E 40 40 78 40 40 7E 00 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00;
0240: 42 42 42 7E 42 42 42 00 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00;
0258: 42 44 48 70 48 44 42 00 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00;
0270: 42 62 52 4A 46 42 42 00 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00;
0288: 18 24 42 42 4A 24 1A 00 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00;
02A0: 3E 08 08 08 08 08 08 00 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00;
02B8: 42 42 42 5A 5A 66 42 00 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00;
02D0: 7E 02 04 18 20 40 7E 00 3C 20 20 20 20 20 3C 00 00 40 20 10 08 04 02 00;
02E8: 3C 04 04 04 04 04 3C 00 08 14 22 00 00 00 00 00 FF 00 00 00 00 00 00 00;
0300: 20 10 08 00 00 00 00 00 00 00 3C 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00;
0318: 00 00 3C 42 40 42 3C 00 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00;
0330: 0C 12 10 7C 10 10 10 00 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00;
0348: 08 00 18 08 08 08 1C 00 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00;
0360: 18 08 08 08 08 08 1C 00 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00;
0378: 00 00 3C 42 42 42 3C 00 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02;
0390: 00 00 5C 62 40 40 40 00 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00;
03A8: 00 00 42 42 42 46 3A 00 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
03C0: 00 00 42 24 18 24 42 00 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00;
03D8: 08 10 10 20 10 10 08 00 18 18 18 18 18 18 18 00 10 08 08 04 08 08 10 00;
03F0: 00 00 00 32 4C 00 00 00 00 7C 04 04 15 0E 04 00 28 28 28 28 28 28 28 28;
0408: 00 08 08 08 2A 1C 08 00 00 08 1C 2A 08 08 08 00 00 08 04 7E 04 08 00 00;
0420: 00 10 20 7E 20 10 00 00 08 1C 3E 7F 7F 1C 3E 00 36 7F 7F 7F 3E 1C 08 00;
0438: 08 1C 3E 7F 3E 1C 08 00 1C 1C 6B 7F 6B 08 1C 00 10 10 10 1F 1F 10 10 10;
0450: 10 10 10 F0 F0 10 10 10 00 00 00 FF 28 28 28 28 28 28 28 FF 00 00 00 00;
0468: 28 28 28 FF FF 28 28 28 10 10 10 FF FF 10 10 10 28 28 28 FF 28 28 28 28;
0480: 00 00 00 FF FF 00 00 00 22 14 3E 08 3E 08 08 00 0C 12 10 38 10 10 3E 00;
0498: 00 3C 7E 7E 7E 7E 3C 00 00 3C 42 42 42 42 3C 00 00 00 00 F0 10 10 10 10;
04B0: 10 10 10 F0 00 00 00 00 00 00 00 1F 10 10 10 10 10 10 10 1F 00 00 00 00;
04C8: 10 10 10 FF 10 10 10 10 10 10 10 10 10 10 10 10 00 00 00 FF 00 00 00 00;
04E0: 10 10 10 FF 00 00 00 00 00 00 00 FF 10 10 10 10 10 10 10 F0 10 10 10 10;
04F8: 10 10 10 1F 10 10 10 10 FF FF FF FF FF FF FF FF F7 F7 F7 F7 FF FF F7 FF;
0510: DB DB DB FF FF FF FF FF DB DB 81 DB 81 DB DB FF F7 E1 D7 E3 F5 C3 F7 FF;
0528: FF 9D 9B F7 EF D9 B9 FF CF B7 B7 CF B5 BB C5 FF FB F7 EF FF FF FF FF FF;
0540: FB F7 EF EF EF F7 FB FF DF EF F7 F7 F7 EF DF FF F7 D5 E3 C1 E3 D5 F7 FF;
0558: FF F7 F7 C1 F7 F7 FF FF FF FF FF FF FF F7 F7 EF FF FF FF 81 FF FF FF FF;
0570: FF FF FF FF FF E7 E7 FF FF FD FB F7 EF DF BF FF C3 BD B9 A5 9D BD C3 FF;
0588: F7 E7 D7 F7 F7 F7 C1 FF C3 BD FD F3 CF BF 81 FF C3 BD FD C3 FD BD C3 FF;
05A0: FB F3 EB DB 81 FB FB FF 81 BF 87 FB FD BB C7 FF E3 DF BF 83 BD BD C3 FF;
05B8: 81 BD FB F7 EF EF EF FF C3 BD BD C3 BD BD C3 FF C3 BD BD C1 FD FB C7 FF;
05D0: FF FF F7 FF FF F7 FF FF FF FF F7 FF FF F7 F7 EF F1 E7 CF 9F CF E7 F1 FF;
05E8: FF FF 81 FF 81 FF FF FF 8F E7 F3 F9 F3 E7 8F FF C3 BD FD F3 EF FF EF FF;
0600: E3 DD B5 A9 B3 DF E1 FF E7 DB BD 81 BD BD BD FF 83 DD DD C3 DD DD 83 FF;
0618: E3 DD BF BF BF DD E3 FF 87 DB DD DD DD DB 87 FF 81 BF BF 87 BF BF 81 FF;
0630: 81 BF BF 87 BF BF BF FF E3 DD BF B1 BD DD E3 FF BD BD BD 81 BD BD BD FF;
0648: E3 F7 F7 F7 F7 F7 E3 FF F1 FB FB FB FB BB C7 FF BD BB B7 8F B7 BB BD FF;
0660: BF BF BF BF BF BF 81 FF BD 99 A5 A5 BD BD BD FF BD 9D AD B5 B9 BD BD FF;
0678: E7 DB BD BD BD DB E7 FF 83 BD BD 83 BF BF BF FF E7 DB BD BD B5 DB E5 FF;
0690: 83 BD BD 83 B7 BB BD FF C3 BD BF C3 FD BD C3 FF C1 F7 F7 F7 F7 F7 F7 FF;
06A8: BD BD BD BD BD BD C3 FF BD BD BD DB DB E7 E7 FF BD BD BD A5 A5 99 BD FF;
06C0: BD BD DB E7 DB BD BD FF DD DD DD E3 F7 F7 F7 FF 81 FD FB E7 DF BF 81 FF;
06D8: C3 DF DF DF DF DF C3 FF FF BF DF EF F7 FB FD FF C3 FB FB FB FB FB C3 FF;
06F0: F7 EB DD FF FF FF FF FF 00 FF FF FF FF FF FF FF;
0700: DF EF F7 FF FF FF FF FF FF FF C3 FB C3 BB C5 FF BF BF A3 9D BD 9D A3 FF;
0718: FF FF C3 BD BF BD C3 FF FD FD C5 B9 BD B9 C5 FF FF FF C3 BD 81 BF C3 FF;
0730: F3 ED EF 83 EF EF EF FF FF FF C5 B9 B9 C5 FD C3 BF BF A3 9D BD BD BD FF;
0748: F7 FF E7 F7 F7 F7 E3 FF FB FF F3 FB FB FB BB C7 BF BF BB B7 AF 97 BB FF;
0760: E7 F7 F7 F7 F7 F7 E3 FF FF FF 89 B6 B6 B6 B6 FF FF FF A3 9D BD BD BD FF;
0778: FF FF C3 BD BD BD C3 FF FF FF A3 9D 9D A3 BF BF FF FF C5 B9 B9 C5 FD FD;
0790: FF FF A3 9D BF BF BF FF FF FF C1 BF C3 FD 83 FF EF EF 83 EF EF ED F3 FF;
07A8: FF FF BD BD BD B9 C5 FF FF FF BD BD BD DB E7 FF FF FF BE B6 B6 B6 C9 FF;
07C0: FF FF BD DB E7 DB BD FF FF FF BD BD B9 C5 FD C3 FF FF 81 FB E7 DF 81 FF;
07D8: F7 EF EF DF EF EF F7 FF E7 E7 E7 E7 E7 E7 E7 FF EF F7 F7 FB F7 F7 EF FF;
07F0: FF FF FF CD B3 FF FF FF 00 00 01 3E 54 14 14 00;
END;

39
software/mif/PALETTE_B.mif Normal file
View File

@@ -0,0 +1,39 @@
DEPTH = 512;
WIDTH = 5;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0040: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0050: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0060: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0070: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0080: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0090: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0100: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0110: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0120: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0130: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0140: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0150: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0160: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0170: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0180: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0190: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
END;

39
software/mif/PALETTE_G.mif Normal file
View File

@@ -0,0 +1,39 @@
DEPTH = 512;
WIDTH = 5;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0040: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0050: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0060: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0070: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0080: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0090: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0100: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0110: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0120: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0130: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0140: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0150: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0160: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0170: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0180: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0190: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
END;

39
software/mif/PALETTE_R.mif Normal file
View File

@@ -0,0 +1,39 @@
DEPTH = 512;
WIDTH = 5;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0040: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0050: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0060: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0070: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0080: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0090: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
00e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
00f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0100: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0110: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0120: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0130: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0140: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0150: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0160: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0170: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0180: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0190: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
01e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
01f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
END;

96
software/mif/mz-80acg.mif Normal file
View File

@@ -0,0 +1,96 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 2048;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00;
0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00;
0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00;
0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00;
0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00;
0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00;
00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00;
00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00;
00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00;
00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00;
0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00;
0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00;
0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00;
0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10;
0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF;
0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10;
01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00;
01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F;
01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF;
01F8: 03 03 03 03 03 03 03 03 10 08 08 04 08 08 10 00 08 1C 3E 7F 7F 1C 3E 00;
0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00;
0228: 00 00 10 20 7F 20 10 00 1C 1C 6B 7F 6B 08 1C 00 00 3C 7E 7E 7E 7E 3C 00;
0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF;
0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF;
0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00;
0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00;
02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80;
02B8: 70 18 0C 06 0C 18 70 00 00 08 08 08 2A 1C 08 00 00 40 20 10 08 04 02 00;
02D0: 00 00 04 02 7F 02 04 00 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08;
02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08;
0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00;
0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00;
0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00;
0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00;
0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00;
0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00;
03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00;
03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02;
03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 18 18 18 18 18 18 18 00;
0408: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00;
0420: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00;
0438: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00;
0450: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00;
0468: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00;
0480: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00;
0498: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 46 3A 00;
04B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00;
04C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 24 00 38 04 3C 44 3A 00;
04E0: 00 00 00 01 02 04 08 10 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00;
04F8: 00 00 00 80 40 20 10 08 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00;
0510: 44 44 44 44 44 44 44 44 44 FF 44 44 44 FF 44 44 20 10 08 00 00 00 00 00;
0528: 00 00 00 32 4C 00 00 00 AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0;
0540: 03 0C 30 C0 00 00 00 00 C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00;
0558: 00 22 00 22 22 26 1A 00 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00;
0570: 42 18 24 42 7E 42 42 00 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80;
0588: 01 06 18 20 20 40 40 80 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
05A0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80;
05B8: 01 01 02 02 02 04 04 08 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03;
05D0: 00 00 00 00 01 06 38 C0 08 10 20 40 80 00 00 00 08 10 10 20 10 10 08 00;
05E8: 08 08 08 08 FF 08 08 08 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7E 00;
0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF;
0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF;
0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00;
0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00;
0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C;
0678: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05;
0690: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55;
06A8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55;
06C0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01;
06D8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08;
06F0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00;
0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02;
0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 88 44 22 11 88 44 22 11;
0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 43 45 49 F1 49 45 43;
0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80;
0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04;
0778: 55 AA 55 AA 55 AA 55 AA 22 44 88 11 22 44 88 11 00 70 70 70 00 00 00 00;
0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70;
07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07;
07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
END;