189 lines
10 KiB
Tcl
189 lines
10 KiB
Tcl
## Generated SDC file "VideoController.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
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## DATE "Fri Jul 3 00:11:58 2020"
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##
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## DEVICE "EP3C25E144C8"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#create_generated_clock -name {vcpll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {vcpll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLOCK_50} [get_pins {vcpll|altpll_component|auto_generated|pll1|clk[0]}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[10]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[9]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[8]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[7]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[6]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[5]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[4]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[0]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[9]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[8]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[7]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[6]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[5]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[4]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[3]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[2]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[1]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[0]}]
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# Required for the Serial Flash Loader.
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tck}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdi}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tms}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_VS}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_HS}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNCn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSRVIDEO_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VHBLNK_OUTn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VHSY_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSYNCH_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVBLNK_OUTn}]
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# Required for the Serial Flash Loader.
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SFL:sfl|altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {altera_reserved_tdo}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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