From 82a4166db146c820f3241831b58cf7a85f76e196 Mon Sep 17 00:00:00 2001 From: Philip Smart Date: Mon, 2 Nov 2020 01:19:20 +0000 Subject: [PATCH] New video module developments --- .gitignore | 1 + CPLD/VideoInterface.vhd | 420 +++-- CPLD/VideoInterface_Toplevel.vhd | 28 +- CPLD/VideoInterface_pkg.vhd | 93 +- CPLD/build/VideoInterface.qsf | 36 +- CPLD/build/VideoInterface.srf | 33 + CPLD/build/VideoInterface_constraints.sdc | 37 +- FPGA/VideoController.vhd | 1826 ++++++++++++++------ FPGA/VideoController_Toplevel.vhd | 27 +- FPGA/VideoController_pkg.vhd | 90 +- FPGA/build/VideoController.qsf | 47 +- FPGA/build/VideoController_constraints.sdc | 10 +- software/mif/COLOURBOARD_CG.mif | 1382 +++++++++++++++ software/mif/MZ700_cgrom.mif | 182 ++ software/mif/MZ700_cgrom_jp.mif | 182 ++ software/mif/MZ80B.mif | 96 + software/mif/MZ80K2E_Jap_cgrom.mif | 96 + software/mif/MZ80K_cgrom.mif | 96 + software/mif/MZFONT.mif | 96 + software/mif/PALETTE_B.mif | 39 + software/mif/PALETTE_G.mif | 39 + software/mif/PALETTE_R.mif | 39 + software/mif/mz-80acg.mif | 96 + 23 files changed, 4191 insertions(+), 800 deletions(-) create mode 100644 software/mif/COLOURBOARD_CG.mif create mode 100644 software/mif/MZ700_cgrom.mif create mode 100644 software/mif/MZ700_cgrom_jp.mif create mode 100644 software/mif/MZ80B.mif create mode 100644 software/mif/MZ80K2E_Jap_cgrom.mif create mode 100644 software/mif/MZ80K_cgrom.mif create mode 100644 software/mif/MZFONT.mif create mode 100644 software/mif/PALETTE_B.mif create mode 100644 software/mif/PALETTE_G.mif create mode 100644 software/mif/PALETTE_R.mif create mode 100644 software/mif/mz-80acg.mif diff --git a/.gitignore b/.gitignore index 5e305db..84379ed 100644 --- a/.gitignore +++ b/.gitignore @@ -62,3 +62,4 @@ CPLD/VideoInterface.vhd.16mhz CPLD/VideoInterface_Toplevel.vhd.16mhz FPGA/build/core FPGA/vidsav +CPLD/build/VideoInterface.qws diff --git a/CPLD/VideoInterface.vhd b/CPLD/VideoInterface.vhd index 6ae1864..5695712 100644 --- a/CPLD/VideoInterface.vhd +++ b/CPLD/VideoInterface.vhd @@ -45,14 +45,13 @@ entity VideoInterface is CLOCK_50 : in std_logic; -- 50Hz base clock for system board, video timing and gate clocking. -- Z80 Address and Data. Address is muxed with video addressing, not direct. - -- A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board. + A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board. D : inout std_logic_vector(7 downto 0); -- Z80 Data bus, from the Colour Card CN! connector. -- Z80 Control signals. - -- WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector. + WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector. RDn : in std_logic; -- Z80 Read signal from the Colour Card CN! connector. RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board. - -- IORQn : in std_logic; -- Z80 IORQ signal from the tranZPUter board. -- Video and Mainboard signals. SRVIDEO_OUT : out std_logic; -- Shift Register 74LS165 Video Output onto mainboard. @@ -71,21 +70,20 @@ entity VideoInterface is VRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket. GTn : in std_logic; -- GATE signal from the Colour Card CN! connector. CSn : in std_logic; -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector. - -- MEM_CSn : in std_logic; -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board. OUTCLK : out std_logic; -- CPU signal serialiser clock. INDATA : in std_logic_vector(3 downto 0); -- Incoming serialised CPU signals. -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage. - VADDR : out std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address. + VADDR : out std_logic_vector(15 downto 0); -- Z80 Address bus, multiplexed with video address. VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector.. VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals. - VMEM_CSn : out std_logic; -- Extended memory select to FPGA. + --VMEM_CSn : out std_logic; -- Extended memory select to FPGA. VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket. - VIORQn : out std_logic; -- IORQn to FPGA. - VRDn : out std_logic; -- RDn to FPGA. + VZ80_IORQn : out std_logic; -- IORQn to FPGA. + VZ80_RDn : out std_logic; -- Z80_RDn from tranZPUter to FPGA. VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA. VGTn : out std_logic; -- Video Gate (GTn) - VWRn : out std_logic; -- WRn to FPGA. + VZ80_WRn : out std_logic; -- WRn to FPGA. -- VSRVIDEO_OUT : in std_logic; -- Video out from 74LS165 on mainboard, pre-GATE. VHBLNK_OUTn : in std_logic; -- Horizontal blanking. @@ -118,21 +116,53 @@ architecture rtl of VideoInterface is signal CLK31500i : std_logic; -- 8253 Clock base frequency used for RTC, signal ENASERCLK : std_logic; -- Enable serializer clock. - signal IORQn : std_logic; - signal MEM_CSn : std_logic; + signal S_IORQn : std_logic; -- Serialiser signal - IORQn + signal S_VIDEO_RDn : std_logic; -- Serialiser signal - Video FPGA RDn + signal S_VIDEO_WRn : std_logic; -- Serialiser signal - Video FPGA WRn signal INBUF : std_logic_vector(11 downto 0); - signal RCV_CYCLE : integer range 0 to 1; signal INCOUNT : integer range 0 to 3; - signal VA : std_logic_vector(14 downto 0); - signal CS_LAST_LEVEL : std_logic_vector(1 downto 0); -- Register to store the previous chip select level for edge detection. - signal CS_IO_FXX_n : std_logic; -- Chip select for block F0:FF - signal CS_CPLD_CTRL_n : std_logic; -- Chip select for the CPLD Control Register at 0xF0 + signal VA : std_logic_vector(15 downto 0); - signal MODE_MZ80A : std_logic := '1'; -- The System board is running in MZ80A mode. - signal MODE_MZ700 : std_logic := '0'; -- The System board is running in MZ700 mode. - signal MODE_MZ80B : std_logic := '0'; -- The System board is running in MZ80B mode. - signal MODE_CUSTOM : std_logic := '0'; -- The System board is running in custom mode. - signal CPLD_CTRL_REG : std_logic_vector(7 downto 0); -- Current value of the CPLD control register. + -- CPLD configuration signals. + signal MODE_CPLD_MZ80K : std_logic; + signal MODE_CPLD_MZ80C : std_logic; + signal MODE_CPLD_MZ1200 : std_logic; + signal MODE_CPLD_MZ80A : std_logic; + signal MODE_CPLD_MZ700 : std_logic; + signal MODE_CPLD_MZ800 : std_logic; + signal MODE_CPLD_MZ80B : std_logic; + signal MODE_CPLD_MZ2000 : std_logic; + signal MODE_CPLD_SWITCH : std_logic; + signal MODE_CPLD_MB_VIDEOn : std_logic; -- Mainboard video, 0 = enabled, 1 = disabled. + signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register. + + -- IO Decode signals. + signal CS_IO_6XXn : std_logic; -- IO decode for the 0x60-0x6f region used by the CPLD. + signal CS_IO_EXXn : std_logic; -- Chip select for block E0:EF + signal CS_IO_FXXn : std_logic; -- Chip select for block F0:FF + signal CS_CPLD_CFGn : std_logic; -- Select to set the CPLD configuration register. + signal CS_FB_VMn : std_logic; -- Chip Select for the Video Mode register. + signal CS_FB_PAGEn : std_logic; -- Chip Select for the Page select register. + signal CS_80B_PIOn : std_logic; -- Chip select for MZ80B PIO when in MZ80B mode. + signal CS_LAST_LEVEL : std_logic_vector(4 downto 0); -- Register to store the previous chip select level for edge detection. + signal CS_DXXXn : std_logic; -- Chip select range for the VRAM/ARAM. + signal CS_EXXXn : std_logic; -- Chip select range for the memory mapped I/O. + signal CS_DVRAMn : std_logic; -- Chip select for the Video RAM. + signal CS_DARAMn : std_logic; -- Chip select for the Attribute RAM. + + -- Video module signal mirrors. + signal MODE_VIDEO_MZ80A : std_logic := '1'; -- The machine is running in MZ80A mode. + signal MODE_VIDEO_MZ700 : std_logic := '0'; -- The machine is running in MZ700 mode. + signal MODE_VIDEO_MZ800 : std_logic := '0'; -- The machine is running in MZ800 mode. + signal MODE_VIDEO_MZ80B : std_logic := '0'; -- The machine is running in MZ80B mode. + signal MODE_VIDEO_MZ80K : std_logic := '0'; -- The machine is running in MZ80K mode. + signal MODE_VIDEO_MZ80C : std_logic := '0'; -- The machine is running in MZ80C mode. + signal MODE_VIDEO_MZ1200 : std_logic := '0'; -- The machine is running in MZ1200 mode. + signal MODE_VIDEO_MZ2000 : std_logic := '0'; -- The machine is running in MZ2000 mode. + signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable. + signal GRAM_MZ80B_ENABLE : std_logic; -- MZ80B Graphics memory enabled flag. + signal MZ80B_VRAM_HI_ADDR : std_logic; -- Video RAM located at D000:FFFF when high. + signal MZ80B_VRAM_LO_ADDR : std_logic; -- Video RAM located at 5000:7FFF when high. function to_std_logic(L: boolean) return std_logic is begin @@ -144,108 +174,64 @@ architecture rtl of VideoInterface is end function to_std_logic; begin - -- - -- Instantiation - -- - - -- Voltage translation. The FPGA is max 3.3v tolerant (as are nearly all FPGA's) so the 5V signals from the mainboard would have to go through a diode clamp - -- or converter. Given the pricing of the MAX7000 series chips it is easier and cheaper to use a CPLD to perform the voltage translation as they are 5V tolerant - -- and the mainboard accepts 3.3V output voltages. - -- - VADDR <= VA(13 downto 0); - - -- Data bus is muxed between the Z80 data bus and VRAMD which is the gated data bus after the video buffers. - -- The write signal WRn from the motherboard is actually a gated Write for the Video and Attribute RAM. The logic has been updated in the tranZPUter to - -- combine MEM_CSn with Z80 RD/WR such that use of RDn = 0 for read and RDn = 1 for write works as intended for all memory/IO operations. - -- - VDATA <= D when RDn = '1' and MEM_CSn = '0' -- All memory write data sent to FPGA in region D000:FFFF - else - D when RDn = '1' and IORQn = '0' -- All I/O write data sent to FPGA. - else - (others => 'Z'); - D <= VDATA when RDn = '0' and MEM_CSn = '0' and VA(13 downto 11) = "011" -- D800:DFFF via data bus. - else - VDATA when RDn = '0' and IORQn = '0' and ((VA(7 downto 4) = "1111" and VA(3 downto 0) > 3 and VA(3 downto 0) < 14) or VA(7 downto 5) = "000") -- I/O region F4:FD or 00:1F - else - CPLD_CTRL_REG when CS_CPLD_CTRL_n = '0' and RDn = '0' -- CPLD Control register at 0xF0 - else - (others => 'Z'); - VRAMD <= VDATA when RDn = '0' and MEM_CSn = '0' and VA(13 downto 11) = "010" -- D000:D7FF via IC16 74LS245. - else - (others => 'Z'); - VIORQn <= IORQn; - VRDn <= RDn; - VWRn <= '0' when RDn = '1' and (MEM_CSn = '0' or IORQn = '0') - else '1'; - VGTn <= GTn; - VCSn <= CSn; - VMEM_CSn <= MEM_CSn; - VVRAM_CS_INn <= VRAM_CS_INn; - - -- - -- CPU / RAM signals and selects. - -- - CS_IO_FXX_n <= '0' when IORQn = '0' and VA(7 downto 4) = "1111" - else '1'; - -- CPLD Control Register, 0xF0 - CS_CPLD_CTRL_n <= '0' when CS_IO_FXX_n = '0' and VA(3 downto 0) = "0000" - else '1'; - - -- A tranZPUter signal serializer. Signals required by the Video Module but not accessible physically (without hardware hacks) are captured and serialised by the tranZPUter - -- as a set of 4 x 4 blocks, clocked by the video interace CPLD, As the mainboard can not run faster than 4MHz, a 24MHz serialiser clock should be sufficient to bring the + -- as a set of x 4 blocks, clocked by the video interace CPLD, As the mainboard can not run faster than 4MHz, a 24MHz serialiser clock should be sufficient to bring the -- signals across but can be increased as necessary. -- Reset synchronises the Video Module CPLD with the tranZPUter CPLD and the signals are sent during valid mainboard accesses. During tranZPUter accesses, both - -- IORQn and MEM_CSn are sent as 0, an invalid state, to indicate the signals are not valid. + -- S_VIDEO_RDn and S_VIDEO_WRn are sent as 0, an invalid state, to indicate the signals are not valid. -- - SIGNALSERIALIZER: process(RESETn, CLK24Mi, ENASERCLK) + SIGNALSERIALIZER: process(RESETn, CLK16Mi, ENASERCLK) + variable RCV_CYCLE : integer range 0 to 1; begin -- Each reset the FPGA and CPLD are in sync, set the signals to the starting level ready to commence serialization. if RESETn = '0' then ENASERCLK <= '0'; - RCV_CYCLE <= 0; - INCOUNT <= 3; + RCV_CYCLE := 0; + INCOUNT <= 1; INBUF <= "000000000000"; - VA <= (others => '0'); - IORQn <= '1'; - MEM_CSn <= '1'; + VA(15 downto 11) <= (others => '0'); + S_IORQn <= '1'; + S_VIDEO_RDn <= '1'; + S_VIDEO_WRn <= '1'; - elsif falling_edge(CLK24Mi) then + elsif falling_edge(CLK16Mi) then case RCV_CYCLE is -- Cycle starts by enabling the clock which the tranZPUter sees the rising edge and captures the 16 signals and places the -- first block of 4 onto the mux-bus. when 0 => ENASERCLK <= '1'; - RCV_CYCLE <= 1; + RCV_CYCLE := 1; -- Each clock period, a block of signals are placed on the bus with sufficient time for the signals to settle and to capture them. when 1 => if INCOUNT > 0 then - INBUF(7 downto 0) <= INBUF(11 downto 4); - INBUF(11 downto 8) <= INDATA; + INBUF(3 downto 0) <= INDATA; --INBUF(7 downto 4); + --INBUF(7 downto 4) <= INDATA; INCOUNT <= INCOUNT - 1; else - -- If MEM_CSn and IORQn are both zero it indicates an invalid data set so dont act on it. + -- If S_VIDEO_WRn and S_VIDEO_RDn are both zero it indicates an invalid data set so dont act on it. -- - if INDATA(3 downto 2) /= "00" then - VA(13 downto 0) <= INDATA(1 downto 0) & INBUF(11 downto 0); - MEM_CSn <= INDATA(2); - IORQn <= INDATA(3); + if INDATA(3 downto 1) /= "000" then + VA(15 downto 11) <= INDATA(0) & INBUF(3 downto 0); + S_VIDEO_RDn <= INDATA(1); + S_VIDEO_WRn <= INDATA(2); + S_IORQn <= INDATA(3); else - VA(13 downto 0) <= (others => '0'); - MEM_CSn <= '1'; - IORQn <= '1'; + VA(15 downto 11) <= (others => '0'); + S_VIDEO_RDn <= '1'; + S_VIDEO_WRn <= '1'; + S_IORQn <= '1'; end if; - INCOUNT <= 3; + INCOUNT <= 1; end if; - RCV_CYCLE <= 1; + RCV_CYCLE := 1; end case; end if; -- Enable the clock directly onto the bus clock line when data required. if ENASERCLK = '1' then - OUTCLK <= CLK24Mi; + OUTCLK <= CLK16Mi; else OUTCLK <= '0'; end if; @@ -311,7 +297,7 @@ begin -- The 48MHz clock is used to create the base system clocks, 16MHz being the original machine base clock along with 4, 2 and 1MHz. -- This logic was originally performed by the MB14298 Gate Array on the mainboard. -- - SYSCLOCKS: process(RESETn, CLOCK_48, CLK24Mi, CLK4_8Mi, CLK4Mi, CLK3_54Mi, CLK2Mi, CLK1Mi, CLK31500i, MODE_MZ80A, MODE_MZ80B, MODE_MZ700, MODE_CUSTOM) + SYSCLOCKS: process(RESETn, CLOCK_48, CLK24Mi, CLK4_8Mi, CLK4Mi, CLK3_54Mi, CLK2Mi, CLK1Mi, CLK31500i, CPLD_CFG_DATA) variable counter24Mi : unsigned(1 downto 0); -- Binary divider to create 24Mi clock. variable counter16Mi : unsigned(1 downto 0); -- Binary divider to create 16Mi clock. variable counter4_8Mi : unsigned(2 downto 0); -- Binary divider to create 4_8Mi clock. @@ -397,17 +383,22 @@ begin -- CLK_31_5K_OUT <= CLK31500i; CLK_1MHZ_OUT <= CLK1Mi; - if MODE_MZ80A = '1' then - CLK_2MHZ_OUT <= CLK2Mi; - elsif MODE_MZ80B = '1' then - CLK_2MHZ_OUT <= CLK4Mi; - elsif MODE_MZ700 = '1' then - CLK_2MHZ_OUT <= CLK3_54Mi; - elsif MODE_CUSTOM = '1' then - CLK_2MHZ_OUT <= CLK4_8Mi; - else -- Additional modes go here. - CLK_2MHZ_OUT <= CLK2Mi; - end if; + case to_integer(unsigned(CPLD_CFG_DATA(6 downto 4))) is + when MODE_FREQ_MZ80A => + CLK_2MHZ_OUT <= CLK2Mi; + + when MODE_FREQ_MZ80B => + CLK_2MHZ_OUT <= CLK4Mi; + + when MODE_FREQ_MZ700 => + CLK_2MHZ_OUT <= CLK3_54Mi; + + when MODE_FREQ_CUSTOM => + CLK_2MHZ_OUT <= CLK4_8Mi; + + when others => + CLK_2MHZ_OUT <= CLK2Mi; + end case; end process; -- Process to subdivide the main 50MHz clock to obtain the MZ700 frequencies. @@ -432,54 +423,205 @@ begin end if; end process; - -- Control Registers. + -- Control Registers - This mirrors the Video Module control registers as we need to know when video memory is to be mapped into main memory. -- - -- I/O Port: - -- 0xF0 - [2;0] = Mainboard/CPU clock. - -- 000 = Sharp MZ80A 2MHz System Clock. - -- 001 = Sharp MZ80B 4MHz System Clock. - -- 010 = Sharp MZ700 3.54MHz System Clock. - -- 011 -111 = Reserved, defaults to 2MHz System Clock. - CTRLREGISTERS: process(RESETn, CLK16Mi) + -- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF8->. + -- 0xF8= sets the mode that of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. + -- 0xFD= memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. + -- + CTRLREGISTERS: process( RESETn, CLK16Mi, GRAM_PAGE_ENABLE, MZ80B_VRAM_HI_ADDR, MZ80B_VRAM_LO_ADDR ) begin + -- Ensure default values at reset. if RESETn = '0' then - MODE_MZ80A <= '1'; - MODE_MZ80B <= '0'; - MODE_MZ700 <= '0'; - MODE_CUSTOM <= '0'; - CPLD_CTRL_REG <= "00000000"; - + MODE_VIDEO_MZ80A <= '0'; + MODE_VIDEO_MZ700 <= '1'; + MODE_VIDEO_MZ800 <= '0'; + MODE_VIDEO_MZ80B <= '0'; + MODE_VIDEO_MZ80K <= '0'; + MODE_VIDEO_MZ80C <= '0'; + MODE_VIDEO_MZ1200 <= '0'; + MODE_VIDEO_MZ2000 <= '0'; + GRAM_PAGE_ENABLE <= "00"; + MZ80B_VRAM_HI_ADDR <= '0'; + MZ80B_VRAM_LO_ADDR <= '0'; + MODE_CPLD_SWITCH <= '0'; + CPLD_CFG_DATA <= "00000011"; + elsif rising_edge(CLK16Mi) then - -- Write to the CPLD Control Register? - if CS_CPLD_CTRL_n = '0' and CS_LAST_LEVEL(0) = '1' and RDn = '1' then - CPLD_CTRL_REG <= D; - MODE_MZ80A <= '0'; - MODE_MZ80B <= '0'; - MODE_MZ700 <= '0'; - MODE_CUSTOM <= '0'; + -- Write to config register. + -- CPLD Configuration register. + -- + -- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used + -- by host software such as RFS. + -- + -- [2:0] - Mode/emulated machine. + -- 000 = MZ-80K + -- 001 = MZ-80C + -- 010 = MZ-1200 + -- 011 = MZ-80A + -- 100 = MZ-700 + -- 101 = MZ-800 + -- 110 = MZ-80B + -- 111 = MZ-2000 + -- [3] - Mainboard Video - 1 = Enable, 0 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions + -- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality. + -- [6:4] = Mainboard/CPU clock. + -- 000 = Sharp MZ80A 2MHz System Clock. + -- 001 = Sharp MZ80B 4MHz System Clock. + -- 010 = Sharp MZ700 3.54MHz System Clock. + -- 011 -111 = Reserved, defaults to 2MHz System Clock. + -- + if(CS_CPLD_CFGn = '0' and CS_LAST_LEVEL(0) = '1' and S_VIDEO_WRn = '0') then - -- Bits 2:0 select the system clock which drives the mainboard/CPU. + -- Set the mode switch event flag if the mode changes. + if CPLD_CFG_DATA(2 downto 0) /= D(2 downto 0) then + MODE_CPLD_SWITCH <= '1'; + end if; + + -- Store the new value into the register, used for read operations. + CPLD_CFG_DATA <= D; + else + MODE_CPLD_SWITCH <= '0'; + end if; + + -- Setup the video mode. + if CS_FB_VMn = '0' and CS_LAST_LEVEL(1) = '1' and S_VIDEO_WRn = '0' then + MODE_VIDEO_MZ80K <= '0'; + MODE_VIDEO_MZ80C <= '0'; + MODE_VIDEO_MZ1200 <= '0'; + MODE_VIDEO_MZ80A <= '0'; + MODE_VIDEO_MZ700 <= '0'; + MODE_VIDEO_MZ800 <= '0'; + MODE_VIDEO_MZ80B <= '0'; + MODE_VIDEO_MZ2000 <= '0'; + + -- Bits [2:0] define the machine compatibility. -- - case D(2 downto 0) is - when "000" => - MODE_MZ80A <= '1'; - when "001" => - MODE_MZ80B <= '1'; - when "010" => - MODE_MZ700 <= '1'; - when "011" => - MODE_CUSTOM <= '1'; - + case to_integer(unsigned(D(2 downto 0))) is + when MODE_MZ80K => + MODE_VIDEO_MZ80K <= '1'; + when MODE_MZ80C => + MODE_VIDEO_MZ80C <= '1'; + when MODE_MZ1200 => + MODE_VIDEO_MZ1200 <= '1'; + when MODE_MZ80A => + MODE_VIDEO_MZ80A <= '1'; + when MODE_MZ700 => + MODE_VIDEO_MZ700 <= '1'; + when MODE_MZ800 => + MODE_VIDEO_MZ800 <= '1'; + when MODE_MZ80B => + MODE_VIDEO_MZ80B <= '1'; + when MODE_MZ2000 => + MODE_VIDEO_MZ2000 <= '1'; when others => - MODE_MZ80A <= '1'; end case; end if; + -- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF. + if CS_FB_PAGEn = '0' and CS_LAST_LEVEL(2) = '1' then + GRAM_PAGE_ENABLE <= D(1 downto 0); + end if; + + -- MZ80B Z80 PIO. + if CS_80B_PIOn = '0' and CS_LAST_LEVEL(3) = '1' and MODE_VIDEO_MZ80B = '1' and S_VIDEO_WRn = '0' then + + -- Write to PIO A. + -- 7 = Assigns addresses $DOOO-$FFFF to V-RAM. + -- 6 = Assigns addresses $5000-$7FFF to V-RAM. + -- 5 = Changes screen to 80-character mode (L: 40-character mode). + if VA(1 downto 0) = "00" then + MZ80B_VRAM_HI_ADDR <= D(7); + MZ80B_VRAM_LO_ADDR <= D(6); + end if; + end if; + -- Remember the previous level so we can detect the edge transition. As the clock of this process is not necessarily running at the clock of the CPU -- this step is important to guarantee transaction integrity. - CS_LAST_LEVEL <= '0' & CS_IO_FXX_n; + CS_LAST_LEVEL <= '0' & CS_80B_PIOn & CS_FB_PAGEn & CS_FB_VMn & CS_CPLD_CFGn; + end if; + + -- MZ80B Graphics RAM is enabled whenever one of the two control lines goes active. + GRAM_MZ80B_ENABLE <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR; end process; - + + -- Voltage translation. The FPGA is max 3.3v tolerant (as are nearly all FPGA's) so the 5V signals from the mainboard would have to go through a diode clamp + -- or converter. Given the pricing of the MAX7000 series chips it is easier and cheaper to use a CPLD to perform the voltage translation as they are 5V tolerant + -- and the mainboard accepts 3.3V output voltages. + -- + VADDR <= VA(15 downto 11) & A(10 downto 0); + + -- Data bus is muxed between the Z80 data bus and VRAMD which is the gated data bus after the video buffers. + -- The write signal WRn from the motherboard is actually a gated Write with video memory or I/O select. The read signal RDn from the motherboard is a gated Read with video memory or I/O select. + -- The logic has been updated in the tranZPUter to combine the Video Select with Z80 RD/WR such that use of S_VIDEO_RDn = 0 for read and S_VIDEO_WRn = 0 for write works as intended for all memory/IO operations. To + -- differentiate between memory and access, I/O operations use S_IORQn = 0. + -- + VDATA <= D when S_VIDEO_WRn = '0' -- All memory write data sent to FPGA in region C000:FFFF + else + (others => 'Z'); + D <= VDATA when S_VIDEO_RDn = '0' and CS_EXXXn = '1' -- C000:FFFF or FPGA IO Registers via data bus. + else + (others => 'Z'); + VRAMD <= (others => 'Z'); + VA(10 downto 0) <= A(10 downto 0); -- Lower 11 address bits taken from address bus. + VZ80_IORQn <= S_IORQn; + VZ80_WRn <= S_VIDEO_WRn; -- Write based on Z80_WRn and Video FPGA select signal from tranZPUter. + VZ80_RDn <= S_VIDEO_RDn; -- Read signal based on Z80_RDn and Video FPGA select from tranZPUter. + VGTn <= GTn; + VCSn <= CSn; + VVRAM_CS_INn <= VRAM_CS_INn; + + -- Standard access to VRAM/ARAM. + CS_DXXXn <= '0' when S_IORQn = '1' and VA(15 downto 12) = "1101" + else '1'; + CS_DVRAMn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11010" + else '1'; + CS_DARAMn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11011" + else '1'; + CS_EXXXn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11100" and GRAM_PAGE_ENABLE = "00" and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled. + else '1'; + + -- + -- CPU / RAM signals and selects. + -- + CS_IO_6XXn <= '0' when S_IORQn = '0' and VA(7 downto 4) = "0110" + else '1'; + CS_IO_EXXn <= '0' when S_IORQn = '0' and VA(7 downto 4) = "1110" + else '1'; + CS_IO_FXXn <= '0' when S_IORQn = '0' and VA(7 downto 4) = "1111" + else '1'; + CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and VA(3 downto 0) = "1110" -- IO 6E + else '1'; + -- 0xF8 set the video mode. [2:0] = mode, 000 = MZ80A, 001 = MZ-700, 010 = MZ-80B, 011 = MZ-800, 111 = Pixel graphics. + CS_FB_VMn <= '0' when CS_IO_FXXn = '0' and VA(3 downto 0) = "1000" + else '1'; + -- 0xFD set the Video memory page in block C000:FFFF bit 0, set the CGROM upload access in bit 7. + CS_FB_PAGEn <= '0' when CS_IO_FXXn = '0' and VA(3 downto 0) = "1101" + else '1'; + -- MZ80B/MZ2000 I/O Registers E0-EB, + CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and VA(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1' + else '1'; + + + -- Set the mainboard video state, 0 = enabled, 1 = disabled. + MODE_CPLD_MB_VIDEOn <= CPLD_CFG_DATA(3); + -- Set CPLD mode flag according to value given in config 2:0 + MODE_CPLD_MZ80K <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80K + else '0'; + MODE_CPLD_MZ80C <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80C + else '0'; + MODE_CPLD_MZ1200 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ1200 + else '0'; + MODE_CPLD_MZ80A <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80A + else '0'; + MODE_CPLD_MZ700 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ700 + else '0'; + MODE_CPLD_MZ800 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ800 + else '0'; + MODE_CPLD_MZ80B <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80B + else '0'; + MODE_CPLD_MZ2000 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ2000 + else '0'; end architecture; diff --git a/CPLD/VideoInterface_Toplevel.vhd b/CPLD/VideoInterface_Toplevel.vhd index 09d7612..29036f0 100644 --- a/CPLD/VideoInterface_Toplevel.vhd +++ b/CPLD/VideoInterface_Toplevel.vhd @@ -41,15 +41,14 @@ entity VideoInterfaceCPLD is CLOCK_50 : in std_logic; -- 50MHz base clock for system board, video timing and gate clocking. -- Z80 Address and Data. Address is muxed with video addressing, not direct. - -- A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board. + A : in std_logic_vector(10 downto 0); -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board. D : inout std_logic_vector(7 downto 0); -- Z80 Data bus, from the Colour Card CN! connector. -- Z80 Control signals. - -- WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector. + WRn : in std_logic; -- Z80 Write signal from the Colour Card CN! connector. RDn : in std_logic; -- Z80 Read signal from the Colour Card CN! connector. RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board. MB_RESETn : in std_logic; -- Z80 RESET signal from the tranZPUter board. - -- IORQn : in std_logic; -- Z80 IORQ signal from the tranZPUter board. -- Video and Mainboard signals. SRVIDEO_OUT : out std_logic; -- Shift Register 74LS165 Video Output onto mainboard. @@ -68,21 +67,20 @@ entity VideoInterfaceCPLD is VRAM_CS_INn : in std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket. GTn : in std_logic; -- GATE signal from the Colour Card CN! connector. CSn : in std_logic; -- Chip Select for the Video Attribute RAM from the Colour Card CN! connector. - -- MEM_CSn : in std_logic; -- Extended memory select for region 0xE000 - 0xFFFF from the tranZPUter board. OUTCLK : out std_logic; -- CPU signal serialiser clock. INDATA : in std_logic_vector(3 downto 0); -- Incoming serialised CPU signals. -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage. - VADDR : out std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address. + VADDR : out std_logic_vector(15 downto 0); -- Z80 Address bus, multiplexed with video address. VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector.. VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals. - VMEM_CSn : out std_logic; -- Extended memory select to FPGA. + --VMEM_CSn : out std_logic; -- Extended memory select to FPGA. + VZ80_IORQn : out std_logic; -- IORQn to FPGA. + VZ80_RDn : out std_logic; -- RDn to FPGA. + VZ80_WRn : out std_logic; -- WRn to FPGA. VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket. - VIORQn : out std_logic; -- IORQn to FPGA. - VRDn : out std_logic; -- RDn to FPGA. VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA. VGTn : out std_logic; -- Video Gate (GTn) - VWRn : out std_logic; -- WRn to FPGA. VRESETn : out std_logic; -- Reset to FPGA. -- VSRVIDEO_OUT : in std_logic; -- Video out from 74LS165 on mainboard, pre-GATE. @@ -119,11 +117,11 @@ begin CLOCK_50 => CLOCK_50, -- 50MHz base clock for system board, video timing and gate clocking. -- Z80 Address and Data. Address is muxed with video addressing, not direct. - -- A => A, -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board. + A => A, -- Z80 Address bus, multiplexed with video address. 13..11 come from the tranZPUter board. D => D, -- Z80 Data bus, from the Colour Card CN! connector. -- Z80 Control signals. - -- WRn => WRn, -- Z80 Write signal from the Colour Card CN! connector. + WRn => WRn, -- Z80 Write signal from the Colour Card CN! connector. RDn => RDn, -- Z80 Read signal from the Colour Card CN! connector. RESETn => CPLDRESETn, -- Z80 RESET signal from the tranZPUter board. -- IORQn => IORQn, -- Z80 IORQ signal from the tranZPUter board. @@ -153,13 +151,13 @@ begin VADDR => VADDR, -- Z80 Address bus, multiplexed with video address. VDATA => VDATA, -- Z80 Data bus from mainboard Colour Card CD connector.. VRAMD => VRAMD, -- Z80 Data bus from the VRAM chip, gated according to state signals. - VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA. + --VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA. + VZ80_IORQn => VZ80_IORQn, -- IORQn to FPGA. + VZ80_RDn => VZ80_RDn, -- RDn to FPGA. + VZ80_WRn => VZ80_WRn, -- WRn to FPGA. VVRAM_CS_INn => VVRAM_CS_INn, -- Chip Select for access to the Video RAM from the mainboard IC15 socket. - VIORQn => VIORQn, -- IORQn to FPGA. - VRDn => VRDn, -- RDn to FPGA. VCSn => VCSn, -- Video RAM Attribute Chip Select (CSn) to FPGA. VGTn => VGTn, -- Video Gate (GTn) - VWRn => VWRn, -- WRn to FPGA. VSRVIDEO_OUT => VSRVIDEO_OUT, -- Video out from 74LS165 on mainboard, pre-GATE. VHBLNK_OUTn => VHBLNK_OUTn, -- Horizontal blanking. diff --git a/CPLD/VideoInterface_pkg.vhd b/CPLD/VideoInterface_pkg.vhd index 176386e..597ec72 100644 --- a/CPLD/VideoInterface_pkg.vhd +++ b/CPLD/VideoInterface_pkg.vhd @@ -35,17 +35,6 @@ use ieee.numeric_std.all; use ieee.math_real.all; package VideoInterface_pkg is - ------------------------------------------------------------ - -- Function prototypes - ------------------------------------------------------------ - -- Find the maximum of two integers. - function IntMax(a : in integer; b : in integer) return integer; - - -- Find the number of bits required to represent an integer. - function log2ceil(arg : positive) return natural; - - -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. - function clockTicks(period : in integer; clock : in integer) return integer; ------------------------------------------------------------ -- Constants @@ -60,6 +49,78 @@ package VideoInterface_pkg is constant ZERO : std_logic := '0'; constant HIZ : std_logic := 'Z'; + -- Target hardware modes. + constant MODE_MZ80K : integer := 0; + constant MODE_MZ80C : integer := 1; + constant MODE_MZ1200 : integer := 2; + constant MODE_MZ80A : integer := 3; + constant MODE_MZ700 : integer := 4; + constant MODE_MZ800 : integer := 5; + constant MODE_MZ80B : integer := 6; + constant MODE_MZ2000 : integer := 7; + + -- Target Bus frequency modes. + constant MODE_FREQ_MZ80A : integer := 0; + constant MODE_FREQ_MZ80B : integer := 1; + constant MODE_FREQ_MZ700 : integer := 2; + constant MODE_FREQ_CUSTOM : integer := 7; + + -- Memory management modes. + constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063). + constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted. + constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected. + constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1. + constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2. + constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3. + constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected. + -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_COMPAT : integer := 08; -- Compatible monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF. + constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard. + constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. + constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. + constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. + constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. + constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. + constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. + constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. + + ------------------------------------------------------------ + -- Configurable parameters. + ------------------------------------------------------------ + -- Target hardware. + constant CPLD_HOST_HW : integer := MODE_MZ80A; + + -- Target video hardware. + constant CPLD_HAS_FPGA_VIDEO : std_logic := '1'; + + -- Version of hdl. + constant CPLD_VERSION : integer := 1; + + -- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator. + -- + constant USE_K64F_CTL_CLOCK : integer := 1; + + + ------------------------------------------------------------ + -- Function prototypes + ------------------------------------------------------------ + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer; + + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural; ------------------------------------------------------------ -- Records @@ -117,4 +178,14 @@ package body VideoInterface_pkg is end if; end function; + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural is + begin + if s = '1' then + return 1; + else + return 0; + end if; + end function; + end package body; diff --git a/CPLD/build/VideoInterface.qsf b/CPLD/build/VideoInterface.qsf index 5e2fabf..7fef4b0 100644 --- a/CPLD/build/VideoInterface.qsf +++ b/CPLD/build/VideoInterface.qsf @@ -63,21 +63,23 @@ set_location_assignment PIN_125 -to CLOCK_50 #set_location_assignment PIN_90 -to A[13] #set_location_assignment PIN_88 -to A[12] #set_location_assignment PIN_87 -to A[11] -#set_location_assignment PIN_98 -to A[10] -#set_location_assignment PIN_101 -to A[9] -#set_location_assignment PIN_103 -to A[8] -#set_location_assignment PIN_106 -to A[7] -#set_location_assignment PIN_108 -to A[6] -#set_location_assignment PIN_110 -to A[5] -#set_location_assignment PIN_112 -to A[4] -#set_location_assignment PIN_114 -to A[3] -#set_location_assignment PIN_117 -to A[2] -#set_location_assignment PIN_119 -to A[1] -#set_location_assignment PIN_121 -to A[0] +set_location_assignment PIN_98 -to A[10] +set_location_assignment PIN_101 -to A[9] +set_location_assignment PIN_103 -to A[8] +set_location_assignment PIN_106 -to A[7] +set_location_assignment PIN_108 -to A[6] +set_location_assignment PIN_110 -to A[5] +set_location_assignment PIN_112 -to A[4] +set_location_assignment PIN_114 -to A[3] +set_location_assignment PIN_117 -to A[2] +set_location_assignment PIN_119 -to A[1] +set_location_assignment PIN_121 -to A[0] # Video Interface Address Bus # =========================== +set_location_assignment PIN_69 -to VADDR[15] +set_location_assignment PIN_68 -to VADDR[14] set_location_assignment PIN_42 -to VADDR[13] set_location_assignment PIN_41 -to VADDR[12] set_location_assignment PIN_40 -to VADDR[11] @@ -108,7 +110,7 @@ set_location_assignment PIN_93 -to GTn set_location_assignment PIN_86 -to MB_RESETn set_location_assignment PIN_127 -to RESETn set_location_assignment PIN_91 -to RDn -#set_location_assignment PIN_96 -to WRn +set_location_assignment PIN_96 -to WRn set_location_assignment PIN_16 -to VRAM_CS_INn set_location_assignment PIN_90 -to INDATA[3] @@ -186,17 +188,15 @@ set_location_assignment PIN_77 -to VVBLNK_OUTn # ====================== set_location_assignment PIN_46 -to VCSn set_location_assignment PIN_47 -to VGTn -set_location_assignment PIN_44 -to VIORQn -set_location_assignment PIN_43 -to VMEM_CSn -set_location_assignment PIN_45 -to VRDn +set_location_assignment PIN_44 -to VZ80_IORQn +#set_location_assignment PIN_43 -to VMEM_CSn +set_location_assignment PIN_45 -to VZ80_RDn set_location_assignment PIN_49 -to VRESETn set_location_assignment PIN_27 -to VVRAM_CS_INn -set_location_assignment PIN_48 -to VWRn +set_location_assignment PIN_48 -to VZ80_WRn # Reserved. # ========= -#set_location_assignment PIN_69 -to TBA[4] -#set_location_assignment PIN_68 -to TBA[3] #set_location_assignment PIN_67 -to TBA[2] #set_location_assignment PIN_66 -to TBA[1] #set_location_assignment PIN_65 -to TBA[0] diff --git a/CPLD/build/VideoInterface.srf b/CPLD/build/VideoInterface.srf index fb05910..186d3b1 100644 --- a/CPLD/build/VideoInterface.srf +++ b/CPLD/build/VideoInterface.srf @@ -2,5 +2,38 @@ { "" "" "" "Macrocell buffer inserted after node \"Z80_BUSACKn\"" { } { } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "Found combinational loop of 5 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(127): object \"MODE_CPLD_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(157): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(153): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(158): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(136): object \"MODE_CPLD_MB_VIDEOn\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(134): object \"MODE_CPLD_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(133): object \"MODE_CPLD_MZ80B\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(132): object \"MODE_CPLD_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(131): object \"MODE_CPLD_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(130): object \"MODE_CPLD_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(129): object \"MODE_CPLD_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(135): object \"MODE_CPLD_SWITCH\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(128): object \"MODE_CPLD_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"GRAM_PAGE_ENABLE\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MZ80B_VRAM_HI_ADDR\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(162): object \"MZ80B_VRAM_LO_ADDR\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(150): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(151): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(154): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(158): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "*" { } { } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/CPLD/build/VideoInterface_constraints.sdc b/CPLD/build/VideoInterface_constraints.sdc index e1c61f8..4ef28a4 100644 --- a/CPLD/build/VideoInterface_constraints.sdc +++ b/CPLD/build/VideoInterface_constraints.sdc @@ -45,6 +45,7 @@ create_clock -name {CLOCK_50} -period 20.00 -waveform { 0.000 10.00 } [get_ports # Create Generated Clock #************************************************************** create_clock -name {VideoInterface:myVirtualToplevel|CLK16Mi} -period 62.5 [get_keepers {VideoInterface:myVirtualToplevel|CLK16Mi}] +create_clock -name {VideoInterface:myVirtualToplevel|CLK24Mi} -period 41.667 [get_keepers {VideoInterface:myVirtualToplevel|CLK24Mi}] #************************************************************** @@ -67,24 +68,24 @@ set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CL #set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[13]}] #set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[12]}] #set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[11]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[10]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[9]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[8]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[7]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[6]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[5]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[4]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[3]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[2]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[1]}] -#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[0]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[10]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[9]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[8]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[7]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[6]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[5]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[4]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[3]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[2]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[1]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[0]}] #set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {IORQn}] #set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MEM_CSn}] #set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {WRn}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSn}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {GTn}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RESETn}] -set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RDn}] +#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RDn}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[3]}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[2]}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[1]}] @@ -138,6 +139,8 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[2]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[1]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[0]}] +set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}] +set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}] @@ -152,7 +155,6 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[2]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[1]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[0]}] -set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[7]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}] @@ -161,6 +163,7 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}] +set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[7]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[6]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[5]}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[4]}] @@ -175,12 +178,12 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {S set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VBLNK_OUTn}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VCSn}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGTn}] -set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIORQn}] -set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}] -set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRDn}] +set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}] +#set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}] +set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVRAM_CS_INn}] -set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWRn}] +set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_HBLNKn}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_LOAD}] set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_SYNCH}] diff --git a/FPGA/VideoController.vhd b/FPGA/VideoController.vhd index 8ebb64b..749c31a 100644 --- a/FPGA/VideoController.vhd +++ b/FPGA/VideoController.vhd @@ -31,6 +31,7 @@ -- monitor when using VGA modes on the external display but this requires -- another framebuffer and the FPGA hasnt got the resources. Maybe v2.1 -- will contain a bigger FPGA (or external RAM)!!!! +-- Oct 2020 - Merge with the tranZPUterSW700 logic to incorporate new developments. -- --------------------------------------------------------------------------------------------------------- -- This source file is free software: you can redistribute it and-or modify @@ -71,18 +72,16 @@ entity VideoController is VIDCLK_40MHZ : in std_logic; -- 40MHz base clock for video timing and gate clocking. -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage. - -- Addres Bus - VADDR : in std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address. + -- Address Bus + VADDR : in std_logic_vector(15 downto 0); -- Z80 Address bus. -- Data Bus - VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector.. + VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus. -- Control signals. - VMEM_CSn : in std_logic; -- Extended memory select to FPGA. - VIORQn : in std_logic; -- IORQn to FPGA. - VRDn : in std_logic; -- RDn to FPGA. - VWRn : in std_logic; -- WRn to FPGA. - VRESETn : in std_logic; -- Reset to FPGA. + VZ80_IORQn : in std_logic; -- IORQn to FPGA. + VZ80_RDn : in std_logic; -- RDn to FPGA. + VZ80_WRn : in std_logic; -- WRn to FPGA. -- VGA signals. VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output. @@ -98,10 +97,13 @@ entity VideoController is VHBLNK_OUTn : out std_logic; -- Horizontal blanking. VHSY_OUT : out std_logic; -- Horizontal Sync. VSYNCH_OUT : out std_logic; -- Veritcal Sync. - VVBLNK_OUTn : out std_logic -- Vertical blanking. + VVBLNK_OUTn : out std_logic; -- Vertical blanking. + + -- Reset. + VRESETn : in std_logic -- Reset to FPGA. -- Reserved. - --TBA : in std_logic_vector(4 downto 0) -- Reserved signals. + --TBA <= (others => '1'); ); end entity; @@ -143,8 +145,27 @@ architecture rtl of VideoController is ( 0, 800, 0, 640, 0, 600, 0, 600, 1055, 627, 40, 800 + 40, 800 + 40 + 128, 600 + 1, 600 + 1 + 4, 1, 1, 1, 2), -- 14 Mode 2 upscaled as 800x600 @ 60Hz timings for 40Char mode colour. ( 0, 800, 0, 640, 0, 600, 0, 600, 1055, 627, 80, 800 + 40, 800 + 40 + 128, 600 + 1, 600 + 1 + 4, 1, 1, 0, 2) -- 15 Mode 3 upscaled as 800x600 @ 60Hz timings for 80Char mode colour. ); - -- + + -- State machine states for the Graphics Processing Unit. + -- + type GPUStateType is + ( + GPU_State_Idle, + GPU_FB_Clear, + GPU_FB_Clear_Param, + GPU_FB_Clear_Start, + GPU_FB_Clear_1, + GPU_FB_Clear_2, + GPU_FB_Clear_3, + GPU_VRAM_Clear, + GPU_VRAM_Clear_Attr, + GPU_VRAM_Clear_Param, + GPU_VRAM_Clear_Start, + GPU_VRAM_Clear_1, + GPU_VRAM_Clear_2, + GPU_VRAM_Clear_3 + ); -- -- Registers -- @@ -172,23 +193,45 @@ architecture rtl of VideoController is signal DISPLAY_INVERT : std_logic; -- Invert display Mode of MZ80A/1200 signal H_SHIFT_CNT : integer range 0 to 7; signal H_PX : unsigned(7 downto 0); -- Variable to indicate if horizontal pixels should be multiplied (for conversion to alternate formats). - signal H_PX_CNT : integer range 0 to 3; -- Variable to indicate if horizontal pixels should be multiplied (for conversion to alternate formats). + signal H_PX_CNT : integer range 0 to 3; signal V_PX : unsigned(7 downto 0); -- Variable to indicate if vertical pixels should be multiplied (for conversion to alternate formats). signal V_PX_CNT : integer range 0 to 3; -- Variable to indicate if vertical pixels should be multiplied (for conversion to alternate formats). signal VPARAM_DO : std_logic_vector(7 downto 0); -- Video Parameter register read signal. signal PCGRAM : std_logic := '0'; -- PCG RAM, allow access to the programmable character generator memory. - signal MODE_MZ80A : std_logic := '1'; -- The Video Module is running in MZ80A mode. - signal MODE_MZ700 : std_logic := '0'; -- The Video Module is running in MZ700 mode. - signal MODE_MZ800 : std_logic := '0'; -- The Video Module is running in MZ800 mode. - signal MODE_MZ80B : std_logic := '0'; -- The Video Module is running in MZ80B mode. - signal MODE_MZ80K : std_logic := '0'; -- The Video Module is running in MZ80K mode. - signal MODE_MZ80C : std_logic := '0'; -- The Video Module is running in MZ80C mode. - signal MODE_MZ1200 : std_logic := '0'; -- The Video Module is running in MZ1200 mode. - signal MODE_MZ2000 : std_logic := '0'; -- The Video Module is running in MZ2000 mode. - signal MODE_MONO : std_logic := '1'; -- The Video Module is running in monochrome 40 character mode. - signal MODE_MONO80 : std_logic := '0'; -- The Video Module is running in monochrome 80 character mode. - signal MODE_COLOUR : std_logic := '0'; -- The Video Module is running in colour 40 character mode. - signal MODE_COLOUR80 : std_logic := '0'; -- The Video Module is running in colour 80 character mode. + signal MODE_VIDEO_MZ80K : std_logic := '0'; -- The Video Module is running in MZ80K mode. + signal MODE_VIDEO_MZ80C : std_logic := '0'; -- The Video Module is running in MZ80C mode. + signal MODE_VIDEO_MZ1200 : std_logic := '0'; -- The Video Module is running in MZ1200 mode. + signal MODE_VIDEO_MZ80A : std_logic := '0'; -- The Video Module is running in MZ80A mode. + signal MODE_VIDEO_MZ700 : std_logic := '1'; -- The Video Module is running in MZ700 mode. + signal MODE_VIDEO_MZ800 : std_logic := '0'; -- The Video Module is running in MZ800 mode. + signal MODE_VIDEO_MZ80B : std_logic := '0'; -- The Video Module is running in MZ80B mode. + signal MODE_VIDEO_MZ2000 : std_logic := '0'; -- The Video Module is running in MZ2000 mode. + signal MODE_VIDEO_MONO : std_logic := '1'; -- The Video Module is running in monochrome 40 character mode. + signal MODE_VIDEO_MONO80 : std_logic := '0'; -- The Video Module is running in monochrome 80 character mode. + signal MODE_VIDEO_COLOUR : std_logic := '0'; -- The Video Module is running in colour 40 character mode. + signal MODE_VIDEO_COLOUR80 : std_logic := '0'; -- The Video Module is running in colour 80 character mode. + signal MODE_CPLD_MZ80A : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ80A mode. + signal MODE_CPLD_MZ700 : std_logic := '1'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ700 mode. + signal MODE_CPLD_MZ800 : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ800 mode. + signal MODE_CPLD_MZ80B : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ80B mode. + signal MODE_CPLD_MZ80K : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ80K mode. + signal MODE_CPLD_MZ80C : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ80C mode. + signal MODE_CPLD_MZ1200 : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ1200 mode. + signal MODE_CPLD_MZ2000 : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, it is running in MZ2000 mode. + signal MODE_CPLD_MB_VIDEOn : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the mainboard video logic is enabled, disabling or blending with the FPGA graphics. + signal MODE_CPLD_SWITCH : std_logic := '1'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the machine mode has changed. Flag is active for 1 clock cycle. + signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register. + signal DSP_PARAM_SEL : std_logic_vector(3 downto 0); -- Display parameter selection register. + signal PALETTE_PARAM_SEL : std_logic_vector(8 downto 0); -- Palette parameter selection register. + signal PALETTE_DO_R : std_logic_vector(4 downto 0); -- Read Red palette output. + signal PALETTE_DO_G : std_logic_vector(4 downto 0); -- Read Green palette output. + signal PALETTE_DO_B : std_logic_vector(4 downto 0); -- Read Blue palette output. + signal PALETTE_WEN_R : std_logic; -- Write enable for Red palette map. + signal PALETTE_WEN_G : std_logic; -- Write enable for Green palette map. + signal PALETTE_WEN_B : std_logic; -- Write enable for Blue palette map. + signal FB_PALETTE_R : std_logic_vector(4 downto 0); -- Current palette map value for given video state input. + signal FB_PALETTE_G : std_logic_vector(4 downto 0); -- Current palette map value for given video state input. + signal FB_PALETTE_B : std_logic_vector(4 downto 0); -- Current palette map value for given video state input. -- -- CPU/Video Access @@ -196,10 +239,20 @@ architecture rtl of VideoController is signal VRAM_VIDEO_DATA : std_logic_vector(7 downto 0); -- Display data output to CPU. signal VRAM_DO : std_logic_vector(7 downto 0); -- VRAM Data out. signal VRAM_WEN : std_logic; -- VRAM Write enable signal. + signal VRAM_GPU_WEN : std_logic; -- VRAM Write enable signal from the GPU. + signal VRAM_GPU_ADDR : std_logic_vector(12 downto 0); -- VRAM RAM Address from the GPU. + signal VRAM_ADDR : std_logic_vector(11 downto 0); -- VRAM RAM Address. + signal VRAM_GPU_ENABLE : std_logic; -- Enable GPU VRAM access. + signal VRAM_DI : std_logic_vector(7 downto 0); -- VRAM Data input. + signal VRAM_GPU_DI : std_logic_vector(7 downto 0); -- VRAM Data input from the GPU. signal GRAM_ADDR : std_logic_vector(13 downto 0); -- Graphics RAM Address. + signal GRAM_GPU_ADDR : std_logic_vector(13 downto 0); -- Graphics RAM Address. signal GRAM_DI_R : std_logic_vector(7 downto 0); -- Graphics Red RAM Data. signal GRAM_DI_G : std_logic_vector(7 downto 0); -- Graphics Green RAM Data. signal GRAM_DI_B : std_logic_vector(7 downto 0); -- Graphics Blue RAM Data. + signal GRAM_GPU_DI_R : std_logic_vector(7 downto 0); -- Graphics Red RAM Data generated by GPU. + signal GRAM_GPU_DI_G : std_logic_vector(7 downto 0); -- Graphics Green RAM Data generated by GPU. + signal GRAM_GPU_DI_B : std_logic_vector(7 downto 0); -- Graphics Blue RAM Data generated by GPU. signal GRAM_DI_GI : std_logic_vector(7 downto 0); -- Graphics Option GRAM I for MZ80B signal GRAM_DI_GII : std_logic_vector(7 downto 0); -- Graphics Option GRAM II for MZ80B signal GRAM_DI_GIII : std_logic_vector(7 downto 0); -- Graphics Option GRAM III to provide RGB mode. @@ -212,9 +265,13 @@ architecture rtl of VideoController is signal GRAM_WEN_GI : std_logic; -- Graphics Option GRAM I Write enable signal for MZ80B. signal GRAM_WEN_GII : std_logic; -- Graphics Option GRAM II Write enable signal for MZ80B. signal GRAM_WEN_GIII : std_logic; -- Graphics Option GRAM III Write enable signal RGB mode. + signal GRAM_GPU_ENABLE : std_logic; -- Enable GPU GRAM access. signal GWEN_R : std_logic; -- Write enable to Red GRAM. signal GWEN_G : std_logic; -- Write enable to Green GRAM. signal GWEN_B : std_logic; -- Write enable to Blue GRAM. + signal GWEN_GPU_R : std_logic; -- Write enable to Red GRAM by GPU. + signal GWEN_GPU_G : std_logic; -- Write enable to Green GRAM by GPU. + signal GWEN_GPU_B : std_logic; -- Write enable to Blue GRAM by GPU. signal GWEN_GI : std_logic; -- Write enable to for GRAMI option on MZ80B/2000. signal GWEN_GII : std_logic; -- Write enable to for GRAMII option on MZ80B/2000. signal GRAM_MODE_REG : std_logic_vector(7 downto 0); -- Programmable mode register to control GRAM operations. @@ -224,29 +281,42 @@ architecture rtl of VideoController is signal GRAM_OPT_WRITE : std_logic; -- Graphics write to GRAMI (0) or GRAMII (1) for MZ80B/MZ2000 signal GRAM_OPT_OUT1 : std_logic; -- Graphics enable GRAMI output to display signal GRAM_OPT_OUT2 : std_logic; -- Graphics enable GRAMII output to display - signal GRAM_PAGE_ENABLE : std_logic; -- Graphics mode page enable. + signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable. signal VIDEO_MODE_REG : std_logic_vector(7 downto 0); -- Programmable mode register to control video mode. signal PAGE_MODE_REG : std_logic_vector(7 downto 0); -- Current value of the Page register. + signal PALETTE_REG : std_logic_vector(7 downto 0); -- Palette register to apply mapping to the digital RGB output. + signal GPU_PARAMS : std_logic_vector(127 downto 0); -- GPU parameter register. + signal GPU_COMMAND : std_logic_vector(7 downto 0); -- GPU command register. + signal GPU_STATUS : std_logic_vector(7 downto 0); -- GPU Status register. + signal GPU_STATE : GPUStateType; -- GPU FSM State. signal Z80_MA : std_logic_vector(11 downto 0); -- CPU Address Masked according to machine model. - signal CS_INVERT_n : std_logic; -- Chip Select to enable Inverse mode. - signal CS_SCROLL_n : std_logic; -- Chip Select to perform a hardware scroll. - signal CS_GRAM_OPT_n : std_logic; -- Chip Select to write the graphics options for MZ80B/MZ2000. - signal CS_FB_VM_n : std_logic; -- Chip Select for the Video Mode register. - signal CS_FB_PAGE_n : std_logic; -- Chip Select for the Page select register. - signal CS_FB_CTL_n : std_logic; -- Chip Select to write to the Graphics mode register. - signal CS_FB_RED_n : std_logic; -- Chip Select to write to the Red pixel per byte indirect write register. - signal CS_FB_GREEN_n : std_logic; -- Chip Select to write to the Green pixel per byte indirect write register. - signal CS_FB_BLUE_n : std_logic; -- Chip Select to write to the Blue pixel per byte indirect write register. - signal CS_PCG_n : std_logic; -- Chip select for the programmable character generator. - signal CS_LAST_LEVEL : std_logic_vector(16 downto 0); -- Register to store the previous chip select level for edge detection. - signal CS_DXXX_n : std_logic; -- Chip select range for the VRAM/ARAM. - signal CS_EXXX_n : std_logic; -- Chip select range for the memory mapped I/O. - signal CS_DVRAM_n : std_logic; -- Chip select for the Video RAM. - signal CS_DARAM_n : std_logic; -- Chip select for the Attribute RAM. - signal CS_GRAM_n : std_logic; -- Chip select for the MZ80B Graphics Mode register. - signal VGAMODE : std_logic_vector(1 downto 0) := "11"; -- Current VGA mode - selectable VGA frequency output for the external display. - signal CS_IO_0XX_n : std_logic; -- Chip select for Video Parameter block 00:0F - signal CS_IO_1XX_n : std_logic; -- Chip select for Video Parameter registers block 10:1F + signal CS_INVERTn : std_logic; -- Chip Select to enable Inverse mode. + signal CS_SCROLLn : std_logic; -- Chip Select to perform a hardware scroll. + signal CS_GRAM_OPTn : std_logic; -- Chip Select to write the graphics options for MZ80B/MZ2000. + signal CS_CPLD_CFGn : std_logic; -- Chip Select to write to the CPLD configuration register at 0x6E. + signal CS_FB_PALETTEn : std_logic; -- Chip Select for setting the active pallette. + signal CS_FB_PARAMSn : std_logic; -- Chip Select for storing GPU parameters in a FILO stack. + signal CS_FB_GPUn : std_logic; -- Chip Select for GPU command register. + signal CS_FB_VMn : std_logic; -- Chip Select for the Video Mode register. + signal CS_FB_PAGEn : std_logic; -- Chip Select for the Page select register. + signal CS_FB_CTLn : std_logic; -- Chip Select to write to the Graphics mode register. + signal CS_FB_REDn : std_logic; -- Chip Select to write to the Red pixel per byte indirect write register. + signal CS_FB_GREENn : std_logic; -- Chip Select to write to the Green pixel per byte indirect write register. + signal CS_FB_BLUEn : std_logic; -- Chip Select to write to the Blue pixel per byte indirect write register. + signal CS_PCGn : std_logic; -- Chip select for the programmable character generator. + signal CS_DXXXn : std_logic; -- Chip select range for the VRAM/ARAM. + signal CS_EXXXn : std_logic; -- Chip select range for the memory mapped I/O. + signal CS_DVRAMn : std_logic; -- Chip select for the Video RAM. + signal CS_DARAMn : std_logic; -- Chip select for the Attribute RAM. + signal CS_GRAMn : std_logic; -- Chip select for the MZ80B Graphics Mode register. + signal CS_FBRAMn : std_logic; -- Chip select for the Graphics Framebuffer RAM. + signal VGAMODE : std_logic_vector(1 downto 0) := "00"; -- Current VGA mode - selectable VGA frequency output for the external display. + signal CS_IO_6XXn : std_logic; -- Chip select for CPLD configuration registers. + signal CS_IO_DXXn : std_logic; -- Chip select for block D0:DF + signal CS_IO_EXXn : std_logic; -- Chip select for block E0:EF + signal CS_IO_FXXn : std_logic; -- Chip select for block F0:FF + signal VZ80_WR_LASTn : std_logic; -- Edge detection on the Z80 write signal. + signal VZ80_RD_LASTn : std_logic; -- Edge detection on the Z80 read signal. -- -- MZ80B Signals. -- @@ -256,17 +326,17 @@ architecture rtl of VideoController is signal MZ80B_VRAM_HI_ADDR : std_logic; -- Video RAM located at D000:FFFF when high. signal MZ80B_VRAM_LO_ADDR : std_logic; -- Video RAM located at 5000:7FFF when high. signal GRAM_MZ80B_ENABLE : std_logic; -- MZ80B Graphics memory enabled flag. - signal CS_IO_EXX_n : std_logic; -- Chip select for block E0:EF - signal CS_IO_FXX_n : std_logic; -- Chip select for block F0:FF - signal CS_80B_PPI_n : std_logic; -- Chip select for MZ80B PPI when in MZ80B mode. - signal CS_80B_PIT_n : std_logic; -- Chip select for MZ80B PIT when in MZ80B mode. - signal CS_80B_PIO_n : std_logic; -- Chip select for MZ80B PIO when in MZ80B mode. + signal MZ80B_VMODE_REG : std_logic_vector(7 downto 0); -- MZ80B Input/Output mode to combine the VRAM/GRAM. + signal CS_80B_PPIn : std_logic; -- Chip select for MZ80B PPI when in MZ80B mode. + signal CS_80B_PITn : std_logic; -- Chip select for MZ80B PIT when in MZ80B mode. + signal CS_80B_PIOn : std_logic; -- Chip select for MZ80B PIO when in MZ80B mode. + signal CS_80B_VMODEn : std_logic; -- Chip select for MZ80B to set the video mode for VRAM/GRAM I/II. -- -- Display Signals -- signal H_COUNT : unsigned(10 downto 0); -- Horizontal pixel counter signal H_BLANKi : std_logic; -- Horizontal Blanking - signal H_SYNC_ni : std_logic; -- Horizontal Blanking + signal H_SYNCni : std_logic; -- Horizontal Blanking signal H_DSP_START : unsigned(15 downto 0); signal H_DSP_END : unsigned(15 downto 0); signal H_DSP_WND_START : unsigned(15 downto 0); -- Window within the horizontal display when data is output. @@ -278,7 +348,7 @@ architecture rtl of VideoController is signal V_POLARITY : unsigned( 0 downto 0); -- Vertical polarity. signal V_COUNT : unsigned(10 downto 0); -- Vertical pixel counter signal V_BLANKi : std_logic; -- Vertical Blanking - signal V_SYNC_ni : std_logic; -- Horizontal Blanking + signal V_SYNCni : std_logic; -- Horizontal Blanking signal V_DSP_START : unsigned(15 downto 0); signal V_DSP_END : unsigned(15 downto 0); signal V_DSP_WND_START : unsigned(15 downto 0); -- Window within the vertical display when data is output. @@ -291,7 +361,7 @@ architecture rtl of VideoController is -- signal H_I_COUNT : unsigned(10 downto 0); -- Horizontal pixel counter signal H_I_BLANKi : std_logic; -- Horizontal Blanking - signal H_I_SYNC_ni : std_logic; -- Horizontal Blanking + signal H_I_SYNCni : std_logic; -- Horizontal Blanking signal H_I_DSP_START : unsigned(15 downto 0); signal H_I_DSP_END : unsigned(15 downto 0); signal H_I_SYNC_START : unsigned(15 downto 0); @@ -299,7 +369,7 @@ architecture rtl of VideoController is signal H_I_LINE_END : unsigned(15 downto 0); signal V_I_COUNT : unsigned(10 downto 0); -- Vertical pixel counter signal V_I_BLANKi : std_logic; -- Vertical Blanking - signal V_I_SYNC_ni : std_logic; -- Horizontal Blanking + signal V_I_SYNCni : std_logic; -- Horizontal Blanking signal V_I_DSP_START : unsigned(15 downto 0); signal V_I_DSP_END : unsigned(15 downto 0); signal V_I_SYNC_START : unsigned(15 downto 0); @@ -321,8 +391,8 @@ architecture rtl of VideoController is signal CGRAM_ADDR : std_logic_vector(11 downto 0); signal PCG_DATA : std_logic_vector(7 downto 0); signal CGRAM_DI : std_logic_vector(7 downto 0); - signal CGRAM_WE_n : std_logic; - signal CGRAM_WEN : std_logic; + signal CGRAM_WEn : std_logic; + signal CGRAM_WREN : std_logic; signal CGRAM_SEL : std_logic; -- -- Clocks @@ -371,7 +441,86 @@ begin -- -- Instantiation -- + + PALETTE_R: dpram + GENERIC MAP ( + init_file => "../../software/mif/PALETTE_R.mif", + widthad_a => 9, + width_a => 5, + widthad_b => 9, + width_b => 5, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => not SYS_CLK, + clocken_a => '1', + address_a => PALETTE_PARAM_SEL, + data_a => VDATA(4 downto 0), + wren_a => PALETTE_WEN_R, + q_a => PALETTE_DO_R, + -- Port B used for Palette output map. + clock_b => SYS_CLK, + clocken_b => '1', + address_b => PALETTE_REG & SR_R_DATA(7), + data_b => (others => '0'), + wren_b => '0', + q_b => FB_PALETTE_R + ); + PALETTE_G: dpram + GENERIC MAP ( + init_file => "../../software/mif/PALETTE_G.mif", + widthad_a => 9, + width_a => 5, + widthad_b => 9, + width_b => 5, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => not SYS_CLK, + clocken_a => '1', + address_a => PALETTE_PARAM_SEL, + data_a => VDATA(4 downto 0), + wren_a => PALETTE_WEN_G, + q_a => PALETTE_DO_G, + + -- Port B used for Palette output map. + clock_b => SYS_CLK, + clocken_b => '1', + address_b => PALETTE_REG & SR_G_DATA(7), + data_b => (others => '0'), + wren_b => '0', + q_b => FB_PALETTE_G + ); + PALETTE_B: dpram + GENERIC MAP ( + init_file => "../../software/mif/PALETTE_B.mif", + widthad_a => 9, + width_a => 5, + widthad_b => 9, + width_b => 5, + outdata_reg_b => "UNREGISTERED" + ) + PORT MAP ( + -- Port A used for CPU access. + clock_a => not SYS_CLK, + clocken_a => '1', + address_a => PALETTE_PARAM_SEL, + data_a => VDATA(4 downto 0), + wren_a => PALETTE_WEN_B, + q_a => PALETTE_DO_B, + + -- Port B used for Palette output map. + clock_b => SYS_CLK, + clocken_b => '1', + address_b => PALETTE_REG & SR_B_DATA(7), + data_b => (others => '0'), + wren_b => '0', + q_b => FB_PALETTE_B + ); + -- Video memory as seen by the MZ Series. This is a 1K or 2K or 2K + 2K Attribute RAM -- organised as 4K x 8 on the CPU side and 2K x 16 on the display side, top bits are not used for MZ80K/C/1200/A. -- @@ -387,10 +536,10 @@ begin ) PORT MAP ( -- Port A used for CPU access. - clock_a => IF_CLK, + clock_a => not SYS_CLK, clocken_a => '1', - address_a => VADDR(10 downto 0) & VADDR(11), - data_a => VDATA, + address_a => VRAM_ADDR(10 downto 0) & VRAM_ADDR(11), + data_a => VRAM_DI, wren_a => VRAM_WEN, q_a => VRAM_DO, @@ -417,7 +566,7 @@ begin ) PORT MAP ( -- Port A used for CPU access. - clock_a => IF_CLK, + clock_a => not SYS_CLK, clocken_a => '1', address_a => GRAM_ADDR(13 downto 0), data_a => GRAM_DI_R, @@ -447,7 +596,7 @@ begin ) PORT MAP ( -- Port A used for CPU access. - clock_a => IF_CLK, + clock_a => not SYS_CLK, clocken_a => '1', address_a => GRAM_ADDR(13 downto 0), data_a => GRAM_DI_B, @@ -478,7 +627,7 @@ begin ) PORT MAP ( -- Port A used for CPU access. - clock_a => IF_CLK, + clock_a => not SYS_CLK, clocken_a => '1', address_a => GRAM_ADDR(13 downto 0), data_a => GRAM_DI_G, @@ -537,7 +686,7 @@ begin clocken_a => '1', address_a => CG_ADDR(11 downto 0), data_a => CGRAM_DI, - wren_a => CGRAM_WEN, + wren_a => CGRAM_WREN, q_a => CGRAM_DO, clock_b => SYS_CLK, @@ -649,11 +798,11 @@ begin when 2 => -- Check to see if VRAM is disabled, if it is, skip. -- - if GRAM_MODE_REG(4) = '0' and (MODE_MONO = '1' or MODE_MONO80 = '1') then + if GRAM_MODE_REG(4) = '0' and (MODE_VIDEO_MONO = '1' or MODE_VIDEO_MONO80 = '1') then -- Monochrome modes? XFER_CYCLE := 4; - elsif GRAM_MODE_REG(4) = '0' and (MODE_COLOUR = '1' or MODE_COLOUR80 = '1') then + elsif GRAM_MODE_REG(4) = '0' and (MODE_VIDEO_COLOUR = '1' or MODE_VIDEO_COLOUR80 = '1') then -- Colour modes? XFER_CYCLE := 3; @@ -741,61 +890,61 @@ begin XFER_CYCLE := 6; -- Monochrome modes? - -- Expand and store the slice of the character. + -- Expand and store the slice of the character in monochrome according to machine mode. MZ80K/C = white, MZ80A/1200 = Green. -- when 4 => if CGROM_DATA(7) = '1' then XFER_MAPPED_DATA(23) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80K = '1' then XFER_MAPPED_DATA(7) <= '1'; XFER_MAPPED_DATA(15) <= '1'; end if; end if; if CGROM_DATA(6) = '1' then XFER_MAPPED_DATA(22) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(6) <= '1'; XFER_MAPPED_DATA(14) <= '1'; end if; end if; if CGROM_DATA(5) = '1' then XFER_MAPPED_DATA(21) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(5) <= '1'; XFER_MAPPED_DATA(13) <= '1'; end if; end if; if CGROM_DATA(4) = '1' then XFER_MAPPED_DATA(20) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(4) <= '1'; XFER_MAPPED_DATA(12) <= '1'; end if; end if; if CGROM_DATA(3) = '1' then XFER_MAPPED_DATA(19) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(3) <= '1'; XFER_MAPPED_DATA(11) <= '1'; end if; end if; if CGROM_DATA(2) = '1' then XFER_MAPPED_DATA(18) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(2) <= '1'; XFER_MAPPED_DATA(10) <= '1'; end if; end if; if CGROM_DATA(1) = '1' then XFER_MAPPED_DATA(17) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(1) <= '1'; XFER_MAPPED_DATA(9) <= '1'; end if; end if; if CGROM_DATA(0) = '1' then XFER_MAPPED_DATA(16) <= '1'; - if MODE_MZ80K = '1' or MODE_MZ80C = '1' then + if MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' then XFER_MAPPED_DATA(0) <= '1'; XFER_MAPPED_DATA(8) <= '1'; end if; @@ -805,8 +954,7 @@ begin when 5 => -- If invert option selected, invert green. -- - -- if (MODE_MZ80B = '1' and INVERSE_n = '0') or (MODE_MZ80A = '1' and DISPLAY_INVERT = '1') then - if (MODE_MZ80A = '1' or MODE_MZ80B = '1')and DISPLAY_INVERT = '1' then + if (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80B = '1')and DISPLAY_INVERT = '1' then XFER_MAPPED_DATA(23 downto 16) <= not XFER_MAPPED_DATA(23 downto 16); end if; XFER_CYCLE := 6; @@ -819,13 +967,17 @@ begin -- case GRAM_MODE_REG(7 downto 6) is when "00" => - XFER_MAPPED_DATA <= XFER_MAPPED_DATA or reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + --XFER_MAPPED_DATA <= XFER_MAPPED_DATA or reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + XFER_MAPPED_DATA <= XFER_MAPPED_DATA or DISPLAY_DATA(23 downto 16) & DISPLAY_DATA(15 downto 8) & DISPLAY_DATA(7 downto 0); when "01" => - XFER_MAPPED_DATA <= XFER_MAPPED_DATA and reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + --XFER_MAPPED_DATA <= XFER_MAPPED_DATA and reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + XFER_MAPPED_DATA <= XFER_MAPPED_DATA and DISPLAY_DATA(23 downto 16) & DISPLAY_DATA(15 downto 8) & DISPLAY_DATA(7 downto 0); when "10" => - XFER_MAPPED_DATA <= XFER_MAPPED_DATA nand reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + --XFER_MAPPED_DATA <= XFER_MAPPED_DATA nand reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + XFER_MAPPED_DATA <= XFER_MAPPED_DATA nand DISPLAY_DATA(23 downto 16) & DISPLAY_DATA(15 downto 8) & DISPLAY_DATA(7 downto 0); when "11" => - XFER_MAPPED_DATA <= XFER_MAPPED_DATA xor reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + --XFER_MAPPED_DATA <= XFER_MAPPED_DATA xor reverse_vector(DISPLAY_DATA(23 downto 16)) & reverse_vector(DISPLAY_DATA(15 downto 8)) & reverse_vector(DISPLAY_DATA(7 downto 0)); + XFER_MAPPED_DATA <= XFER_MAPPED_DATA xor DISPLAY_DATA(23 downto 16) & DISPLAY_DATA(15 downto 8) & DISPLAY_DATA(7 downto 0); end case; end if; XFER_CYCLE := 7; @@ -833,7 +985,7 @@ begin when 7 => -- For MZ80B, if enabled, blend in the graphics memory. -- - if MODE_MZ80B = '1' and XFER_DST_ADDR < 8192 then + if MODE_VIDEO_MZ80B = '1' and XFER_DST_ADDR < 8192 then if GRAM_OPT_OUT1 = '1' and GRAM_OPT_OUT2 = '1' then XFER_MAPPED_DATA(23 downto 16) <= XFER_MAPPED_DATA(23 downto 16) or reverse_vector(DISPLAY_DATA(7 downto 0)) or reverse_vector(DISPLAY_DATA(15 downto 8)); elsif GRAM_OPT_OUT1 = '1' then @@ -898,7 +1050,7 @@ begin if V_COUNT = V_LINE_END and H_COUNT = H_LINE_END - 1 then -- Start of display, setup the start of VRAM for display according to machine. - if MODE_MZ80A = '1' then + if MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ700 = '1' then XFER_VRAM_ADDR <= (OFFSET_ADDR & "000"); else XFER_VRAM_ADDR <= (others => '0'); @@ -961,8 +1113,8 @@ begin V_COUNT <= (others => '0'); H_BLANKi <= '1'; V_BLANKi <= '1'; - H_SYNC_ni <= '1'; - V_SYNC_ni <= '1'; + H_SYNCni <= '1'; + V_SYNCni <= '1'; H_PX_CNT <= 0; V_PX_CNT <= 0; H_SHIFT_CNT <= 0; @@ -1005,8 +1157,8 @@ begin V_COUNT <= (others => '0'); H_BLANKi <= '1'; V_BLANKi <= '1'; - H_SYNC_ni <= not std_logic_vector(to_unsigned(FB_PARAMS(VIDEOMODE, 15), 1))(0); - V_SYNC_ni <= not std_logic_vector(to_unsigned(FB_PARAMS(VIDEOMODE, 16), 1))(0); + H_SYNCni <= not std_logic_vector(to_unsigned(FB_PARAMS(VIDEOMODE, 15), 1))(0); + V_SYNCni <= not std_logic_vector(to_unsigned(FB_PARAMS(VIDEOMODE, 16), 1))(0); H_PX_CNT <= 0; V_PX_CNT <= 0; H_SHIFT_CNT <= 0; @@ -1016,75 +1168,87 @@ begin -- Ability to adjust the video parameter registers to tune or override the default values from the lookup table. This can be useful in debugging, -- adjusting to a new monitor etc. -- - if CS_IO_0XX_n = '0' and CS_LAST_LEVEL(12) = '1' and VWRn = '0' then + if CS_IO_DXXn = '0' and VZ80_WRn = '0' then + case VADDR(3 downto 0) is + -- 0xD0 - Set the parameter number to update. when "0000" => - H_DSP_START(7 downto 0) <= unsigned(VDATA); + DSP_PARAM_SEL <= VDATA(3 downto 0); + + -- 0xD1 - Update the lower selected parameter byte. when "0001" => - H_DSP_START(15 downto 8) <= unsigned(VDATA); + case DSP_PARAM_SEL is + when "0000" => + H_DSP_START(7 downto 0) <= unsigned(VDATA); + when "0001" => + H_DSP_END(7 downto 0) <= unsigned(VDATA); + when "0010" => + H_DSP_WND_START(7 downto 0) <= unsigned(VDATA); + when "0011" => + H_DSP_WND_END(7 downto 0) <= unsigned(VDATA); + when "0100" => + V_DSP_START(7 downto 0) <= unsigned(VDATA); + when "0101" => + V_DSP_END(7 downto 0) <= unsigned(VDATA); + when "0110" => + V_DSP_WND_START(7 downto 0) <= unsigned(VDATA); + when "0111" => + V_DSP_WND_END(7 downto 0) <= unsigned(VDATA); + when "1000" => + H_LINE_END(7 downto 0) <= unsigned(VDATA); + when "1001" => + V_LINE_END(7 downto 0) <= unsigned(VDATA); + when "1010" => + MAX_COLUMN(7 downto 0) <= unsigned(VDATA); + when "1011" => + H_SYNC_START(7 downto 0) <= unsigned(VDATA); + when "1100" => + H_SYNC_END(7 downto 0) <= unsigned(VDATA); + when "1101" => + V_SYNC_START(7 downto 0) <= unsigned(VDATA); + when "1110" => + V_SYNC_END(7 downto 0) <= unsigned(VDATA); + when "1111" => + H_PX(7 downto 0) <= unsigned(VDATA); + end case; + + -- 0xD2 - Update the upper selected parameter byte. when "0010" => - H_DSP_END(7 downto 0) <= unsigned(VDATA); - when "0011" => - H_DSP_END(15 downto 8) <= unsigned(VDATA); - when "0100" => - H_DSP_WND_START(7 downto 0) <= unsigned(VDATA); - when "0101" => - H_DSP_WND_START(15 downto 8) <= unsigned(VDATA); - when "0110" => - H_DSP_WND_END(7 downto 0) <= unsigned(VDATA); - when "0111" => - H_DSP_WND_END(15 downto 8) <= unsigned(VDATA); - when "1000" => - V_DSP_START(7 downto 0) <= unsigned(VDATA); - when "1001" => - V_DSP_START(15 downto 8) <= unsigned(VDATA); - when "1010" => - V_DSP_END(7 downto 0) <= unsigned(VDATA); - when "1011" => - V_DSP_END(15 downto 8) <= unsigned(VDATA); - when "1100" => - V_DSP_WND_START(7 downto 0) <= unsigned(VDATA); - when "1101" => - V_DSP_WND_START(15 downto 8) <= unsigned(VDATA); - when "1110" => - V_DSP_WND_END(7 downto 0) <= unsigned(VDATA); - when "1111" => - V_DSP_WND_END(15 downto 8) <= unsigned(VDATA); - end case; - end if; - if CS_IO_1XX_n = '0' and CS_LAST_LEVEL(13) = '1' and VWRn = '0' then - case VADDR(3 downto 0) is - when "0000" => - H_LINE_END(7 downto 0) <= unsigned(VDATA); - when "0001" => - H_LINE_END(15 downto 8) <= unsigned(VDATA); - when "0010" => - V_LINE_END(7 downto 0) <= unsigned(VDATA); - when "0011" => - V_LINE_END(15 downto 8) <= unsigned(VDATA); - when "0100" => - MAX_COLUMN(7 downto 0) <= unsigned(VDATA); - when "0101" => - when "0110" => - H_SYNC_START(7 downto 0) <= unsigned(VDATA); - when "0111" => - H_SYNC_START(15 downto 8) <= unsigned(VDATA); - when "1000" => - H_SYNC_END(7 downto 0) <= unsigned(VDATA); - when "1001" => - H_SYNC_END(15 downto 8) <= unsigned(VDATA); - when "1010" => - V_SYNC_START(7 downto 0) <= unsigned(VDATA); - when "1011" => - V_SYNC_START(15 downto 8) <= unsigned(VDATA); - when "1100" => - V_SYNC_END(7 downto 0) <= unsigned(VDATA); - when "1101" => - V_SYNC_END(15 downto 8) <= unsigned(VDATA); - when "1110" => - H_PX(7 downto 0) <= unsigned(VDATA); - when "1111" => - V_PX(7 downto 0) <= unsigned(VDATA); + case DSP_PARAM_SEL is + when "0000" => + H_DSP_START(15 downto 8) <= unsigned(VDATA); + when "0001" => + H_DSP_END(15 downto 8) <= unsigned(VDATA); + when "0010" => + H_DSP_WND_START(15 downto 8) <= unsigned(VDATA); + when "0011" => + H_DSP_WND_END(15 downto 8) <= unsigned(VDATA); + when "0100" => + V_DSP_START(15 downto 8) <= unsigned(VDATA); + when "0101" => + V_DSP_END(15 downto 8) <= unsigned(VDATA); + when "0110" => + V_DSP_WND_START(15 downto 8) <= unsigned(VDATA); + when "0111" => + V_DSP_WND_END(15 downto 8) <= unsigned(VDATA); + when "1000" => + H_LINE_END(15 downto 8) <= unsigned(VDATA); + when "1001" => + V_LINE_END(15 downto 8) <= unsigned(VDATA); + when "1010" => + when "1011" => + H_SYNC_START(15 downto 8) <= unsigned(VDATA); + when "1100" => + H_SYNC_END(15 downto 8) <= unsigned(VDATA); + when "1101" => + V_SYNC_START(15 downto 8) <= unsigned(VDATA); + when "1110" => + V_SYNC_END(15 downto 8) <= unsigned(VDATA); + when "1111" => + V_PX(7 downto 0) <= unsigned(VDATA); + end case; + + when others => end case; end if; @@ -1093,13 +1257,13 @@ begin if H_COUNT = H_DSP_START then H_BLANKi <= '0'; end if; -- if H_COUNT = H_LINE_END then H_BLANKi <= '0'; end if; if H_COUNT = H_DSP_END then H_BLANKi <= '1'; end if; - if H_COUNT = H_SYNC_END then H_SYNC_ni <= '1'; end if; - if H_COUNT = H_SYNC_START then H_SYNC_ni <= '0'; end if; + if H_COUNT = H_SYNC_END then H_SYNCni <= '1'; end if; + if H_COUNT = H_SYNC_START then H_SYNCni <= '0'; end if; if V_COUNT = V_DSP_START then V_BLANKi <= '0'; end if; -- if V_COUNT = V_LINE_END then V_BLANKi <= '0'; end if; if V_COUNT = V_DSP_END then V_BLANKi <= '1'; end if; - if V_COUNT = V_SYNC_START then V_SYNC_ni <= '0'; end if; - if V_COUNT = V_SYNC_END then V_SYNC_ni <= '1'; end if; + if V_COUNT = V_SYNC_START then V_SYNCni <= '0'; end if; + if V_COUNT = V_SYNC_END then V_SYNCni <= '1'; end if; -- If we are in the active visible area, stream the required output based on the various buffers. -- @@ -1219,8 +1383,8 @@ begin V_I_COUNT <= (others => '0'); H_I_BLANKi <= '1'; V_I_BLANKi <= '1'; - H_I_SYNC_ni <= '1'; - V_I_SYNC_ni <= '1'; + H_I_SYNCni <= '1'; + V_I_SYNCni <= '1'; elsif rising_edge(VID_CLK_I) then @@ -1231,7 +1395,7 @@ begin -- Load up configuration using static values. Internal display can only display 40 or 80 chars. -- - if MODE_MONO or MODE_COLOUR then + if MODE_VIDEO_MONO or MODE_VIDEO_COLOUR then H_I_DSP_START <= to_unsigned(0, H_I_DSP_START'length); H_I_DSP_END <= to_unsigned(320, H_I_DSP_END'length); V_I_DSP_START <= to_unsigned(0, V_I_DSP_START'length); @@ -1259,22 +1423,22 @@ begin V_I_COUNT <= (others => '0'); H_I_BLANKi <= '0'; V_I_BLANKi <= '0'; - H_I_SYNC_ni <= '1'; - V_I_SYNC_ni <= '1'; + H_I_SYNCni <= '1'; + V_I_SYNCni <= '1'; else -- Activate/deactivate signals according to pixel position. -- - --if H_I_COUNT = H_I_LINE_END then H_I_BLANKi <= '0'; end if; - if H_I_COUNT = H_I_DSP_START then H_I_BLANKi <= '0'; end if; - if H_I_COUNT = H_I_DSP_END then H_I_BLANKi <= '1'; end if; - if H_I_COUNT = H_I_SYNC_END then H_I_SYNC_ni <= '1'; end if; - if H_I_COUNT = H_I_SYNC_START then H_I_SYNC_ni <= '0'; end if; - -- if V_I_COUNT = V_I_LINE_END then V_I_BLANKi <= '0'; end if; - if V_I_COUNT = V_I_DSP_START then V_I_BLANKi <= '0'; end if; - if V_I_COUNT = V_I_DSP_END then V_I_BLANKi <= '1'; end if; - if V_I_COUNT = V_I_SYNC_START then V_I_SYNC_ni <= '0'; end if; - if V_I_COUNT = V_I_SYNC_END then V_I_SYNC_ni <= '1'; end if; + --if H_I_COUNT = H_I_LINE_END then H_I_BLANKi <= '0'; end if; + if H_I_COUNT = H_I_DSP_START then H_I_BLANKi <= '0'; end if; + if H_I_COUNT = H_I_DSP_END then H_I_BLANKi <= '1'; end if; + if H_I_COUNT = H_I_SYNC_END then H_I_SYNCni <= '1'; end if; + if H_I_COUNT = H_I_SYNC_START then H_I_SYNCni <= '0'; end if; + -- if V_I_COUNT = V_I_LINE_END then V_I_BLANKi <= '0'; end if; + if V_I_COUNT = V_I_DSP_START then V_I_BLANKi <= '0'; end if; + if V_I_COUNT = V_I_DSP_END then V_I_BLANKi <= '1'; end if; + if V_I_COUNT = V_I_SYNC_START then V_I_SYNCni <= '0'; end if; + if V_I_COUNT = V_I_SYNC_END then V_I_SYNCni <= '1'; end if; -- Horizontal/Vertical counters are updated each clock cycle to accurately track pixel/timing. -- @@ -1295,16 +1459,359 @@ begin end if; end process; + -- A basic Graphics Processing Unit. The idea is to speed up certain tasks such as clearing the screen or setting a fixed colour. + -- The GPU works by several writes to the FB_PARAMS register which stores upto 128bits of parameters, the bit allocation depending upon the command given later. + -- Once the parameters are stored, a command is written into the GPU control register and the requested task is undertaken. + -- + -- Command word:- + -- Bit [7] - 0 = VRAN, 1 = Pixel Frame Buffer + -- Bits [6:0] - Command:- + -- 0x00 = NOP/Idle. + -- + -- VRAM commands. + -- 0x01 = Clear VRAM screen. + -- 0x02 = Clear VRAM screen with char and attribute: Parameters: [15:8] - character, [7:0] - attribute byte + -- 0x03 = Parameterised Clear VRAM screen: Parameters: [47:40] - Start X, [39:32] - Start Y, [31:24] - End X, [23:16] - End Y, [15:8] - display char, [7:0] - attribute byte + -- Framebuffer commands. + -- 0x81 = Clear framebuffer screen. Clear entire screen using current R/G/B filters. + -- 0x82 = Parameterised Clear framebuffer screen. Parameters: start x [87:72], start y [71:56], end x [55:40], end y [39:24], R Filter [23:16], G Filter [15:8], B Filter [7:0] - R/G/B Filters are 8 pixel wide. + -- Other commands. + -- 0xFF = Immediate GPU reset, cancel current command and return to idle. + GPU: process( VRESETn, IF_CLK, SYS_CLK ) + variable GPU_START_ADDR : std_logic_vector(13 downto 0); -- Current start address being worked on by the GPU. + variable GPU_START_X : integer range 0 to 640; -- X starting location. + variable GPU_START_Y : integer range 0 to 200; -- Y starting location. + variable GPU_END_X : integer range 0 to 640; -- X ending location. + variable GPU_END_Y : integer range 0 to 200; -- Y ending location. + variable GPU_COLUMNS : integer range 0 to 132; -- Number of char per row, setting is dynamic based on video mode. + variable GPU_ROWS : integer range 0 to 50; -- Number of rows, setting is dynamic based on video mode. + variable GPU_VAR_Y : integer range 0 to 200; -- Working Y position + variable GPU_FILTER_R : std_logic_vector(7 downto 0); -- Byte wide filter for 8 pixels, 0 = pixel off, 1 = pixel on. + variable GPU_FILTER_G : std_logic_vector(7 downto 0); -- Byte wide filter for 8 pixels, 0 = pixel off, 1 = pixel on. + variable GPU_FILTER_B : std_logic_vector(7 downto 0); -- Byte wide filter for 8 pixels, 0 = pixel off, 1 = pixel on. + variable GPU_VRAM_CHAR : std_logic_vector(7 downto 0); -- Character byte to write into VRAM. + variable GPU_VRAM_ATTR : std_logic_vector(7 downto 0); -- Attribute byte to write into VRAM. + begin + -- Ensure default values at reset. + if VRESETn='0' then + GPU_STATUS <= "00000000"; + GRAM_GPU_DI_R <= (others => '0'); + GRAM_GPU_DI_G <= (others => '0'); + GRAM_GPU_DI_B <= (others => '0'); + GWEN_GPU_R <= '0'; + GWEN_GPU_G <= '0'; + GWEN_GPU_B <= '0'; + VRAM_GPU_WEN <= '0'; + GRAM_GPU_ADDR <= (others => '0'); + GPU_STATE <= GPU_State_Idle; + + elsif rising_edge(SYS_CLK) then + + -- GPU access to GRAM is controlled by state rather than setting a flag in each state which waits for a clock edge to latch. + -- + if GPU_STATE = GPU_FB_Clear_1 or GPU_STATE = GPU_FB_Clear_2 then + GRAM_GPU_ENABLE <= '1'; + else + GRAM_GPU_ENABLE <= '0'; + end if; + + -- GPU access to VRAM is controlled by state rather than setting a flag in each state which waits for a clock edge to latch. + -- + if GPU_STATE = GPU_VRAM_Clear_1 or GPU_STATE = GPU_VRAM_Clear_2 then + VRAM_GPU_ENABLE <= '1'; + else + VRAM_GPU_ENABLE <= '0'; + end if; + + -- Debug, view the FSM state via the status register. + GPU_STATUS(7 downto 1) <= std_logic_vector(to_unsigned(GPUStateType'POS(GPU_STATE), 7)); + + -- A reset command whilst the GPU FSM is busy cancels the operation and returns the FSM to idle. + if GPU_COMMAND = X"FF" then + GPU_STATE <= GPU_State_Idle; + GPU_STATUS(0) <= '0'; + + -- If a command has been given and we are not executing a command, start the FSM. + elsif GPU_COMMAND(6 downto 0) /= "0000000" and GPU_STATE = GPU_State_Idle then + -- GPU busy. + GPU_STATUS(0) <= '1'; + + case GPU_COMMAND is + -- Clear the VRAM without updating attributes. + when X"01" => + GPU_STATE <= GPU_VRAM_Clear; + + -- Clear the VRAM/ARAM with given attribute byte, + when X"02" => + GPU_STATE <= GPU_VRAM_Clear_Attr; + + -- Clear the VRAM/ARAM with parameters. + when X"03" => + GPU_STATE <= GPU_VRAM_Clear_Param; + + -- Clear the entire Framebuffer. + when X"81" => + GPU_STATE <= GPU_FB_Clear; + -- Clear the Framebuffer according to parameters. + when X"82" => + GPU_STATE <= GPU_FB_Clear_Param; + + when others => + GPU_STATE <= GPU_State_Idle; + end case; + + else + + -- FSM for the Graphics Processing Unit. + -- + case GPU_STATE is + -- Clear the entire display, all pixels off. + when GPU_FB_Clear => + GPU_START_X := 0; + GPU_START_Y := 0; + GPU_END_X := 640; + GPU_END_Y := 200; + GPU_FILTER_R := (others => '0'); + GPU_FILTER_G := (others => '0'); + GPU_FILTER_B := (others => '0'); + GPU_STATE <= GPU_FB_Clear_Start; + + -- Clear a parameterised part of the display, + -- Parameters: start x [87:72], start y [71:56], end x [55:40], end y [39:24], R Filter [23:16], G Filter [15:8], B Filter [7:0] - R/G/B Filters are 8 pixel wide. + when GPU_FB_Clear_Param => + if to_integer(unsigned(GPU_PARAMS(87 downto 72))) >= 640 then + GPU_START_X := 0; + else + GPU_START_X := to_integer(unsigned(GPU_PARAMS(87 downto 72))); + end if; + if to_integer(unsigned(GPU_PARAMS(71 downto 56))) >= 200 then + GPU_START_Y := 0; + else + GPU_START_Y := to_integer(unsigned(GPU_PARAMS(71 downto 56))); + end if; + if to_integer(unsigned(GPU_PARAMS(55 downto 40))) <= to_integer(unsigned(GPU_PARAMS(87 downto 72))) or to_integer(unsigned(GPU_PARAMS(55 downto 40))) >= 640 then + GPU_END_X := 640; + else + GPU_END_X := to_integer(unsigned(GPU_PARAMS(55 downto 40))); + end if; + if to_integer(unsigned(GPU_PARAMS(39 downto 24))) <= to_integer(unsigned(GPU_PARAMS(71 downto 56))) or to_integer(unsigned(GPU_PARAMS(39 downto 24))) >= 200 then + GPU_END_Y := 200; + else + GPU_END_Y := to_integer(unsigned(GPU_PARAMS(39 downto 24))); + end if; + GPU_FILTER_R := GPU_PARAMS(23 downto 16); + GPU_FILTER_G := GPU_PARAMS(15 downto 8); + GPU_FILTER_B := GPU_PARAMS(7 downto 0); + GPU_STATE <= GPU_FB_Clear_Start; + + when GPU_FB_Clear_Start => + GPU_START_ADDR := std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14)); + GRAM_GPU_ADDR <= std_logic_vector(to_unsigned(((GPU_START_X / 8) + (GPU_START_Y * 80)), 14)); + GRAM_GPU_DI_R <= GPU_FILTER_R; + GRAM_GPU_DI_G <= GPU_FILTER_G; + GRAM_GPU_DI_B <= GPU_FILTER_B; + GPU_VAR_Y := GPU_START_Y; + GPU_STATE <= GPU_FB_Clear_1; + + -- Wait for the vertical blanking period before writing into the framebuffer. + when GPU_FB_Clear_1 => + if V_BLANKi = '1' then + GWEN_GPU_R <= '1'; + GWEN_GPU_G <= '1'; + GWEN_GPU_B <= '1'; + GPU_STATE <= GPU_FB_Clear_2; + end if; + + when GPU_FB_Clear_2 => + GWEN_GPU_R <= '0'; + GWEN_GPU_G <= '0'; + GWEN_GPU_B <= '0'; + + if to_integer(unsigned(GRAM_GPU_ADDR)) >= to_integer(unsigned(GPU_START_ADDR)) + ((GPU_END_X - GPU_START_X)/8) or GRAM_GPU_ADDR = X"3FFF" then + if GPU_VAR_Y >= GPU_END_Y then + GPU_STATE <= GPU_FB_Clear_3; + else + GRAM_GPU_ADDR <= GPU_START_ADDR + 80; + GPU_START_ADDR:= GPU_START_ADDR + 80; + GPU_VAR_Y := GPU_VAR_Y + 1; + GPU_STATE <= GPU_FB_Clear_1; + end if; + else + GRAM_GPU_ADDR <= GRAM_GPU_ADDR + 1; + GPU_STATE <= GPU_FB_Clear_1; + end if; + + when GPU_FB_Clear_3 => + GPU_STATE <= GPU_State_Idle; + + -- Clear the entire VRAM display to no characters and a blue background (for the MZ-700/colour modes). + when GPU_VRAM_Clear => + GPU_COLUMNS := 128; + GPU_ROWS := 16; + GPU_START_X := 0; + GPU_START_Y := 0; + GPU_END_X := GPU_COLUMNS - 1; + GPU_END_Y := GPU_ROWS - 1; + GPU_VRAM_CHAR := X"00"; + GPU_VRAM_ATTR := X"71"; + GPU_STATE <= GPU_VRAM_Clear_Start; + + -- Clear the entire VRAM display to a character and a colour given as a parameter, [15:8] = character, [7:0] = attribute byte. + when GPU_VRAM_Clear_Attr => + GPU_COLUMNS := 128; + GPU_ROWS := 16; + GPU_START_X := 0; + GPU_START_Y := 0; + GPU_END_X := GPU_COLUMNS - 1; + GPU_END_Y := GPU_ROWS - 1; + GPU_VRAM_CHAR := GPU_PARAMS(15 downto 8); + GPU_VRAM_ATTR := GPU_PARAMS(7 downto 0); + GPU_STATE <= GPU_VRAM_Clear_Start; + + -- Clear the VRAM display according to given parameters: + -- Parameters: [47:40] - Start X, [39:32] - Start Y, [31:24] - End X, [23:16] - End Y, [15:8] - display char, [7:0] - attribute byte + when GPU_VRAM_Clear_Param => + -- Update the column setting according to the dynamic mode. + if MODE_VIDEO_MONO = '1' or MODE_VIDEO_COLOUR = '1' then + GPU_COLUMNS := 40; + else + GPU_COLUMNS := 80; + end if; + GPU_ROWS := 25; + + -- Read and check the parameters. + if to_integer(unsigned(GPU_PARAMS(47 downto 40))) >= GPU_COLUMNS - 1 then + GPU_START_X := GPU_COLUMNS - 1; + else + GPU_START_X := to_integer(unsigned(GPU_PARAMS(47 downto 40))); + end if; + if to_integer(unsigned(GPU_PARAMS(39 downto 32))) >= GPU_ROWS - 1 then + GPU_START_Y := GPU_ROWS - 1; + else + GPU_START_Y := to_integer(unsigned(GPU_PARAMS(39 downto 32))); + end if; + if to_integer(unsigned(GPU_PARAMS(31 downto 24))) < to_integer(unsigned(GPU_PARAMS(47 downto 40))) or to_integer(unsigned(GPU_PARAMS(31 downto 24))) >= GPU_COLUMNS - 1 then + GPU_END_X := GPU_COLUMNS - 1; + else + GPU_END_X := to_integer(unsigned(GPU_PARAMS(31 downto 24))); + end if; + if to_integer(unsigned(GPU_PARAMS(23 downto 16))) < to_integer(unsigned(GPU_PARAMS(39 downto 32))) or to_integer(unsigned(GPU_PARAMS(23 downto 16))) >= GPU_ROWS - 1 then + GPU_END_Y := GPU_ROWS - 1; + else + GPU_END_Y := to_integer(unsigned(GPU_PARAMS(23 downto 16))); + end if; + GPU_VRAM_CHAR := GPU_PARAMS(15 downto 8); + GPU_VRAM_ATTR := GPU_PARAMS(7 downto 0); + GPU_STATE <= GPU_VRAM_Clear_Start; + + when GPU_VRAM_Clear_Start => + -- For modes with hardware scroll, add in the current offset so the visible part of the display is updated. + if MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ700 = '1' then + GPU_START_ADDR:= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14)) + (OFFSET_ADDR & "000"); + VRAM_GPU_ADDR <= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 13)) + (OFFSET_ADDR & "000"); + else + GPU_START_ADDR:= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 14)); + VRAM_GPU_ADDR <= std_logic_vector(to_unsigned((GPU_START_X + (GPU_START_Y * GPU_COLUMNS)), 13)); + end if; + GPU_VAR_Y := GPU_START_Y; + GPU_STATE <= GPU_VRAM_Clear_1; + + when GPU_VRAM_Clear_1 => + + -- Set data according to region being filled, character (000:7FF) or attribute (800:FFF) + if VRAM_GPU_ADDR < X"800" then + VRAM_GPU_DI <= GPU_VRAM_CHAR; + else + VRAM_GPU_DI <= GPU_VRAM_ATTR; + end if; + + -- Need to wait for the vertical blanking interval even though were using dual port RAM, this is to avoid part display or + -- old data and new data causing a visible tear. + if V_BLANKi = '1' then + VRAM_GPU_WEN <= '1'; + end if; + + -- Keep the Write Enable active for one full clock cycle before moving on to the next state. + if VRAM_GPU_WEN = '1' then + GPU_STATE <= GPU_VRAM_Clear_2; + end if; + + when GPU_VRAM_Clear_2 => + VRAM_GPU_WEN <= '0'; + GPU_STATE <= GPU_VRAM_Clear_1; + + if (to_integer(unsigned(VRAM_GPU_ADDR)) >= to_integer(unsigned(GPU_START_ADDR)) + (GPU_END_X - GPU_START_X)) or VRAM_GPU_ADDR >= X"FFF" then + + -- If we have completed filling in the entire char and attr RAM, exit. + if VRAM_GPU_ADDR >= X"FFF" then + GPU_STATE <= GPU_VRAM_Clear_3; + else + -- Alternate between character ram and attribute ram, they differ by 0x800 bytes, ie; 0xD000:D7FF and 0xD800:0xDFFF + if VRAM_GPU_ADDR < X"800" then + VRAM_GPU_ADDR <= GPU_START_ADDR(12 downto 0) + X"800"; + GPU_START_ADDR := GPU_START_ADDR + X"800"; + else + VRAM_GPU_ADDR <= GPU_START_ADDR(12 downto 0) - X"800" + GPU_COLUMNS; + GPU_START_ADDR := GPU_START_ADDR - X"800" + GPU_COLUMNS; + GPU_VAR_Y := GPU_VAR_Y + 1; + + -- If we have filled to the set line, exit. + if GPU_VAR_Y > GPU_END_Y then + GPU_STATE <= GPU_VRAM_Clear_3; + end if; + end if; + end if; + else + VRAM_GPU_ADDR <= VRAM_GPU_ADDR + 1; + end if; + + when GPU_VRAM_Clear_3 => + GPU_STATE <= GPU_State_Idle; + + -- Set to idle and cancel any active signals. + when others => + -- GPU idle. + GPU_STATUS(0) <= '0'; + GWEN_GPU_R <= '0'; + GWEN_GPU_G <= '0'; + GWEN_GPU_B <= '0'; + VRAM_GPU_WEN <= '0'; + end case; + end if; + end if; + end process; -- Control Registers -- -- MZ1200/80A: INVERT display, accessed at E014 -- SCROLL display, accessed at E200 - E2FF, the address determines the offset. - -- F4-F7 set ths MZ80B/MZ2000 graphics options. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. - -- Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display. -- - -- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF8->. - -- 0xF8= sets the mode that of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col. + -- Video Mode (display output): + -- 0xD0 - Set the Video Mode parameter number to update. + -- 0xD1 - Update the lower selected Video Mode parameter byte. + -- 0xD2 - Update the upper selected Video Mode parameter byte. + -- Palette configuration: + -- 0xD3 - set the palette slot (PALETTE_PARAM_SEL) Off position to be adjusted. + -- 0xD4 - set the palette slot (PALETTE_PARAM_SEL) On position to be adjusted. + -- 0xD5 - set the red palette value according to the PALETTE_PARAM_SEL address. + -- 0xD6 - set the green palette value according to the PALETTE_PARAM_SEL address. + -- 0xD7 - set the blue palette value according to the PALETTE_PARAM_SEL address. + -- MZ-80B GRAM: + -- 0xF4 set the MZ80B/MZ2000 graphics options. + -- Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. + -- Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display. + -- Select Palette: + -- 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output. + -- Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input. + -- GPU: + -- 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor. + -- The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0. + -- 0xF7 set the graphics processor unit commands. + -- Bits [5:0] - 0 = Reset parameters. + -- 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter + -- + -- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF5->. + -- 0xF8= sets the mode of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col. -- 0xF9= sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). -- 0xFA= sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte). -- 0xFB= sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte). @@ -1324,64 +1831,135 @@ begin GRAM_OPT_WRITE <= '0'; GRAM_OPT_OUT1 <= '0'; GRAM_OPT_OUT2 <= '0'; - GRAM_MZ80B_ENABLE <= '0'; PCGRAM <= '0'; - MODE_MZ80A <= '1'; - MODE_MZ700 <= '0'; - MODE_MZ800 <= '0'; - MODE_MZ80B <= '0'; - MODE_MZ80K <= '0'; - MODE_MZ80C <= '0'; - MODE_MZ1200 <= '0'; - MODE_MZ2000 <= '0'; - MODE_MONO <= '1'; - MODE_MONO80 <= '0'; - MODE_COLOUR <= '0'; - MODE_COLOUR80 <= '0'; + MODE_VIDEO_MZ80A <= '1'; + MODE_VIDEO_MZ700 <= '0'; + MODE_VIDEO_MZ800 <= '0'; + MODE_VIDEO_MZ80B <= '0'; + MODE_VIDEO_MZ80K <= '0'; + MODE_VIDEO_MZ80C <= '0'; + MODE_VIDEO_MZ1200 <= '0'; + MODE_VIDEO_MZ2000 <= '0'; + MODE_VIDEO_MONO <= '1'; + MODE_VIDEO_MONO80 <= '0'; + MODE_VIDEO_COLOUR <= '0'; + MODE_VIDEO_COLOUR80 <= '0'; + MODE_CPLD_SWITCH <= '0'; VIDEO_MODE_REG <= "00000000"; VGAMODE <= "00"; - GRAM_PAGE_ENABLE <= '0'; + GRAM_PAGE_ENABLE <= "00"; CGROM_PAGE <= '0'; - CS_LAST_LEVEL <= (others => '1'); DISABLE_INT_DISPLAY <= '0'; DISPLAY_VGATE <= '0'; VIDEOMODE_RESET_TIMER <= to_unsigned(2, VIDEOMODE_RESET_TIMER'length); --(others => '0') & '1'; CGRAM_ADDR <= (others=>'0'); PCG_DATA <= (others=>'0'); - CGRAM_WE_n <= '1'; + CPLD_CFG_DATA <= "00000011"; + PALETTE_REG <= (others => '0'); + PALETTE_PARAM_SEL <= (others => '0'); + CGRAM_WEn <= '1'; + GPU_PARAMS <= (others => '0'); + GPU_COMMAND <= (others => '0'); elsif rising_edge(IF_CLK) then + -- Edge detection on the Z80 RD/WR signals. The clock is potentially running at a multiple of the CPU clock + -- so detecting an edge is important so as not to act on the signals more than once per transaction. + VZ80_WR_LASTn <= VZ80_WRn; + VZ80_RD_LASTn <= VZ80_RDn; + + -- If the GPU goes busy, clear the command register ready for next command. + -- + if CS_FB_GPUn = '1' and GPU_STATUS(0) = '1' then + GPU_COMMAND <= (others => '0'); + end if; + + -- Clear write enables to the palette register. + -- + PALETTE_WEN_R <= '0'; + PALETTE_WEN_G <= '0'; + PALETTE_WEN_B <= '0'; + -- MZ80A has hardware inversion which is basically the inversion of the video out stream. A signal is set when inversion is required by a read to E014 and reset -- with a read to E015. - if CS_INVERT_n='0' and CS_LAST_LEVEL(0) = '1' and VRDn='0' then + if CS_INVERTn='0' and VZ80_RDn='0' and VZ80_RD_LASTn = '1' and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ700 = '1') then DISPLAY_INVERT <= Z80_MA(0); end if; -- MZ80A has hardware scrolling which is basically the addition, in blocks of 8, to the video address line. A read from E200 will set the addition to 0, -- a read from each location, E201 - E2FE will add X x 8 bytes to the address, a read from E2FF will scroll fully to the end of the VRAM buffer. - if CS_SCROLL_n='0' and CS_LAST_LEVEL(1) = '1' and VRDn='0' then - if MODE_MONO80 = '1' or MODE_COLOUR80 = '1' then + if CS_SCROLLn='0' and VZ80_RDn='0' and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ700 = '1') then + if MODE_VIDEO_MONO80 = '1' or MODE_VIDEO_COLOUR80 = '1' then OFFSET_ADDR <= (others => '0'); else OFFSET_ADDR <= VADDR(7 downto 0); end if; end if; + + -- Setup the palette register to given value. + if CS_FB_PALETTEn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then + PALETTE_REG <= VDATA; + end if; + + -- Setup the palette values for off and on states. + -- + if CS_IO_DXXn = '0' and VZ80_WRn = '0' then + + case VADDR(3 downto 0) is + -- 0xD3 - set the palette slot Off position to be adjusted. + when "0011" => + PALETTE_PARAM_SEL <= VDATA & '0'; + + -- 0xD4 - set the palette slot On position to be adjusted. + when "0100" => + PALETTE_PARAM_SEL <= VDATA & '1'; + + -- 0xD5 - set the red palette value according to the PALETTE_PARAM_SEL address. + when "0101" => + PALETTE_WEN_R <= '1'; + + -- 0xD6 - set the green palette value according to the PALETTE_PARAM_SEL address. + when "0110" => + PALETTE_WEN_G <= '1'; + + -- 0xD7 - set the blue palette value according to the PALETTE_PARAM_SEL address. + when "0111" => + PALETTE_WEN_B <= '1'; + + when others => + end case; + end if; + + -- Store the incoming GPU parameters in a 128bit register. + if CS_FB_PARAMSn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then + GPU_PARAMS(127 downto 8) <= GPU_PARAMS(119 downto 0); + GPU_PARAMS(7 downto 0) <= VDATA; + end if; + + -- Read out the rightmost byte of the GPU parameters and shift right, this allows reading or manipulating the parameters. + if CS_FB_PARAMSn = '0' and VZ80_RDn = '0' and VZ80_RD_LASTn = '1' then + GPU_PARAMS(119 downto 0) <= GPU_PARAMS(127 downto 8); + end if; + + -- Store the incoming GPU command. + if CS_FB_GPUn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then + GPU_COMMAND <= VDATA; + end if; -- Setup the machine mode and video mode. - if CS_FB_VM_n = '0' and CS_LAST_LEVEL(2) = '1' and VWRn = '0' then - MODE_MZ80A <= '0'; - MODE_MZ700 <= '0'; - MODE_MZ800 <= '0'; - MODE_MZ80B <= '0'; - MODE_MZ80K <= '0'; - MODE_MZ80C <= '0'; - MODE_MZ1200 <= '0'; - MODE_MZ2000 <= '0'; - MODE_MONO <= '0'; - MODE_MONO80 <= '0'; - MODE_COLOUR <= '0'; - MODE_COLOUR80 <= '0'; + if CS_FB_VMn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then + MODE_VIDEO_MZ80A <= '0'; + MODE_VIDEO_MZ700 <= '0'; + MODE_VIDEO_MZ800 <= '0'; + MODE_VIDEO_MZ80B <= '0'; + MODE_VIDEO_MZ80K <= '0'; + MODE_VIDEO_MZ80C <= '0'; + MODE_VIDEO_MZ1200 <= '0'; + MODE_VIDEO_MZ2000 <= '0'; + MODE_VIDEO_MONO <= '0'; + MODE_VIDEO_MONO80 <= '0'; + MODE_VIDEO_COLOUR <= '0'; + MODE_VIDEO_COLOUR80<= '0'; VIDEO_MODE_REG <= VDATA; -- Store the programmed setting for CPU readback. -- Bits [2:0] define the Video Module machine compatibility. @@ -1390,96 +1968,98 @@ begin -- Bit [5] defines wether PCGRAM is enabled, 0 = disabled, 1 = enabled. -- Bits [7:6] define the VGA mode. -- - case VDATA(2 downto 0) is - when "000" => - MODE_MZ80A <= '1'; + case to_integer(unsigned(VDATA(2 downto 0))) is + when MODE_MZ80A => + MODE_VIDEO_MZ80A <= '1'; -- The MZ-80A is a monochrome machine by default but can have the optional colour board, so consider the -- colour flage (4) and the 40/80 column flag (3) to setup correct mode. -- if VDATA(4) = '0' and VDATA(3) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; elsif VDATA(3) = '1' and VDATA(4) = '0' then - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; elsif VDATA(3) = '0' and VDATA(4) = '1' then - MODE_COLOUR <= '1'; + MODE_VIDEO_COLOUR <= '1'; else - MODE_COLOUR80 <= '1'; + MODE_VIDEO_COLOUR80 <= '1'; end if; - when "001" => - MODE_MZ700 <= '1'; - - -- MZ-700 is a colour machine, so only consider the 40/80 column switch. - if VDATA(3) = '0' then - MODE_COLOUR <= '1'; - else - MODE_COLOUR80 <= '1'; - end if; - - when "010" => - MODE_MZ800 <= '1'; + when MODE_MZ800 => + MODE_VIDEO_MZ800 <= '1'; -- MZ-800 is a colour machine, so only consider the 40/80 column switch. -- This flag is also updated in the MZ-800 emulation using the original port/bit. The two modes provide a common -- interface, for the superset code and for original machine compatibility. if VDATA(3) = '0' then - MODE_COLOUR <= '1'; + MODE_VIDEO_COLOUR <= '1'; else - MODE_COLOUR80 <= '1'; + MODE_VIDEO_COLOUR80 <= '1'; end if; - when "011" => - MODE_MZ80B <= '1'; + when MODE_MZ80B => + MODE_VIDEO_MZ80B <= '1'; -- The MZ-80B is a monochrome machine so only consider monochrome. This is intentional as the GRAM used by the MZ80B -- is used for the colour framebuffer, so true colour is not possible when using MZ80B compatible graphics. Colour is -- possible if direct access to the colour frame buffers is used but this is a superset feature. if VDATA(3) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; else - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; end if; - when "100" => - MODE_MZ80K <= '1'; + when MODE_MZ80K => + MODE_VIDEO_MZ80K <= '1'; -- The MZ-80K is a mono machine, so only consider the 40/80 column flag as extensions to the original hardware were made for CP/M. if VDATA(3) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; else - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; end if; - when "101" => - MODE_MZ80C <= '1'; + when MODE_MZ80C => + MODE_VIDEO_MZ80C <= '1'; -- The MZ-80C is a mono machine, so only consider the 40/80 column flag as extensions to the original hardware were made for CP/M. if VDATA(3) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; else - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; end if; - when "110" => - MODE_MZ1200 <= '1'; + when MODE_MZ1200 => + MODE_VIDEO_MZ1200 <= '1'; -- The MZ-1200 is a mono machine, so only consider the 40/80 column flag as extensions to the original hardware were made for CP/M. if VDATA(3) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; else - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; end if; - when "111" => - MODE_MZ2000 <= '1'; + when MODE_MZ2000 => + MODE_VIDEO_MZ2000 <= '1'; -- The MZ-2000 is an enhancement of the MZ80B. At the moment the logic hasnt been written so we set it as an MZ80B for the time being. if VDATA(3) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; else - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; end if; + + when MODE_MZ700 => + MODE_VIDEO_MZ700 <= '1'; + + -- MZ-700 is a colour machine, so only consider the 40/80 column switch. + if VDATA(3) = '0' then + MODE_VIDEO_COLOUR <= '1'; + else + MODE_VIDEO_COLOUR80 <= '1'; + end if; + + when others => end case; -- PCG RAM, enable/disable. @@ -1503,36 +2083,36 @@ begin -- Framebuffer control register. -- sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). - if CS_FB_CTL_n = '0' and CS_LAST_LEVEL(3) = '1' and VWRn = '0' then + if CS_FB_CTLn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then GRAM_MODE_REG <= VDATA; end if; -- sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte). - if CS_FB_RED_n = '0' and CS_LAST_LEVEL(4) = '1' and VWRn = '0' then + if CS_FB_REDn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then GRAM_R_FILTER <= VDATA; end if; -- sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte). - if CS_FB_GREEN_n = '0' and CS_LAST_LEVEL(5) = '1' and VWRn = '0' then + if CS_FB_GREENn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then GRAM_G_FILTER <= VDATA; end if; -- sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte). - if CS_FB_BLUE_n = '0' and CS_LAST_LEVEL(6) = '1' and VWRn = '0' then + if CS_FB_BLUEn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then GRAM_B_FILTER <= VDATA; end if; -- set ths MZ80B/MZ2000 graphics options. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. -- Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display. - if CS_GRAM_OPT_n = '0' and CS_LAST_LEVEL(7) = '1' and VWRn = '0' then + if CS_GRAM_OPTn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then GRAM_OPT_WRITE <= VDATA(0); GRAM_OPT_OUT1 <= VDATA(1); GRAM_OPT_OUT2 <= VDATA(2); end if; - -- memory page register. [0] switches in a 16Kb page of graphics ram to C000 - FFFF as determined by the GRAM_MODE_REG[3:0]. [0] = 0 - graphics RAM off (paged out), [0] = 1 - graphics RAM on (paged in). This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal CGROM operation, 1 - switches in CGROM for upload at D000:DFFF. - if CS_FB_PAGE_n = '0' and CS_LAST_LEVEL(8) = '1' then - GRAM_PAGE_ENABLE <= VDATA(0); + -- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF. + if CS_FB_PAGEn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then + GRAM_PAGE_ENABLE <= VDATA(1 downto 0); CGROM_PAGE <= VDATA(7); end if; @@ -1543,7 +2123,7 @@ begin -- PC3 = 0 = Starts IPL. -- PC1 = 1 = Sets memory in normal state, starting $0000. -- PC0 = 1 = Unconditionally clears the display screen. - if CS_80B_PPI_n = '0' and CS_LAST_LEVEL(9) = '1' and VWRn = '0' then + if CS_80B_PPIn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then -- Port A if VADDR(1 downto 0) = "00" then @@ -1572,11 +2152,11 @@ begin end if; -- MZ80B 8253 PIT. - if CS_80B_PIT_n = '0' and CS_LAST_LEVEL(10) = '1' and VWRn = '0' then + if CS_80B_PITn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then end if; -- MZ80B Z80 PIO. - if CS_80B_PIO_n = '0' and CS_LAST_LEVEL(11) = '1' and VWRn = '0' then + if CS_80B_PIOn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then -- Write to PIO A. -- 7 = Assigns addresses $DOOO-$FFFF to V-RAM. @@ -1586,13 +2166,19 @@ begin MZ80B_VRAM_HI_ADDR <= VDATA(7); MZ80B_VRAM_LO_ADDR <= VDATA(6); if VDATA(5) = '0' then - MODE_MONO <= '1'; + MODE_VIDEO_MONO <= '1'; else - MODE_MONO80 <= '1'; + MODE_VIDEO_MONO80 <= '1'; end if; end if; end if; + -- MZ80B Video Mode. + -- + if CS_80B_VMODEn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then + MZ80B_VMODE_REG <= VDATA; + end if; + -- -- PCG Access Registers -- @@ -1610,7 +2196,7 @@ begin -- - set the first row address of the character: PCG_ADDR[0..7] = row[0..7] and PCG_CTRL[0..1] = row[8..9] -- - set the 8 pixels of the row in PCG_DATA -- - if CS_PCG_n = '0' and CS_LAST_LEVEL(16) = '1' and VWRn = '0' then + if CS_PCGn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then -- Set the PCG Data to program to RAM. if VADDR(1 downto 0) = "00" then PCG_DATA <= VDATA; @@ -1623,275 +2209,390 @@ begin -- Set the PCG Control register. if VADDR(1 downto 0) = "10" then - CGRAM_ADDR(11 downto 8) <= (VDATA(2) and MODE_MZ80A) & '1' & VDATA(1 downto 0); - CGRAM_WE_n <= not VDATA(4); + CGRAM_ADDR(11 downto 8) <= (VDATA(2) and MODE_VIDEO_MZ80A) & '1' & VDATA(1 downto 0); + CGRAM_WEn <= not VDATA(4); CGRAM_SEL <= VDATA(5); end if; end if; - -- Remember the previous level so we can detect the edge transition. As the clock of this process is not necessarily running at the clock of the CPU - -- this step is important to guarantee transaction integrity. - CS_LAST_LEVEL <= CS_PCG_n & CS_IO_FXX_n & CS_IO_EXX_n & CS_IO_1XX_n & CS_IO_0XX_n & CS_80B_PIO_n & CS_80B_PIT_n & CS_80B_PPI_n & CS_FB_PAGE_n & CS_GRAM_OPT_n & CS_FB_BLUE_n & CS_FB_GREEN_n & CS_FB_RED_n & CS_FB_CTL_n & CS_FB_VM_n & CS_SCROLL_n & CS_INVERT_n; + -- CPLD Configuration register. + -- + -- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used + -- by host software such as RFS. + -- + -- [2:0] - Mode/emulated machine. + -- 000 = MZ-80K + -- 001 = MZ-80C + -- 010 = MZ-1200 + -- 011 = MZ-80A + -- 100 = MZ-700 + -- 101 = MZ-800 + -- 110 = MZ-80B + -- 111 = MZ-2000 + -- [3] - Mainboard Video - 1 = Enable, 0 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions + -- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality. + -- [6:4] = Mainboard/CPU clock. + -- 000 = Sharp MZ80A 2MHz System Clock. + -- 001 = Sharp MZ80B 4MHz System Clock. + -- 010 = Sharp MZ700 3.54MHz System Clock. + -- 011 -111 = Reserved, defaults to 2MHz System Clock. + -- + if(CS_CPLD_CFGn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1') then + + -- Set the mode switch event flag if the mode changes. + if CPLD_CFG_DATA(2 downto 0) /= VDATA(2 downto 0) then + MODE_CPLD_SWITCH <= '1'; + end if; + + -- Store the new value into the register, used for read operations. + CPLD_CFG_DATA <= VDATA; + else + MODE_CPLD_SWITCH <= '0'; + end if; -- If video mode has changed then the reset timer is started, decrement it if it hasnt expired on each clock cycle. if VIDEOMODE_RESET_TIMER /= 0 and VID_CLK_IN_SYNC = '1' then - VIDEOMODE_RESET_TIMER <= VIDEOMODE_RESET_TIMER - 1; + VIDEOMODE_RESET_TIMER <= VIDEOMODE_RESET_TIMER - 1; end if; end if; -- Non-registered signal vectors for readback. -- Page register: [7] = CGROM Page setting, [6:1] = Current video mode, [1:0] = GRAM Page setting. - PAGE_MODE_REG <= CGROM_PAGE & std_logic_vector(to_unsigned(VIDEOMODE, 6)) & GRAM_PAGE_ENABLE; + PAGE_MODE_REG <= CGROM_PAGE & std_logic_vector(to_unsigned(VIDEOMODE, 5)) & GRAM_PAGE_ENABLE; -- MZ80B Graphics RAM is enabled whenever one of the two control lines goes active. - GRAM_MZ80B_ENABLE <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR; + GRAM_MZ80B_ENABLE <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR; end process; -- CPU / RAM signals and selects. -- - Z80_MA <= "00" & VADDR(9 downto 0) when MODE_MZ80K = '1' or MODE_MZ80C = '1' - else - VADDR(11 downto 0); - CS_DXXX_n <= '0' when VMEM_CSn = '0' and VADDR(13 downto 12) = "01" - else '1'; - CS_DVRAM_n <= '0' when VMEM_CSn = '0' and VADDR(13 downto 11) = "010" - else '1'; - CS_DARAM_n <= '0' when VMEM_CSn = '0' and VADDR(13 downto 11) = "011" - else '1'; - CS_EXXX_n <= '0' when VMEM_CSn = '0' and VADDR(13 downto 11) = "100" and GRAM_PAGE_ENABLE = '0' and (MODE_MZ80B = '0' or (MODE_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled. - else '1'; - CS_GRAM_n <= '0' when VMEM_CSn = '0' and VADDR(13) = '1' and MODE_MZ80B = '1' and GRAM_MZ80B_ENABLE = '1' -- Graphics Option Memory enabled, will be located from E000:FFFF (8K) - else '1'; - CS_IO_0XX_n <= '0' when VIORQn = '0' and VADDR(7 downto 4) = "0000" - else '1'; - CS_IO_1XX_n <= '0' when VIORQn = '0' and VADDR(7 downto 4) = "0001" - else '1'; - CS_IO_EXX_n <= '0' when VIORQn = '0' and VADDR(7 downto 4) = "1110" - else '1'; - CS_IO_FXX_n <= '0' when VIORQn = '0' and VADDR(7 downto 4) = "1111" - else '1'; + Z80_MA <= "00" & VADDR(9 downto 0) when MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' + else + VADDR(11 downto 0); + CS_DXXXn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 12) = "01" + else '1'; + -- Standard access to VRAM/ARAM. + CS_DVRAMn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "010" + else '1'; + CS_DARAMn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "011" + else '1'; + CS_EXXXn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "100" and GRAM_PAGE_ENABLE = "00" and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled. + else '1'; + -- MZ80B Graphics RAM enabled, range E000:FFFF is mapped to graphics RAMI + II and D000:DFFF to standard video. + CS_GRAMn <= '0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"D000" and unsigned(VADDR(15 downto 0)) <= X"FFFF" and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1' + else + -- MZ80B Graphics RAM enabled, range 6000:7FFF is mapped to graphics RAMI + II and 5000:5FFF to standard video. + '0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"5000" and unsigned(VADDR(15 downto 0)) <= X"7FFF" and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1' + else '1'; + -- Graphics RAM enabled, range C000:FFFF is mapped to graphics RAM. + CS_FBRAMn <= '0' when VZ80_IORQn = '1' and VADDR(15 downto 14) = "11" and GRAM_PAGE_ENABLE /= "00" + else '0'; + CS_IO_6XXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "0110" + else '1'; + CS_IO_DXXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "1101" + else '1'; + CS_IO_EXXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "1110" + else '1'; + CS_IO_FXXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "1111" + else '1'; + + -- CPLD mirrored logic. Registers on the CPLD which need to be known by the FPGA are duplicated within the FPGA. + CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and VADDR(3 downto 0) = "1110" -- IO 6E - CPLD configuration register. + else '1'; -- Program Character Generator RAM. E010 - Write cycle (Read cycle = reset memory swap). - CS_PCG_n <= '0' when CS_EXXX_n = '0' and VADDR(10 downto 4) = "0000001" - else '1'; -- E010 -> E01f + CS_PCGn <= '0' when CS_EXXXn = '0' and VADDR(10 downto 4) = "0000001" + else '1'; -- E010 -> E01f -- Invert display register. E014/E015 - CS_INVERT_n <= '0' when CS_EXXX_n = '0' and MODE_MZ80A = '1' and Z80_MA(11 downto 2) = "0000000101" - else '1'; + CS_INVERTn <= '0' when CS_EXXXn = '0' and Z80_MA(11 downto 2) = "0000000101" + else '1'; -- Scroll display register. E200 - E2FF - CS_SCROLL_n <= '0' when CS_EXXX_n = '0' and VADDR(10 downto 8)="010" and MODE_MZ80A='1' - else '1'; + CS_SCROLLn <= '0' when CS_EXXXn = '0' and VADDR(10 downto 8)="010" + else '1'; -- MZ80B/MZ2000 Graphics Options Register select. F4-F7 - CS_GRAM_OPT_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 2) = "01" - else '1'; + CS_GRAM_OPTn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 2) = "01" + else '1'; -- MZ80B/MZ2000 I/O Registers E0-EB, - CS_80B_PPI_n <= '0' when CS_IO_EXX_n = '0' and VADDR(3 downto 2) = "00" and MODE_MZ80B = '1' - else '1'; - CS_80B_PIT_n <= '0' when CS_IO_EXX_n = '0' and VADDR(3 downto 2) = "01" and MODE_MZ80B = '1' - else '1'; - CS_80B_PIO_n <= '0' when CS_IO_EXX_n = '0' and VADDR(3 downto 2) = "10" and MODE_MZ80B = '1' - else '1'; + CS_80B_PPIn <= '0' when CS_IO_EXXn = '0' and VADDR(3 downto 2) = "00" and MODE_VIDEO_MZ80B = '1' + else '1'; + CS_80B_PITn <= '0' when CS_IO_EXXn = '0' and VADDR(3 downto 2) = "01" and MODE_VIDEO_MZ80B = '1' + else '1'; + CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and VADDR(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1' + else '1'; - -- 0xF8 set the video mode. [2:0] = mode, 000 = MZ80A, 001 = MZ-700, 010 = MZ-80B, 011 = MZ-800, 111 = Pixel graphics. - CS_FB_VM_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 0) = "1000" - else '1'; + -- 0xF4 set the MZ80B video in/out mode. + -- Output data | V-RAM GRPH I | V-RAM GRPH II + -- to port $F4 | Input Output | Input Output + -- 00 0 X X X + -- 01 X X 0 X + -- 02 0 0 X X + -- 03 X 0 0 X + -- oc 0 X X O + -- OD X X 0 O + -- OE 0 0 X O + -- OF X 0 0 O + -- Note Input 0: V-RAM transfer enabled + -- X: V-RAM transfer disabled + -- Output 0: shown on CRT display + -- X: not shown on CRT display + CS_80B_VMODEn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "0100" + else '1'; + + -- 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output. + -- Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input. + CS_FB_PALETTEn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "0101" + else '1'; + -- 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor. + -- The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0. + CS_FB_PARAMSn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "0110" + else '1'; + -- 0xF7 set the graphics processor unit commands. + -- Bits [5:0] - 0 = Reset parameters. + -- 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter + CS_FB_GPUn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "0111" + else '1'; + -- 0xF8 set the video mode. + -- Bits [2:0] define the Video Module machine compatibility. 000 = MZ80K, 001 = MZ80C, 010 = MZ1200, 011 = MZ80A, 100 = MZ-700, 101 = MZ-800, 110 = MZ-80B, 111 = MZ2000, + -- Bit [3] defines the 40/80 column mode, 0 = 40 col, 1 = 80 col. + -- Bit [4] defines the colour mode, 0 = mono, 1 = colour - ignored on certain modes. + -- Bit [5] defines wether PCGRAM is enabled, 0 = disabled, 1 = enabled. + -- Bits [7:6] define the VGA mode. + CS_FB_VMn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "1000" + else '1'; -- 0xF9 set the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), - -- 5 = GRAM Output Enable, 4 = VRAM Output Enable, + -- 5 = GRAM Output Enable (=0), 4 = VRAM Output Enable (=0), -- 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), -- 1/0 = Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used). - CS_FB_CTL_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 0) = "1001" - else '1'; + CS_FB_CTLn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "1001" + else '1'; -- 0xFA set the Red bit mask (1 bit = 1 pixel, 8 pixels per byte). - CS_FB_RED_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 0) = "1010" - else '1'; + CS_FB_REDn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "1010" + else '1'; -- 0xFB set the Green bit mask (1 bit = 1 pixel, 8 pixels per byte). - CS_FB_GREEN_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 0) = "1011" - else '1'; + CS_FB_GREENn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "1011" + else '1'; -- 0xFC set the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte). - CS_FB_BLUE_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 0) = "1100" - else '1'; + CS_FB_BLUEn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "1100" + else '1'; -- 0xFD set the Video memory page in block C000:FFFF bit 0, set the CGROM upload access in bit 7. - CS_FB_PAGE_n <= '0' when CS_IO_FXX_n = '0' and VADDR(3 downto 0) = "1101" - else '1'; + CS_FB_PAGEn <= '0' when CS_IO_FXXn = '0' and VADDR(3 downto 0) = "1101" + else '1'; -- Data for CPU to read, dependent on what is being accessed. - VDATA <= VRAM_VIDEO_DATA when VRDn = '0' and CS_DXXX_n = '0' and CGROM_PAGE = '0' - else - GRAM_DO_R when VRDn = '0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(1 downto 0) = "00" -- For direct framebuffer access, C000:FFFF is assigned to the framebuffer during a read if the GRAM_PAGE_ENABLE register is not 0. - else - GRAM_DO_B when VRDn = '0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(1 downto 0) = "01" - else - GRAM_DO_G when VRDn = '0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(1 downto 0) = "10" - else - GRAM_DO_GI when VRDn = '0' and CS_GRAM_n = '0' and GRAM_OPT_WRITE = '0' -- For MZ80B GRAM I memory read - lower 8K of red framebuffer. - else - GRAM_DO_GII when VRDn = '0' and CS_GRAM_n = '0' and GRAM_OPT_WRITE = '1' -- For MZ80B GRAM II memory read - lower 8K of blue framebuffer. - else - VIDEO_MODE_REG when VRDn = '0' and CS_FB_VM_n = '0' - else - GRAM_MODE_REG when VRDn = '0' and CS_FB_CTL_n = '0' - else - GRAM_R_FILTER when VRDn = '0' and CS_FB_RED_n = '0' - else - GRAM_G_FILTER when VRDn = '0' and CS_FB_GREEN_n = '0' - else - GRAM_B_FILTER when VRDn = '0' and CS_FB_BLUE_n = '0' - else - PAGE_MODE_REG when VRDn = '0' and CS_FB_PAGE_n = '0' - else - CGROM_DO when VRDn = '0' and CS_DXXX_n = '0' and CGROM_PAGE = '1' - else - std_logic_vector(H_DSP_START(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0000" - else - std_logic_vector(H_DSP_START(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0001" - else - std_logic_vector(H_DSP_END(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0010" - else - std_logic_vector(H_DSP_END(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0011" - else - std_logic_vector(H_DSP_WND_START(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0100" - else - std_logic_vector(H_DSP_WND_START(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0101" - else - std_logic_vector(H_DSP_WND_END(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0110" - else - std_logic_vector(H_DSP_WND_END(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "0111" - else - std_logic_vector(V_DSP_START(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1000" - else - std_logic_vector(V_DSP_START(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1001" - else - std_logic_vector(V_DSP_END(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1010" - else - std_logic_vector(V_DSP_END(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1011" - else - std_logic_vector(V_DSP_WND_START(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1100" - else - std_logic_vector(V_DSP_WND_START(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1101" - else - std_logic_vector(V_DSP_WND_END(7 downto 0)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1110" - else - std_logic_vector(V_DSP_WND_END(15 downto 8)) when VRDn = '0' and CS_IO_0XX_n = '0' and VADDR(3 downto 0) = "1111" - else - std_logic_vector(H_LINE_END(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0000" - else - std_logic_vector(H_LINE_END(15 downto 8)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0001" - else - std_logic_vector(V_LINE_END(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0010" - else - std_logic_vector(V_LINE_END(15 downto 8)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0011" - else - std_logic_vector(MAX_COLUMN(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0100" - else - (others => '0') when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0101" - else - std_logic_vector(H_SYNC_START(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0110" - else - std_logic_vector(H_SYNC_START(15 downto 8)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "0111" - else - std_logic_vector(H_SYNC_END(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1000" - else - std_logic_vector(H_SYNC_END(15 downto 8)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1001" - else - std_logic_vector(V_SYNC_START(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1010" - else - std_logic_vector(V_SYNC_START(15 downto 8)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1011" - else - std_logic_vector(V_SYNC_END(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1100" - else - std_logic_vector(V_SYNC_END(15 downto 8)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1101" - else - std_logic_vector(H_PX(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1110" - else - std_logic_vector(V_PX(7 downto 0)) when VRDn = '0' and CS_IO_1XX_n = '0' and VADDR(3 downto 0) = "1111" - else - (others=>'Z'); + VDATA <= VRAM_VIDEO_DATA when VZ80_RDn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0' + else + GRAM_DO_R when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "01" and GRAM_MODE_REG(1 downto 0) = "00" -- For direct framebuffer access, C000:FFFF is assigned to the framebuffer during a read if the GRAM_PAGE_ENABLE register is not 0. + else + GRAM_DO_B when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "10" and GRAM_MODE_REG(1 downto 0) = "01" + else + GRAM_DO_G when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "11" and GRAM_MODE_REG(1 downto 0) = "10" + else + GRAM_DO_GI when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '0' -- For MZ80B GRAM I memory read - lower 8K of red framebuffer. + else + GRAM_DO_GII when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '1' -- For MZ80B GRAM II memory read - lower 8K of blue framebuffer. + else + VIDEO_MODE_REG when VZ80_RDn = '0' and CS_FB_VMn = '0' + else + GRAM_MODE_REG when VZ80_RDn = '0' and CS_FB_CTLn = '0' + else + GRAM_R_FILTER when VZ80_RDn = '0' and CS_FB_REDn = '0' + else + GRAM_G_FILTER when VZ80_RDn = '0' and CS_FB_GREENn = '0' + else + GRAM_B_FILTER when VZ80_RDn = '0' and CS_FB_BLUEn = '0' + else + PAGE_MODE_REG when VZ80_RDn = '0' and CS_FB_PAGEn = '0' + else + CGROM_DO when VZ80_RDn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' + else + GPU_STATUS when VZ80_RDn = '0' and CS_FB_GPUn = '0' + else + GPU_PARAMS(7 downto 0) when VZ80_RDn = '0' and CS_FB_PARAMSn = '0' + else + std_logic_vector(H_DSP_START(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0000" + else + std_logic_vector(H_DSP_START(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0000" + else + std_logic_vector(H_DSP_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0001" + else + std_logic_vector(H_DSP_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0001" + else + std_logic_vector(H_DSP_WND_START(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0010" + else + std_logic_vector(H_DSP_WND_START(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0010" + else + std_logic_vector(H_DSP_WND_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0011" + else + std_logic_vector(H_DSP_WND_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0011" + else + std_logic_vector(V_DSP_START(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0100" + else + std_logic_vector(V_DSP_START(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0100" + else + std_logic_vector(V_DSP_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0101" + else + std_logic_vector(V_DSP_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0101" + else + std_logic_vector(V_DSP_WND_START(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0110" + else + std_logic_vector(V_DSP_WND_START(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0110" + else + std_logic_vector(V_DSP_WND_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "0111" + else + std_logic_vector(V_DSP_WND_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "0111" + else + std_logic_vector(H_LINE_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1000" + else + std_logic_vector(H_LINE_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1000" + else + std_logic_vector(V_LINE_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1001" + else + std_logic_vector(V_LINE_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1001" + else + std_logic_vector(MAX_COLUMN(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1010" + else + (others => '0') when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1010" + else + std_logic_vector(H_SYNC_START(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1011" + else + std_logic_vector(H_SYNC_START(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1011" + else + std_logic_vector(H_SYNC_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1100" + else + std_logic_vector(H_SYNC_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1100" + else + std_logic_vector(V_SYNC_START(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1101" + else + std_logic_vector(V_SYNC_START(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1101" + else + std_logic_vector(V_SYNC_END(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1110" + else + std_logic_vector(V_SYNC_END(15 downto 8)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1110" + else + std_logic_vector(H_PX(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0001" and DSP_PARAM_SEL = "1111" + else + std_logic_vector(V_PX(7 downto 0)) when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0010" and DSP_PARAM_SEL = "1111" + else + PALETTE_REG when VZ80_RDn = '0' and CS_FB_PALETTEn = '0' + else + "000" & PALETTE_DO_R when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0101" + else + "000" & PALETTE_DO_G when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0110" + else + "000" & PALETTE_DO_B when VZ80_RDn = '0' and CS_IO_DXXn = '0' and VADDR(3 downto 0) = "0111" + else + (others=>'Z'); - VRAM_WEN <= '1' when VWRn = '0' and CS_DXXX_n = '0' and CGROM_PAGE = '0' and GRAM_PAGE_ENABLE = '0' - else '0'; - VRAM_VIDEO_DATA <= VRAM_DO; + -- VRAM mux between the CPU signals and the GPU. GPU takes priority. + -- + VRAM_ADDR <= VRAM_GPU_ADDR(11 downto 0) when VRAM_GPU_ENABLE = '1' + else + VADDR(11 downto 0); + VRAM_DI <= VRAM_GPU_DI when VRAM_GPU_ENABLE = '1' + else + VDATA; + VRAM_WEN <= '1' when VRAM_GPU_WEN = '1' + else + '1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0' and GRAM_PAGE_ENABLE = "00" + else '0'; + VRAM_VIDEO_DATA <= VRAM_DO; -- CGROM Data to CG RAM, either ROM -> RAM copy or Z80 provides map. -- - CGRAM_DI <= CGROM_BIT_DO when CGRAM_SEL = '1' -- Data from ROM - else - PCG_DATA when CGRAM_SEL = '0' -- Data from PCG - else (others=>'0'); - CGRAM_WEN <= not (CGRAM_WE_n or CS_PCG_n) and not VWRn; + CGRAM_DI <= CGROM_BIT_DO when CGRAM_SEL = '1' -- Data from ROM + else + PCG_DATA when CGRAM_SEL = '0' -- Data from PCG + else (others=>'0'); + CGRAM_WREN <= not (CGRAM_WEn or CS_PCGn) and not VZ80_WRn; -- -- Font select -- - CGROM_DATA <= CGROM_BIT_DO when PCGRAM='0' - else - PCG_DATA when CS_PCG_n='0' and VADDR(1 downto 0)="10" and VWRn='0' - else - CGRAM_DO when PCGRAM='1' - else (others => '1'); - CG_ADDR <= CGRAM_ADDR(11 downto 0) when CGRAM_WE_n = '0' - else XFER_CGROM_ADDR; - CGROM_WEN <= '1' when VWRn = '0' and CS_DXXX_n = '0' and CGROM_PAGE = '1' and GRAM_PAGE_ENABLE = '0' - else '0'; + CGROM_DATA <= CGROM_BIT_DO when PCGRAM='0' + else + PCG_DATA when CS_PCGn='0' and VADDR(1 downto 0)="10" and VZ80_WRn='0' + else + CGRAM_DO when PCGRAM='1' + else (others => '1'); + CG_ADDR <= CGRAM_ADDR(11 downto 0) when CGRAM_WEn = '0' + else XFER_CGROM_ADDR; + CGROM_WEN <= '1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' and GRAM_PAGE_ENABLE = "00" + else '0'; -- As the Graphics RAM is an odd size, 16384 x 3 colour planes, it has to be in 3 seperate 16K blocks to avoid wasting memory (or having it synthesized away), -- thus there are 3 sets of signals, 1 per colour. -- - GRAM_ADDR <= VADDR(13 downto 0); + GRAM_ADDR <= GRAM_GPU_ADDR(13 downto 0) when GRAM_GPU_ENABLE = '1' + else + VADDR(13 downto 0); -- direct writes when accessing individual pages. - GRAM_DI_R <= VDATA when GRAM_MODE_REG(3 downto 2) = "00" - else - VDATA and GRAM_R_FILTER when GRAM_MODE_REG(3 downto 2) = "11" - else - (others=>'0'); + GRAM_DI_R <= GRAM_GPU_DI_R when GRAM_GPU_ENABLE = '1' + else + VDATA when GRAM_MODE_REG(3 downto 2) = "00" + else + VDATA and GRAM_R_FILTER when GRAM_MODE_REG(3 downto 2) = "11" + else + (others=>'0'); -- direct writes when accessing individual pages. - GRAM_DI_B <= VDATA when GRAM_MODE_REG(3 downto 2) = "10" - else - VDATA and GRAM_B_FILTER when GRAM_MODE_REG(3 downto 2) = "11" - else - (others=>'0'); + GRAM_DI_B <= GRAM_GPU_DI_B when GRAM_GPU_ENABLE = '1' + else + VDATA when GRAM_MODE_REG(3 downto 2) = "10" + else + VDATA and GRAM_B_FILTER when GRAM_MODE_REG(3 downto 2) = "11" + else + (others=>'0'); -- direct writes when accessing individual pages. - GRAM_DI_G <= VDATA when GRAM_MODE_REG(3 downto 2) = "01" - else - VDATA and GRAM_G_FILTER when GRAM_MODE_REG(3 downto 2) = "11" - else - (others=>'0'); + GRAM_DI_G <= GRAM_GPU_DI_G when GRAM_GPU_ENABLE = '1' + else + VDATA when GRAM_MODE_REG(3 downto 2) = "01" + else + VDATA and GRAM_G_FILTER when GRAM_MODE_REG(3 downto 2) = "11" + else + (others=>'0'); -- For this implementation, a seperate Graphics RAM isnt implemented due to lack of memory, the Graphics RAM is shared -- by the MZ80B GRAM and the individual colour framebuffer. - GRAM_DO_R <= GRAM_DO_GI; - GRAM_DO_B <= GRAM_DO_GII; - GRAM_DO_G <= GRAM_DO_GIII; - GWEN_R <= '1' when VWRn = '0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(3 downto 2) = "00" - else - '1' when VWRn = '0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(3 downto 2) = "11" - else - '0'; - GWEN_B <= '1' when VWRn='0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(3 downto 2) = "10" - else - '1' when VWRn='0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(3 downto 2) = "11" - else - '0'; - GWEN_G <= '1' when VWRn='0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(3 downto 2) = "01" - else - '1' when VWRn='0' and VMEM_CSn = '0' and GRAM_PAGE_ENABLE = '1' and GRAM_MODE_REG(3 downto 2) = "11" - else - '0'; + GRAM_DO_R <= GRAM_DO_GI; + GRAM_DO_B <= GRAM_DO_GII; + GRAM_DO_G <= GRAM_DO_GIII; + GWEN_R <= '1' when GWEN_GPU_R = '1' + else + '1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "01" and GRAM_MODE_REG(3 downto 2) = "00" + else + '1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11" + else + '0'; + GWEN_B <= '1' when GWEN_GPU_B = '1' + else + '1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "11" and GRAM_MODE_REG(3 downto 2) = "10" + else + '1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11" + else + '0'; + GWEN_G <= '1' when GWEN_GPU_G = '1' + else + '1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "10" and GRAM_MODE_REG(3 downto 2) = "01" + else + '1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11" + else + '0'; -- MZ80B/MZ2000 Graphics Option RAM. -- - GRAM_DI_GI <= VDATA; - GRAM_DI_GII <= VDATA; - GRAM_DI_GIII <= VDATA; - GWEN_GI <= '1' when VWRn = '0' and CS_GRAM_n = '0' and GRAM_OPT_WRITE = '0' - else - '0'; - GWEN_GII <= '1' when VWRn='0' and CS_GRAM_n = '0' and GRAM_OPT_WRITE = '1' - else - '0'; + GRAM_DI_GI <= VDATA; + GRAM_DI_GII <= VDATA; + GRAM_DI_GIII <= VDATA; + GWEN_GI <= '1' when VZ80_WRn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '0' + else + '0'; + GWEN_GII <= '1' when VZ80_WRn='0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '1' + else + '0'; -- Write signals to the frame buffer memory are based on direct writes and writes to the MZ80B GRAM I/II which basically is the same memory, enabled differently. - GRAM_WEN_GI <= GWEN_GI or GWEN_R; - GRAM_WEN_GII <= GWEN_GII or GWEN_B; - GRAM_WEN_GIII <= GWEN_G; + GRAM_WEN_GI <= GWEN_GI or GWEN_R; + GRAM_WEN_GII <= GWEN_GII or GWEN_B; + GRAM_WEN_GIII <= GWEN_G; -- Work out the current video mode, which is used to look up the parameters for frame generation. -- @@ -1908,65 +2609,65 @@ begin -- 10 Mode 2 upscaled as 640x480 @ 72Hz timings for 40Char mode colour. -- 11 Mode 3 upscaled as 640x480 @ 72Hz timings for 80Char mode colour. -- - VIDEOMODE <= 0 when VIDEO_DEBUG = '1' - else - 0 when VGAMODE = "00" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO = '1' - else - 1 when VGAMODE = "00" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO80 = '1' - else - 2 when VGAMODE = "00" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR = '1' - else - 3 when VGAMODE = "00" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR80 = '1' - else - 4 when VGAMODE = "01" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO = '1' - else - 5 when VGAMODE = "01" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO80 = '1' - else - 6 when VGAMODE = "01" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR = '1' - else - 7 when VGAMODE = "01" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR80 = '1' - else - 8 when VGAMODE = "10" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO = '1' - else - 9 when VGAMODE = "10" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO80 = '1' - else - 10 when VGAMODE = "10" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR = '1' - else - 11 when VGAMODE = "10" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR80 = '1' - else - 12 when VGAMODE = "11" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO = '1' - else - 13 when VGAMODE = "11" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ80B = '1') and MODE_MONO80 = '1' - else - 14 when VGAMODE = "11" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR = '1' - else - 15 when VGAMODE = "11" and (MODE_MZ80A = '1' or MODE_MZ80K = '1' or MODE_MZ80C = '1' or MODE_MZ1200 = '1' or MODE_MZ700 = '1' or MODE_MZ800 = '1') and MODE_COLOUR80 = '1' - else - 0; + VIDEOMODE <= 0 when VIDEO_DEBUG = '1' + else + 0 when VGAMODE = "00" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO = '1' + else + 1 when VGAMODE = "00" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO80 = '1' + else + 2 when VGAMODE = "00" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR = '1' + else + 3 when VGAMODE = "00" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR80 = '1' + else + 4 when VGAMODE = "01" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO = '1' + else + 5 when VGAMODE = "01" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO80 = '1' + else + 6 when VGAMODE = "01" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR = '1' + else + 7 when VGAMODE = "01" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR80 = '1' + else + 8 when VGAMODE = "10" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO = '1' + else + 9 when VGAMODE = "10" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO80 = '1' + else + 10 when VGAMODE = "10" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR = '1' + else + 11 when VGAMODE = "10" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR80 = '1' + else + 12 when VGAMODE = "11" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO = '1' + else + 13 when VGAMODE = "11" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ80B = '1') and MODE_VIDEO_MONO80 = '1' + else + 14 when VGAMODE = "11" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR = '1' + else + 15 when VGAMODE = "11" and (MODE_VIDEO_MZ80A = '1' or MODE_VIDEO_MZ80K = '1' or MODE_VIDEO_MZ80C = '1' or MODE_VIDEO_MZ1200 = '1' or MODE_VIDEO_MZ700 = '1' or MODE_VIDEO_MZ800 = '1') and MODE_VIDEO_COLOUR80 = '1' + else + 0; -- Select the video clock based on the mode. -- -- - VID_CLK <= VIDCLK_8MHZ when (VIDEOMODE = 0 or VIDEOMODE = 2) - else - VIDCLK_16MHZ when (VIDEOMODE = 1 or VIDEOMODE = 3) - else - VIDCLK_25_175MHZ when (VIDEOMODE = 4 or VIDEOMODE = 5 or VIDEOMODE = 6 or VIDEOMODE = 7) - else - VIDCLK_65MHZ when (VIDEOMODE = 8 or VIDEOMODE = 9 or VIDEOMODE = 10 or VIDEOMODE = 11) - else - VIDCLK_40MHZ when (VIDEOMODE = 12 or VIDEOMODE = 13 or VIDEOMODE = 14 or VIDEOMODE = 15) - else - VIDCLK_8MHZ; + VID_CLK <= VIDCLK_8MHZ when (VIDEOMODE = 0 or VIDEOMODE = 2) + else + VIDCLK_16MHZ when (VIDEOMODE = 1 or VIDEOMODE = 3) + else + VIDCLK_25_175MHZ when (VIDEOMODE = 4 or VIDEOMODE = 5 or VIDEOMODE = 6 or VIDEOMODE = 7) + else + VIDCLK_65MHZ when (VIDEOMODE = 8 or VIDEOMODE = 9 or VIDEOMODE = 10 or VIDEOMODE = 11) + else + VIDCLK_40MHZ when (VIDEOMODE = 12 or VIDEOMODE = 13 or VIDEOMODE = 14 or VIDEOMODE = 15) + else + VIDCLK_8MHZ; -- Internal monitor clock, 40/80 character modes. - VID_CLK_I <= VIDCLK_8MHZ when (MODE_MONO = '1' or MODE_COLOUR = '1') - else - VIDCLK_16MHZ; + VID_CLK_I <= VIDCLK_8MHZ when (MODE_VIDEO_MONO = '1' or MODE_VIDEO_COLOUR = '1') + else + VIDCLK_16MHZ; -- Synchronise video reset by ensuring all the clocks are at the MARK state. - VID_CLK_IN_SYNC <= '1' when SYS_CLK = '0' and VID_CLK = '1' and VID_CLK_I = '1' - else '0'; + VID_CLK_IN_SYNC <= '1' when SYS_CLK = '0' and VID_CLK = '1' and VID_CLK_I = '1' + else '0'; -- Output the VGA signals on the main clock edge, helps a bit with jitter. @@ -1974,7 +2675,7 @@ begin -- process(SYS_CLK) -- begin -- if rising_edge(SYS_CLK) then --- if H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_MZ80B = '1') or MODE_MZ80B = '0') then +-- if H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') then -- VGA_R <= (others => SR_R_DATA(7)); -- VGA_G <= (others => SR_G_DATA(7)); -- VGA_B <= (others => SR_B_DATA(7)); @@ -1984,47 +2685,68 @@ begin -- VGA_B <= (others => '0'); -- end if; -- if H_POLARITY(0) = '0' then --- VGA_HS <= H_SYNC_ni; +-- VGA_HS <= H_SYNCni; -- else --- VGA_HS <= not H_SYNC_ni; +-- VGA_HS <= not H_SYNCni; -- end if; -- if V_POLARITY(0) = '0' then --- VGA_VS <= V_SYNC_ni; +-- VGA_VS <= V_SYNCni; -- else --- VGA_VS <= not V_SYNC_ni; +-- VGA_VS <= not V_SYNCni; -- end if; -- end if; -- end process; - VGA_R <= (others => SR_R_DATA(7)) when H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_MZ80B = '1') or MODE_MZ80B = '0') - else (others => '0'); - VGA_G <= (others => SR_G_DATA(7)) when H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_MZ80B = '1') or MODE_MZ80B = '0') - else (others => '0'); - VGA_B <= (others => SR_B_DATA(7)) when H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_MZ80B = '1') or MODE_MZ80B = '0') - else (others => '0'); - VGA_HS <= H_SYNC_ni when H_POLARITY(0) = '0' - else - not H_SYNC_ni; - VGA_VS <= V_SYNC_ni when V_POLARITY(0) = '0' - else - not V_SYNC_ni; + + -- Set the mainboard video state, 0 = enabled, 1 = disabled. + MODE_CPLD_MB_VIDEOn <= CPLD_CFG_DATA(3); + -- Set CPLD mode flag according to value given in config 2:0 + MODE_CPLD_MZ80K <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80K + else '0'; + MODE_CPLD_MZ80C <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80C + else '0'; + MODE_CPLD_MZ1200 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ1200 + else '0'; + MODE_CPLD_MZ80A <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80A + else '0'; + MODE_CPLD_MZ700 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ700 + else '0'; + MODE_CPLD_MZ800 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ800 + else '0'; + MODE_CPLD_MZ80B <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ80B + else '0'; + MODE_CPLD_MZ2000 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ2000 + else '0'; + + VGA_R <= FB_PALETTE_R(3 downto 0) when H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') + else (others => '0'); + VGA_G <= FB_PALETTE_G(3 downto 0) when H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') + else (others => '0'); + VGA_B <= FB_PALETTE_B(3 downto 0) when H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') + else (others => '0'); + VGA_HS <= H_SYNCni when H_POLARITY(0) = '0' + else + not H_SYNCni; + VGA_VS <= V_SYNCni when V_POLARITY(0) = '0' + else + not V_SYNCni; -- Mainboard Video output circuitry. This is the emulation of the MB14298/MB14299 gate arrays. We inject the video (serialised data) and the sync/blanking signals into the MB14298 socket -- and these are combined on the mainboard to generate the internal monitor signals. -- - VSRVIDEO_OUT <= (SR_R_DATA(7) xor SR_B_DATA(7)) or (SR_R_DATA(7) xor SR_G_DATA(7)) or (SR_B_DATA(7) xor SR_G_DATA(7)) when DISABLE_INT_DISPLAY = '0' -- Video out from 74LS165 on mainboard, pre-GATE. - else '0'; - VHBLNK_OUTn <= not H_BLANKi when DISABLE_INT_DISPLAY = '0' -- Horizontal blanking. - else H_I_BLANKi; - VHSY_OUT <= not H_SYNC_ni when DISABLE_INT_DISPLAY = '0' -- Horizontal Sync. - else H_I_SYNC_ni; - VSYNCH_OUT <= not V_SYNC_ni when DISABLE_INT_DISPLAY = '0' -- Veritcal Sync. - else V_I_SYNC_ni; - VVBLNK_OUTn <= not V_BLANKi when DISABLE_INT_DISPLAY = '0' -- Vertical blanking. - else V_I_BLANKi; + VSRVIDEO_OUT <= (SR_R_DATA(7) xor SR_B_DATA(7)) or (SR_R_DATA(7) xor SR_G_DATA(7)) or (SR_B_DATA(7) xor SR_G_DATA(7)) when DISABLE_INT_DISPLAY = '0' -- Video out from 74LS165 on mainboard, pre-GATE. + else '0'; + VHBLNK_OUTn <= not H_BLANKi when DISABLE_INT_DISPLAY = '0' -- Horizontal blanking. + else H_I_BLANKi; + VHSY_OUT <= not H_SYNCni when DISABLE_INT_DISPLAY = '0' -- Horizontal Sync. + else H_I_SYNCni; + VSYNCH_OUT <= not V_SYNCni when DISABLE_INT_DISPLAY = '0' -- Veritcal Sync. + else V_I_SYNCni; + VVBLNK_OUTn <= not V_BLANKi when DISABLE_INT_DISPLAY = '0' -- Vertical blanking. + else V_I_BLANKi; -- Composite video signal output. Composite video is formed in hardware by the combination of VGA R/G/B signals. - CSYNCn <= not (H_SYNC_ni or V_SYNC_ni); - CSYNC <= H_SYNC_ni or V_SYNC_ni; + CSYNCn <= not (H_SYNCni or V_SYNCni); + CSYNC <= H_SYNCni or V_SYNCni; end architecture rtl; diff --git a/FPGA/VideoController_Toplevel.vhd b/FPGA/VideoController_Toplevel.vhd index 6dd1659..7b4fdf3 100644 --- a/FPGA/VideoController_Toplevel.vhd +++ b/FPGA/VideoController_Toplevel.vhd @@ -42,17 +42,15 @@ entity VideoControllerFPGA is -- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage. -- Addres Bus - VADDR : in std_logic_vector(13 downto 0); -- Z80 Address bus, multiplexed with video address. + VADDR : in std_logic_vector(15 downto 0); -- Z80 Address bus, multiplexed with video address. -- Data Bus VDATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus from mainboard Colour Card CD connector.. -- Control signals. - VMEM_CSn : in std_logic; -- Extended memory select to FPGA. - VIORQn : in std_logic; -- IORQn to FPGA. - VRDn : in std_logic; -- RDn to FPGA. - VWRn : in std_logic; -- WRn to FPGA. - VRESETn : in std_logic; -- Reset to FPGA. + VZ80_IORQn : in std_logic; -- IORQn to FPGA. + VZ80_RDn : in std_logic; -- RDn to FPGA. + VZ80_WRn : in std_logic; -- WRn to FPGA. -- VGA signals. VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output. @@ -68,8 +66,10 @@ entity VideoControllerFPGA is VHBLNK_OUTn : out std_logic; -- Horizontal blanking. VHSY_OUT : out std_logic; -- Horizontal Sync. VSYNCH_OUT : out std_logic; -- Veritcal Sync. - VVBLNK_OUTn : out std_logic -- Vertical blanking. + VVBLNK_OUTn : out std_logic; -- Vertical blanking. + -- Reset. + VRESETn : in std_logic -- Reset to FPGA. -- Reserved. --TBA : in std_logic_vector(4 downto 0) -- Reserved signal paths to the CPLD. ); @@ -147,11 +147,9 @@ begin VDATA => VDATA, -- Z80 Data bus from mainboard Colour Card CD connector.. -- Control signals. - VMEM_CSn => VMEM_CSn, -- Extended memory select to FPGA. - VIORQn => VIORQn, -- IORQn to FPGA. - VRDn => VRDn, -- RDn to FPGA. - VWRn => VWRn, -- WRn to FPGA. - VRESETn => RESETn, -- Reset to FPGA. + VZ80_IORQn => VZ80_IORQn, -- IORQn to FPGA. + VZ80_RDn => VZ80_RDn, -- RDn to FPGA. + VZ80_WRn => VZ80_WRn, -- WRn to FPGA. -- VGA signals. VGA_R => VGA_R, -- 16 level Red output. @@ -167,7 +165,10 @@ begin VHBLNK_OUTn => VHBLNK_OUTn, -- Horizontal blanking. VHSY_OUT => VHSY_OUT, -- Horizontal Sync. VSYNCH_OUT => VSYNCH_OUT, -- Veritcal Sync. - VVBLNK_OUTn => VVBLNK_OUTn -- Vertical blanking. + VVBLNK_OUTn => VVBLNK_OUTn, -- Vertical blanking. + + -- Reset. + VRESETn => RESETn -- Reset to FPGA. -- Reserved. --TBA => TBA -- Reserved signals. diff --git a/FPGA/VideoController_pkg.vhd b/FPGA/VideoController_pkg.vhd index d0bfe11..ad50dfa 100644 --- a/FPGA/VideoController_pkg.vhd +++ b/FPGA/VideoController_pkg.vhd @@ -35,6 +35,72 @@ use ieee.numeric_std.all; use ieee.math_real.all; package VideoController_pkg is + + ------------------------------------------------------------ + -- Constants + ------------------------------------------------------------ + + -- Potential logic state constants. + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + -- Target hardware modes. + constant MODE_MZ80K : integer := 0; + constant MODE_MZ80C : integer := 1; + constant MODE_MZ1200 : integer := 2; + constant MODE_MZ80A : integer := 3; + constant MODE_MZ700 : integer := 4; + constant MODE_MZ800 : integer := 5; + constant MODE_MZ80B : integer := 6; + constant MODE_MZ2000 : integer := 7; + + -- Memory management modes. + constant TZMM_ORIG : integer := 00; -- Original Sharp mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063). + constant TZMM_BOOT : integer := 01; -- Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted. + constant TZMM_TZFS : integer := 02; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected. + constant TZMM_TZFS2 : integer := 03; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1. + constant TZMM_TZFS3 : integer := 04; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2. + constant TZMM_TZFS4 : integer := 05; -- TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3. + constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected. + -- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard. + constant TZMM_COMPAT : integer := 08; -- Compatiblilty monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF. + constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard. + constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6. + constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible. + constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. + constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. + constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. + constant TZMM_TZPU3 : integer := 27; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. + constant TZMM_TZPU4 : integer := 28; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. + constant TZMM_TZPU5 : integer := 29; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. + constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. + constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. + + + ------------------------------------------------------------ + -- Configurable parameters. + ------------------------------------------------------------ + -- Target hardware. + constant CPLD_HOST_HW : integer := MODE_MZ80A; + + -- Target video hardware. + constant CPLD_HAS_FPGA_VIDEO : std_logic := '1'; + + -- Version of hdl. + constant CPLD_VERSION : integer := 1; + + -- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator. + -- + constant USE_K64F_CTL_CLOCK : integer := 1; + ------------------------------------------------------------ -- Function prototypes ------------------------------------------------------------ @@ -55,19 +121,8 @@ package VideoController_pkg is -- function to_std_logic(i : in integer) return std_logic; - ------------------------------------------------------------ - -- Constants - ------------------------------------------------------------ - - -- Potential logic state constants. - constant YES : std_logic := '1'; - constant NO : std_logic := '0'; - constant HI : std_logic := '1'; - constant LO : std_logic := '0'; - constant ONE : std_logic := '1'; - constant ZERO : std_logic := '0'; - constant HIZ : std_logic := 'Z'; - + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural; ------------------------------------------------------------ -- Records @@ -142,4 +197,13 @@ package body VideoController_pkg is return '1'; end function; + -- Function to return the value of a bit as an integer for array indexing etc. + function bit_to_integer( s : std_logic ) return natural is + begin + if s = '1' then + return 1; + else + return 0; + end if; + end function; end package body; diff --git a/FPGA/build/VideoController.qsf b/FPGA/build/VideoController.qsf index 9d4dd20..02ce80f 100644 --- a/FPGA/build/VideoController.qsf +++ b/FPGA/build/VideoController.qsf @@ -86,6 +86,8 @@ set_location_assignment PIN_129 -to CLOCK_50 # Video Interface Address Bus # =========================== +set_location_assignment PIN_80 -to VADDR[15] +set_location_assignment PIN_83 -to VADDR[14] set_location_assignment PIN_120 -to VADDR[13] set_location_assignment PIN_121 -to VADDR[12] set_location_assignment PIN_125 -to VADDR[11] @@ -100,6 +102,8 @@ set_location_assignment PIN_143 -to VADDR[3] set_location_assignment PIN_144 -to VADDR[2] set_location_assignment PIN_7 -to VADDR[1] set_location_assignment PIN_4 -to VADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[14] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[13] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[12] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VADDR[11] @@ -146,20 +150,20 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[0 # ====================== #set_location_assignment PIN_113 -to VCSn #set_location_assignment PIN_112 -to VGTn -set_location_assignment PIN_115 -to VIORQn -set_location_assignment PIN_119 -to VMEM_CSn -set_location_assignment PIN_114 -to VRDn +set_location_assignment PIN_115 -to VZ80_IORQn +#set_location_assignment PIN_119 -to VMEM_CSn +set_location_assignment PIN_114 -to VZ80_RDn set_location_assignment PIN_110 -to VRESETn #set_location_assignment PIN_28 -to VVRAM_CS_INn -set_location_assignment PIN_111 -to VWRn +set_location_assignment PIN_111 -to VZ80_WRn #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCSn #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGTn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIORQn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMEM_CSn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRDn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMEM_CSn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRESETn #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVRAM_CS_INn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWRn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn # VGA/RGB signals. # ================ @@ -230,23 +234,27 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VHSY_OU set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNCH_OUT set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VVBLNK_OUTn + +# Mainboard video signals on the CN1 connector passed to the FPGA. +# ================================================================ +set_location_assignment PIN_71 -to VMB_HBLNKn +set_location_assignment PIN_72 -to VMB_LOAD +set_location_assignment PIN_76 -to VMB_SYNCH +set_location_assignment PIN_77 -to VMB_V_HBLNKn +set_location_assignment PIN_79 -to VMB_VIDEO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_HBLNKn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_LOAD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_SYNCH +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_V_HBLNKn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_VIDEO + # Reserved. # ========= -#set_location_assignment PIN_71 -to TBA[9] -#set_location_assignment PIN_72 -to TBA[8] -#set_location_assignment PIN_76 -to TBA[7] -#set_location_assignment PIN_77 -to TBA[6] -#set_location_assignment PIN_79 -to TBA[5] #set_location_assignment PIN_80 -to TBA[4] #set_location_assignment PIN_83 -to TBA[3] #set_location_assignment PIN_85 -to TBA[2] #set_location_assignment PIN_86 -to TBA[1] #set_location_assignment PIN_87 -to TBA[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[9] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[8] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[7] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[6] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[5] #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[4] #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[3] #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[2] @@ -271,4 +279,7 @@ set_global_assignment -name SDC_FILE VideoController_constraints.sdc + + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA/build/VideoController_constraints.sdc b/FPGA/build/VideoController_constraints.sdc index 8e33638..080c726 100644 --- a/FPGA/build/VideoController_constraints.sdc +++ b/FPGA/build/VideoController_constraints.sdc @@ -67,10 +67,12 @@ derive_clock_uncertainty set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}] -set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWRn}] -set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRDn}] -set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIORQn}] -set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}] +#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}] set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}] diff --git a/software/mif/COLOURBOARD_CG.mif b/software/mif/COLOURBOARD_CG.mif new file mode 100644 index 0000000..80be97c --- /dev/null +++ b/software/mif/COLOURBOARD_CG.mif @@ -0,0 +1,1382 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 32768; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00; +0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00; +0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00; +0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00; +0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00; +0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00; +00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00; +00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00; +00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 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00 00 FF 00 02 02 02 02 02 02 02 02 00 00 00 00 00 FF FF FF; +7BF8: 07 07 07 07 07 07 07 07 18 18 18 18 18 18 18 00 00 00 38 04 3C 44 3A 00; +7C10: 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00 02 02 3A 46 42 46 3A 00; +7C28: 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00 00 00 3A 46 46 3A 02 3C; +7C40: 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00 04 00 0C 04 04 04 44 38; +7C58: 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00 00 00 76 49 49 49 49 00; +7C70: 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00 00 00 5C 62 62 5C 40 40; +7C88: 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00 00 00 3E 40 3C 02 7C 00; +7CA0: 10 10 7C 10 10 12 0C 00 00 00 42 42 42 46 3A 00 00 00 42 42 42 24 18 00; +7CB8: 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00 00 00 42 42 46 3A 02 3C; +7CD0: 00 00 7E 04 18 20 7E 00 24 00 38 04 3C 44 3A 00 00 00 00 01 02 04 08 10; +7CE8: 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08; +7D00: 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00 44 44 44 44 44 44 44 44; +7D18: 44 FF 44 44 44 FF 44 44 20 10 08 00 00 00 00 00 00 00 00 32 4C 00 00 00; +7D30: AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0 03 0C 30 C0 00 00 00 00; +7D48: C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00 00 22 00 22 22 26 1A 00; +7D60: 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00 42 18 24 42 7E 42 42 00; +7D78: 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80; +7D90: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01 80 80 40 40 40 20 20 10; +7DA8: 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08; +7DC0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03 00 00 00 00 01 06 38 C0; +7DD8: 08 10 20 40 80 00 00 00 08 10 10 20 10 10 08 00 08 08 08 08 FF 08 08 08; +7DF0: 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7E 00; +7E00: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +7E18: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF; +7E30: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +7E48: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +7E60: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C; +7E78: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05; +7E90: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55; +7EA8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55; +7EC0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01; +7ED8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08; +7EF0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00 00 00 00 00 00 02 FF 02; +7F08: 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02 00 00 20 50 88 05 02 00; +7F20: 00 0E 11 22 C4 04 02 01 88 44 22 11 88 44 22 11 00 70 88 44 23 20 40 80; +7F38: 00 C4 A4 94 8F 94 A4 C4 00 43 45 49 F1 49 45 43 88 90 A0 C0 C0 A8 98 B8; +7F50: A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80 00 00 24 24 E7 24 24 00; +7F68: 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04 55 AA 55 AA 55 AA 55 AA; +7F80: 22 44 88 11 22 44 88 11 00 70 70 70 00 00 00 00 00 07 07 07 00 00 00 00; +7F98: 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70; +7FB0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70 00 00 00 00 00 07 07 07; +7FC8: 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07; +7FE0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77 00 07 07 07 00 77 77 77; +7FF8: 00 77 77 77 00 77 77 77; +END; diff --git a/software/mif/MZ700_cgrom.mif b/software/mif/MZ700_cgrom.mif new file mode 100644 index 0000000..135235f --- /dev/null +++ b/software/mif/MZ700_cgrom.mif @@ -0,0 +1,182 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 4096; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00; +0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00; +0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00; +0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00; +0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00; +0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00; +00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00; +00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00; +00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00; +00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00; +0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00; +0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00; +0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00; 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00 00 08 00 00 00 08 1C 2A 08 08 08 00; +0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00; +02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80; +02B8: 70 18 0C 06 0C 18 70 00 00 08 08 08 2A 1C 08 00 00 40 20 10 08 04 02 00; +02D0: 00 00 04 02 7F 02 04 00 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08; +02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08; +0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00; +0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00; +0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00; +0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00; +0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00; +0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80; +0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00; 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04 18 20 7E 00 24 00 38 04 3C 44 3A 00; +04E0: 00 00 00 01 02 04 08 10 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00; +04F8: 00 00 00 80 40 20 10 08 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00; +0510: 44 44 44 44 44 44 44 44 44 FF 44 44 44 FF 44 44 20 10 08 00 00 00 00 00; +0528: 00 00 00 32 4C 00 00 00 AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0; +0540: 03 0C 30 C0 00 00 00 00 C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00; +0558: 00 22 00 22 22 26 1A 00 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00; +0570: 42 18 24 42 7E 42 42 00 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80; +0588: 01 06 18 20 20 40 40 80 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01; +05A0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80; +05B8: 01 01 02 02 02 04 04 08 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03; +05D0: 00 00 00 00 01 06 38 C0 08 10 20 40 80 00 00 00 08 10 10 20 10 10 08 00; +05E8: 08 08 08 08 FF 08 08 08 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7E 00; +0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF; +0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C; +0678: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05; +0690: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55; +06A8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55; +06C0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01; +06D8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08; +06F0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00; +0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02; +0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 11 22 44 88 11 22 44 88; +0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23; +0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80; +0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04; +0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00; +0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70; +07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70; +07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07; +07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77; +07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77 00 00 00 00 00 00 00 00; +0808: 7C C6 BA BA 82 BA AA EE FC 86 BA 84 BA BA 86 FC 7E C2 BE A0 A0 BE C2 7E; +0820: F8 8C B6 AA AA B6 8C F8 FE 82 BE 88 88 BE 82 FE FE 82 BE 88 B8 A0 A0 E0; +0838: 7E 82 BE A0 AE BA 82 7E EE AA BA 82 BA AA AA EE FE 82 EE 28 28 EE 82 FE; +0850: 1F 11 1B 0A EA BA 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FF A0 AF A0 FF; +0BE0: 00 00 00 FF 41 41 55 FF A0 9F 80 FF 30 30 30 78 11 E1 01 FF 0C 0C 0C 1E; +0BF8: 80 AA 80 95 80 8F 80 FF 01 A9 01 51 01 E1 01 FF 3C 42 AB D5 10 10 14 08; +0C10: 00 00 18 24 24 18 00 00 00 18 24 42 42 24 18 00 3C 42 81 81 81 81 42 3C; +0C28: 00 00 00 18 18 00 00 00 00 00 3C 3C 3C 3C 00 00 00 7E 7E 7E 7E 7E 7E 00; +0C40: 3C 42 9D A1 A1 9D 42 3C FF FF FF E7 E7 FF FF FF FF FF C3 C3 C3 C3 FF FF; +0C58: FF 81 81 81 81 81 81 FF 20 30 20 20 FF 7E 3C 00 3C 42 81 FF FF 81 42 3C; +0C70: 3C 5A 99 99 99 99 5A 3C 3C 5A 99 FF FF 99 5A 3C 00 28 FE AA FE 54 38 10; +0C88: 0F 30 40 4E 8A 8E 80 81 F0 0C 02 72 51 71 01 81 0F 30 40 40 8E 80 80 81; +0CA0: F0 0C 02 02 71 01 01 81 81 80 88 84 43 40 30 0F 81 01 11 21 C2 02 0C F0; +0CB8: 81 80 80 87 40 40 30 0F 81 01 01 E1 02 02 0C F0 81 80 83 84 43 40 30 0F; +0CD0: 81 01 C1 21 C2 02 0C F0 81 80 87 88 48 40 30 0F 81 01 E1 11 12 02 0C F0; +0CE8: 08 10 54 FE FE FE FE 7C 00 06 08 10 30 78 78 30 00 52 34 06 60 2C 4A 00; +0D00: 91 52 00 03 C0 00 4A 89 80 C0 E0 F0 FF FF FF FF 00 00 01 02 FF C3 C3 FF; +0D18: 00 00 80 40 FF C3 C3 FF 00 C0 20 10 FC FE FF FC 01 03 07 0F FF FF FF FF; +0D30: 02 14 28 08 14 14 08 00 00 FE 42 20 10 20 42 FE 00 03 04 08 3F 7F FF 3F; +0D48: 00 20 10 10 10 28 48 86 00 3C 42 42 42 24 A5 E7 00 44 82 82 92 6C 00 00; +0D60: 00 00 6C 92 92 6C 00 00 00 02 6C 90 90 6E 00 00 00 1E 10 50 50 B0 10 00; +0D78: 00 00 10 00 7C 00 10 00 00 F1 5B 55 55 51 51 00 FF 89 91 C5 A3 89 91 FF; +0D90: FF C3 A5 99 99 A5 C3 FF 00 92 54 38 EE 38 54 92 FF 99 99 FF FF 99 99 FF; +0DA8: 92 54 38 10 10 10 10 10 38 10 38 10 38 10 38 10 00 00 00 AA FF AA 00 00; +0DC0: 00 10 10 7C 10 10 00 7C 7E 42 7E 42 7E 42 7E 42 00 FF 55 55 55 55 FF 00; +0DD8: 00 00 00 C0 B0 8C 83 FF 00 00 00 03 0D 31 C1 FF 00 00 00 00 3C 7E FF FF; +0DF0: FF FF 7E 3C 00 00 00 00 C0 E0 F0 F0 F0 F0 E0 C0; +0E00: 03 07 0F 0F 0F 0F 07 03 03 0C 3F 3F FF 7F 37 1F C0 30 B8 DC EE F6 FB FB; +0E18: 0E 0E 0A 04 01 01 03 0F 7A 74 F4 F4 F4 FA FD FD 04 4E E4 46 6F 7F 60 3F; +0E30: 20 72 27 62 F6 FE 06 FC 3B 31 1B 1F 10 1F 0F 07 DC 8C D8 F8 08 F8 F0 E0; +0E48: 01 03 07 06 0E 3E 70 30 80 C0 E0 60 70 7C 0E 0C 1E 0E 06 07 03 37 7F 8B; +0E60: 78 70 60 E0 C0 EC FE D1 01 33 7B 59 8C DF 7F 3F 80 CC DE 9A 31 FB FE FC; +0E78: 3F 1F 1F 0F 0F 7F 00 FF FC F8 F8 F0 F0 FE 00 FF 00 01 02 04 02 01 1F 1F; +0E90: 00 80 40 20 40 80 F8 F8 02 02 02 02 1F 20 7F 00 40 40 40 40 F8 04 FE 00; +0EA8: 73 73 73 7F 3F 1F 0F 0F CE CE CE FE FC F8 F0 F0 0F 0F 0F 18 7F 40 7F FF; +0EC0: F0 F0 F0 18 FE 02 FE FF F8 44 42 21 21 42 44 F8 FF 05 07 00 00 07 05 FF; +0ED8: FC 86 82 81 81 82 86 FC 00 00 80 40 7F 80 00 00 00 00 00 00 FF 01 01 01; +0EF0: 01 01 01 01 FF 00 00 00 FF 80 80 80 80 00 00 00 00 00 00 00 80 80 80 FF; +0F08: 00 08 0C 0A F9 0A 0C 08 00 08 0C 3A E9 3A 0C 08 1F 28 48 FE 88 88 8F 00; +0F20: 40 C0 40 E6 09 02 04 0F 40 C0 40 E2 06 0A 1F 02 40 C0 40 EF 01 07 01 0F; +0F38: 40 A0 20 4F E1 07 01 0F C0 60 18 06 18 60 80 FE 01 06 18 60 18 06 01 7F; +0F50: 00 01 06 1D 2A 2A 2A 1F 1B 8F 65 11 C9 A9 B1 F3 4C F7 F0 18 07 02 3E FE; +0F68: 7F 9F 31 41 81 81 F9 FD 88 02 40 00 88 41 00 91 40 01 88 00 40 04 80 11; +0F80: 00 30 58 FD FF 79 30 00 00 0C 1A BF FF 9E 0C 00 00 30 58 FD 3F F9 30 00; +0F98: 00 0C 1A BF FC 9F 0C 00 10 28 68 BC FC 78 10 38 BA EE AA 38 38 BA FE BA; +0FB0: BA FE BA 38 38 AA EE BA 00 E7 42 FF 9F FF 42 E7 00 E7 42 FF F9 FF 42 E7; +0FC8: 00 00 FC 1C 7F 63 3E 00 00 00 3F 38 FE C6 7C 00 FF 81 A5 81 81 A5 81 FF; +0FE0: E7 81 81 00 00 81 81 E7 00 04 08 FE 10 FE 20 40 18 24 24 20 10 10 10 10; +0FF8: 08 08 08 08 04 24 24 18; +END; diff --git a/software/mif/MZ700_cgrom_jp.mif b/software/mif/MZ700_cgrom_jp.mif new file mode 100644 index 0000000..6ca2392 --- /dev/null +++ b/software/mif/MZ700_cgrom_jp.mif @@ -0,0 +1,182 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 4096; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00; +0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00; +0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00; +0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00; +0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00; +0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00; +00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00; +00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00; +00D8: 08 08 08 08 FF 08 08 08 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00; +00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00; +0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00; +0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00; +0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00; +0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10; +0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10; +0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF; +0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10; +01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00; +01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F; +01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF; +01F8: 03 03 03 03 03 03 03 03 00 00 08 04 FE 04 08 00 08 1C 3E 7F 7F 1C 3E 00; +0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00; +0228: 00 00 10 20 7F 20 10 00 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00; +0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF; +0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF; +0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00; +0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00; +02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80; +02B8: 70 18 0C 06 0C 18 70 00 A0 50 A0 50 A0 50 A0 50 00 40 20 10 08 04 02 00; +02D0: AA 55 AA 55 AA 55 AA 55 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08; +02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08; +0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00; +0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 3C 08 00 00 62 64 08 10 26 46 00; +0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00; +0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00; +0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00; +0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80; +0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00; +03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01; +03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00; +03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02; +03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 00 08 08 08 2A 1C 08 00; +0408: 04 38 08 3E 08 08 10 00 00 3E 02 02 02 02 3E 00 00 22 22 12 02 04 18 00; +0420: 00 30 02 32 02 04 38 00 02 04 08 18 28 08 08 00 00 08 04 22 22 22 22 00; +0438: 08 3E 08 3E 08 08 08 00 00 1E 12 22 02 04 18 00 00 1C 00 00 00 00 3E 00; +0450: 00 3E 02 02 14 08 04 00 04 04 04 04 04 08 10 00 24 24 24 24 04 08 10 00; +0468: 00 3E 10 3E 10 10 0E 00 00 1C 00 1C 00 3C 02 00 1C 00 3E 02 02 04 08 00; +0480: 10 3E 12 14 10 10 0E 00 00 1E 12 2A 06 04 18 00 00 3E 02 04 08 14 22 00; +0498: 10 10 10 18 14 10 10 00 10 3E 12 12 12 12 24 00 08 08 3E 08 08 10 20 00; +04B0: 20 20 3E 20 20 20 1E 00 1C 00 3E 08 08 08 10 00 14 3E 14 14 04 08 10 00; +04C8: 00 30 00 02 02 04 38 00 00 2A 2A 2A 02 04 08 00 00 3E 22 22 22 22 3E 00; +04E0: 10 1E 24 04 04 04 08 00 1E 10 10 10 00 00 00 00 00 00 3E 02 0C 08 10 00; +04F8: 00 00 10 3E 12 14 10 00 00 3E 22 22 02 04 08 00 00 3E 02 14 08 14 20 00; +0510: 00 3E 02 02 02 04 18 00 3E 02 0A 0C 08 08 10 00 08 3E 22 22 02 04 08 00; +0528: 00 3E 08 08 08 08 3E 00 04 3E 04 0C 14 24 04 00 10 10 3E 12 14 10 10 00; +0540: 00 1C 04 04 04 04 3E 00 00 3E 02 3E 02 02 3E 00 08 3E 08 08 2A 2A 08 00; +0558: 00 10 28 04 02 02 00 00 00 20 20 22 24 28 30 00 00 02 02 14 08 14 20 00; +0570: 00 08 28 28 2A 2A 2C 00 08 3E 04 08 1C 2A 08 00 00 08 10 20 22 3E 02 00; +0588: 00 00 00 08 08 08 78 00 00 00 04 08 18 28 08 00 00 00 00 1C 04 04 3E 00; +05A0: 00 3E 02 3E 02 04 08 00 00 00 00 00 40 20 10 00 00 00 08 3E 22 02 0C 00; +05B8: 00 00 3C 04 3C 04 3C 00 70 50 70 00 00 00 00 00 00 00 00 00 00 00 20 00; +05D0: 00 00 00 3E 08 08 3E 00 00 00 00 2A 2A 02 0C 00 10 48 20 00 00 00 00 00; +05E8: 00 00 00 00 70 50 70 00 00 00 04 3E 0C 14 24 00 00 00 00 1C 00 00 00 00; +0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BB BB BB 83 BB BB BB FF; +0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C; +0678: 3C 42 81 A5 81 99 42 3C 3E 22 22 3E 22 22 3E 00 3E 22 3E 22 3E 22 42 00; +0690: 08 2A 2A 08 14 22 41 00 08 09 3A 0C 1C 2A 49 00 08 08 3E 08 1C 2A 49 00; +06A8: 08 14 3E 49 3E 1C 7F 00 00 08 08 3E 08 08 7F 00 08 48 7E 48 3E 08 7F 00; +06C0: 20 3E 48 3C 28 7E 08 00 04 7E 54 7F 52 7F 0A 00 08 14 22 7F 12 12 24 00; +06D8: 38 12 7F 17 3B 52 14 00 7F 49 49 7F 41 41 41 00 22 14 3E 08 3E 08 08 00; +06F0: 0C 12 10 38 10 10 3E 00 00 C0 C8 54 54 55 22 00; +0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02; +0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00; +0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23; +0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80; +0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04; +0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00; +0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70; +07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70; +07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07; +07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77; +07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77 00 00 00 00 00 00 00 00; +0808: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00; +0820: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00; +0838: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00; +0850: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00; +0868: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00; +0880: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00; +0898: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 42 3C 00; +08B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00; +08C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 08 08 08 08 FF 08 08 08; +08E0: 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00 08 08 08 08 0F 08 08 08; +08F8: 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00 08 18 28 08 08 08 3E 00; +0910: 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00 04 0C 14 24 7E 04 04 00; +0928: 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00 7E 42 04 08 10 10 10 00; +0940: 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00 00 00 00 7E 00 00 00 00; +0958: 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00; +0970: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10 00 FF 00 00 00 00 00 00; +0988: 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 FF; +09A0: 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10 FF FF 00 00 00 00 00 00; +09B8: C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00 04 04 04 04 04 04 04 04; +09D0: 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F 00 00 00 00 00 00 00 FF; +09E8: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF 03 03 03 03 03 03 03 03; +0A00: 00 00 08 04 FE 04 08 00 08 1C 3E 7F 7F 1C 3E 00 FF 7F 3F 1F 0F 07 03 01; +0A18: FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00 00 00 10 20 7F 20 10 00; +0A30: 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00 00 3C 42 42 42 42 3C 00; +0A48: 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF 00 00 00 00 03 04 08 08; +0A60: 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF 01 03 07 0F 1F 3F 7F FF; +0A78: 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00 0E 18 30 60 30 18 0E 00; +0A90: 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00 3C 04 04 04 04 04 3C 00; +0AA8: 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80 70 18 0C 06 0C 18 70 00; +0AC0: A0 50 A0 50 A0 50 A0 50 00 40 20 10 08 04 02 00 AA 55 AA 55 AA 55 AA 55; +0AD8: F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08 00 00 00 00 F8 08 08 08; +0AF0: 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08 00 00 01 3E 54 14 14 00; +0B08: 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00 24 24 7E 24 7E 24 24 00; +0B20: 08 1E 28 1C 0A 3C 08 00 00 62 64 08 10 26 46 00 30 48 48 30 4A 44 3A 00; +0B38: 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00; +0B50: 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00 0F 0F 0F 0F F0 F0 F0 F0; +0B68: 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00 08 08 04 03 00 00 00 00; +0B80: FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80 FF 80 80 80 80 80 80 80; +0B98: FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00 20 20 20 20 20 20 20 20; +0BB0: 04 08 11 22 44 88 10 20 20 10 88 44 22 11 08 04 00 00 00 00 FF 00 00 00; +0BC8: 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00 F0 F0 F0 F0 F0 F0 F0 F0; +0BE0: 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02 00 00 00 00 00 FF FF FF; +0BF8: 07 07 07 07 07 07 07 07 00 08 08 08 2A 1C 08 00 10 FE 20 7C 02 02 FC 00; +0C10: 00 FC 02 00 00 80 7E 00 3C 08 10 7E 08 10 0C 00 40 40 40 40 44 44 38 00; +0C28: 84 82 82 82 82 90 60 00 84 9E 84 84 9C A6 5C 00 10 7E 08 7E 04 02 60 18; +0C40: 0C 18 30 60 30 18 0C 00 9E 80 80 80 80 90 DE 00 10 7E 10 7E 10 70 9C 72; +0C58: 38 54 92 92 92 92 64 00 44 44 44 64 04 08 10 00 20 F8 20 F8 22 22 1C 00; +0C70: 70 10 14 7E 94 94 64 00 60 00 9C A2 C2 82 1C 00 44 44 FE 44 58 40 3E 00; +0C88: 20 FC 40 5E 80 A0 BE 00 08 FE 08 38 48 38 08 10 20 22 2C 30 40 80 7E 00; +0CA0: 22 F9 25 24 24 24 48 00 20 FA 41 44 9C A6 1C 00 E0 26 45 84 84 88 70 00; +0CB8: FE 04 08 10 10 08 04 00 20 FE 10 08 44 20 18 00 10 20 20 70 48 88 86 00; +0CD0: 80 7C 02 02 02 04 18 00 7C 08 10 2C 42 02 24 18 84 BE 84 84 84 84 48 00; +0CE8: 1E 10 10 10 00 00 00 00 00 20 70 20 78 94 68 00 00 00 58 E4 28 20 10 00; +0D00: 20 E4 2A 32 62 A2 24 00 04 44 7C 4A B2 97 66 00 38 00 10 4A 4A 8A 30 00; +0D18: 20 FC 20 7C AA 92 64 00 18 00 3C 42 02 04 08 00 10 00 7C 08 10 28 46 00; +0D30: 20 FD 21 7C A2 A2 64 00 48 4C 32 E2 24 10 10 08 08 9C AA CA CA 8C 18 00; +0D48: 08 0E 08 08 78 8E 78 00 9E 84 9E 84 9C A6 DC 00 00 20 50 88 04 02 02 00; +0D60: 20 E6 2C 34 64 A4 22 00 04 44 7C 4A B2 92 64 00 7C 08 10 3C 42 1A 24 18; +0D78: 20 E4 2A 32 66 AB 26 00 20 FD 21 60 A0 62 3E 00 00 00 00 00 08 08 08 78; +0D90: 00 00 48 44 44 44 20 00 00 00 10 B8 D4 98 30 00 10 FE 20 74 B8 48 7E 00; +0DA8: 00 00 00 00 00 40 20 10 00 20 00 78 04 04 08 00 00 00 20 38 20 78 60 00; +0DC0: 70 50 70 00 00 00 00 00 00 00 00 00 00 00 20 00 00 20 00 78 10 30 4C 00; +0DD8: 00 00 00 F8 04 04 18 00 20 90 40 00 00 00 00 00 00 00 00 00 00 70 50 70; +0DF0: 00 20 74 20 78 A4 68 00 00 00 00 1C 00 00 00 00; +0E00: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +0E18: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BB BB BB 83 BB BB BB FF; +0E30: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +0E48: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +0E60: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C; +0E78: 3C 42 81 A5 81 99 42 3C 3E 22 22 3E 22 22 3E 00 3E 22 3E 22 3E 22 42 00; +0E90: 08 2A 2A 08 14 22 41 00 08 09 3A 0C 1C 2A 49 00 08 08 3E 08 1C 2A 49 00; +0EA8: 08 14 3E 49 3E 1C 7F 00 00 08 08 3E 08 08 7F 00 08 48 7E 48 3E 08 7F 00; +0EC0: 20 3E 48 3C 28 7E 08 00 04 7E 54 7F 52 7F 0A 00 08 14 22 7F 12 12 24 00; +0ED8: 38 12 7F 17 3B 52 14 00 7F 49 49 7F 41 41 41 00 22 14 3E 08 3E 08 08 00; +0EF0: 0C 12 10 38 10 10 3E 00 00 C0 C8 54 54 55 22 00 00 00 00 00 00 02 FF 02; +0F08: 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02 00 00 20 50 88 05 02 00; +0F20: 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00 00 70 88 44 23 20 40 80; +0F38: 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23 88 90 A0 C0 C0 A8 98 B8; +0F50: A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80 00 00 24 24 E7 24 24 00; +0F68: 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04 55 AA 55 AA 55 AA 55 AA; +0F80: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00 00 07 07 07 00 00 00 00; +0F98: 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70; +0FB0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70 00 00 00 00 00 07 07 07; +0FC8: 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07; +0FE0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77 00 07 07 07 00 77 77 77; +0FF8: 00 77 77 77 00 77 77 77; +END; diff --git a/software/mif/MZ80B.mif b/software/mif/MZ80B.mif new file mode 100644 index 0000000..675e366 --- /dev/null +++ b/software/mif/MZ80B.mif @@ -0,0 +1,96 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 2048; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 18 04 3E 03 D3 E3 3E 82 D3 E3 3E 0F D3 E9 3E CF D3 EB 3E FF D3 EB 3E 58; +0018: D3 E2 3E 12 D3 E0 AF D3 F4 31 E0 FF 21 00 D0 3E B3 D3 E8 36 00 23 7C B5; +0030: 20 F9 3E 13 D3 E8 AF 32 EC FF 32 E6 FF CD 4B 00 CB 5F 28 27 CB 47 CA EF; +0048: 05 18 0C 06 14 DB E8 E6 F0 B0 D3 E8 DB EA C9 CD 5F 00 CA 3C 03 18 0C 3E; +0060: A5 47 D3 D9 CD D6 05 DB D9 B8 C9 CD B5 01 CD 1D 02 CD CE 01 CD AE 00 38; +0078: 17 CD 30 02 21 01 CF 1E 10 0E 10 CD 39 02 3A 00 CF FE 01 20 11 CD CF 00; +0090: F5 CD 1D 02 CD 0B 02 F1 DA 5F 05 C3 02 00 21 26 03 1E 0A 0E 0F CD 46 02; +00A8: CD B5 01 37 18 E2 F3 16 04 01 80 00 21 00 CF CD 86 01 38 0E CD 52 01 38; +00C0: 09 CD DB 00 38 04 CB 5A 28 03 CD B5 01 FB C9 F3 16 08 ED 4B 12 CF 21 00; +00D8: 80 18 DC D5 C5 E5 26 02 CD 7A 01 38 38 28 F9 54 21 00 00 22 E0 FF E1 C1; +00F0: C5 E5 CD 32 01 38 26 77 23 0B 78 B1 20 F4 2A E0 FF CD 32 01 38 17 5F CD; +0108: 32 01 38 11 BD 20 04 7B BC 28 0A 15 28 03 62 18 C7 CD 3F 02 37 E1 C1 D1; +0120: C9 DB E1 2F 07 D8 07 30 F8 DB E1 2F 07 D8 07 38 F8 C9 E5 21 00 08 CD 7A; +0138: 01 38 15 28 0A E5 2A E0 FF 23 22 E0 FF E1 37 CB 15 25 20 EA CD 21 01 7D; +0150: E1 C9 E5 21 14 14 CB 5A 20 01 29 22 E2 FF 2A E2 FF CD 7A 01 38 EA 28 F6; +0168: 25 20 F6 CD 7A 01 38 E0 20 EC 2D 20 F6 CD 21 01 18 D6 CD 21 01 D8 CD 29; +0180: 02 DB E1 E6 40 C9 D5 C5 E5 DB E1 E6 20 28 1F 21 8B 02 1E 0A 0E 0E CD 46; +0198: 02 CD C2 01 DB EA 2F 07 38 0F DB E1 E6 20 20 F4 CD CE 01 CD 23 02 CD D9; +01B0: 01 E1 C1 D1 C9 3E 0D D3 E3 3E 1A D3 E0 CD 1D 02 18 2D 3E 08 D3 E3 CD 1D; +01C8: 02 3E 09 D3 E3 C9 21 6F 02 1E 04 0E 1C CD 46 02 C9 CD F4 01 CD 1D 02 3E; +01E0: 16 D3 E0 18 0A CD 1D 02 CD EF 01 3E 13 D3 E0 3E 12 D3 E0 C9 3E 12 D3 E0; +01F8: CD 1D 02 3E 0B D3 E3 CD 1D 02 3E 0A D3 E3 C9 3E 10 18 EB CD 07 02 18 D5; +0210: F5 AF 3D 20 FD 0B 78 B1 20 F7 F1 C1 C9 C5 01 E9 00 18 ED C5 01 0F 06 18; +0228: E7 3E 31 3D C2 2B 02 C9 21 61 02 1E 00 0E 0E 18 0D 3E 93 D3 E8 18 17 21; +0240: 99 02 1E 0A 0E 0D 3E 93 D3 E8 D9 21 00 D0 36 00 23 7C B5 20 F9 D9 AF 47; +0258: 16 D0 ED B0 3E 13 D3 E8 C9 49 50 4C 20 69 73 20 6C 6F 61 64 69 6E 67 49; +0270: 50 4C 20 69 73 20 6C 6F 6F 6B 69 6E 67 20 66 6F 72 20 61 20 70 72 6F 67; +0288: 72 61 6D 4D 61 6B 65 20 72 65 61 64 79 20 43 4D 54 4C 6F 61 64 69 6E 67; +02A0: 20 65 72 72 6F 72 4D 61 6B 65 20 72 65 61 64 79 20 46 44 50 72 65 73 73; +02B8: 20 46 20 6F 72 20 43 46 3A 46 6C 6F 70 70 79 20 64 69 73 6B 65 74 74 65; +02D0: 43 3A 43 61 73 73 65 74 74 65 20 74 61 70 65 44 72 69 76 65 20 4E 6F 3F; +02E8: 20 28 31 2D 34 29 54 68 69 73 20 64 69 73 6B 65 74 74 65 20 69 73 20 6E; +0300: 6F 74 20 6D 61 73 74 65 72 50 72 65 73 73 69 6E 67 20 53 20 6B 65 79 20; +0318: 73 74 61 72 74 73 20 74 68 65 20 43 4D 54 46 69 6C 65 20 6D 6F 64 65 20; +0330: 65 72 72 6F 72 01 49 50 4C 50 52 4F DD 21 00 CF AF 32 1E CF 32 1F CF FD; +0348: 21 E0 FF 21 00 01 FD 75 02 FD 74 03 CD 7A 04 21 00 CF 11 35 03 06 06 4E; +0360: 1A B9 C2 4A 05 23 13 10 F6 CD 30 02 21 07 CF 1E 10 0E 0A CD 39 02 DD 21; +0378: 00 80 2A 14 CF FD 75 02 FD 74 03 CD 7A 04 CD F3 03 C3 02 00 21 A6 02 1E; +0390: 0A 0E 0D CD 46 02 C3 59 05 3A E6 FF 0F D4 CC 03 3A EC FF F6 84 D3 DC AF; +03A8: CD E4 05 21 00 00 2B 7C B5 28 D9 DB D8 2F 07 38 F5 3A EC FF 4F 21 E7 FF; +03C0: 06 00 09 CB 46 C0 CD 09 04 CB C6 C9 3E 80 D3 DC 06 0A 21 19 3C 2B 7D B4; +03D8: 20 FB 10 F6 3E 01 32 E6 FF C9 3E 1B 2F D3 D8 CD 21 04 CD E4 05 DB D8 2F; +03F0: E6 99 C9 CD DD 05 AF D3 DC 32 E7 FF 32 E8 FF 32 E9 FF 32 EA FF 32 E6 FF; +0408: C9 E5 3E 0B 2F D3 D8 CD 21 04 CD E4 05 DB D8 2F E6 85 EE 04 E1 C8 C3 56; +0420: 05 D5 E5 CD D6 05 1E 07 21 00 00 2B 7C B5 28 09 DB D8 2F 0F 38 F5 E1 D1; +0438: C9 1D 20 EC C3 56 05 06 00 11 10 00 2A 1E CF AF ED 52 38 03 04 18 F9 19; +0450: 60 2C FD 74 04 FD 75 05 3A EC FF FE 04 30 18 FD 7E 04 FE 46 30 11 FD 7E; +0468: 05 B7 28 0B FE 11 30 07 FD 7E 02 FD B6 03 C0 C3 56 05 F3 CD 3F 04 3E 0A; +0480: 32 EB FF CD 99 03 FD 56 03 FD 7E 02 B7 28 01 14 FD 7E 05 FD 77 01 FD 7E; +0498: 04 FD 77 00 DD E5 E1 CB 3F 2F D3 DB 30 04 3E 01 18 02 3E 00 2F D3 DD CD; +04B0: E2 03 20 6A 0E DB FD 7E 00 CB 3F 2F D3 D9 FD 7E 01 2F D3 DA D9 21 F7 04; +04C8: E5 D9 3E 94 2F D3 D8 CD 2D 05 06 00 DB D8 0F D8 0F 38 F9 ED A2 20 F5 FD; +04E0: 34 01 FD 7E 01 FE 11 28 05 15 20 E6 18 01 15 3E D8 2F D3 D8 CD 21 04 DB; +04F8: D8 2F E6 FF 20 20 D9 E1 D9 FD 7E 01 FE 11 20 08 3E 01 FD 77 01 FD 34 00; +0510: 7A B7 20 05 3E 80 D3 DC C9 FD 7E 00 18 81 3A EB FF 3D 32 EB FF 28 2F CD; +0528: 09 04 C3 83 04 D5 E5 CD D6 05 1E 08 21 00 00 2B 7C B5 28 09 DB D8 2F 0F; +0540: 30 F5 E1 D1 C9 1D 20 EC 18 0C 21 EE 02 1E 07 0E 1B CD 46 02 18 03 CD 3F; +0558: 02 CD F3 03 31 E0 FF CD 5F 00 20 47 21 B3 02 1E 5A 0E 0C CD 39 02 1E AB; +0570: 0E 11 CD 39 02 1E D3 0E 0F CD 39 02 CD 4B 00 CB 5F CA 6B 00 CB 77 28 02; +0588: 18 F2 21 DF 02 1E 0A 0E 0F CD 46 02 16 12 CD C1 05 30 09 16 18 CD C1 05; +05A0: 30 02 18 F0 78 32 EC FF C3 3C 03 21 09 03 1E 54 0E 1D CD 39 02 06 06 CD; +05B8: 4D 00 CB 5F CA 6B 00 18 F6 DB E8 E6 F0 B2 D3 E8 DB EA 06 00 0E 04 0F 0F; +05D0: D0 04 0D 20 FA C9 D5 11 0D 00 C3 E8 05 D5 11 82 00 C3 E8 05 D5 11 2C 1A; +05E8: 1B 7B B2 20 FB D1 C9 21 00 80 DD 21 F8 05 18 1A DB F9 FE 00 C2 57 00 DD; +0600: 21 05 06 18 0D DB F9 77 23 7D B4 20 F6 D3 F8 C3 02 00 7C D3 F8 7D D3 F9; +0618: 16 04 15 20 FD DD E9 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0630: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0648: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0660: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0678: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0690: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +06A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +06C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +06D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +06F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0700: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0718: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0730: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0748: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0760: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0778: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0790: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +07A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +07C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +07D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +07F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +END; diff --git a/software/mif/MZ80K2E_Jap_cgrom.mif b/software/mif/MZ80K2E_Jap_cgrom.mif new file mode 100644 index 0000000..4e36e4f --- /dev/null +++ b/software/mif/MZ80K2E_Jap_cgrom.mif @@ -0,0 +1,96 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 2048; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00; +0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00; +0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00; +0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00; +0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00; +0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00; +00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00; +00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00; +00D8: 08 08 08 08 FF 08 08 08 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00; +00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00; +0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00; +0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00; +0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00; +0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10; +0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10; +0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF; +0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10; +01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00; +01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F; +01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF; +01F8: 03 03 03 03 03 03 03 03 00 00 00 00 00 00 00 00 08 1C 3E 7F 7F 1C 3E 00; +0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00; +0228: 00 00 10 20 7F 20 10 00 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00; +0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF; +0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF; +0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00; +0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00; +02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80; +02B8: 70 18 0C 06 0C 18 70 00 A0 50 A0 50 A0 50 A0 50 00 40 20 10 08 04 02 00; +02D0: AA 55 AA 55 AA 55 AA 55 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08; +02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08; +0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00; +0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00; +0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00; +0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00; +0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00; +0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80; +0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00; +03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01; +03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00; +03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02; +03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 00 00 00 00 00 00 00 00; +0408: 04 38 08 3E 08 08 10 00 00 3E 02 02 02 02 3E 00 00 22 22 12 02 04 18 00; +0420: 00 30 02 32 02 04 38 00 02 04 08 18 28 08 08 00 00 08 04 22 22 22 22 00; +0438: 08 3E 08 3E 08 08 08 00 00 1E 12 22 02 04 18 00 00 1C 00 00 00 00 3E 00; +0450: 00 3E 02 02 14 08 04 00 04 04 04 04 04 08 10 00 24 24 24 24 04 08 10 00; +0468: 00 3E 10 3E 10 10 0E 00 00 1C 00 1C 00 3C 02 00 1C 00 3E 02 02 04 08 00; +0480: 10 3E 12 14 10 10 0E 00 00 1E 12 2A 06 04 18 00 00 3E 02 04 08 14 22 00; +0498: 10 10 10 18 14 10 10 00 10 3E 12 12 12 12 24 00 08 08 3E 08 08 10 20 00; +04B0: 20 20 3E 20 20 20 1E 00 1C 00 3E 08 08 08 10 00 14 3E 14 14 04 08 10 00; +04C8: 00 30 00 02 02 04 38 00 00 2A 2A 2A 02 04 08 00 00 3E 22 22 22 22 3E 00; +04E0: 10 1E 24 04 04 04 08 00 1E 10 10 10 00 00 00 00 00 00 3E 02 0C 08 10 00; +04F8: 00 00 10 3E 12 14 10 00 00 3E 22 22 02 04 08 00 00 3E 02 14 08 14 20 00; +0510: 00 3E 02 02 02 04 18 00 3E 02 0A 0C 08 08 10 00 08 3E 22 22 02 04 08 00; +0528: 00 3E 08 08 08 08 3E 00 04 3E 04 0C 14 24 04 00 10 10 3E 12 14 10 10 00; +0540: 00 1C 04 04 04 04 3E 00 00 3E 02 3E 02 02 3E 00 08 3E 08 08 2A 2A 08 00; +0558: 00 10 28 04 02 02 00 00 00 20 20 22 24 28 30 00 00 02 02 14 08 14 20 00; +0570: 00 08 28 28 2A 2A 2C 00 08 3E 04 08 1C 2A 08 00 00 08 10 20 22 3E 02 00; +0588: 00 00 00 08 08 08 78 00 00 00 04 08 18 28 08 00 00 00 00 1C 04 04 3E 00; +05A0: 00 3E 02 3E 02 04 08 00 00 00 00 00 40 20 10 00 00 00 08 3E 22 02 0C 00; +05B8: 00 00 3C 04 3C 04 3C 00 70 50 70 00 00 00 00 00 00 00 00 00 00 00 20 00; +05D0: 00 00 00 3E 08 08 3E 00 00 00 00 2A 2A 02 0C 00 10 48 20 00 00 00 00 00; +05E8: 00 00 00 00 70 50 70 00 00 00 04 3E 0C 14 24 00 00 00 00 1C 00 00 00 00; +0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BB BB BB 81 BB BB BB FF; +0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C; +0678: 3C 42 81 A5 81 99 42 3C 3E 22 22 3E 22 22 3E 00 3E 22 3E 22 3E 22 42 00; +0690: 08 2A 2A 08 14 22 41 00 08 09 3A 0C 1C 2A 49 00 08 08 3E 08 1C 2A 49 00; +06A8: 08 14 3E 49 3E 1C 7F 00 00 08 08 3E 08 08 7F 00 08 48 7E 48 3E 08 7F 00; +06C0: 20 3E 48 3C 28 7E 08 00 04 7E 54 7F 52 7F 0A 00 08 14 22 7F 12 12 24 00; +06D8: 38 12 7F 17 3B 52 14 00 7F 49 49 7F 41 41 41 00 22 14 3E 08 3E 08 08 00; +06F0: 0C 12 10 38 10 10 3E 00 00 C0 C8 54 54 55 22 00; +0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02; +0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00; +0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 29 F1 29 25 23; +0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80; +0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04; +0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00; +0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70; +07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70; +07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07; +07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77; +07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77; +END; diff --git a/software/mif/MZ80K_cgrom.mif b/software/mif/MZ80K_cgrom.mif new file mode 100644 index 0000000..89877bd --- /dev/null +++ b/software/mif/MZ80K_cgrom.mif @@ -0,0 +1,96 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 2048; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00; +0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00; +0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00; +0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00; +0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00; +0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00; +00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00; +00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00; +00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00; +00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00; +0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00; +0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00; +0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00; +0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10; +0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10; +0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF; +0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10; +01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00; +01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F; +01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF; +01F8: 03 03 03 03 03 03 03 03 00 00 00 00 00 00 00 00 08 1C 3E 7F 7F 1C 3E 00; +0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00; +0228: 00 00 10 20 7F 20 10 00 08 1C 2A 7F 2A 08 08 00 00 3C 7E 7E 7E 7E 3C 00; +0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF; +0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF; +0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00; +0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00; +02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80; +02B8: 70 18 0C 06 0C 18 70 00 00 08 08 08 2A 1C 08 00 00 40 20 10 08 04 02 00; +02D0: 00 00 04 02 7F 02 04 00 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08; +02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08; +0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00; +0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00; +0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00; +0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00; +0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00; +0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80; +0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00; +03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01; +03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00; +03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02; +03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 00 00 00 00 00 00 00 00; +0408: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00; +0420: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00; +0438: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00; +0450: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00; +0468: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00; +0480: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00; +0498: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 42 3C 00; +04B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00; +04C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 24 00 38 04 3C 44 3A 00; +04E0: 00 00 00 01 02 04 08 10 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00; +04F8: 00 00 00 80 40 20 10 08 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00; +0510: 44 44 44 44 44 44 44 44 44 FF 44 44 44 FF 44 44 22 44 88 11 22 44 88 11; +0528: 88 44 22 11 88 44 22 11 AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0; +0540: 03 0C 30 C0 00 00 00 00 C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00; +0558: 00 22 00 22 22 22 1C 00 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00; +0570: 42 18 24 42 7E 42 42 00 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80; +0588: 01 06 18 20 20 40 40 80 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01; +05A0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80; +05B8: 01 01 02 02 02 04 04 08 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03; +05D0: 00 00 00 00 01 06 38 C0 08 10 20 40 80 00 00 00 22 14 3E 08 3E 08 08 00; +05E8: 08 08 08 08 FF 08 08 08 24 24 24 24 C3 81 42 3C 00 3C 7A A9 A9 7A 3C 00; +0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF; +0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF 67 7E 3C; +0678: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05; +0690: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55; +06A8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55; +06C0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01; +06D8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08; +06F0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00; +0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02; +0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 00 FF 00 81 42 42 81 00; +0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 23 25 49 F1 49 25 23; +0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80; +0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04; +0778: 55 AA 55 AA 55 AA 55 AA 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00; +0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70; +07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70; +07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07; +07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77; +07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77; +END; diff --git a/software/mif/MZFONT.mif b/software/mif/MZFONT.mif new file mode 100644 index 0000000..6cb867a --- /dev/null +++ b/software/mif/MZFONT.mif @@ -0,0 +1,96 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 2048; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 1C 14 14 77 22 14 08 00 08 14 22 77 14 14 1C 00; +0018: 08 0C 7A 41 7A 0C 08 00 08 18 2F 41 2F 18 08 00 77 55 5D 41 5D 55 77 00; +0030: 1E 21 4F 50 4F 21 1E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +0048: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +0078: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +00A8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +00D8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; +00F0: 00 00 00 00 00 00 00 00 AA 55 AA 55 AA 55 AA 55 00 00 00 00 00 00 00 00; +0108: 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00 24 24 7E 24 7E 24 24 00; +0120: 08 1E 28 1C 0A 3C 08 00 00 62 64 08 10 26 46 00 30 48 48 30 4A 44 3A 00; +0138: 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00; +0150: 08 2A 1C 3E 1C 2A 08 00 00 08 08 3E 08 08 00 00 00 00 00 00 00 08 08 10; +0168: 00 00 00 7E 00 00 00 00 00 00 00 00 00 18 18 00 00 02 04 08 10 20 40 00; +0180: 3C 42 46 5A 62 42 3C 00 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00; +0198: 3C 42 02 3C 02 42 3C 00 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00; +01B0: 1C 20 40 7C 42 42 3C 00 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00; +01C8: 3C 42 42 3E 02 04 38 00 00 00 08 00 00 08 00 00 00 00 08 00 00 08 08 10; +01E0: 0E 18 30 60 30 18 0E 00 00 00 7E 00 7E 00 00 00 70 18 0C 06 0C 18 70 00; +01F8: 3C 42 02 0C 10 00 10 00 1C 22 4A 56 4C 20 1E 00 18 24 42 7E 42 42 42 00; +0210: 7C 22 22 3C 22 22 7C 00 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00; +0228: 7E 40 40 78 40 40 7E 00 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00; +0240: 42 42 42 7E 42 42 42 00 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00; +0258: 42 44 48 70 48 44 42 00 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00; +0270: 42 62 52 4A 46 42 42 00 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00; +0288: 18 24 42 42 4A 24 1A 00 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00; +02A0: 3E 08 08 08 08 08 08 00 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00; +02B8: 42 42 42 5A 5A 66 42 00 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00; +02D0: 7E 02 04 18 20 40 7E 00 3C 20 20 20 20 20 3C 00 00 40 20 10 08 04 02 00; +02E8: 3C 04 04 04 04 04 3C 00 08 14 22 00 00 00 00 00 FF 00 00 00 00 00 00 00; +0300: 20 10 08 00 00 00 00 00 00 00 3C 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00; +0318: 00 00 3C 42 40 42 3C 00 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00; +0330: 0C 12 10 7C 10 10 10 00 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00; +0348: 08 00 18 08 08 08 1C 00 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00; +0360: 18 08 08 08 08 08 1C 00 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00; +0378: 00 00 3C 42 42 42 3C 00 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02; +0390: 00 00 5C 62 40 40 40 00 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00; +03A8: 00 00 42 42 42 46 3A 00 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00; +03C0: 00 00 42 24 18 24 42 00 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00; +03D8: 08 10 10 20 10 10 08 00 18 18 18 18 18 18 18 00 10 08 08 04 08 08 10 00; +03F0: 00 00 00 32 4C 00 00 00 00 7C 04 04 15 0E 04 00 28 28 28 28 28 28 28 28; +0408: 00 08 08 08 2A 1C 08 00 00 08 1C 2A 08 08 08 00 00 08 04 7E 04 08 00 00; +0420: 00 10 20 7E 20 10 00 00 08 1C 3E 7F 7F 1C 3E 00 36 7F 7F 7F 3E 1C 08 00; +0438: 08 1C 3E 7F 3E 1C 08 00 1C 1C 6B 7F 6B 08 1C 00 10 10 10 1F 1F 10 10 10; +0450: 10 10 10 F0 F0 10 10 10 00 00 00 FF 28 28 28 28 28 28 28 FF 00 00 00 00; +0468: 28 28 28 FF FF 28 28 28 10 10 10 FF FF 10 10 10 28 28 28 FF 28 28 28 28; +0480: 00 00 00 FF FF 00 00 00 22 14 3E 08 3E 08 08 00 0C 12 10 38 10 10 3E 00; +0498: 00 3C 7E 7E 7E 7E 3C 00 00 3C 42 42 42 42 3C 00 00 00 00 F0 10 10 10 10; +04B0: 10 10 10 F0 00 00 00 00 00 00 00 1F 10 10 10 10 10 10 10 1F 00 00 00 00; +04C8: 10 10 10 FF 10 10 10 10 10 10 10 10 10 10 10 10 00 00 00 FF 00 00 00 00; +04E0: 10 10 10 FF 00 00 00 00 00 00 00 FF 10 10 10 10 10 10 10 F0 10 10 10 10; +04F8: 10 10 10 1F 10 10 10 10 FF FF FF FF FF FF FF FF F7 F7 F7 F7 FF FF F7 FF; +0510: DB DB DB FF FF FF FF FF DB DB 81 DB 81 DB DB FF F7 E1 D7 E3 F5 C3 F7 FF; +0528: FF 9D 9B F7 EF D9 B9 FF CF B7 B7 CF B5 BB C5 FF FB F7 EF FF FF FF FF FF; +0540: FB F7 EF EF EF F7 FB FF DF EF F7 F7 F7 EF DF FF F7 D5 E3 C1 E3 D5 F7 FF; +0558: FF F7 F7 C1 F7 F7 FF FF FF FF FF FF FF F7 F7 EF FF FF FF 81 FF FF FF FF; +0570: FF FF FF FF FF E7 E7 FF FF FD FB F7 EF DF BF FF C3 BD B9 A5 9D BD C3 FF; +0588: F7 E7 D7 F7 F7 F7 C1 FF C3 BD FD F3 CF BF 81 FF C3 BD FD C3 FD BD C3 FF; +05A0: FB F3 EB DB 81 FB FB FF 81 BF 87 FB FD BB C7 FF E3 DF BF 83 BD BD C3 FF; +05B8: 81 BD FB F7 EF EF EF FF C3 BD BD C3 BD BD C3 FF C3 BD BD C1 FD FB C7 FF; +05D0: FF FF F7 FF FF F7 FF FF FF FF F7 FF FF F7 F7 EF F1 E7 CF 9F CF E7 F1 FF; +05E8: FF FF 81 FF 81 FF FF FF 8F E7 F3 F9 F3 E7 8F FF C3 BD FD F3 EF FF EF FF; +0600: E3 DD B5 A9 B3 DF E1 FF E7 DB BD 81 BD BD BD FF 83 DD DD C3 DD DD 83 FF; +0618: E3 DD BF BF BF DD E3 FF 87 DB DD DD DD DB 87 FF 81 BF BF 87 BF BF 81 FF; +0630: 81 BF BF 87 BF BF BF FF E3 DD BF B1 BD DD E3 FF BD BD BD 81 BD BD BD FF; +0648: E3 F7 F7 F7 F7 F7 E3 FF F1 FB FB FB FB BB C7 FF BD BB B7 8F B7 BB BD FF; +0660: BF BF BF BF BF BF 81 FF BD 99 A5 A5 BD BD BD FF BD 9D AD B5 B9 BD BD FF; +0678: E7 DB BD BD BD DB E7 FF 83 BD BD 83 BF BF BF FF E7 DB BD BD B5 DB E5 FF; +0690: 83 BD BD 83 B7 BB BD FF C3 BD BF C3 FD BD C3 FF C1 F7 F7 F7 F7 F7 F7 FF; +06A8: BD BD BD BD BD BD C3 FF BD BD BD DB DB E7 E7 FF BD BD BD A5 A5 99 BD FF; +06C0: BD BD DB E7 DB BD BD FF DD DD DD E3 F7 F7 F7 FF 81 FD FB E7 DF BF 81 FF; +06D8: C3 DF DF DF DF DF C3 FF FF BF DF EF F7 FB FD FF C3 FB FB FB FB FB C3 FF; +06F0: F7 EB DD FF FF FF FF FF 00 FF FF FF FF FF FF FF; +0700: DF EF F7 FF FF FF FF FF FF FF C3 FB C3 BB C5 FF BF BF A3 9D BD 9D A3 FF; +0718: FF FF C3 BD BF BD C3 FF FD FD C5 B9 BD B9 C5 FF FF FF C3 BD 81 BF C3 FF; +0730: F3 ED EF 83 EF EF EF FF FF FF C5 B9 B9 C5 FD C3 BF BF A3 9D BD BD BD FF; +0748: F7 FF E7 F7 F7 F7 E3 FF FB FF F3 FB FB FB BB C7 BF BF BB B7 AF 97 BB FF; +0760: E7 F7 F7 F7 F7 F7 E3 FF FF FF 89 B6 B6 B6 B6 FF FF FF A3 9D BD BD BD FF; +0778: FF FF C3 BD BD BD C3 FF FF FF A3 9D 9D A3 BF BF FF FF C5 B9 B9 C5 FD FD; +0790: FF FF A3 9D BF BF BF FF FF FF C1 BF C3 FD 83 FF EF EF 83 EF EF ED F3 FF; +07A8: FF FF BD BD BD B9 C5 FF FF FF BD BD BD DB E7 FF FF FF BE B6 B6 B6 C9 FF; +07C0: FF FF BD DB E7 DB BD FF FF FF BD BD B9 C5 FD C3 FF FF 81 FB E7 DF 81 FF; +07D8: F7 EF EF DF EF EF F7 FF E7 E7 E7 E7 E7 E7 E7 FF EF F7 F7 FB F7 F7 EF FF; +07F0: FF FF FF CD B3 FF FF FF 00 00 01 3E 54 14 14 00; +END; diff --git a/software/mif/PALETTE_B.mif b/software/mif/PALETTE_B.mif new file mode 100644 index 0000000..5a035f2 --- /dev/null +++ b/software/mif/PALETTE_B.mif @@ -0,0 +1,39 @@ +DEPTH = 512; +WIDTH = 5; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN + +0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0040: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0050: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0060: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0070: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0080: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0090: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0100: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0110: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0120: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0130: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0140: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0150: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0160: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0170: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0180: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0190: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +END; diff --git a/software/mif/PALETTE_G.mif b/software/mif/PALETTE_G.mif new file mode 100644 index 0000000..5a035f2 --- /dev/null +++ b/software/mif/PALETTE_G.mif @@ -0,0 +1,39 @@ +DEPTH = 512; +WIDTH = 5; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN + +0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0040: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0050: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0060: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0070: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0080: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0090: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0100: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0110: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0120: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0130: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0140: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0150: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0160: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0170: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0180: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0190: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +END; diff --git a/software/mif/PALETTE_R.mif b/software/mif/PALETTE_R.mif new file mode 100644 index 0000000..5a035f2 --- /dev/null +++ b/software/mif/PALETTE_R.mif @@ -0,0 +1,39 @@ +DEPTH = 512; +WIDTH = 5; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN + +0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0040: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0050: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0060: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0070: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0080: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0090: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +00e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +00f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0100: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0110: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0120: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0130: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0140: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0150: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0160: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0170: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +0180: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +0190: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01a0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01b0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01c0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01d0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +01e0: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07; +01f0: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F; +END; diff --git a/software/mif/mz-80acg.mif b/software/mif/mz-80acg.mif new file mode 100644 index 0000000..6e5b02f --- /dev/null +++ b/software/mif/mz-80acg.mif @@ -0,0 +1,96 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 2048; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 00 00 00 00 00 00 00 00 18 24 42 7E 42 42 42 00 7C 22 22 3C 22 22 7C 00; +0018: 1C 22 40 40 40 22 1C 00 78 24 22 22 22 24 78 00 7E 40 40 78 40 40 7E 00; +0030: 7E 40 40 78 40 40 40 00 1C 22 40 4E 42 22 1C 00 42 42 42 7E 42 42 42 00; +0048: 1C 08 08 08 08 08 1C 00 0E 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00; +0060: 40 40 40 40 40 40 7E 00 42 66 5A 5A 42 42 42 00 42 62 52 4A 46 42 42 00; +0078: 18 24 42 42 42 24 18 00 7C 42 42 7C 40 40 40 00 18 24 42 42 4A 24 1A 00; +0090: 7C 42 42 7C 48 44 42 00 3C 42 40 3C 02 42 3C 00 3E 08 08 08 08 08 08 00; +00A8: 42 42 42 42 42 42 3C 00 42 42 42 24 24 18 18 00 42 42 42 5A 5A 66 42 00; +00C0: 42 42 24 18 24 42 42 00 22 22 22 1C 08 08 08 00 7E 02 04 18 20 40 7E 00; +00D8: 0C 12 10 38 10 10 3E 00 08 08 08 08 0F 00 00 00 08 08 08 08 F8 00 00 00; +00F0: 08 08 08 08 0F 08 08 08 08 08 08 08 FF 00 00 00 3C 42 46 5A 62 42 3C 00; +0108: 08 18 28 08 08 08 3E 00 3C 42 02 0C 30 40 7E 00 3C 42 02 3C 02 42 3C 00; +0120: 04 0C 14 24 7E 04 04 00 7E 40 78 04 02 44 38 00 1C 20 40 7C 42 42 3C 00; +0138: 7E 42 04 08 10 10 10 00 3C 42 42 3C 42 42 3C 00 3C 42 42 3E 02 04 38 00; +0150: 00 00 00 7E 00 00 00 00 00 00 7E 00 7E 00 00 00 00 00 08 00 00 08 08 10; +0168: 00 02 04 08 10 20 40 00 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10; +0180: 00 FF 00 00 00 00 00 00 40 40 40 40 40 40 40 40 80 80 80 80 80 80 80 FF; +0198: 01 01 01 01 01 01 01 FF 00 00 00 FF 00 00 00 00 10 10 10 10 10 10 10 10; +01B0: FF FF 00 00 00 00 00 00 C0 C0 C0 C0 C0 C0 C0 C0 00 00 00 00 00 FF 00 00; +01C8: 04 04 04 04 04 04 04 04 00 00 00 00 FF FF FF FF 0F 0F 0F 0F 0F 0F 0F 0F; +01E0: 00 00 00 00 00 00 00 FF 01 01 01 01 01 01 01 01 00 00 00 00 00 00 FF FF; +01F8: 03 03 03 03 03 03 03 03 10 08 08 04 08 08 10 00 08 1C 3E 7F 7F 1C 3E 00; +0210: FF 7F 3F 1F 0F 07 03 01 FF FF FF FF FF FF FF FF 08 1C 3E 7F 3E 1C 08 00; +0228: 00 00 10 20 7F 20 10 00 1C 1C 6B 7F 6B 08 1C 00 00 3C 7E 7E 7E 7E 3C 00; +0240: 00 3C 42 42 42 42 3C 00 3C 42 02 0C 10 00 10 00 FF C3 81 81 81 81 C3 FF; +0258: 00 00 00 00 03 04 08 08 00 00 00 00 C0 20 10 10 80 C0 E0 F0 F8 FC FE FF; +0270: 01 03 07 0F 1F 3F 7F FF 00 00 08 00 00 08 00 00 00 08 1C 2A 08 08 08 00; +0288: 0E 18 30 60 30 18 0E 00 3C 20 20 20 20 20 3C 00 36 7F 7F 7F 3E 1C 08 00; +02A0: 3C 04 04 04 04 04 3C 00 1C 22 4A 56 4C 20 1E 00 FF FE FC F8 F0 E0 C0 80; +02B8: 70 18 0C 06 0C 18 70 00 00 08 08 08 2A 1C 08 00 00 40 20 10 08 04 02 00; +02D0: 00 00 04 02 7F 02 04 00 F0 F0 F0 F0 0F 0F 0F 0F 00 00 00 00 0F 08 08 08; +02E8: 00 00 00 00 F8 08 08 08 08 08 08 08 F8 08 08 08 00 00 00 00 FF 08 08 08; +0300: 00 00 01 3E 54 14 14 00 08 08 08 08 00 00 08 00 24 24 24 00 00 00 00 00; +0318: 24 24 7E 24 7E 24 24 00 08 1E 28 1C 0A 1C 08 00 00 62 64 08 10 26 46 00; +0330: 30 48 48 30 4A 44 3A 00 04 08 10 00 00 00 00 00 04 08 10 10 10 08 04 00; +0348: 20 10 08 08 08 10 20 00 00 08 08 3E 08 08 00 00 08 2A 1C 3E 1C 2A 08 00; +0360: 0F 0F 0F 0F F0 F0 F0 F0 81 42 24 18 18 24 42 81 10 10 20 C0 00 00 00 00; +0378: 08 08 04 03 00 00 00 00 FF 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80; +0390: FF 80 80 80 80 80 80 80 FF 01 01 01 01 01 01 01 00 00 FF 00 00 00 00 00; +03A8: 20 20 20 20 20 20 20 20 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01; +03C0: 00 00 00 00 FF 00 00 00 08 08 08 08 08 08 08 08 FF FF FF FF 00 00 00 00; +03D8: F0 F0 F0 F0 F0 F0 F0 F0 00 00 00 00 00 00 FF 00 02 02 02 02 02 02 02 02; +03F0: 00 00 00 00 00 FF FF FF 07 07 07 07 07 07 07 07 18 18 18 18 18 18 18 00; +0408: 00 00 38 04 3C 44 3A 00 40 40 5C 62 42 62 5C 00 00 00 3C 42 40 42 3C 00; +0420: 02 02 3A 46 42 46 3A 00 00 00 3C 42 7E 40 3C 00 0C 12 10 7C 10 10 10 00; +0438: 00 00 3A 46 46 3A 02 3C 40 40 5C 62 42 42 42 00 08 00 18 08 08 08 1C 00; +0450: 04 00 0C 04 04 04 44 38 40 40 44 48 50 68 44 00 18 08 08 08 08 08 1C 00; +0468: 00 00 76 49 49 49 49 00 00 00 5C 62 42 42 42 00 00 00 3C 42 42 42 3C 00; +0480: 00 00 5C 62 62 5C 40 40 00 00 3A 46 46 3A 02 02 00 00 5C 62 40 40 40 00; +0498: 00 00 3E 40 3C 02 7C 00 10 10 7C 10 10 12 0C 00 00 00 42 42 42 46 3A 00; +04B0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00 00 00 44 28 10 28 44 00; +04C8: 00 00 42 42 46 3A 02 3C 00 00 7E 04 18 20 7E 00 24 00 38 04 3C 44 3A 00; +04E0: 00 00 00 01 02 04 08 10 03 1C 60 80 00 00 00 00 C0 38 06 01 00 00 00 00; +04F8: 00 00 00 80 40 20 10 08 00 00 00 00 C0 30 0C 03 00 FF 00 00 00 FF 00 00; +0510: 44 44 44 44 44 44 44 44 44 FF 44 44 44 FF 44 44 20 10 08 00 00 00 00 00; +0528: 00 00 00 32 4C 00 00 00 AA 44 AA 11 AA 44 AA 11 00 00 00 00 03 0C 30 C0; +0540: 03 0C 30 C0 00 00 00 00 C0 30 0C 03 00 00 00 00 38 44 44 4A 42 52 4C 00; +0558: 00 22 00 22 22 26 1A 00 00 22 00 1C 22 22 1C 00 42 00 42 42 42 42 3C 00; +0570: 42 18 24 42 7E 42 42 00 42 18 24 42 42 24 18 00 10 20 20 40 40 40 80 80; +0588: 01 06 18 20 20 40 40 80 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01; +05A0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01 01 02 02 04 04 18 60 80; +05B8: 01 01 02 02 02 04 04 08 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1C 03; +05D0: 00 00 00 00 01 06 38 C0 08 10 20 40 80 00 00 00 08 10 10 20 10 10 08 00; +05E8: 08 08 08 08 FF 08 08 08 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7E 00; +0600: 1C 1C 3E 1C 08 00 3E 00 FF F7 F7 F7 D5 E3 F7 FF FF F7 E3 D5 F7 F7 F7 FF; +0618: FF FF F7 FB 81 FB F7 FF FF FF EF DF 81 DF EF FF BD BD BD 81 BD BD BD FF; +0630: E3 DD BF BF BF DD E3 FF 18 24 7E FF 5A 24 00 00 E0 47 42 7E 42 47 E0 00; +0648: 22 3E 2A 08 08 49 7F 41 1C 1C 08 3E 08 08 14 22 00 11 D2 FC D2 11 00 00; +0660: 00 88 4B 3F 4B 88 00 00 22 14 08 08 3E 08 1C 1C 3C 7E FF DB FF E7 7E 3C; +0678: 3C 42 81 A5 81 99 42 3C AA 55 AA 55 AA 55 AA 55 0A 05 0A 05 0A 05 0A 05; +0690: A0 50 A0 50 A0 50 A0 50 AA 55 AA 55 00 00 00 00 00 00 00 00 AA 55 AA 55; +06A8: AA 54 A8 50 A0 40 80 00 AA 55 2A 15 0A 05 02 01 80 40 A0 50 A8 54 AA 55; +06C0: 00 01 02 05 0A 15 2A 55 80 80 40 40 20 20 10 10 08 08 04 04 02 02 01 01; +06D8: 38 28 38 00 00 00 00 00 00 54 2A 54 2A 54 2A 00 01 01 02 02 04 04 08 08; +06F0: 10 10 20 20 40 40 80 80 00 C0 C8 54 54 55 22 00; +0700: 00 00 00 00 00 02 FF 02 02 02 02 02 02 02 07 02 02 02 02 02 02 02 FF 02; +0718: 00 00 20 50 88 05 02 00 00 0E 11 22 C4 04 02 01 88 44 22 11 88 44 22 11; +0730: 00 70 88 44 23 20 40 80 00 C4 A4 94 8F 94 A4 C4 00 43 45 49 F1 49 45 43; +0748: 88 90 A0 C0 C0 A8 98 B8 A8 B0 B8 C0 C0 A0 90 88 80 40 20 10 1F 20 40 80; +0760: 00 00 24 24 E7 24 24 00 08 08 3E 00 00 3E 08 08 08 10 20 10 08 04 02 04; +0778: 55 AA 55 AA 55 AA 55 AA 22 44 88 11 22 44 88 11 00 70 70 70 00 00 00 00; +0790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00 00 00 00 00 00 70 70 70; +07A8: 00 70 70 70 00 70 70 70 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70; +07C0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07 00 07 07 07 00 07 07 07; +07D8: 00 77 77 77 00 07 07 07 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77; +07F0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77; +END;