218 lines
8.5 KiB
Plaintext
218 lines
8.5 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 16:29:32 June 24, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# tranZPUterSW_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY MAX7000AE
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set_global_assignment -name DEVICE "EPM7512AETC144-12"
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set_global_assignment -name TOP_LEVEL_ENTITY VideoInterfaceCPLD
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
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set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
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set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
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# Global clocks.
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# ==============
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set_location_assignment PIN_125 -to CLOCK_50
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# Z80 Address Bus
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# ===============
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#set_location_assignment PIN_90 -to A[13]
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#set_location_assignment PIN_88 -to A[12]
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#set_location_assignment PIN_87 -to A[11]
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set_location_assignment PIN_98 -to A[10]
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set_location_assignment PIN_101 -to A[9]
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set_location_assignment PIN_103 -to A[8]
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set_location_assignment PIN_106 -to A[7]
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set_location_assignment PIN_108 -to A[6]
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set_location_assignment PIN_110 -to A[5]
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set_location_assignment PIN_112 -to A[4]
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set_location_assignment PIN_114 -to A[3]
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set_location_assignment PIN_117 -to A[2]
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set_location_assignment PIN_119 -to A[1]
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set_location_assignment PIN_121 -to A[0]
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# Video Interface Address Bus
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# ===========================
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set_location_assignment PIN_69 -to VADDR[15]
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set_location_assignment PIN_68 -to VADDR[14]
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set_location_assignment PIN_42 -to VADDR[13]
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set_location_assignment PIN_41 -to VADDR[12]
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set_location_assignment PIN_40 -to VADDR[11]
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set_location_assignment PIN_39 -to VADDR[10]
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set_location_assignment PIN_38 -to VADDR[9]
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set_location_assignment PIN_37 -to VADDR[8]
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set_location_assignment PIN_36 -to VADDR[7]
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set_location_assignment PIN_35 -to VADDR[6]
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set_location_assignment PIN_34 -to VADDR[5]
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set_location_assignment PIN_32 -to VADDR[4]
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set_location_assignment PIN_31 -to VADDR[3]
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set_location_assignment PIN_30 -to VADDR[2]
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set_location_assignment PIN_29 -to VADDR[1]
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set_location_assignment PIN_28 -to VADDR[0]
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# Clock outputs.
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# ==============
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set_location_assignment PIN_7 -to CLK_1MHZ_OUT
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set_location_assignment PIN_10 -to CLK_2MHZ_OUT
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set_location_assignment PIN_9 -to CLK_31_5K_OUT
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# Z80 control signals
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# ===================
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set_location_assignment PIN_92 -to CSn
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set_location_assignment PIN_93 -to GTn
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#set_location_assignment PIN_84 -to IORQn
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#set_location_assignment PIN_83 -to MEM_CSn
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set_location_assignment PIN_86 -to MB_RESETn
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set_location_assignment PIN_127 -to RESETn
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set_location_assignment PIN_91 -to RDn
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set_location_assignment PIN_96 -to WRn
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set_location_assignment PIN_16 -to VRAM_CS_INn
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set_location_assignment PIN_90 -to INDATA[3]
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set_location_assignment PIN_88 -to INDATA[2]
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set_location_assignment PIN_87 -to INDATA[1]
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set_location_assignment PIN_84 -to INDATA[0]
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set_location_assignment PIN_83 -to OUTCLK
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# Z80 Data Bus
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# ============
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set_location_assignment PIN_107 -to D[7]
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set_location_assignment PIN_109 -to D[6]
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set_location_assignment PIN_111 -to D[5]
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set_location_assignment PIN_113 -to D[4]
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set_location_assignment PIN_116 -to D[3]
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set_location_assignment PIN_118 -to D[2]
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set_location_assignment PIN_120 -to D[1]
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set_location_assignment PIN_122 -to D[0]
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# Video Data Bus
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# ==============
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set_location_assignment PIN_53 -to VDATA[7]
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set_location_assignment PIN_54 -to VDATA[6]
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set_location_assignment PIN_55 -to VDATA[5]
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set_location_assignment PIN_56 -to VDATA[4]
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set_location_assignment PIN_60 -to VDATA[3]
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set_location_assignment PIN_61 -to VDATA[2]
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set_location_assignment PIN_62 -to VDATA[1]
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set_location_assignment PIN_63 -to VDATA[0]
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# VRAM Data Bus
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# =============
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set_location_assignment PIN_18 -to VRAMD[7]
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set_location_assignment PIN_19 -to VRAMD[6]
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set_location_assignment PIN_21 -to VRAMD[5]
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set_location_assignment PIN_22 -to VRAMD[4]
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set_location_assignment PIN_23 -to VRAMD[3]
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set_location_assignment PIN_14 -to VRAMD[2]
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set_location_assignment PIN_12 -to VRAMD[1]
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set_location_assignment PIN_11 -to VRAMD[0]
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# Mainboard video signals on the CN1 connector.
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# =============================================
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set_location_assignment PIN_94 -to MB_HBLNKn
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set_location_assignment PIN_100 -to MB_LOAD
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set_location_assignment PIN_97 -to MB_SYNCH
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set_location_assignment PIN_99 -to MB_V_HBLNKn
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set_location_assignment PIN_102 -to MB_VIDEO
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# Mainboard video signals on the CN1 connector passed to the FPGA.
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# ================================================================
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set_location_assignment PIN_75 -to VMB_HBLNKn
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set_location_assignment PIN_74 -to VMB_LOAD
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set_location_assignment PIN_72 -to VMB_SYNCH
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set_location_assignment PIN_71 -to VMB_V_HBLNKn
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set_location_assignment PIN_70 -to VMB_VIDEO
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# Generated video signals.
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# ========================
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set_location_assignment PIN_1 -to HBLNK_OUTn
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set_location_assignment PIN_2 -to HSY_OUT
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set_location_assignment PIN_15 -to SRVIDEO_OUT
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set_location_assignment PIN_8 -to SYNCH_OUT
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set_location_assignment PIN_6 -to VBLNK_OUTn
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# FPGA Generated video signals.
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# =============================
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set_location_assignment PIN_80 -to VHBLNK_OUTn
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set_location_assignment PIN_79 -to VHSY_OUT
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set_location_assignment PIN_81 -to VSRVIDEO_OUT
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set_location_assignment PIN_78 -to VSYNCH_OUT
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set_location_assignment PIN_77 -to VVBLNK_OUTn
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# Video control signals.
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# ======================
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set_location_assignment PIN_46 -to VCSn
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set_location_assignment PIN_47 -to VGTn
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set_location_assignment PIN_44 -to VZ80_IORQn
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#set_location_assignment PIN_43 -to VMEM_CSn
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set_location_assignment PIN_45 -to VZ80_RDn
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set_location_assignment PIN_49 -to VRESETn
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set_location_assignment PIN_27 -to VVRAM_CS_INn
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set_location_assignment PIN_48 -to VZ80_WRn
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# Reserved.
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# =========
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#set_location_assignment PIN_67 -to TBA[2]
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#set_location_assignment PIN_66 -to TBA[1]
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#set_location_assignment PIN_65 -to TBA[0]
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set_global_assignment -name VHDL_FILE ../VideoInterface_Toplevel.vhd
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set_global_assignment -name VHDL_FILE ../VideoInterface_pkg.vhd
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set_global_assignment -name VHDL_FILE ../VideoInterface.vhd
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set_global_assignment -name SDC_FILE VideoInterface_constraints.sdc
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name AUTO_RESOURCE_SHARING OFF
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set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
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set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
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set_global_assignment -name AUTO_LCELL_INSERTION OFF
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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