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T80: fix INIR/INDR timings.

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sorgelig
2018-07-12 04:30:57 +08:00
parent 76662059cf
commit e7bdf5b6fa
1 changed files with 1 additions and 1 deletions
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2
t80/T80_MCode.vhd
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@@ -1901,6 +1901,7 @@ begin
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
@@ -1917,7 +1918,6 @@ begin
else
IncDec_16 <= "1110";
end if;
TStates <= "100";
Write <= '1';
I_BTR <= '1';
when 4 =>