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birdybro
2024-07-27 11:27:49 -06:00
parent 2936db0d4c
commit f6ecb2d30a
19 changed files with 631 additions and 1054 deletions
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2
SlugCross.sv
View File

@@ -54,6 +54,7 @@ module emu
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
output HDMI_BLACKOUT,
`ifdef MISTER_FB
// Use framebuffer in DDRAM
@@ -185,6 +186,7 @@ assign VGA_F1 = 0;
assign VGA_SCALER = 0;
assign VGA_DISABLE = 0;
assign HDMI_FREEZE = 0;
assign HDMI_BLACKOUT = 0;
assign AUDIO_S = 0;
assign AUDIO_L = 0;

5
sys/arcade_video.v
View File

@@ -99,6 +99,11 @@ generate
assign G = {RGB_fix[7:4],RGB_fix[7:4]};
assign B = {RGB_fix[3:0],RGB_fix[3:0]};
end
else if(DW == 18) begin
assign R = {RGB_fix[17:12],RGB_fix[17:16]};
assign G = {RGB_fix[11: 6],RGB_fix[11:10]};
assign B = {RGB_fix[ 5: 0],RGB_fix[ 5: 4]};
end
else begin // 24
assign R = RGB_fix[23:16];
assign G = RGB_fix[15:8];

13
sys/ascal.vhd
View File

@@ -222,6 +222,7 @@ ENTITY ascal IS
vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp
vrr : IN std_logic := '0';
vrrmax : IN natural RANGE 0 TO 4095 := 0;
swblack : IN std_logic := '0'; -- will output 3 black frame on every resolution switch
-- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp
format : IN unsigned(1 DOWNTO 0) :="01";
@@ -510,6 +511,7 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_divrun : std_logic;
SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0);
SIGNAL o_vacptl : unsigned(1 DOWNTO 0);
signal o_newres : integer range 0 to 3;
-----------------------------------------------------------------------------
FUNCTION shift_ishift(shift : unsigned(0 TO 119);
@@ -1890,6 +1892,14 @@ BEGIN
o_ivsize<=i_vrsize; -- <ASYNC>
o_hdown<=i_hdown; -- <ASYNC>
o_vdown<=i_vdown; -- <ASYNC>
IF (o_newres > 0) then
o_newres <= o_newres- 1;
END IF;
END IF;
IF (swblack = '1' and o_fb_ena = '0' and (o_ihsize /= i_hrsize or o_ivsize /= i_vrsize)) then
o_newres <= 3;
END IF;
-- Simultaneous change of input and output framebuffers
@@ -2219,6 +2229,9 @@ BEGIN
hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8),
b=>o_fb_pal_dr(7 DOWNTO 0));
END IF;
IF (o_newres > 0) then
hpix_v := (others => (others => '0'));
END IF;
o_hpix0<=hpix_v;
o_hpix1<=o_hpix0;
o_hpix2<=o_hpix1;

2
sys/hps_io.sv
View File

@@ -233,7 +233,7 @@ video_calc video_calc
/////////////////////////////////////////////////////////
localparam STRLEN = $size(CONF_STR)>>3;
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
localparam MAX_W = $clog2((64 > (STRLEN+2)) ? 64 : (STRLEN+2))-1;
wire [7:0] conf_byte;
generate

17
sys/mcp23009.sv
View File

@@ -8,10 +8,12 @@ module mcp23009
output reg [2:0] btn,
input [2:0] led,
output reg sd_cd,
output reg flg_sd_cd,
output reg flg_present,
output reg flg_mode,
output scl,
inout sda
output scl,
inout sda
);
@@ -50,7 +52,9 @@ always@(posedge clk) begin
idx <= 0;
btn <= 0;
rw <= 0;
sd_cd <= 1;
flg_sd_cd <= 1;
flg_present <= 0;
flg_mode <= 1;
end
else begin
if(~&init_data[idx]) begin
@@ -84,7 +88,10 @@ always@(posedge clk) begin
state <= 0;
rw <= 0;
if(!error) begin
if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
if(rw) begin
{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
flg_present <= 1;
end
rw <= ~rw;
end
end

43
sys/pll_cfg.qip
View File

@@ -1,44 +1,5 @@
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"]
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"]
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"

6
sys/pll_cfg/altera_pll_reconfig_core.v
View File

@@ -16,7 +16,7 @@
module altera_pll_reconfig_core
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter device_family = "Cyclone V",
// MIF Streaming parameters
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
@@ -1883,7 +1883,7 @@ module fpll_dprio_init (
endmodule
module dyn_phase_shift
#(
parameter device_family = "Stratix V"
parameter device_family = "Cyclone V"
) (
input wire clk,
@@ -2112,7 +2112,7 @@ endmodule
module generic_lcell_comb
#(
//parameter
parameter family = "Stratix V",
parameter family = "Cyclone V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (

2
sys/pll_cfg/altera_pll_reconfig_top.v
View File

@@ -16,7 +16,7 @@
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter device_family = "Cyclone V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,

172
sys/pll_cfg.v → sys/pll_cfg/pll_cfg.v
View File

@@ -1,86 +1,86 @@
// megafunction wizard: %Altera PLL Reconfig v17.0%
// GENERATION: XML
// pll_cfg.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_cfg #(
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter reconf_width = 64,
parameter WAIT_FOR_LOCK = 1
) (
input wire mgmt_clk, // mgmt_clk.clk
input wire mgmt_reset, // mgmt_reset.reset
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
input wire mgmt_read, // .read
input wire mgmt_write, // .write
output wire [31:0] mgmt_readdata, // .readdata
input wire [5:0] mgmt_address, // .address
input wire [31:0] mgmt_writedata, // .writedata
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
.reconf_width (reconf_width),
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
) pll_cfg_inst (
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
.mgmt_read (mgmt_read), // .read
.mgmt_write (mgmt_write), // .write
.mgmt_readdata (mgmt_readdata), // .readdata
.mgmt_address (mgmt_address), // .address
.mgmt_writedata (mgmt_writedata), // .writedata
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.mgmt_byteenable (4'b0000) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : pll_cfg.vo
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
// megafunction wizard: %Altera PLL Reconfig v17.0%
// GENERATION: XML
// pll_cfg.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_cfg #(
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter reconf_width = 64,
parameter WAIT_FOR_LOCK = 1
) (
input wire mgmt_clk, // mgmt_clk.clk
input wire mgmt_reset, // mgmt_reset.reset
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
input wire mgmt_read, // .read
input wire mgmt_write, // .write
output wire [31:0] mgmt_readdata, // .readdata
input wire [5:0] mgmt_address, // .address
input wire [31:0] mgmt_writedata, // .writedata
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
.reconf_width (reconf_width),
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
) pll_cfg_inst (
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
.mgmt_read (mgmt_read), // .read
.mgmt_write (mgmt_write), // .write
.mgmt_readdata (mgmt_readdata), // .readdata
.mgmt_address (mgmt_address), // .address
.mgmt_writedata (mgmt_writedata), // .writedata
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.mgmt_byteenable (4'b0000) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : pll_cfg.vo
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v

494
sys/pll_cfg_hdmi.v → sys/pll_cfg/pll_cfg_hdmi.v
View File

@@ -1280,497 +1280,3 @@ module pll_cfg_hdmi
assign phase_done = reconfig_from_pll [17];
endmodule
module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0]counter;
reg local_reset;
reg usr_mode_init_wait;
initial
begin
local_reset = 1'b1;
counter = 0;
usr_mode_init_wait = 0;
end
always @(posedge clk)
begin
if (mgmt_reset)
begin
counter <= 0;
end
else
begin
if (!usr_mode_init_wait)
begin
if (counter == INITIAL_WAIT_VALUE)
begin
local_reset <= 0;
usr_mode_init_wait <= 1'b1;
counter <= 0;
end
else
begin
counter <= counter + 1'b1;
end
end
else
begin
if (counter == RESET_COUNTER_VALUE)
local_reset <= 0;
else
counter <= counter + 1'b1;
end
end
end
assign reset = mgmt_reset | local_reset;
assign init_reset = local_reset;
endmodule
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_ser_shift_load,
input dprio_init_done,
// Inputs from avmm master
input [ 5:0] avmm_dprio_address,
input avmm_dprio_read,
input [ 1:0] avmm_dprio_byteen,
input avmm_dprio_write,
input [15:0] avmm_dprio_writedata,
input avmm_atpgmode,
input avmm_mdio_dis,
input avmm_scanen,
input avmm_ser_shift_load,
// Outputs to fpll
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output atpgmode,
output mdio_dis,
output scanen,
output ser_shift_load
);
assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address;
assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read;
assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen;
assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write;
assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata;
assign atpgmode = init_atpgmode;
assign scanen = init_scanen;
assign mdio_dis = init_mdio_dis;
assign ser_shift_load = init_ser_shift_load ;
endmodule
module fpll_dprio_init (
input clk,
input reset_n,
input locked,
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output reg atpgmode,
output reg mdio_dis,
output reg scanen,
output reg ser_shift_load,
output reg dprio_init_done
);
reg [1:0] rst_n = 2'b00;
reg [6:0] count = 7'd0;
reg init_done_forever;
// Internal versions of control signals
wire int_mdio_dis;
wire int_ser_shift_load;
wire int_dprio_init_done;
wire int_atpgmode/*synthesis keep*/;
wire int_scanen/*synthesis keep*/;
assign dprio_address = count[6] ? 5'b0 : count[5:0] ;
assign dprio_byteen = 2'b11; // always enabled
assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles
assign dprio_read = 1'b0;
assign dprio_writedata = 16'd0;
assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1;
assign int_mdio_dis = count[6] ? ~count[2] : 1'b1;
assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0)
: 1'b1;
assign int_atpgmode = 0;
assign int_scanen = 0;
initial begin
count = 7'd0;
init_done_forever = 0;
mdio_dis = 1'b1;
ser_shift_load = 1'b1;
dprio_init_done = 1'b0;
scanen = 1'b0;
atpgmode = 1'b0;
end
// reset synch.
always @(posedge clk or negedge reset_n)
if(!reset_n) rst_n <= 2'b00;
else rst_n <= {rst_n[0],1'b1};
// counter
always @(posedge clk)
begin
if (!rst_n[1])
init_done_forever <= 1'b0;
else
begin
if (count[6] && &count[1:0])
init_done_forever <= 1'b1;
end
end
always @(posedge clk or negedge rst_n[1])
begin
if(!rst_n[1])
begin
count <= 7'd0;
end
else if(~int_dprio_init_done)
begin
count <= count + 7'd1;
end
else
begin
count <= count;
end
end
// outputs
always @(posedge clk) begin
mdio_dis <= int_mdio_dis;
ser_shift_load <= int_ser_shift_load;
dprio_init_done <= int_dprio_init_done;
atpgmode <= int_atpgmode;
scanen <= int_scanen;
end
endmodule
module dyn_phase_shift
#(
parameter device_family = "Stratix V"
) (
input wire clk,
input wire reset,
input wire phase_done,
input wire pll_start_valid,
input wire dps_changed,
input wire dprio_write_done,
input wire [15:0] usr_num_shifts,
input wire [4:0] usr_cnt_sel,
input wire usr_up_dn,
input wire locked,
//output
output wire dps_done,
output reg phase_en,
output wire up_dn,
output wire dps_changed_valid,
output wire [4:0] cnt_sel);
reg first_phase_shift_d;
reg first_phase_shift_q;
reg [15:0] phase_en_counter;
reg [3:0] dps_current_state;
reg [3:0] dps_next_state;
localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5;
localparam PHASE_EN_WAIT_COUNTER = 5'd1;
reg [15:0] shifts_done_counter;
reg phase_done_final;
wire gnd /*synthesis keep*/;
//fsm
//always block controlling the state regs
always @(posedge clk)
begin
if (reset)
begin
dps_current_state <= DPS_DONE;
end
else
begin
dps_current_state <= dps_next_state;
end
end
//the combinational part. assigning the next state
//this turns on the phase_done_final signal when phase_done does this:
//_____ ______
// |______|
always @(*)
begin
phase_done_final = 0;
first_phase_shift_d = 0;
phase_en = 0;
dps_next_state = DPS_DONE;
case (dps_current_state)
DPS_START:
begin
phase_en = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
DPS_WAIT_PHASE_EN:
begin
phase_en = 1'b1;
if (first_phase_shift_q)
begin
first_phase_shift_d = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
else
begin
if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
dps_next_state = DPS_WAIT_PHASE_DONE;
else dps_next_state = DPS_WAIT_PHASE_EN;
end
end
DPS_WAIT_PHASE_DONE:
begin
if (!phase_done | !locked)
begin
dps_next_state = DPS_WAIT_PHASE_DONE;
end
else
begin
if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
begin
dps_next_state = DPS_START;
phase_done_final = 1'b1;
end
else
begin
dps_next_state = DPS_DONE;
end
end
end
DPS_DONE:
begin
phase_done_final = 0;
if (dps_changed)
dps_next_state = DPS_CHANGED;
else dps_next_state = DPS_DONE;
end
DPS_CHANGED:
begin
if (pll_start_valid)
dps_next_state = DPS_WAIT_DPRIO_WRITING;
else
dps_next_state = DPS_CHANGED;
end
DPS_WAIT_DPRIO_WRITING:
begin
if (dprio_write_done)
dps_next_state = DPS_START;
else
dps_next_state = DPS_WAIT_DPRIO_WRITING;
end
default: dps_next_state = 4'bxxxx;
endcase
end
always @(posedge clk)
begin
if (dps_current_state == DPS_WAIT_PHASE_DONE)
phase_en_counter <= 0;
else if (dps_current_state == DPS_WAIT_PHASE_EN)
phase_en_counter <= phase_en_counter + 1'b1;
if (reset)
begin
phase_en_counter <= 0;
shifts_done_counter <= 1'b1;
first_phase_shift_q <= 1;
end
else
begin
if (first_phase_shift_d)
first_phase_shift_q <= 0;
if (dps_done)
begin
shifts_done_counter <= 1'b1;
end
else
begin
if (phase_done_final & (dps_next_state!= DPS_DONE))
shifts_done_counter <= shifts_done_counter + 1'b1;
else
shifts_done_counter <= shifts_done_counter;
end
end
end
assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
assign up_dn = usr_up_dn;
assign gnd = 1'b0;
//cnt select luts (5)
generic_lcell_comb lcell_cnt_sel_0 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[0]));
defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_cnt_sel_0.dont_touch = "on";
defparam lcell_cnt_sel_0.family = device_family;
generic_lcell_comb lcell_cnt_sel_1 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[1]));
defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_cnt_sel_1.dont_touch = "on";
defparam lcell_cnt_sel_1.family = device_family;
generic_lcell_comb lcell_cnt_sel_2 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[2]));
defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam lcell_cnt_sel_2.dont_touch = "on";
defparam lcell_cnt_sel_2.family = device_family;
generic_lcell_comb lcell_cnt_sel_3 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[3]));
defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
defparam lcell_cnt_sel_3.dont_touch = "on";
defparam lcell_cnt_sel_3.family = device_family;
generic_lcell_comb lcell_cnt_sel_4 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[4]));
defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
defparam lcell_cnt_sel_4.dont_touch = "on";
defparam lcell_cnt_sel_4.family = device_family;
endmodule
module generic_lcell_comb
#(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (family == "Stratix V")
begin
stratixv_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V")
begin
arriav_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V GZ")
begin
arriavgz_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Cyclone V")
begin
cyclonev_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule

5
sys/pll_q13.qip
View File

@@ -1,7 +1,4 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg_hdmi.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]

1
sys/pll_q17.qip
View File

@@ -2,4 +2,3 @@ set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg_hdmi.v ]

7
sys/sys.tcl
View File

@@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# I2C LEDS/BUTTONS
#============================================================

6
sys/sys_top.sdc
View File

@@ -25,6 +25,7 @@ set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -from [get_ports {VGA_EN}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
@@ -34,6 +35,7 @@ set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_false_path -to {hdmi_width[*] hdmi_height[*]}
set_false_path -to {deb_* btn_en btn_up}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
@@ -58,6 +60,7 @@ set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
set_false_path -from {aflt_* acx* acy* areset* arc*}
set_false_path -from {arx* ary*}
set_false_path -from {vs_line*}
set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en}
set_false_path -from {ascal|o_ihsize*}
set_false_path -from {ascal|o_ivsize*}
@@ -70,4 +73,5 @@ set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
set_false_path -from {mcp23009|sd_cd}
set_false_path -from {mcp23009|flg_*}
set_false_path -to {sysmem|fpga_interfaces|clocks_resets*}

840
sys/sys_top.v
View File

File diff suppressed because it is too large Load Diff

9
sys/vga_out.sv
View File

@@ -7,13 +7,15 @@ module vga_out
input hsync,
input vsync,
input csync,
input de,
input [23:0] din,
output [23:0] dout,
output reg hsync_o,
output reg vsync_o,
output reg csync_o
output reg csync_o,
output reg de_o
);
wire [7:0] red = din[23:16];
@@ -35,8 +37,8 @@ always @(posedge clk) begin
reg [18:0] y_1b, pb_1b, pr_1b;
reg [18:0] y_2, pb_2, pr_2;
reg [23:0] din1, din2;
reg hsync2, vsync2, csync2;
reg hsync1, vsync1, csync1;
reg hsync2, vsync2, csync2, de2;
reg hsync1, vsync1, csync1, de1;
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
@@ -61,6 +63,7 @@ always @(posedge clk) begin
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
de_o <= de2; de2 <= de1; de1 <= de;
rgb <= din2; din2 <= din1; din1 <= din;
end

13
sys/video_cleaner.sv
View File

@@ -26,6 +26,10 @@ module video_cleaner
//optional de
input DE_in,
//optional interlace support
input interlace,
input f1,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
@@ -56,14 +60,19 @@ always @(posedge clk_vid) begin
HBlank_out <= hbl;
VGA_HS <= hs;
if(~VGA_HS & hs) VGA_VS <= vs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
DE_out <= DE_in;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
if (interlace & f1) begin
VGA_VS <= vs;
VBlank_out <= vbl;
end else begin
if(~VGA_HS & hs) VGA_VS <= vs;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
end

33
sys/video_freak.sv
View File

@@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
wire [23:0] mul_res;
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
wire [11:0] wideres = mul_res[11:0] + hsize;
always @(posedge CLK_VIDEO) begin
reg [11:0] oheight,htarget,wres;
reg [11:0] oheight,htarget,wres,hinteger,wideres;
reg [12:0] arxf,aryf;
reg [3:0] cnt;
reg narrow;
@@ -264,7 +262,8 @@ always @(posedge CLK_VIDEO) begin
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
7: if(mul_res <= HDMI_WIDTH) begin
cnt <= 10;
hinteger = mul_res[11:0];
cnt <= 12;
end
8: begin
@@ -285,9 +284,21 @@ always @(posedge CLK_VIDEO) begin
// [2] 1920 / 640 * 640 -> 1920
// [3] 1920 / 512 * 512 -> 1536
10: begin
narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres;
10: begin
hinteger <= mul_res[11:0];
mul_arg1 <= vsize;
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
mul_start <= 1;
end
11: begin
oheight <= mul_res[11:0];
end
12: begin
wideres <= hinteger + hsize;
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
wres <= hinteger == htarget ? hinteger : wideres;
end
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
@@ -299,11 +310,11 @@ always @(posedge CLK_VIDEO) begin
// to target width, meaning it is not optimal for source aspect ratio.
// otherwise it is set to narrow width that is optimal.
11: begin
13: begin
case(SCALE)
2: arxf <= {1'b1, mul_res[11:0]};
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
2: arxf <= {1'b1, hinteger};
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
4: arxf <= {1'b1, narrow ? hinteger : wres};
default: arxf <= {1'b1, div_num[11:0]};
endcase
aryf <= {1'b1, oheight};

15
sys/yc_out.sv
View File

@@ -36,13 +36,15 @@ module yc_out
input hsync,
input vsync,
input csync,
input de,
input [23:0] din,
output [23:0] dout,
output reg hsync_o,
output reg vsync_o,
output reg csync_o
output reg csync_o,
output reg de_o
);
wire [7:0] red = din[23:16];
@@ -61,6 +63,7 @@ typedef struct {
logic hsync;
logic vsync;
logic csync;
logic de;
} phase_t;
localparam MAX_PHASES = 7'd8;
@@ -211,11 +214,11 @@ always_ff @(posedge clk) begin
end
// Adjust sync timing correctly
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync;
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync;
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync;
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync;
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync;
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de;
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de;
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de;
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de;
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de;
phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;