From f6ecb2d30ab8b652cbd18d31e75d183b46791bbd Mon Sep 17 00:00:00 2001 From: birdybro Date: Sat, 27 Jul 2024 11:27:49 -0600 Subject: [PATCH] Update Sys --- SlugCross.sv | 2 + sys/arcade_video.v | 5 + sys/ascal.vhd | 13 + sys/hps_io.sv | 2 +- sys/mcp23009.sv | 17 +- sys/pll_cfg.qip | 43 +- sys/pll_cfg/altera_pll_reconfig_core.v | 6 +- sys/pll_cfg/altera_pll_reconfig_top.v | 2 +- sys/{ => pll_cfg}/pll_cfg.v | 172 ++--- sys/{ => pll_cfg}/pll_cfg_hdmi.v | 494 --------------- sys/pll_q13.qip | 5 +- sys/pll_q17.qip | 1 - sys/sys.tcl | 7 - sys/sys_top.sdc | 6 +- sys/sys_top.v | 840 +++++++++++++------------ sys/vga_out.sv | 9 +- sys/video_cleaner.sv | 13 +- sys/video_freak.sv | 33 +- sys/yc_out.sv | 15 +- 19 files changed, 631 insertions(+), 1054 deletions(-) rename sys/{ => pll_cfg}/pll_cfg.v (98%) rename sys/{ => pll_cfg}/pll_cfg_hdmi.v (77%) diff --git a/SlugCross.sv b/SlugCross.sv index d26ee8f..4b5c728 100644 --- a/SlugCross.sv +++ b/SlugCross.sv @@ -54,6 +54,7 @@ module emu input [11:0] HDMI_WIDTH, input [11:0] HDMI_HEIGHT, output HDMI_FREEZE, + output HDMI_BLACKOUT, `ifdef MISTER_FB // Use framebuffer in DDRAM @@ -185,6 +186,7 @@ assign VGA_F1 = 0; assign VGA_SCALER = 0; assign VGA_DISABLE = 0; assign HDMI_FREEZE = 0; +assign HDMI_BLACKOUT = 0; assign AUDIO_S = 0; assign AUDIO_L = 0; diff --git a/sys/arcade_video.v b/sys/arcade_video.v index f53b136..f41d042 100644 --- a/sys/arcade_video.v +++ b/sys/arcade_video.v @@ -99,6 +99,11 @@ generate assign G = {RGB_fix[7:4],RGB_fix[7:4]}; assign B = {RGB_fix[3:0],RGB_fix[3:0]}; end + else if(DW == 18) begin + assign R = {RGB_fix[17:12],RGB_fix[17:16]}; + assign G = {RGB_fix[11: 6],RGB_fix[11:10]}; + assign B = {RGB_fix[ 5: 0],RGB_fix[ 5: 4]}; + end else begin // 24 assign R = RGB_fix[23:16]; assign G = RGB_fix[15:8]; diff --git a/sys/ascal.vhd b/sys/ascal.vhd index f3e5370..7ac95a6 100644 --- a/sys/ascal.vhd +++ b/sys/ascal.vhd @@ -222,6 +222,7 @@ ENTITY ascal IS vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp vrr : IN std_logic := '0'; vrrmax : IN natural RANGE 0 TO 4095 := 0; + swblack : IN std_logic := '0'; -- will output 3 black frame on every resolution switch -- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp format : IN unsigned(1 DOWNTO 0) :="01"; @@ -510,6 +511,7 @@ ARCHITECTURE rtl OF ascal IS SIGNAL o_divrun : std_logic; SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0); SIGNAL o_vacptl : unsigned(1 DOWNTO 0); + signal o_newres : integer range 0 to 3; ----------------------------------------------------------------------------- FUNCTION shift_ishift(shift : unsigned(0 TO 119); @@ -1890,6 +1892,14 @@ BEGIN o_ivsize<=i_vrsize; -- o_hdown<=i_hdown; -- o_vdown<=i_vdown; -- + + IF (o_newres > 0) then + o_newres <= o_newres- 1; + END IF; + END IF; + + IF (swblack = '1' and o_fb_ena = '0' and (o_ihsize /= i_hrsize or o_ivsize /= i_vrsize)) then + o_newres <= 3; END IF; -- Simultaneous change of input and output framebuffers @@ -2219,6 +2229,9 @@ BEGIN hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8), b=>o_fb_pal_dr(7 DOWNTO 0)); END IF; + IF (o_newres > 0) then + hpix_v := (others => (others => '0')); + END IF; o_hpix0<=hpix_v; o_hpix1<=o_hpix0; o_hpix2<=o_hpix1; diff --git a/sys/hps_io.sv b/sys/hps_io.sv index 45510a9..4fac671 100644 --- a/sys/hps_io.sv +++ b/sys/hps_io.sv @@ -233,7 +233,7 @@ video_calc video_calc ///////////////////////////////////////////////////////// localparam STRLEN = $size(CONF_STR)>>3; -localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1; +localparam MAX_W = $clog2((64 > (STRLEN+2)) ? 64 : (STRLEN+2))-1; wire [7:0] conf_byte; generate diff --git a/sys/mcp23009.sv b/sys/mcp23009.sv index 40cbf5e..82eaf37 100644 --- a/sys/mcp23009.sv +++ b/sys/mcp23009.sv @@ -8,10 +8,12 @@ module mcp23009 output reg [2:0] btn, input [2:0] led, - output reg sd_cd, + output reg flg_sd_cd, + output reg flg_present, + output reg flg_mode, - output scl, - inout sda + output scl, + inout sda ); @@ -50,7 +52,9 @@ always@(posedge clk) begin idx <= 0; btn <= 0; rw <= 0; - sd_cd <= 1; + flg_sd_cd <= 1; + flg_present <= 0; + flg_mode <= 1; end else begin if(~&init_data[idx]) begin @@ -84,7 +88,10 @@ always@(posedge clk) begin state <= 0; rw <= 0; if(!error) begin - if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]}; + if(rw) begin + {flg_sd_cd, flg_mode, btn} <= {dout[7:3]}; + flg_present <= 1; + end rw <= ~rw; end end diff --git a/sys/pll_cfg.qip b/sys/pll_cfg.qip index c3394be..0b560f9 100644 --- a/sys/pll_cfg.qip +++ b/sys/pll_cfg.qip @@ -1,44 +1,5 @@ -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"] -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" - -set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"] +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"] +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"] set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"] set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"] - -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_cfg/altera_pll_reconfig_core.v b/sys/pll_cfg/altera_pll_reconfig_core.v index 4bc1fbb..a9e2b8c 100644 --- a/sys/pll_cfg/altera_pll_reconfig_core.v +++ b/sys/pll_cfg/altera_pll_reconfig_core.v @@ -16,7 +16,7 @@ module altera_pll_reconfig_core #( parameter reconf_width = 64, - parameter device_family = "Stratix V", + parameter device_family = "Cyclone V", // MIF Streaming parameters parameter RECONFIG_ADDR_WIDTH = 6, parameter RECONFIG_DATA_WIDTH = 32, @@ -1883,7 +1883,7 @@ module fpll_dprio_init ( endmodule module dyn_phase_shift #( - parameter device_family = "Stratix V" + parameter device_family = "Cyclone V" ) ( input wire clk, @@ -2112,7 +2112,7 @@ endmodule module generic_lcell_comb #( //parameter - parameter family = "Stratix V", + parameter family = "Cyclone V", parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, parameter dont_touch = "on" ) ( diff --git a/sys/pll_cfg/altera_pll_reconfig_top.v b/sys/pll_cfg/altera_pll_reconfig_top.v index c1bfa8b..843c970 100644 --- a/sys/pll_cfg/altera_pll_reconfig_top.v +++ b/sys/pll_cfg/altera_pll_reconfig_top.v @@ -16,7 +16,7 @@ module altera_pll_reconfig_top #( parameter reconf_width = 64, - parameter device_family = "Stratix V", + parameter device_family = "Cyclone V", parameter RECONFIG_ADDR_WIDTH = 6, parameter RECONFIG_DATA_WIDTH = 32, diff --git a/sys/pll_cfg.v b/sys/pll_cfg/pll_cfg.v similarity index 98% rename from sys/pll_cfg.v rename to sys/pll_cfg/pll_cfg.v index 0adc36f..2a2f078 100644 --- a/sys/pll_cfg.v +++ b/sys/pll_cfg/pll_cfg.v @@ -1,86 +1,86 @@ -// megafunction wizard: %Altera PLL Reconfig v17.0% -// GENERATION: XML -// pll_cfg.v - -// Generated using ACDS version 17.0 598 - -`timescale 1 ps / 1 ps -module pll_cfg #( - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter reconf_width = 64, - parameter WAIT_FOR_LOCK = 1 - ) ( - input wire mgmt_clk, // mgmt_clk.clk - input wire mgmt_reset, // mgmt_reset.reset - output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest - input wire mgmt_read, // .read - input wire mgmt_write, // .write - output wire [31:0] mgmt_readdata, // .readdata - input wire [5:0] mgmt_address, // .address - input wire [31:0] mgmt_writedata, // .writedata - output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll - input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll - ); - - altera_pll_reconfig_top #( - .device_family ("Cyclone V"), - .ENABLE_MIF (0), - .MIF_FILE_NAME ("sys/pll_cfg.mif"), - .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), - .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), - .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), - .reconf_width (reconf_width), - .WAIT_FOR_LOCK (WAIT_FOR_LOCK) - ) pll_cfg_inst ( - .mgmt_clk (mgmt_clk), // mgmt_clk.clk - .mgmt_reset (mgmt_reset), // mgmt_reset.reset - .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest - .mgmt_read (mgmt_read), // .read - .mgmt_write (mgmt_write), // .write - .mgmt_readdata (mgmt_readdata), // .readdata - .mgmt_address (mgmt_address), // .address - .mgmt_writedata (mgmt_writedata), // .writedata - .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll - .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll - .mgmt_byteenable (4'b0000) // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll_cfg.vo -// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v +// megafunction wizard: %Altera PLL Reconfig v17.0% +// GENERATION: XML +// pll_cfg.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll_cfg #( + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter reconf_width = 64, + parameter WAIT_FOR_LOCK = 1 + ) ( + input wire mgmt_clk, // mgmt_clk.clk + input wire mgmt_reset, // mgmt_reset.reset + output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest + input wire mgmt_read, // .read + input wire mgmt_write, // .write + output wire [31:0] mgmt_readdata, // .readdata + input wire [5:0] mgmt_address, // .address + input wire [31:0] mgmt_writedata, // .writedata + output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll + ); + + altera_pll_reconfig_top #( + .device_family ("Cyclone V"), + .ENABLE_MIF (0), + .MIF_FILE_NAME ("sys/pll_cfg.mif"), + .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), + .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), + .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), + .reconf_width (reconf_width), + .WAIT_FOR_LOCK (WAIT_FOR_LOCK) + ) pll_cfg_inst ( + .mgmt_clk (mgmt_clk), // mgmt_clk.clk + .mgmt_reset (mgmt_reset), // mgmt_reset.reset + .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest + .mgmt_read (mgmt_read), // .read + .mgmt_write (mgmt_write), // .write + .mgmt_readdata (mgmt_readdata), // .readdata + .mgmt_address (mgmt_address), // .address + .mgmt_writedata (mgmt_writedata), // .writedata + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll + .mgmt_byteenable (4'b0000) // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll_cfg.vo +// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v diff --git a/sys/pll_cfg_hdmi.v b/sys/pll_cfg/pll_cfg_hdmi.v similarity index 77% rename from sys/pll_cfg_hdmi.v rename to sys/pll_cfg/pll_cfg_hdmi.v index 1f86ed2..1912c2a 100644 --- a/sys/pll_cfg_hdmi.v +++ b/sys/pll_cfg/pll_cfg_hdmi.v @@ -1280,497 +1280,3 @@ module pll_cfg_hdmi assign phase_done = reconfig_from_pll [17]; endmodule -module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); - - localparam RESET_COUNTER_VALUE = 3'd2; - localparam INITIAL_WAIT_VALUE = 9'd340; - reg [9:0]counter; - reg local_reset; - reg usr_mode_init_wait; - initial - begin - local_reset = 1'b1; - counter = 0; - usr_mode_init_wait = 0; - end - - always @(posedge clk) - begin - if (mgmt_reset) - begin - counter <= 0; - end - else - begin - if (!usr_mode_init_wait) - begin - if (counter == INITIAL_WAIT_VALUE) - begin - local_reset <= 0; - usr_mode_init_wait <= 1'b1; - counter <= 0; - end - else - begin - counter <= counter + 1'b1; - end - end - else - begin - if (counter == RESET_COUNTER_VALUE) - local_reset <= 0; - else - counter <= counter + 1'b1; - end - end - end - assign reset = mgmt_reset | local_reset; - assign init_reset = local_reset; -endmodule - -module dprio_mux ( - // Inputs from init block - input [ 5:0] init_dprio_address, - input init_dprio_read, - input [ 1:0] init_dprio_byteen, - input init_dprio_write, - input [15:0] init_dprio_writedata, - - input init_atpgmode, - input init_mdio_dis, - input init_scanen, - input init_ser_shift_load, - input dprio_init_done, - - // Inputs from avmm master - input [ 5:0] avmm_dprio_address, - input avmm_dprio_read, - input [ 1:0] avmm_dprio_byteen, - input avmm_dprio_write, - input [15:0] avmm_dprio_writedata, - - input avmm_atpgmode, - input avmm_mdio_dis, - input avmm_scanen, - input avmm_ser_shift_load, - - // Outputs to fpll - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output atpgmode, - output mdio_dis, - output scanen, - output ser_shift_load -); - - assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; - assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; - assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; - assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; - assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; - - assign atpgmode = init_atpgmode; - assign scanen = init_scanen; - assign mdio_dis = init_mdio_dis; - assign ser_shift_load = init_ser_shift_load ; -endmodule -module fpll_dprio_init ( - input clk, - input reset_n, - input locked, - - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output reg atpgmode, - output reg mdio_dis, - output reg scanen, - output reg ser_shift_load, - output reg dprio_init_done -); - - reg [1:0] rst_n = 2'b00; - reg [6:0] count = 7'd0; - reg init_done_forever; - - // Internal versions of control signals - wire int_mdio_dis; - wire int_ser_shift_load; - wire int_dprio_init_done; - wire int_atpgmode/*synthesis keep*/; - wire int_scanen/*synthesis keep*/; - - - assign dprio_address = count[6] ? 5'b0 : count[5:0] ; - assign dprio_byteen = 2'b11; // always enabled - assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles - assign dprio_read = 1'b0; - assign dprio_writedata = 16'd0; - - assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; - assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; - assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) - : 1'b1; - assign int_atpgmode = 0; - assign int_scanen = 0; - - initial begin - count = 7'd0; - init_done_forever = 0; - mdio_dis = 1'b1; - ser_shift_load = 1'b1; - dprio_init_done = 1'b0; - scanen = 1'b0; - atpgmode = 1'b0; - end - - // reset synch. - always @(posedge clk or negedge reset_n) - if(!reset_n) rst_n <= 2'b00; - else rst_n <= {rst_n[0],1'b1}; - - // counter - always @(posedge clk) - begin - if (!rst_n[1]) - init_done_forever <= 1'b0; - else - begin - if (count[6] && &count[1:0]) - init_done_forever <= 1'b1; - end - end - always @(posedge clk or negedge rst_n[1]) - begin - if(!rst_n[1]) - begin - count <= 7'd0; - end - else if(~int_dprio_init_done) - begin - count <= count + 7'd1; - end - else - begin - count <= count; - end - end - - // outputs - always @(posedge clk) begin - mdio_dis <= int_mdio_dis; - ser_shift_load <= int_ser_shift_load; - dprio_init_done <= int_dprio_init_done; - atpgmode <= int_atpgmode; - scanen <= int_scanen; - end - -endmodule -module dyn_phase_shift -#( - parameter device_family = "Stratix V" -) ( - - input wire clk, - input wire reset, - input wire phase_done, - input wire pll_start_valid, - input wire dps_changed, - input wire dprio_write_done, - input wire [15:0] usr_num_shifts, - input wire [4:0] usr_cnt_sel, - input wire usr_up_dn, - input wire locked, - - //output - output wire dps_done, - output reg phase_en, - output wire up_dn, - output wire dps_changed_valid, - output wire [4:0] cnt_sel); - - - - reg first_phase_shift_d; - reg first_phase_shift_q; - reg [15:0] phase_en_counter; - reg [3:0] dps_current_state; - reg [3:0] dps_next_state; - localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; - localparam PHASE_EN_WAIT_COUNTER = 5'd1; - - reg [15:0] shifts_done_counter; - reg phase_done_final; - wire gnd /*synthesis keep*/; - - //fsm - //always block controlling the state regs - always @(posedge clk) - begin - if (reset) - begin - dps_current_state <= DPS_DONE; - end - else - begin - dps_current_state <= dps_next_state; - end - end - //the combinational part. assigning the next state - //this turns on the phase_done_final signal when phase_done does this: - //_____ ______ - // |______| - always @(*) - begin - phase_done_final = 0; - first_phase_shift_d = 0; - phase_en = 0; - dps_next_state = DPS_DONE; - case (dps_current_state) - DPS_START: - begin - phase_en = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - DPS_WAIT_PHASE_EN: - begin - phase_en = 1'b1; - if (first_phase_shift_q) - begin - first_phase_shift_d = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - else - begin - if (phase_en_counter == PHASE_EN_WAIT_COUNTER) - dps_next_state = DPS_WAIT_PHASE_DONE; - else dps_next_state = DPS_WAIT_PHASE_EN; - end - end - DPS_WAIT_PHASE_DONE: - begin - if (!phase_done | !locked) - begin - dps_next_state = DPS_WAIT_PHASE_DONE; - end - else - begin - if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) - begin - dps_next_state = DPS_START; - phase_done_final = 1'b1; - end - else - begin - dps_next_state = DPS_DONE; - end - - end - end - DPS_DONE: - begin - phase_done_final = 0; - if (dps_changed) - dps_next_state = DPS_CHANGED; - else dps_next_state = DPS_DONE; - - end - DPS_CHANGED: - begin - if (pll_start_valid) - dps_next_state = DPS_WAIT_DPRIO_WRITING; - else - dps_next_state = DPS_CHANGED; - end - DPS_WAIT_DPRIO_WRITING: - begin - if (dprio_write_done) - dps_next_state = DPS_START; - else - dps_next_state = DPS_WAIT_DPRIO_WRITING; - end - - default: dps_next_state = 4'bxxxx; - endcase - - - end - - always @(posedge clk) - begin - - - if (dps_current_state == DPS_WAIT_PHASE_DONE) - phase_en_counter <= 0; - else if (dps_current_state == DPS_WAIT_PHASE_EN) - phase_en_counter <= phase_en_counter + 1'b1; - - if (reset) - begin - phase_en_counter <= 0; - shifts_done_counter <= 1'b1; - first_phase_shift_q <= 1; - end - else - begin - if (first_phase_shift_d) - first_phase_shift_q <= 0; - if (dps_done) - begin - shifts_done_counter <= 1'b1; - end - else - begin - if (phase_done_final & (dps_next_state!= DPS_DONE)) - shifts_done_counter <= shifts_done_counter + 1'b1; - else - shifts_done_counter <= shifts_done_counter; - end - end - end - - assign dps_changed_valid = (dps_current_state == DPS_CHANGED); - assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); - assign up_dn = usr_up_dn; - assign gnd = 1'b0; - - //cnt select luts (5) - generic_lcell_comb lcell_cnt_sel_0 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[0])); - defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_cnt_sel_0.dont_touch = "on"; - defparam lcell_cnt_sel_0.family = device_family; - generic_lcell_comb lcell_cnt_sel_1 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[1])); - defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_cnt_sel_1.dont_touch = "on"; - defparam lcell_cnt_sel_1.family = device_family; - generic_lcell_comb lcell_cnt_sel_2 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[2])); - defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; - defparam lcell_cnt_sel_2.dont_touch = "on"; - defparam lcell_cnt_sel_2.family = device_family; - generic_lcell_comb lcell_cnt_sel_3 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[3])); - defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; - defparam lcell_cnt_sel_3.dont_touch = "on"; - defparam lcell_cnt_sel_3.family = device_family; - generic_lcell_comb lcell_cnt_sel_4 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[4])); - defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; - defparam lcell_cnt_sel_4.dont_touch = "on"; - defparam lcell_cnt_sel_4.family = device_family; - - -endmodule - -module generic_lcell_comb -#( - //parameter - parameter family = "Stratix V", - parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, - parameter dont_touch = "on" -) ( - - input dataa, - input datab, - input datac, - input datad, - input datae, - input dataf, - - output combout -); - - generate - if (family == "Stratix V") - begin - stratixv_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V") - begin - arriav_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V GZ") - begin - arriavgz_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Cyclone V") - begin - cyclonev_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - endgenerate -endmodule diff --git a/sys/pll_q13.qip b/sys/pll_q13.qip index a1fd9d3..78e7e40 100644 --- a/sys/pll_q13.qip +++ b/sys/pll_q13.qip @@ -1,7 +1,4 @@ set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg_hdmi.v ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] diff --git a/sys/pll_q17.qip b/sys/pll_q17.qip index 573302c..85cc84b 100644 --- a/sys/pll_q17.qip +++ b/sys/pll_q17.qip @@ -2,4 +2,3 @@ set_global_assignment -name QIP_FILE rtl/pll.qip set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg_hdmi.v ] diff --git a/sys/sys.tcl b/sys/sys.tcl index ce83683..93b6247 100644 --- a/sys/sys.tcl +++ b/sys/sys.tcl @@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK set_location_assignment PIN_AC4 -to ADC_SDI set_location_assignment PIN_AD4 -to ADC_SDO -#============================================================ -# ARDUINO -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] - #============================================================ # I2C LEDS/BUTTONS #============================================================ diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 0d8763f..ac21334 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -25,6 +25,7 @@ set_false_path -from [get_ports {KEY*}] set_false_path -from [get_ports {BTN_*}] set_false_path -to [get_ports {LED_*}] set_false_path -to [get_ports {VGA_*}] +set_false_path -from [get_ports {VGA_EN}] set_false_path -to [get_ports {AUDIO_SPDIF}] set_false_path -to [get_ports {AUDIO_L}] set_false_path -to [get_ports {AUDIO_R}] @@ -34,6 +35,7 @@ set_false_path -from {cfg[*]} set_false_path -from {VSET[*]} set_false_path -to {wcalc[*] hcalc[*]} set_false_path -to {hdmi_width[*] hdmi_height[*]} +set_false_path -to {deb_* btn_en btn_up} set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2 set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1 @@ -58,6 +60,7 @@ set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} set_false_path -from {aflt_* acx* acy* areset* arc*} set_false_path -from {arx* ary*} set_false_path -from {vs_line*} +set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en} set_false_path -from {ascal|o_ihsize*} set_false_path -from {ascal|o_ivsize*} @@ -70,4 +73,5 @@ set_false_path -from {ascal|o_htotal* ascal|o_vtotal*} set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*} set_false_path -from {ascal|o_hsize* ascal|o_vsize*} -set_false_path -from {mcp23009|sd_cd} +set_false_path -from {mcp23009|flg_*} +set_false_path -to {sysmem|fpga_interfaces|clocks_resets*} diff --git a/sys/sys_top.v b/sys/sys_top.v index 9cc92a1..c21cc48 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -72,7 +72,7 @@ module sys_top output [5:0] VGA_R, output [5:0] VGA_G, output [5:0] VGA_B, - inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive) + inout VGA_HS, output VGA_VS, input VGA_EN, // active low @@ -125,27 +125,22 @@ module sys_top ); ////////////////////// Secondary SD /////////////////////////////////// -wire SD_CS, SD_CLK, SD_MOSI; +wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD; `ifndef MISTER_DUAL_SDRAM - wire sd_miso = SW[3] | SDIO_DAT[0]; + assign SD_CD = mcp_en ? mcp_sdcd : SDCD_SPDIF; + assign SD_MISO = SD_CD | (mcp_en ? SD_SPI_MISO : (VGA_EN | SDIO_DAT[0])); + assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ; + assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK; + assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI; + assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ}; `else - wire sd_miso = 1; + assign SD_CD = mcp_sdcd; + assign SD_MISO = mcp_sdcd | SD_SPI_MISO; + assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; + assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; + assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; `endif -wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO; - -`ifndef MISTER_DUAL_SDRAM - assign SDIO_DAT[2:1]= 2'bZZ; - assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS; - assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK; - assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI; - assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS; -`else - assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; -`endif - -assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; -assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; ////////////////////// LEDs/Buttons /////////////////////////////////// @@ -157,36 +152,59 @@ wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); wire led_u = ~led_user; wire led_locked; -`ifndef MISTER_DUAL_SDRAM - assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0; - assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0; - assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0; -`endif - -//LEDs on main board +//LEDs on de10-nano board assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); -wire btn_r, btn_o, btn_u; -`ifdef MISTER_DUAL_SDRAM - assign {btn_r,btn_o,btn_u} = SW[3] ? {mcp_btn[1],mcp_btn[2],mcp_btn[0]} : ~{SDRAM2_DQ[9],SDRAM2_DQ[13],SDRAM2_DQ[11]}; -`else - assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; -`endif - wire [2:0] mcp_btn; wire mcp_sdcd; +wire mcp_en; +wire mcp_mode; mcp23009 mcp23009 ( .clk(FPGA_CLK2_50), .btn(mcp_btn), .led({led_p, led_d, led_u}), - .sd_cd(mcp_sdcd), + .flg_sd_cd(mcp_sdcd), + .flg_present(mcp_en), + .flg_mode(mcp_mode), .scl(IO_SCL), .sda(IO_SDA) ); +wire io_dig = mcp_en ? mcp_mode : SW[3]; + +`ifndef MISTER_DUAL_SDRAM + wire av_dis = io_dig | VGA_EN; + assign LED_POWER = av_dis ? 1'bZ : mcp_en ? de1 : led_p ? 1'bZ : 1'b0; + assign LED_HDD = av_dis ? 1'bZ : mcp_en ? (sog & ~cs1) : led_d ? 1'bZ : 1'b0; + //assign LED_USER = av_dis ? 1'bZ : mcp_en ? ~vga_tx_clk : led_u ? 1'bZ : 1'b0; + assign LED_USER = VGA_TX_CLK; + wire BTN_DIS = VGA_EN; +`else + wire BTN_RESET = SDRAM2_DQ[9]; + wire BTN_OSD = SDRAM2_DQ[13]; + wire BTN_USER = SDRAM2_DQ[11]; + wire BTN_DIS = SDRAM2_DQ[15]; +`endif + +reg BTN_EN = 0; +reg [25:0] btn_timeout = 0; +initial btn_timeout = 0; +always @(posedge FPGA_CLK2_50) begin + reg btn_up = 0; + reg btn_en = 0; + + btn_up <= BTN_RESET & BTN_OSD & BTN_USER; + if(~reset & btn_up & ~&btn_timeout) btn_timeout <= btn_timeout + 1'd1; + btn_en <= ~BTN_DIS; + BTN_EN <= &btn_timeout & btn_en; +end + +wire btn_r = (mcp_en | SW[3]) ? mcp_btn[1] : (BTN_EN & ~BTN_RESET); +wire btn_o = (mcp_en | SW[3]) ? mcp_btn[2] : (BTN_EN & ~BTN_OSD ); +wire btn_u = (mcp_en | SW[3]) ? mcp_btn[0] : (BTN_EN & ~BTN_USER ); reg btn_user, btn_osd; always @(posedge FPGA_CLK2_50) begin @@ -212,7 +230,7 @@ end // gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) // used to avoid lockups while JTAG loading -wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys}; +wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], io_dig, 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys}; wire [31:0] gp_out; wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future. @@ -226,7 +244,7 @@ wire io_ss1 = gp_outr[19]; wire io_ss2 = gp_outr[20]; `ifndef MISTER_DEBUG_NOHDMI -wire io_osd_hdmi = io_ss1 & ~io_ss0; + wire io_osd_hdmi = io_ss1 & ~io_ss0; `endif wire io_fpga = ~io_ss1 & io_ss0; @@ -267,14 +285,14 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp reg [15:0] cfg; - reg cfg_set = 0; -wire vga_fb = cfg[12] | vga_force_scaler; `ifdef MISTER_DEBUG_NOHDMI -wire direct_video = 1; + wire vga_fb = 0; + wire direct_video = 1; `else -wire direct_video = cfg[10]; + wire vga_fb = cfg[12] | vga_force_scaler; + wire direct_video = cfg[10]; `endif wire audio_96k = cfg[6]; @@ -283,7 +301,11 @@ wire io_osd_vga = io_ss1 & ~io_ss2; `ifndef MISTER_DUAL_SDRAM wire ypbpr_en = cfg[5]; wire sog = cfg[9]; - wire vga_scaler = cfg[2] | vga_force_scaler; + `ifdef MISTER_DEBUG_NOHDMI + wire vga_scaler = 0; + `else + wire vga_scaler = cfg[2] | vga_force_scaler; + `endif `endif reg cfg_custom_t = 0; @@ -309,6 +331,7 @@ reg [11:0] vs_line = 0; reg scaler_out = 0; reg vrr_mode = 0; +wire hdmi_blackout; reg [31:0] aflt_rate = 7056000; reg [39:0] acx = 4258969; @@ -657,120 +680,121 @@ wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd; wire freeze; `ifndef MISTER_DEBUG_NOHDMI -wire clk_hdmi = hdmi_clk_out; + wire clk_hdmi = hdmi_clk_out; -ascal -#( - .RAMBASE(32'h20000000), -`ifdef MISTER_SMALL_VBUF - .RAMSIZE(32'h00200000), -`else - .RAMSIZE(32'h00800000), -`endif -`ifndef MISTER_FB - .PALETTE2("false"), -`else - `ifndef MISTER_FB_PALETTE + ascal + #( + .RAMBASE(32'h20000000), + `ifdef MISTER_SMALL_VBUF + .RAMSIZE(32'h00200000), + `else + .RAMSIZE(32'h00800000), + `endif + `ifndef MISTER_FB .PALETTE2("false"), + `else + `ifndef MISTER_FB_PALETTE + .PALETTE2("false"), + `endif `endif -`endif -`ifdef MISTER_DISABLE_ADAPTIVE - .ADAPTIVE("false"), -`endif -`ifdef MISTER_DOWNSCALE_NN - .DOWNSCALE_NN("true"), -`endif - .FRAC(8), - .N_DW(128), - .N_AW(28) -) -ascal -( - .reset_na (~reset_req), - .run (1), - .freeze (freeze), - - .i_clk (clk_ihdmi), - .i_ce (ce_hpix), - .i_r (hr_out), - .i_g (hg_out), - .i_b (hb_out), - .i_hs (hhs_fix), - .i_vs (hvs_fix), - .i_fl (f1), - .i_de (hde_emu), - .iauto (1), - .himin (0), - .himax (0), - .vimin (0), - .vimax (0), - - .o_clk (clk_hdmi), - .o_ce (scaler_out), - .o_r (hdmi_data[23:16]), - .o_g (hdmi_data[15:8]), - .o_b (hdmi_data[7:0]), - .o_hs (hdmi_hs), - .o_vs (hdmi_vs), - .o_de (hdmi_de), - .o_vbl (hdmi_vbl), - .o_brd (hdmi_brd), - .o_lltune (lltune), - .htotal (WIDTH + HFP + HBP + HS[11:0]), - .hsstart (WIDTH + HFP), - .hsend (WIDTH + HFP + HS[11:0]), - .hdisp (WIDTH), - .hmin (hmin), - .hmax (hmax), - .vtotal (HEIGHT + VFP + VBP + VS[11:0]), - .vsstart (HEIGHT + VFP), - .vsend (HEIGHT + VFP + VS[11:0]), - .vdisp (HEIGHT), - .vmin (vmin), - .vmax (vmax), - .vrr (vrr_mode), - .vrrmax (HEIGHT + VBP + VS[11:0] + 12'd1), - - .mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}), - .poly_clk (clk_sys), - .poly_a (coef_addr), - .poly_dw (coef_data), - .poly_wr (coef_wr), - - .pal1_clk (clk_pal), - .pal1_dw (pal_d), - .pal1_a (pal_a), - .pal1_wr (pal_wr), - -`ifdef MISTER_FB - `ifdef MISTER_FB_PALETTE - .pal2_clk (fb_pal_clk), - .pal2_dw (fb_pal_d), - .pal2_dr (fb_pal_q), - .pal2_a (fb_pal_a), - .pal2_wr (fb_pal_wr), - .pal_n (fb_en), + `ifdef MISTER_DISABLE_ADAPTIVE + .ADAPTIVE("false"), `endif -`endif + `ifdef MISTER_DOWNSCALE_NN + .DOWNSCALE_NN("true"), + `endif + .FRAC(8), + .N_DW(128), + .N_AW(28) + ) + ascal + ( + .reset_na (~reset_req), + .run (1), + .freeze (freeze), - .o_fb_ena (FB_EN), - .o_fb_hsize (FB_WIDTH), - .o_fb_vsize (FB_HEIGHT), - .o_fb_format (FB_FMT), - .o_fb_base (FB_BASE), - .o_fb_stride (FB_STRIDE), + .i_clk (clk_ihdmi), + .i_ce (ce_hpix), + .i_r (hr_out), + .i_g (hg_out), + .i_b (hb_out), + .i_hs (hhs_fix), + .i_vs (hvs_fix), + .i_fl (f1), + .i_de (hde_emu), + .iauto (1), + .himin (0), + .himax (0), + .vimin (0), + .vimax (0), - .avl_clk (clk_100m), - .avl_waitrequest (vbuf_waitrequest), - .avl_readdata (vbuf_readdata), - .avl_readdatavalid(vbuf_readdatavalid), - .avl_burstcount (vbuf_burstcount), - .avl_writedata (vbuf_writedata), - .avl_address (vbuf_address), - .avl_write (vbuf_write), - .avl_read (vbuf_read), - .avl_byteenable (vbuf_byteenable) -); + .o_clk (clk_hdmi), + .o_ce (scaler_out), + .o_r (hdmi_data[23:16]), + .o_g (hdmi_data[15:8]), + .o_b (hdmi_data[7:0]), + .o_hs (hdmi_hs), + .o_vs (hdmi_vs), + .o_de (hdmi_de), + .o_vbl (hdmi_vbl), + .o_brd (hdmi_brd), + .o_lltune (lltune), + .htotal (WIDTH + HFP + HBP + HS[11:0]), + .hsstart (WIDTH + HFP), + .hsend (WIDTH + HFP + HS[11:0]), + .hdisp (WIDTH), + .hmin (hmin), + .hmax (hmax), + .vtotal (HEIGHT + VFP + VBP + VS[11:0]), + .vsstart (HEIGHT + VFP), + .vsend (HEIGHT + VFP + VS[11:0]), + .vdisp (HEIGHT), + .vmin (vmin), + .vmax (vmax), + .vrr (vrr_mode), + .vrrmax (HEIGHT + VBP + VS[11:0] + 12'd1), + .swblack (hdmi_blackout), + + .mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}), + .poly_clk (clk_sys), + .poly_a (coef_addr), + .poly_dw (coef_data), + .poly_wr (coef_wr), + + .pal1_clk (clk_pal), + .pal1_dw (pal_d), + .pal1_a (pal_a), + .pal1_wr (pal_wr), + + `ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + .pal2_clk (fb_pal_clk), + .pal2_dw (fb_pal_d), + .pal2_dr (fb_pal_q), + .pal2_a (fb_pal_a), + .pal2_wr (fb_pal_wr), + .pal_n (fb_en), + `endif + `endif + + .o_fb_ena (FB_EN), + .o_fb_hsize (FB_WIDTH), + .o_fb_vsize (FB_HEIGHT), + .o_fb_format (FB_FMT), + .o_fb_base (FB_BASE), + .o_fb_stride (FB_STRIDE), + + .avl_clk (clk_100m), + .avl_waitrequest (vbuf_waitrequest), + .avl_readdata (vbuf_readdata), + .avl_readdatavalid(vbuf_readdatavalid), + .avl_burstcount (vbuf_burstcount), + .avl_writedata (vbuf_writedata), + .avl_address (vbuf_address), + .avl_write (vbuf_write), + .avl_read (vbuf_read), + .avl_byteenable (vbuf_byteenable) + ); `endif reg LFB_EN = 0; @@ -811,8 +835,8 @@ always @(posedge clk_sys) begin end `ifdef MISTER_FB -reg fb_vbl; -always @(posedge clk_vid) fb_vbl <= hdmi_vbl; + reg fb_vbl; + always @(posedge clk_vid) fb_vbl <= hdmi_vbl; `endif reg ar_md_start; @@ -938,24 +962,24 @@ always @(posedge clk_vid) begin end `ifndef MISTER_DEBUG_NOHDMI -wire [15:0] lltune; -pll_hdmi_adj pll_hdmi_adj -( - .clk(FPGA_CLK1_50), - .reset_na(~reset_req), + wire [15:0] lltune; + pll_hdmi_adj pll_hdmi_adj + ( + .clk(FPGA_CLK1_50), + .reset_na(~reset_req), - .llena(lowlat), - .lltune({16{cfg_done}} & lltune), - .locked(led_locked), - .i_waitrequest(adj_waitrequest), - .i_write(adj_write), - .i_address(adj_address), - .i_writedata(adj_data), - .o_waitrequest(cfg_waitrequest), - .o_write(cfg_write), - .o_address(cfg_address), - .o_writedata(cfg_data) -); + .llena(lowlat), + .lltune({16{cfg_done}} & lltune), + .locked(led_locked), + .i_waitrequest(adj_waitrequest), + .i_write(adj_write), + .i_address(adj_address), + .i_writedata(adj_data), + .o_waitrequest(cfg_waitrequest), + .o_write(cfg_write), + .o_address(cfg_address), + .o_writedata(cfg_data) + ); `else assign led_locked = 0; `endif @@ -981,15 +1005,15 @@ end ///////////////////////// HDMI output ///////////////////////////////// `ifndef MISTER_DEBUG_NOHDMI -wire hdmi_clk_out; -pll_hdmi pll_hdmi -( - .refclk(FPGA_CLK1_50), - .rst(reset_req), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - .outclk_0(hdmi_clk_out) -); + wire hdmi_clk_out; + pll_hdmi pll_hdmi + ( + .refclk(FPGA_CLK1_50), + .rst(reset_req), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + .outclk_0(hdmi_clk_out) + ); `endif //1920x1080@60 PCLK=148.5MHz CEA @@ -1014,62 +1038,59 @@ reg [5:0] adj_address; reg [31:0] adj_data; `ifndef MISTER_DEBUG_NOHDMI -pll_cfg_hdmi pll_cfg_hdmi -( - .mgmt_clk(FPGA_CLK1_50), - .mgmt_reset(reset_req), - .mgmt_waitrequest(cfg_waitrequest), - .mgmt_write(cfg_write), - .mgmt_address(cfg_address), - .mgmt_writedata(cfg_data), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) -); + pll_cfg_hdmi pll_cfg_hdmi + ( + .mgmt_clk(FPGA_CLK1_50), + .mgmt_reset(reset_req), + .mgmt_waitrequest(cfg_waitrequest), + .mgmt_write(cfg_write), + .mgmt_address(cfg_address), + .mgmt_writedata(cfg_data), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); -reg cfg_got = 0; -always @(posedge clk_sys) begin - reg vsd, vsd2; - if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; - else begin - vsd <= HDMI_TX_VS; - vsd2 <= vsd; - if(~vsd2 & vsd) cfg_got <= cfg_set; - end -end - -reg cfg_ready = 0; -always @(posedge FPGA_CLK1_50) begin - reg gotd = 0, gotd2 = 0; - reg custd = 0, custd2 = 0; - reg old_wait = 0; - - gotd <= cfg_got; - gotd2 <= gotd; - - adj_write <= 0; - - custd <= cfg_custom_t; - custd2 <= custd; - if(custd2 != custd & ~gotd) begin - adj_address <= cfg_custom_p1; - adj_data <= cfg_custom_p2; - adj_write <= 1; + reg cfg_got = 0; + always @(posedge clk_sys) begin + reg vsd, vsd2; + if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; + else begin + vsd <= HDMI_TX_VS; + vsd2 <= vsd; + if(~vsd2 & vsd) cfg_got <= cfg_set; + end end - if(~gotd2 & gotd) begin - adj_address <= 2; - adj_data <= 0; - adj_write <= 1; + reg cfg_ready = 0; + always @(posedge FPGA_CLK1_50) begin + reg gotd = 0, gotd2 = 0; + reg custd = 0, custd2 = 0; + reg old_wait = 0; + + gotd <= cfg_got; + gotd2 <= gotd; + + adj_write <= 0; + + custd <= cfg_custom_t; + custd2 <= custd; + if(custd2 != custd & ~gotd) begin + adj_address <= cfg_custom_p1; + adj_data <= cfg_custom_p2; + adj_write <= 1; + end + + if(~gotd2 & gotd) begin + adj_address <= 2; + adj_data <= 0; + adj_write <= 1; + end + + old_wait <= adj_waitrequest; + if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1; end - - old_wait <= adj_waitrequest; - if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1; -end - `else - -wire cfg_ready = 1; - + wire cfg_ready = 1; `endif assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ; @@ -1085,72 +1106,71 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c ); `ifndef MISTER_DEBUG_NOHDMI + `ifdef MISTER_FB + reg dis_output; + always @(posedge clk_hdmi) begin + reg dis; + dis <= fb_force_blank & ~LFB_EN; + dis_output <= dis; + end + `else + wire dis_output = 0; + `endif -`ifdef MISTER_FB -reg dis_output; -always @(posedge clk_hdmi) begin - reg dis; - dis <= fb_force_blank & ~LFB_EN; - dis_output <= dis; -end -`else -wire dis_output = 0; + wire [23:0] hdmi_data_mask; + wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask; + + reg [15:0] shadowmask_data; + reg shadowmask_wr = 0; + + shadowmask HDMI_shadowmask + ( + .clk(clk_hdmi), + .clk_sys(clk_sys), + + .cmd_wr(shadowmask_wr), + .cmd_in(shadowmask_data), + + .din(dis_output ? 24'd0 : hdmi_data), + .hs_in(hdmi_hs), + .vs_in(hdmi_vs), + .de_in(hdmi_de), + .brd_in(hdmi_brd), + .enable(~LFB_EN), + + .dout(hdmi_data_mask), + .hs_out(hdmi_hs_mask), + .vs_out(hdmi_vs_mask), + .de_out(hdmi_de_mask) + ); + + wire [23:0] hdmi_data_osd; + wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd; + + osd hdmi_osd + ( + .clk_sys(clk_sys), + + .io_osd(io_osd_hdmi), + .io_strobe(io_strobe), + .io_din(io_din), + + .clk_video(clk_hdmi), + .din(hdmi_data_mask), + .hs_in(hdmi_hs_mask), + .vs_in(hdmi_vs_mask), + .de_in(hdmi_de_mask), + + .dout(hdmi_data_osd), + .hs_out(hdmi_hs_osd), + .vs_out(hdmi_vs_osd), + .de_out(hdmi_de_osd) + ); + + wire hdmi_cs_osd; + csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); `endif -wire [23:0] hdmi_data_mask; -wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask; - -reg [15:0] shadowmask_data; -reg shadowmask_wr = 0; - -shadowmask HDMI_shadowmask -( - .clk(clk_hdmi), - .clk_sys(clk_sys), - - .cmd_wr(shadowmask_wr), - .cmd_in(shadowmask_data), - - .din(dis_output ? 24'd0 : hdmi_data), - .hs_in(hdmi_hs), - .vs_in(hdmi_vs), - .de_in(hdmi_de), - .brd_in(hdmi_brd), - .enable(~LFB_EN), - - .dout(hdmi_data_mask), - .hs_out(hdmi_hs_mask), - .vs_out(hdmi_vs_mask), - .de_out(hdmi_de_mask) -); - -wire [23:0] hdmi_data_osd; -wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd; - -osd hdmi_osd -( - .clk_sys(clk_sys), - - .io_osd(io_osd_hdmi), - .io_strobe(io_strobe), - .io_din(io_din), - - .clk_video(clk_hdmi), - .din(hdmi_data_mask), - .hs_in(hdmi_hs_mask), - .vs_in(hdmi_vs_mask), - .de_in(hdmi_de_mask), - - .dout(hdmi_data_osd), - .hs_out(hdmi_hs_osd), - .vs_out(hdmi_vs_osd), - .de_out(hdmi_de_osd) -); -`endif - -wire hdmi_cs_osd; -csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); - reg [23:0] dv_data; reg dv_hs, dv_vs, dv_de; wire [23:0] dv_data_osd; @@ -1201,21 +1221,21 @@ always @(posedge clk_vid) begin end `ifndef MISTER_DISABLE_YC -assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs }; + assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs }; `else -assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd }; + assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd }; `endif wire hdmi_tx_clk; `ifndef MISTER_DEBUG_NOHDMI -cyclonev_clkselect hdmi_clk_sw -( - .clkselect({1'b1, ~vga_fb & direct_video}), - .inclk({clk_vid, hdmi_clk_out, 2'b00}), - .outclk(hdmi_tx_clk) -); + cyclonev_clkselect hdmi_clk_sw + ( + .clkselect({1'b1, ~vga_fb & direct_video}), + .inclk({clk_vid, hdmi_clk_out, 2'b00}), + .outclk(hdmi_tx_clk) + ); `else -assign hdmi_tx_clk = clk_vid; + assign hdmi_tx_clk = clk_vid; `endif altddio_out @@ -1260,10 +1280,17 @@ always @(posedge hdmi_tx_clk) begin hdmi_dv_vs <= dv_vs; hdmi_dv_de <= dv_de; +`ifndef MISTER_DEBUG_NOHDMI hs <= (~vga_fb & direct_video) ? hdmi_dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd; vs <= (~vga_fb & direct_video) ? hdmi_dv_vs : hdmi_vs_osd; de <= (~vga_fb & direct_video) ? hdmi_dv_de : hdmi_de_osd; d <= (~vga_fb & direct_video) ? hdmi_dv_data : hdmi_data_osd; +`else + hs <= hdmi_dv_hs; + vs <= hdmi_dv_vs; + de <= hdmi_dv_de; + d <= hdmi_dv_data; +`endif hdmi_out_hs <= hs; hdmi_out_vs <= vs; @@ -1278,6 +1305,46 @@ assign HDMI_TX_D = hdmi_out_d; ///////////////////////// VGA output ////////////////////////////////// +`ifndef MISTER_DUAL_SDRAM + wire vga_tx_clk; + `ifndef MISTER_DEBUG_NOHDMI + cyclonev_clkselect vga_clk_sw + ( + .clkselect({1'b1, ~vga_fb & ~vga_scaler}), + .inclk({clk_vid, hdmi_clk_out, 2'b00}), + .outclk(vga_tx_clk) + ); + `else + assign vga_tx_clk = clk_vid; + `endif + + wire VGA_TX_CLK; + altddio_out + #( + .extend_oe_disable("OFF"), + .intended_device_family("Cyclone V"), + .invert_output("OFF"), + .lpm_hint("UNUSED"), + .lpm_type("altddio_out"), + .oe_reg("UNREGISTERED"), + .power_up_high("OFF"), + .width(1) + ) + vgaclk_ddr + ( + .datain_h(1'b0), + .datain_l(1'b1), + .outclock(vga_tx_clk), + .dataout(VGA_TX_CLK), + .aclr(~mcp_en & ~av_dis), + .aset(1'b0), + .oe(~av_dis & (mcp_en | ~led_u)), + .outclocken(1'b1), + .sclr(1'b0), + .sset(1'b0) + ); +`endif + wire [23:0] vga_data_sl; wire vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl; scanlines #(0) VGA_scanlines @@ -1299,7 +1366,7 @@ scanlines #(0) VGA_scanlines ); wire [23:0] vga_data_osd; -wire vga_vs_osd, vga_hs_osd; +wire vga_vs_osd, vga_hs_osd, vga_de_osd; osd vga_osd ( .clk_sys(clk_sys), @@ -1317,7 +1384,8 @@ osd vga_osd .dout(vga_data_osd), .hs_out(vga_hs_osd), - .vs_out(vga_vs_osd) + .vs_out(vga_vs_osd), + .de_out(vga_de_osd) ); wire vga_cs_osd; @@ -1330,7 +1398,7 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); reg [16:0] ColorBurst_Range; reg [39:0] PhaseInc; wire [23:0] yc_o; - wire yc_hs, yc_vs, yc_cs; + wire yc_hs, yc_vs, yc_cs, yc_de; yc_out yc_out ( @@ -1342,34 +1410,42 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); .hsync(vga_hs_osd), .vsync(vga_vs_osd), .csync(vga_cs_osd), + .de(vga_de_osd), .dout(yc_o), .din(vga_data_osd), .hsync_o(yc_hs), .vsync_o(yc_vs), - .csync_o(yc_cs) + .csync_o(yc_cs), + .de_o(yc_de) ); `endif `ifndef MISTER_DUAL_SDRAM wire VGA_DISABLE; wire [23:0] vgas_o; - wire vgas_hs, vgas_vs, vgas_cs; - vga_out vga_scaler_out - ( - .clk(clk_hdmi), - .ypbpr_en(ypbpr_en), - .hsync(hdmi_hs_osd), - .vsync(hdmi_vs_osd), - .csync(hdmi_cs_osd), - .dout(vgas_o), - .din({24{hdmi_de_osd}} & hdmi_data_osd), - .hsync_o(vgas_hs), - .vsync_o(vgas_vs), - .csync_o(vgas_cs) - ); + wire vgas_hs, vgas_vs, vgas_cs, vgas_de; + `ifndef MISTER_DEBUG_NOHDMI + vga_out vga_scaler_out + ( + .clk(clk_hdmi), + .ypbpr_en(ypbpr_en), + .hsync(hdmi_hs_osd), + .vsync(hdmi_vs_osd), + .csync(hdmi_cs_osd), + .de(hdmi_de_osd), + .dout(vgas_o), + .din({24{hdmi_de_osd}} & hdmi_data_osd), + .hsync_o(vgas_hs), + .vsync_o(vgas_vs), + .csync_o(vgas_cs), + .de_o(vgas_de) + ); + `else + assign {vgas_o, vgas_hs, vgas_vs, vgas_cs, vgas_de} = 0; + `endif wire [23:0] vga_o, vga_o_t; - wire vga_hs, vga_vs, vga_cs, vga_hs_t, vga_vs_t, vga_cs_t; + wire vga_hs, vga_vs, vga_cs, vga_de, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t; vga_out vga_out ( .clk(clk_vid), @@ -1377,26 +1453,35 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); .hsync(vga_hs_osd), .vsync(vga_vs_osd), .csync(vga_cs_osd), + .de(vga_de_osd), .dout(vga_o_t), .din(vga_data_osd), .hsync_o(vga_hs_t), .vsync_o(vga_vs_t), - .csync_o(vga_cs_t) + .csync_o(vga_cs_t), + .de_o(vga_de_t) ); -`ifndef MISTER_DISABLE_YC - assign {vga_o, vga_hs, vga_vs, vga_cs } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } : {yc_o, yc_hs, yc_vs, yc_cs }; -`else - assign {vga_o, vga_hs, vga_vs, vga_cs } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } ; -`endif + `ifndef MISTER_DISABLE_YC + assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } : {yc_o, yc_hs, yc_vs, yc_cs, yc_de }; + `else + assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } ; + `endif - wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs; + wire vgas_en = vga_fb | vga_scaler; - assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : (((vga_fb | vga_scaler) ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en); - assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs)); - assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18]; - assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10]; - assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ; + wire cs1 = vgas_en ? vgas_cs : vga_cs; + wire de1 = vgas_en ? vgas_de : vga_de; + + assign VGA_VS = av_dis ? 1'bZ : ((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en); + assign VGA_HS = av_dis ? 1'bZ : (vgas_en ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs)); + assign VGA_R = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18]; + assign VGA_G = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10]; + assign VGA_B = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ; + + wire [1:0] vga_r = vgas_en ? vgas_o[17:16] : VGA_DISABLE ? 2'd0 : vga_o[17:16]; + wire [1:0] vga_g = vgas_en ? vgas_o[9:8] : VGA_DISABLE ? 2'd0 : vga_o[9:8]; + wire [1:0] vga_b = vgas_en ? vgas_o[1:0] : VGA_DISABLE ? 2'd0 : vga_o[1:0]; `endif reg video_sync = 0; @@ -1426,14 +1511,14 @@ end ///////////////////////// Audio output //////////////////////////////// -assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ; +assign SDCD_SPDIF = (mcp_en & ~spdif) ? 1'b0 : 1'bZ; `ifndef MISTER_DUAL_SDRAM wire analog_l, analog_r; - assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif; - assign AUDIO_R = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S : analog_r; - assign AUDIO_L = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK : analog_l; + assign AUDIO_SPDIF = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_LRCLK : spdif; + assign AUDIO_R = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_I2S : analog_r; + assign AUDIO_L = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_SCLK : analog_l; `endif assign HDMI_MCLK = clk_audio; @@ -1486,43 +1571,43 @@ audio_out audio_out `ifndef MISTER_DISABLE_ALSA -wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; -cyclonev_hps_interface_peripheral_spi_master spi -( - .sclk_out(aspi_sck), - .txd(aspi_mosi), // mosi - .rxd(aspi_miso), // miso + wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; + cyclonev_hps_interface_peripheral_spi_master spi + ( + .sclk_out(aspi_sck), + .txd(aspi_mosi), // mosi + .rxd(aspi_miso), // miso - .ss_0_n(aspi_ss), - .ss_in_n(1) -); + .ss_0_n(aspi_ss), + .ss_in_n(1) + ); -wire [28:0] alsa_address; -wire [63:0] alsa_readdata; -wire alsa_ready; -wire alsa_req; -wire alsa_late; + wire [28:0] alsa_address; + wire [63:0] alsa_readdata; + wire alsa_ready; + wire alsa_req; + wire alsa_late; -wire [15:0] alsa_l, alsa_r; + wire [15:0] alsa_l, alsa_r; -alsa alsa -( - .reset(reset), - .clk(clk_audio), + alsa alsa + ( + .reset(reset), + .clk(clk_audio), - .ram_address(alsa_address), - .ram_data(alsa_readdata), - .ram_req(alsa_req), - .ram_ready(alsa_ready), + .ram_address(alsa_address), + .ram_data(alsa_readdata), + .ram_req(alsa_req), + .ram_ready(alsa_ready), - .spi_ss(aspi_ss), - .spi_sck(aspi_sck), - .spi_mosi(aspi_mosi), - .spi_miso(aspi_miso), + .spi_ss(aspi_ss), + .spi_sck(aspi_sck), + .spi_mosi(aspi_mosi), + .spi_miso(aspi_miso), - .pcm_l(alsa_l), - .pcm_r(alsa_r) -); + .pcm_l(alsa_l), + .pcm_r(alsa_r) + ); `endif //////////////// User I/O (USB 3.0 connector) ///////////////////////// @@ -1651,6 +1736,7 @@ emu emu .HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width), .HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height), .HDMI_FREEZE(freeze), + .HDMI_BLACKOUT(hdmi_blackout), .CLK_VIDEO(clk_vid), .CE_PIXEL(ce_pix), @@ -1723,7 +1809,7 @@ emu emu .SDRAM2_nRAS(SDRAM2_nRAS), .SDRAM2_nCAS(SDRAM2_nCAS), .SDRAM2_CLK(SDRAM2_CLK), - .SDRAM2_EN(SW[3]), + .SDRAM2_EN(io_dig), `endif .BUTTONS(btn), @@ -1733,11 +1819,7 @@ emu emu .SD_MOSI(SD_MOSI), .SD_MISO(SD_MISO), .SD_CS(SD_CS), -`ifdef MISTER_DUAL_SDRAM - .SD_CD(mcp_sdcd), -`else - .SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))), -`endif + .SD_CD(SD_CD), .UART_CTS(uart_rts), .UART_RTS(uart_cts), @@ -1779,24 +1861,6 @@ always @(posedge clk) begin end end -/* -always @(posedge clk) begin - integer pos = 0, neg = 0, cnt = 0; - reg s1,s2; - - s1 <= sync_in; - s2 <= s1; - - if(~s2 & s1) neg <= cnt; - if(s2 & ~s1) pos <= cnt; - - cnt <= cnt + 1; - if(s2 != s1) cnt <= 0; - - pol <= pos > neg; -end -*/ - endmodule ///////////////////////////////////////////////////////////////////// diff --git a/sys/vga_out.sv b/sys/vga_out.sv index c258712..4160635 100644 --- a/sys/vga_out.sv +++ b/sys/vga_out.sv @@ -7,13 +7,15 @@ module vga_out input hsync, input vsync, input csync, + input de, input [23:0] din, output [23:0] dout, output reg hsync_o, output reg vsync_o, - output reg csync_o + output reg csync_o, + output reg de_o ); wire [7:0] red = din[23:16]; @@ -35,8 +37,8 @@ always @(posedge clk) begin reg [18:0] y_1b, pb_1b, pr_1b; reg [18:0] y_2, pb_2, pr_2; reg [23:0] din1, din2; - reg hsync2, vsync2, csync2; - reg hsync1, vsync1, csync1; + reg hsync2, vsync2, csync2, de2; + reg hsync1, vsync1, csync1, de1; y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red; pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0}); @@ -61,6 +63,7 @@ always @(posedge clk) begin hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; csync_o <= csync2; csync2 <= csync1; csync1 <= csync; + de_o <= de2; de2 <= de1; de1 <= de; rgb <= din2; din2 <= din1; din1 <= din; end diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv index b0acbc3..4c057a8 100644 --- a/sys/video_cleaner.sv +++ b/sys/video_cleaner.sv @@ -26,6 +26,10 @@ module video_cleaner //optional de input DE_in, + //optional interlace support + input interlace, + input f1, + // video output signals output reg [7:0] VGA_R, output reg [7:0] VGA_G, @@ -56,14 +60,19 @@ always @(posedge clk_vid) begin HBlank_out <= hbl; VGA_HS <= hs; - if(~VGA_HS & hs) VGA_VS <= vs; VGA_R <= R; VGA_G <= G; VGA_B <= B; DE_out <= DE_in; - if(HBlank_out & ~hbl) VBlank_out <= vbl; + if (interlace & f1) begin + VGA_VS <= vs; + VBlank_out <= vbl; + end else begin + if(~VGA_HS & hs) VGA_VS <= vs; + if(HBlank_out & ~hbl) VBlank_out <= vbl; + end end end diff --git a/sys/video_freak.sv b/sys/video_freak.sv index 4fe143b..65375cd 100644 --- a/sys/video_freak.sv +++ b/sys/video_freak.sv @@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2; wire [23:0] mul_res; sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); -wire [11:0] wideres = mul_res[11:0] + hsize; - always @(posedge CLK_VIDEO) begin - reg [11:0] oheight,htarget,wres; + reg [11:0] oheight,htarget,wres,hinteger,wideres; reg [12:0] arxf,aryf; reg [3:0] cnt; reg narrow; @@ -264,7 +262,8 @@ always @(posedge CLK_VIDEO) begin // [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024 7: if(mul_res <= HDMI_WIDTH) begin - cnt <= 10; + hinteger = mul_res[11:0]; + cnt <= 12; end 8: begin @@ -285,9 +284,21 @@ always @(posedge CLK_VIDEO) begin // [2] 1920 / 640 * 640 -> 1920 // [3] 1920 / 512 * 512 -> 1536 - 10: begin - narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH); - wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres; + 10: begin + hinteger <= mul_res[11:0]; + mul_arg1 <= vsize; + mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; + mul_start <= 1; + end + + 11: begin + oheight <= mul_res[11:0]; + end + + 12: begin + wideres <= hinteger + hsize; + narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH); + wres <= hinteger == htarget ? hinteger : wideres; end // [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true // [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true @@ -299,11 +310,11 @@ always @(posedge CLK_VIDEO) begin // to target width, meaning it is not optimal for source aspect ratio. // otherwise it is set to narrow width that is optimal. - 11: begin + 13: begin case(SCALE) - 2: arxf <= {1'b1, mul_res[11:0]}; - 3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres}; - 4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres}; + 2: arxf <= {1'b1, hinteger}; + 3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres}; + 4: arxf <= {1'b1, narrow ? hinteger : wres}; default: arxf <= {1'b1, div_num[11:0]}; endcase aryf <= {1'b1, oheight}; diff --git a/sys/yc_out.sv b/sys/yc_out.sv index 2e9a24e..984fc37 100644 --- a/sys/yc_out.sv +++ b/sys/yc_out.sv @@ -36,13 +36,15 @@ module yc_out input hsync, input vsync, input csync, + input de, input [23:0] din, output [23:0] dout, output reg hsync_o, output reg vsync_o, - output reg csync_o + output reg csync_o, + output reg de_o ); wire [7:0] red = din[23:16]; @@ -61,6 +63,7 @@ typedef struct { logic hsync; logic vsync; logic csync; + logic de; } phase_t; localparam MAX_PHASES = 7'd8; @@ -211,11 +214,11 @@ always_ff @(posedge clk) begin end // Adjust sync timing correctly - phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; - phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; - phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; - phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; - hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; + phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de; + phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de; + phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de; + phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de; + hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de; phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;