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https://github.com/MiSTer-devel/SMS_MiSTer.git
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26247dd359
Technically, `Clk’event and clk = ‘1’` can result in non-`0` triggers (e.g. `1`, `U`, `H`, `X`, `Z`, `W`, etc...), whereas `rising_edge(clk)` does not.
514 lines
20 KiB
VHDL
514 lines
20 KiB
VHDL
--
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-- Controller.vhd
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-- The core controller module of VM2413
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--
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-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
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-- All rights reserved.
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--
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-- Redistribution and use of this source code or any derivative works, are
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-- permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. Redistributions may not be sold, nor may they be used in a commercial
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-- product or activity without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- [Description]
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--
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-- The Controller is the beginning module of the OPLL slot calculation.
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-- It manages register accesses from I/O and sends proper voice parameters
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-- to the succeding PhaseGenerator and EnvelopeGenerator modules.
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-- The one cycle of the Controller consists of 4 stages as follows.
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--
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-- 1st stage:
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-- * Prepare to read the register value for the current slot from RegisterMemory.
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-- * Prepare to read the voice parameter for the current slot from VoiceMemory.
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-- * Prepare to read the user-voice data from VoiceMemory.
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--
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-- 2nd stage:
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-- * Wait for RegisterMemory and VoiceMemory
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--
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-- 3rd clock stage:
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-- * Update register value if wr='1' and addr points the current OPLL channel.
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-- * Update voice parameter if wr='1' and addr points the voice parameter area.
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-- * Write register value to RegisterMemory.
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-- * Write voice parameter to VoiceMemory.
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--
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-- 4th stage:
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-- * Send voice and register parameters to PhaseGenerator and EnvelopeGenerator.
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-- * Increment the number of the current slot.
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--
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-- Each stage is completed in one clock. Thus the Controller traverses all 18 opll
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-- slots in 72 clocks.
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--
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--
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-- modified by t.hara
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.vm2413.all;
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entity controller is port (
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clk : in std_logic;
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reset : in std_logic;
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clkena : in std_logic;
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slot : in std_logic_vector( 4 downto 0 );
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stage : in std_logic_vector( 1 downto 0 );
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wr : in std_logic;
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addr : in std_logic_vector( 7 downto 0 );
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data : in std_logic_vector( 7 downto 0 );
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-- output parameters for phasegenerator and envelopegenerator
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am : out am_type;
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pm : out pm_type;
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wf : out wf_type;
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ml : out ml_type;
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tl : out db_type;
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fb : out fb_type;
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ar : out ar_type;
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dr : out dr_type;
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sl : out sl_type;
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rr : out rr_type;
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blk : out blk_type;
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fnum : out fnum_type;
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rks : out rks_type;
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key : out std_logic;
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rhythm : out std_logic
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-- slot_out : out slot_id
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);
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end controller;
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architecture rtl of controller is
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component registermemory
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port (
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clk : in std_logic;
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reset : in std_logic;
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addr : in std_logic_vector( 3 downto 0 );
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wr : in std_logic;
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idata : in std_logic_vector( 23 downto 0 );
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odata : out std_logic_vector( 23 downto 0 )
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);
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end component;
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component voicememory port (
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clk : in std_logic;
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reset : in std_logic;
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idata : in voice_type;
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wr : in std_logic;
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rwaddr : in voice_id_type;
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roaddr : in voice_id_type;
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odata : out voice_type;
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rodata : out voice_type );
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end component;
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-- the array which caches instrument number of each channel.
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type inst_array is array (ch_type'range) of integer range 0 to 15;
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signal inst_cache : inst_array;
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type kl_array is array (0 to 15) of std_logic_vector(5 downto 0);
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constant kl_table : kl_array := (
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"000000", "011000", "100000", "100101",
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"101000", "101011", "101101", "101111",
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"110000", "110010", "110011", "110100",
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"110101", "110110", "110111", "111000"
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); -- 0.75db/step, 6db/oct
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-- signals for the read-only access ports of voicememory module.
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signal slot_voice_addr : voice_id_type;
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signal slot_voice_data : voice_type;
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-- signals for the read-write access ports of voicememory module.
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signal user_voice_wr : std_logic;
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signal user_voice_addr : voice_id_type;
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signal user_voice_rdata : voice_type;
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signal user_voice_wdata : voice_type;
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-- signals for the registermemory module.
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signal regs_wr : std_logic;
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signal regs_addr : std_logic_vector( 3 downto 0 );
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signal regs_rdata : std_logic_vector( 23 downto 0 );
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signal regs_wdata : std_logic_vector( 23 downto 0 );
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signal rflag : std_logic_vector( 7 downto 0 );
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signal w_channel : std_logic_vector( 3 downto 0 );
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-- signal w_is_carrier : std_logic;
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begin -- rtl
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-- レジスタ設定値を保持するためのメモリ
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u_register_memory : RegisterMemory
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port map (
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clk => clk,
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reset => reset,
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addr => regs_addr,
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wr => regs_wr,
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idata => regs_wdata,
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odata => regs_rdata
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);
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vmem : voicememory port map (
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clk, reset, user_voice_wdata, user_voice_wr, user_voice_addr, slot_voice_addr,
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user_voice_rdata, slot_voice_data );
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-- レジスタアドレスラッチ (第１ステージ)
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process( reset, clk )
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begin
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if( reset = '1' )then
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regs_addr <= (others => '0');
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elsif rising_edge(clk) then
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if clkena='1' then
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if( stage = "00" )then
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regs_addr <= slot( 4 downto 1 );
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else
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-- hold
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end if;
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end if;
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end if;
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end process;
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-- 現在のスロットの音色データ読み出しアドレスラッチ (第１ステージ)
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process( reset, clk )
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begin
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if( reset = '1' )then
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slot_voice_addr <= 0;
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elsif rising_edge(clk) then
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if clkena='1' then
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if( stage = "00" )then
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if( rflag(5) = '1' and w_channel >= "0110" )then
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-- リズムモードで ch6 以降
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slot_voice_addr <= conv_integer(slot) - 12 + 32;
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else
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slot_voice_addr <= inst_cache(conv_integer(slot)/2) * 2 + conv_integer(slot) mod 2;
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end if;
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else
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-- hold
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end if;
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end if;
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end if;
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end process;
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w_channel <= slot( 4 downto 1 );
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-- w_is_carrier <= slot( 0 );
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process (clk, reset)
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variable kflag : std_logic;
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variable tll : std_logic_vector(db_type'high+1 downto 0);
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variable kll : std_logic_vector(db_type'high+1 downto 0);
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variable regs_tmp : std_logic_vector(23 downto 0);
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variable user_voice_tmp : voice_type;
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variable fb_buf : fb_type;
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variable wf_buf : wf_type;
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variable extra_mode : std_logic;
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variable vindex : voice_id_type;
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begin -- process
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if(reset = '1') then
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key <= '0';
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rhythm <= '0';
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tll := (others=>'0');
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kll := (others=>'0');
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kflag := '0';
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rflag <= (others=>'0');
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user_voice_wr <= '0';
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user_voice_addr <= 0;
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regs_wr <='0';
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ar <= (others=>'0');
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dr <= (others=>'0');
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sl <= (others=>'0');
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rr <= (others=>'0');
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tl <= (others=>'0');
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fb <= (others=>'0');
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wf <= '0';
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ml <= (others=>'0');
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fnum <= (others=>'0');
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blk <= (others=>'0');
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key <= '0';
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rks <= (others=>'0');
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rhythm <= '0';
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extra_mode := '0';
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vindex := 0;
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elsif rising_edge(clk) then if clkena='1' then
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case stage is
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--------------------------------------------------------------------------
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-- 1st stage (setting up a read request for register and voice memories.)
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--------------------------------------------------------------------------
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when "00" =>
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-- if extra_mode = '0' then
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-- alternately read modulator or carrior.
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vindex := conv_integer(slot) mod 2;
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-- else
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-- if vindex = voice_id_type'high then
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-- vindex:= 0;
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-- else
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-- vindex:= vindex + 1;
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-- end if;
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-- end if;
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user_voice_addr <= vindex;
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regs_wr <= '0';
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user_voice_wr <='0';
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--------------------------------------------------------------------------
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-- 2nd stage (just a wait for register and voice memories.)
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--------------------------------------------------------------------------
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when "01" =>
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null;
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--------------------------------------------------------------------------
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-- 3rd stage (updating a register and voice parameters.)
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--------------------------------------------------------------------------
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when "10" =>
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if wr='1' then
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-- if ( extra_mode = '0' and conv_integer(addr) < 8 ) or
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-- ( extra_mode = '1' and ( conv_integer(addr) - 64 ) / 8 = vindex / 2 ) then
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if( extra_mode = '0' and conv_integer(addr) < 8 )then
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-- update user voice parameter.
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user_voice_tmp := user_voice_rdata;
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case addr(2 downto 1) is
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when "00" =>
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if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
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user_voice_tmp.am := data(7);
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user_voice_tmp.pm := data(6);
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user_voice_tmp.eg := data(5);
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user_voice_tmp.kr := data(4);
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user_voice_tmp.ml := data(3 downto 0);
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user_voice_wr <= '1';
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end if;
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when "01" =>
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if addr(0)='0' and (vindex mod 2 = 0) then
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user_voice_tmp.kl := data(7 downto 6);
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user_voice_tmp.tl := data(5 downto 0);
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user_voice_wr <= '1';
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elsif addr(0)='1' and (vindex mod 2 = 0) then
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user_voice_tmp.wf := data(3);
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user_voice_tmp.fb := data(2 downto 0);
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user_voice_wr <= '1';
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elsif addr(0)='1' and (vindex mod 2 = 1) then
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user_voice_tmp.kl := data(7 downto 6);
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user_voice_tmp.wf := data(4);
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user_voice_wr <= '1';
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end if;
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when "10" =>
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if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
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user_voice_tmp.ar := data(7 downto 4);
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user_voice_tmp.dr := data(3 downto 0);
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user_voice_wr <= '1';
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end if;
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when "11" =>
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if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
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user_voice_tmp.sl := data(7 downto 4);
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user_voice_tmp.rr := data(3 downto 0);
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user_voice_wr <= '1';
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end if;
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end case;
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user_voice_wdata <= user_voice_tmp;
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elsif conv_integer(addr) = 14 then
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rflag <= data;
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elsif conv_integer(addr) < 16 then
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null;
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elsif conv_integer(addr) <= 63 then
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if( conv_integer(addr(3 downto 0) ) = conv_integer(slot) / 2 ) then
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regs_tmp := regs_rdata;
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case addr( 5 downto 4 ) is
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when "01" => -- 10h～18h の場合（下位 F-Number）
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regs_tmp(7 downto 0) := data; -- F-Number
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regs_wr <= '1';
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when "10" => -- 20h～28h の場合（Sus, Key, Block, F-Number MSB）
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regs_tmp(13) := data(5); -- Sus
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regs_tmp(12) := data(4); -- Key
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regs_tmp(11 downto 9) := data(3 downto 1); -- Block
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regs_tmp(8) := data(0); -- F-Number
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regs_wr <= '1';
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when "11" => -- 30h～38h の場合（Inst, Vol）
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regs_tmp(23 downto 20) := data(7 downto 4); -- Inst
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regs_tmp(19 downto 16) := data(3 downto 0); -- Vol
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regs_wr <='1';
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when others =>
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null;
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end case;
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regs_wdata <= regs_tmp;
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end if;
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elsif conv_integer(addr) = 240 then
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if data(7 downto 0) = "10000000" then
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extra_mode := '1';
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else
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extra_mode := '0';
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end if;
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end if;
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end if;
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--------------------------------------------------------------------------
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-- 4th stage (updating a register and voice parameters.)
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--------------------------------------------------------------------------
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when "11" =>
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-- output slot number (for explicit synchonization with other units).
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-- slot_out <= slot;
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-- updating insturument cache
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inst_cache(conv_integer(slot)/2) <= conv_integer(regs_rdata(23 downto 20));
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rhythm <= rflag(5);
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-- updating rhythm status and key flag
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if rflag(5) = '1' and 12 <= slot then
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case slot is
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when "01100" | "01101" => -- bd
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kflag := rflag(4);
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when "01110" => -- hh
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kflag := rflag(0);
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when "01111" => -- sd
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kflag := rflag(3);
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when "10000" => -- tom
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kflag := rflag(2);
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when "10001" => -- cym
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kflag := rflag(1);
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when others => null;
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end case;
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else
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kflag := '0';
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end if;
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kflag := kflag or regs_rdata(12);
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-- calculate key-scale attenuation amount.
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kll := (("0"&kl_table(conv_integer(regs_rdata(8 downto 5))))
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- ("0"&("111"-regs_rdata(11 downto 9))&"000")) & '0';
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if kll(kll'high) ='1' or slot_voice_data.kl = "00" then
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kll := (others=>'0');
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else
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kll := shr(kll, "11" - slot_voice_data.kl );
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end if;
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-- calculate base total level from volume register value.
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if rflag(5) = '1' and (slot = "01110" or slot = "10000") then -- hh and cym
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tll := ('0' & regs_rdata(23 downto 20) & "000");
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elsif( slot(0) = '0' )then
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tll := ('0' & slot_voice_data.tl & '0'); -- mod
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else
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tll := ('0' & regs_rdata(19 downto 16) & "000"); -- car
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end if;
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tll := tll + kll;
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if tll(tll'high) ='1' then
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tl <= (others=>'1');
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else
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tl <= tll(tl'range);
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end if;
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-- output rks, f-number, block and key-status.
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fnum <= regs_rdata(8 downto 0);
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blk <= regs_rdata(11 downto 9);
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key <= kflag;
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if rflag(5) = '1' and 14 <= slot then
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if slot_voice_data.kr = '1' then
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rks <= "0101";
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else
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rks <= "00" & regs_rdata(11 downto 10);
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end if;
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else
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if slot_voice_data.kr = '1' then
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rks <= regs_rdata(11 downto 9) & regs_rdata(8);
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else
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rks <= "00" & regs_rdata(11 downto 10);
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end if;
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end if;
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-- output voice parameters
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-- note that wf and fb output must keep its value
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-- at least 3 clocks since the operator module will fetch
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-- the wf and fb 2 clocks later of this stage.
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am <= slot_voice_data.am;
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pm <= slot_voice_data.pm;
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ml <= slot_voice_data.ml;
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wf_buf := slot_voice_data.wf;
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fb_buf := slot_voice_data.fb;
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wf <= wf_buf;
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fb <= fb_buf;
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ar <= slot_voice_data.ar;
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dr <= slot_voice_data.dr;
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sl <= slot_voice_data.sl;
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-- output release rate (depends on the sustine and envelope type).
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if( kflag = '1' ) then -- key on
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if slot_voice_data.eg = '1' then
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rr <= "0000";
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else
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rr <= slot_voice_data.rr;
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end if;
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else -- key off
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if (slot(0) = '0') and not ( rflag(5) = '1' and (7 <= conv_integer(slot)/2) ) then
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rr <= "0000";
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elsif regs_rdata(13) = '1' then
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rr <= "0101";
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elsif slot_voice_data.eg = '0' then
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rr <= "0111";
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else
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rr <= slot_voice_data.rr;
|
||
end if;
|
||
end if;
|
||
|
||
end case;
|
||
|
||
end if; end if;
|
||
|
||
end process;
|
||
|
||
end rtl;
|