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Author SHA1 Message Date
sorgelig
77553d9ef4 Eliminate async clocks. 2021-03-06 05:18:35 +08:00
sorgelig
fd7a5cbcf0 sdram: use register in I/O buffer. 2021-03-05 23:56:32 +08:00
sorgelig
2bd6650e4b Update sys. Some fixes and tweaks. 2021-03-05 23:55:44 +08:00
Alexey Melnikov
722aee90bd Merge pull request #1 from MarcelKilgus/fx68k 
Fx68k
 2021-03-05 22:04:21 +08:00
MarcelKilgus
11a4270db8 Update readme.md 2021-03-05 00:56:29 +01:00
Marcel Kilgus
965a0ae9cc Merge upstream again 2021-03-04 21:51:06 +01:00
sorgelig
2bb31ad01e Release 20210228. 2021-02-28 23:03:56 +08:00
sorgelig
dae987e89c Update sys. HV-Integer scale. 2021-02-28 23:03:15 +08:00
MarcelKilgus
8dc3143a14 Update readme.md 2021-02-23 00:15:58 +01:00
Marcel Kilgus
44f7e0b9c3 Update sys. Support for custom AR. 
Tracking upstream changes
 2021-02-22 23:11:23 +01:00
Marcel Kilgus
6477105b68 Fixed commented out fractions 2021-02-22 21:27:50 +01:00
MarcelKilgus
a088394bb5 Merge pull request #2 from CodeDreamer/fx68k 
Unbreak full speed
 2021-02-22 00:16:58 +01:00
sorgelig
75d7259bdf Release 20210206. 2021-02-06 22:06:39 +08:00
sorgelig
c6f19f2eb1 Update sys. Support for custom AR. 2021-02-06 22:05:53 +08:00
Daniele Terdina
cbe86dd05e Unbreak full speed 2021-02-03 00:34:05 -08:00
MarcelKilgus
c706cba6d0 Merge pull request #1 from CodeDreamer/fx68k 
Accurate QL speed emulation.
 2021-01-24 12:06:02 +01:00
Daniele Terdina
fde2624b81 Accurate QL speed emulation. 
Main changes:
1) Improve accuracy of ZX8301 bus contention logic, including adding a wait cycle for writes and reducing the amount of ZX8301 bus access during VBLANK.
2) Add wait states to simulate extra bus access by 68008 for 16 bit ROM access.
3) Reworked IPC communication logic in ZX8302 and added a COMDATA latch.
 2021-01-23 20:57:48 -08:00
Marcel Kilgus
134ce2fa73 Implemented fractional divisions for slower clocks 
Moved IPC to clk_sys clock domain
 2020-09-26 10:14:07 +02:00
Marcel Kilgus
386e2ee53f Fixed MDV timings 2020-09-25 23:55:01 +02:00
Marcel Kilgus
7e5530bac3 Fixed OSD reset, added option to load different OS 2020-09-18 09:20:11 +02:00
Marcel Kilgus
f00aa1d873 Fixed path to MGC ROM code 2020-09-18 09:11:30 +02:00
Marcel Kilgus
70e5f0bd9c Tracking upstream changes (new source structure, updated sys) 2020-09-17 00:15:53 +02:00
sorgelig
3f6839cee7 Release 20200513. 2020-05-13 06:16:30 +08:00
sorgelig
b1f6d7f1ea Update TG68K, fix the slacks. 2020-05-13 06:15:17 +08:00
sorgelig
17acf4a0d3 Update sys. Re-organize the sources. 2020-05-13 05:29:11 +08:00
Marcel Kilgus
2b78e8ec04 Updated fx68k core 2020-01-20 21:57:17 +01:00
Marcel Kilgus
fd4d23d99d Implemented support for virtual SD (or rather .WIN container) files 2020-01-20 16:14:31 +01:00
Marcel Kilgus
6e8d8c391f Implemented 16-bit file mode for SD card emulator 2020-01-19 18:21:40 +01:00
Marcel Kilgus
26fe3b99a3 Support for SDRAM v2 boards 2020-01-15 10:18:33 +01:00
Marcel Kilgus
f84a83f607 Try to emulate original QL timings (memory slowdown and 8-bit bus) 2020-01-07 00:02:06 +01:00
Marcel Kilgus
de1e5bebd3 Changed CPU core from tg68k to fx68k 
Changed bus to DTACK handling, including brand new SDRAM controller
This also fixes timing issues with QL-SD hardware, now works with all CPU speeds
Implemented "MiSTer Gold Card" (basically SuperGoldCard with 68000 instead of 68020) to support booting of the SMSQ/E operating system
 2020-01-06 01:04:38 +01:00
sorgelig
9742d576bc Release 20190928. 2019-09-28 01:57:18 +08:00
sorgelig
ece9bb9a8b Tweaks for direct video. 2019-09-28 01:56:41 +08:00
sorgelig
22c57ec119 Update sys. 2019-09-28 01:26:34 +08:00
sorgelig
73cdfc4292 Release 20190719. 2019-07-19 00:25:10 +08:00
sorgelig
88c4dbf640 Update sys. Support for SDRAM v2. 2019-07-18 22:35:20 +08:00
sorgelig
57495b7f23 Release 20190309. 2019-03-09 06:53:26 +08:00
sorgelig
b1b4f967b7 Update sys. 2019-03-09 06:52:46 +08:00
sorgelig
1bf8fe5610 Release 20180305. 2018-03-05 23:54:12 +08:00
sorgelig
bb5a37b50e Add scandoubler with HQ2x. 2018-03-05 23:52:15 +08:00
sorgelig
c50cfe28d8 Update API. 2018-03-05 21:29:00 +08:00
sorgelig
9395456a63 Release 20171031. 2017-10-31 20:01:21 +08:00
sorgelig
cc08d28412 Initial port. 2017-10-31 20:00:46 +08:00