mirror of
https://github.com/MiSTer-devel/QL_MiSTer.git
synced 2026-04-19 03:04:54 +00:00
Implemented fractional divisions for slower clocks
Moved IPC to clk_sys clock domain
This commit is contained in:
Marcel Kilgus
117
QL.sv
117
QL.sv
@@ -176,7 +176,6 @@ always @(posedge clk_sys) if (reset) ram_cfg <= status[5:4];
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///////////////// CLOCKS ////////////////////////
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wire clk_11m;
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wire clk_sys;
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wire pll_locked;
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@@ -185,106 +184,100 @@ pll pll
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys), // System clock
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.outclk_1(clk_11m), // Clock for 8049 IPC
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.locked(pll_locked)
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);
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// 84Mhz sys_clk
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parameter DIV_BUS_QL = 4'd11; // 84Mhz / 11 = 7.64Mhz
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parameter DIV_BUS_16 = 4'd5; // 84Mhz / 5 = 16.8Mhz
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parameter DIV_BUS_24 = 4'd3; // 84Mhz / 3 = 21.5Mhz
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parameter DIV_BUS_FULL = 4'd2; // 84Mhz / 2 = 42Mhz
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// 84MHz sys_clk
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parameter FRACT_BUS_QL = 17'd11702; // 84MHz * 11702 / 65536 = 14.999MHz
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parameter FRACT_BUS_16 = 17'd24966; // 84MHz * 24966 / 65536 = 31.999MHz
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parameter FRACT_BUS_24 = 17'd37449; // 84MHz * 37449 / 65536 = 48.000MHz
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parameter FRACT_BUS_FULL = 17'h10000; // 84MHz
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parameter DIV_131k = 10'd640; // 84Mhz / 640 = 131250Hz
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parameter DIV_VID = 4'd8; // 84Mhz / 8 = 10.5Mhz
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parameter DIV_SD = 3'd2; // 84Mhz / 2 = 42Mhz (effectively 21Mhz SPI speed)
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parameter FRACT_SD = 17'd19505; // 84MHz * 39010 / 65536 = 50Mhz (effectively 25Mhz SPI speed)
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parameter FRACT_11M = 17'd8582; // 84MHz * 8582 / 65536 = 10.999Mhz
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parameter DIV_131k = 10'd640; // 84MHz / 640 = 131250Hz
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parameter DIV_VID = 4'd8; // 84MHz / 8 = 10.5MHz
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// 94.5Mhz sys_clk
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/*parameter DIV_BUS_QL = 4'd13; // 94.5Mhz / 13 = 7.27Mhz
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parameter DIV_BUS_16 = 4'd6; // 94.5Mhz / 6 = 15.75Mhz
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parameter DIV_BUS_24 = 4'd4; // 94.5Mhz / 4 = 23.625Mhz
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parameter DIV_BUS_FULL = 4'd2; // 94.5Mhz / 2 = 47.25Mhz
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// 94.5MHz sys_clk
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/*parameter FRACT_BUS_QL = 17'd11702; // 94.5MHz * 10403 / 65536 = 15.000MHz
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parameter FRACT_BUS_16 = 17'd24966; // 94.5MHz * 22192 / 65536 = 31.999MHz
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parameter FRACT_BUS_24 = 17'd37449; // 94.5MHz * 33288 / 65536 = 48.000MHz
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parameter FRACT_BUS_FULL = 17'h10000; // 94.5MHz
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parameter DIV_131k = 10'd720; // 94.5Mhz / 720 = 131250Hz
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parameter DIV_VID = 4'd9; // 94.5Mhz / 9 = 10.5Mhz
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parameter DIV_SD = 3'd2; // 94.5Mhz / 2 = 47.25Mhz (effectively 23.625Mhz SPI speed)*/
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parameter FRACT_SD = 17'd19505; // 94.5MHz * 34675 / 65536 = 49.999MHz (effectively 25Mhz SPI speed)
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parameter FRACT_11M = 17'd8582; // 94.5MHz * 7629 / 65536 = 11.001MHz
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parameter DIV_131k = 10'd720; // 94.5MHz / 720 = 131250Hz
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parameter DIV_VID = 4'd9; // 94.5MHz / 9 = 10.5MHz*/
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// 105Mhz sys_clk
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/*parameter DIV_BUS_QL = 4'd14; // 105Mhz / 14 = 7.5Mhz
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parameter DIV_BUS_16 = 4'd7; // 105Mhz / 7 = 15Mhz
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parameter DIV_BUS_24 = 4'd4; // 105Mhz / 4 = 26.25Mhz
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parameter DIV_BUS_FULL = 4'd2; // 105Mhz / 2 = 52.5Mhz
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// 105MHz sys_clk
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/*parameter FRACT_BUS_QL = 17'd11702; // 105MHz * 9362 / 65536 = 14.999MHz
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parameter FRACT_BUS_16 = 17'd24966; // 105MHz * 19973 / 65536 = 32.000MHz
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parameter FRACT_BUS_24 = 17'd37449; // 105MHz * 29959 / 65536 = 47.999MHz
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parameter FRACT_BUS_FULL = 17'h10000; // 105MHz
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parameter DIV_131k = 10'd800; // 105Mhz / 800 = 131250Hz
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parameter DIV_VID = 4'd10; // 105Mhz / 10 = 10.5Mhz
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parameter DIV_SD = 3'd3; // 105Mhz / 3 = 35hz (effectively 17.5Mhz SPI speed)*/
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parameter FRACT_SD = 17'd19505; // 105MHz * 31208 / 65536 = 50.000MHz (effectively 25Mhz SPI speed)
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parameter FRACT_11M = 17'd8582; // 105MHz * 6866 / 65536 = 11.001MHz
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parameter DIV_131k = 10'd800; // 105MHz / 800 = 131250Hz
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parameter DIV_VID = 4'd10; // 105MHz / 10 = 10.5MHz*/
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wire [16:0] fract_bus =
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cpu_speed == 0? FRACT_BUS_QL:
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cpu_speed == 1? FRACT_BUS_16:
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cpu_speed == 2? FRACT_BUS_24:
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FRACT_BUS_FULL;
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reg ce_bus_p, ce_bus_n;
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reg ce_131k; // Supposed to be 131025 Hz for SDRAM refresh and clock update
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reg ce_vid; // 10.5Mhz pixel clock
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reg ce_sd; // ~50 Mhz SD clock
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reg ce_11m;
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always @(negedge clk_sys)
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begin
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reg [3:0] divBus;
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reg bus_pol;
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reg bus_tick;
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reg [15:0] cnt_bus;
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reg [15:0] cnt_sd;
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reg [15:0] cnt_11m;
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reg [9:0] div131k;
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reg [3:0] divVid;
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reg [2:0] divSD;
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if (reset)
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begin
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divBus <= 0;
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bus_pol <= 0;
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cnt_bus <= 0;
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div131k <= 0;
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divVid <= 0;
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divSD <= 0;
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end else begin
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divBus <= divBus + 4'd1;
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div131k<= div131k + 10'd1;
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divVid <= divVid + 4'd1;
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divSD <= divSD + 3'd1;
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end
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ce_bus_p <= divBus == 0;
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case (cpu_speed)
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0: begin
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// Original QL speed
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if (divBus == DIV_BUS_QL - 1) divBus <= 0;
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ce_bus_n <= divBus == DIV_BUS_QL / 2;
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end
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// CPU clock
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{bus_tick, cnt_bus} <= cnt_bus + fract_bus;
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ce_bus_p <= bus_tick && !bus_pol;
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ce_bus_n <= bus_tick && bus_pol;
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bus_pol <= bus_tick ^ bus_pol;
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1: begin
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// Gold Card 16Mhz
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if (divBus == DIV_BUS_16 - 1) divBus <= 0;
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ce_bus_n <= divBus == DIV_BUS_16 / 2;
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end
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2: begin
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// Gold Card 24Mhz
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if (divBus == DIV_BUS_24 - 1) divBus <= 0;
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ce_bus_n <= divBus == DIV_BUS_24 / 2;
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end
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3: begin
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// Full speed
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if (divBus == DIV_BUS_FULL - 1) divBus <= 0;
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ce_bus_n <= divBus == DIV_BUS_FULL / 2;
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end
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endcase
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// SDRAM refresh and clock update
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if (div131k == DIV_131k - 1) div131k <= 0;
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ce_131k <= !div131k;
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// 10.5Mhz pixel clock
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if (divVid == DIV_VID - 1) divVid <= 0;
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ce_vid <= !divVid;
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if (divSD == DIV_SD - 1) divSD <= 0;
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ce_sd <= !divSD;
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// QL-SD clock
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{ce_sd, cnt_sd} <= cnt_sd + FRACT_SD;
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// 11Mhz IPC clock
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{ce_11m, cnt_11m} <= cnt_11m + FRACT_11M;
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end
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//////////////// QL RAM timing ////////////////////
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wire ram_delay_dtack;
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wire rom_delay_dtack;
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ql_timing ql_timing(
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.*,
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@@ -646,7 +639,7 @@ zx8302 zx8302
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.reset ( reset ),
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.reset_mdv ( osd_reset ),
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.clk ( clk_sys ),
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.clk11 ( clk_11m ),
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.ce_11m ( ce_11m ),
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.xint ( qimi_irq ),
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.ipl ( cpu_ipl ),
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10
rtl/ipc.v
10
rtl/ipc.v
@@ -22,7 +22,8 @@
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module ipc (
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input reset,
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input clk11,
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input clk,
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input ce_11m,
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// synchronous serial connection
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output comctrl,
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@@ -49,7 +50,8 @@ wire [63:0] kbd_matrix;
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keyboard keyboard (
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.reset ( reset ),
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.clk ( clk11 ),
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.clk ( clk ),
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.ce_11m ( ce_11m ),
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.ps2_key ( ps2_key ),
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@@ -75,8 +77,8 @@ wire [7:0] t8049_p2_i = { comdata_out && comdata_in, 7'b0000000 };
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assign comdata_out = t8049_p2_o[7];
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t8049_notri #(0) t8049 (
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.xtal_i ( clk11 ),
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.xtal_en_i ( 1'b1 ),
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.xtal_i ( clk ),
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.xtal_en_i ( ce_11m ),
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.reset_n_i ( !reset ),
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.t0_i ( 1'b0 ),
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.t1_i ( 1'b0 ),
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@@ -22,6 +22,7 @@
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module keyboard (
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input clk,
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input ce_11m,
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input reset,
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// ps2 interface
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@@ -59,11 +60,11 @@ wire x_f3 = specialD[9] || js0[0];
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wire x_f4 = specialD[10]|| js0[3];
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wire x_f5 = specialD[11]|| js0[4];
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// divide 11mhz clock down to ~1khz some delay
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wire clk_delay = clk_delay_cnt[9];
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reg [9:0] clk_delay_cnt; // 11mhz/1024
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// Divide 11MHz clock down to ~1khz some delay
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wire clk_delay = clk_delay_cnt[12];
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reg [12:0] clk_delay_cnt; // 11MHz / 8192 = 1.342kHz
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always @(posedge clk)
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clk_delay_cnt <= clk_delay_cnt + 10'd1;
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if (ce_11m) clk_delay_cnt <= clk_delay_cnt + 13'd1;
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// The "main" key of a combined modifier key needs to be delayed. Otherwise
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// the QL will not accept it. E.g. when pressing CTRL-LEFT, the CTRL key needs
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@@ -95,7 +96,7 @@ wire [63:0] special_matrix = {
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2'b00, x_f5, x_f3, x_f2, 1'b0, x_f1, x_f4
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};
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// ================================= leyout =============================
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// ================================= layout =============================
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// F1 ESC 1 2 3 4 5 6 7 8 9 0 - = £ \
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// F2 TAB Q W E R T Y U I O P [ ]
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// F3 CAPS A S D F G H J K L ; ' ENTER
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22
rtl/pll.qip
22
rtl/pll.qip
@@ -35,17 +35,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MjA2MTU3MzMwNw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTE=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTcxNzk4NjgzMw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
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@@ -67,9 +67,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTEuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
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set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NTc1::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@@ -256,10 +256,10 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODMuOTk5OTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTAuOTk5OTk4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
@@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OSw5LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw2LDUsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw0Miw0MiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDQwMDAsOTIzLjk5OTg3MiBNSHosMjA2MTU3MzMwNyxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDIsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE5Ljk5OTk5OSBNSHosMTcxNzk4NjgzMyxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
|
||||
@@ -2,14 +2,13 @@
|
||||
// GENERATION: XML
|
||||
// pll.v
|
||||
|
||||
// Generated using ACDS version 17.0 602
|
||||
// Generated using ACDS version 17.0 595
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll (
|
||||
input wire refclk, // refclk.clk
|
||||
input wire rst, // reset.reset
|
||||
output wire outclk_0, // outclk0.clk
|
||||
output wire outclk_1, // outclk1.clk
|
||||
output wire locked // locked.export
|
||||
);
|
||||
|
||||
@@ -17,7 +16,6 @@ module pll (
|
||||
.refclk (refclk), // refclk.clk
|
||||
.rst (rst), // reset.reset
|
||||
.outclk_0 (outclk_0), // outclk0.clk
|
||||
.outclk_1 (outclk_1), // outclk1.clk
|
||||
.locked (locked) // locked.export
|
||||
);
|
||||
|
||||
@@ -63,7 +61,7 @@ endmodule
|
||||
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
// Retrieval info: <generic name="gui_use_locked" value="true" />
|
||||
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
|
||||
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
|
||||
@@ -10,9 +10,6 @@ module pll_0002(
|
||||
// interface 'outclk0'
|
||||
output wire outclk_0,
|
||||
|
||||
// interface 'outclk1'
|
||||
output wire outclk_1,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked
|
||||
);
|
||||
@@ -21,11 +18,11 @@ module pll_0002(
|
||||
.fractional_vco_multiplier("true"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(2),
|
||||
.output_clock_frequency0("83.999992 MHz"),
|
||||
.number_of_clocks(1),
|
||||
.output_clock_frequency0("84.000000 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("10.999998 MHz"),
|
||||
.output_clock_frequency1("0 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("0 MHz"),
|
||||
@@ -80,7 +77,7 @@ module pll_0002(
|
||||
.pll_subtype("General")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_1, outclk_0}),
|
||||
.outclk ({outclk_0}),
|
||||
.locked (locked),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
module zx8302
|
||||
(
|
||||
input clk,
|
||||
input clk11, // 11 MHz ipc
|
||||
input ce_11m, // 11 MHz ipc
|
||||
input reset,
|
||||
input reset_mdv,
|
||||
|
||||
@@ -179,7 +179,8 @@ wire [1:0] ipc_ipl;
|
||||
|
||||
ipc ipc (
|
||||
.reset ( reset ),
|
||||
.clk11 ( clk11 ),
|
||||
.clk ( clk ),
|
||||
.ce_11m ( ce_11m ),
|
||||
|
||||
.comctrl ( ipc_comctrl ),
|
||||
.comdata_in ( ipc_comdata_in ),
|
||||
|
||||
Reference in New Issue
Block a user