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- corrected uncached instruction fetch timing

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- corrected bios instruction fetch timing
- implement partial cache line fetch for BIOS
This commit is contained in:
Robert Peip
2022-09-26 18:16:23 +02:00
parent eb91f221cc
commit 118bd85644
6 changed files with 66 additions and 41 deletions
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1
PSX.sv
View File

@@ -1010,7 +1010,6 @@ psx
.exe_file_size(exe_file_size),
.exe_stackpointer(exe_stackpointer),
.fastboot(status[16]),
.FASTMEM(0),
.TURBO_MEM(TURBO_MEM),
.TURBO_COMP(TURBO_COMP),
.TURBO_CACHE(TURBO_CACHE),

25
rtl/cpu.vhd
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@@ -30,6 +30,7 @@ entity cpu is
mem_rnw : out std_logic;
mem_isData : out std_logic;
mem_isCache : out std_logic;
mem_oldtagvalids : out std_logic_vector(3 downto 0);
mem_addressInstr : out unsigned(31 downto 0);
mem_addressData : out unsigned(31 downto 0);
mem_reqsize : out unsigned(1 downto 0);
@@ -38,6 +39,7 @@ entity cpu is
mem_dataRead : in std_logic_vector(31 downto 0);
mem_done : in std_logic;
mem_fifofull : in std_logic;
mem_tagvalids : in std_logic_vector(3 downto 0);
cache_wr : in std_logic_vector(3 downto 0);
cache_data : in std_logic_vector(31 downto 0);
@@ -193,6 +195,7 @@ architecture arch of cpu is
signal FetchAddr : unsigned(31 downto 0) := (others => '0');
signal FetchLastAddr : unsigned(31 downto 0) := (others => '0');
signal FetchLastCache : std_logic := '0';
signal FetchLastTagvalids : std_logic_vector(3 downto 0);
signal cacheValueLast : unsigned(31 downto 0) := (others => '0');
signal cacheHitLast : std_logic := '0';
@@ -206,6 +209,7 @@ architecture arch of cpu is
-- wires
signal mem1_request : std_logic := '0';
signal mem1_cacherequest : std_logic := '0';
signal mem1_tagvalids : std_logic_vector(3 downto 0);
signal mem1_address : unsigned(31 downto 0) := (others => '0');
signal PCnext : unsigned(31 downto 0) := (others => '0');
@@ -458,8 +462,9 @@ begin
-- IO
mem_request <= mem1_request or mem1_request_latched or mem4_request when (memoryMuxBusy = '0' or mem_done = '1') else '0';
mem_isCache <= FetchLastCache when (mem1_request_latched = '1') else mem1_cacherequest;
mem_addressInstr <= FetchLastAddr when (mem1_request_latched = '1') else mem1_address;
mem_isCache <= FetchLastCache when (mem1_request_latched = '1') else mem1_cacherequest;
mem_oldtagvalids <= FetchLastTagvalids when (mem1_request_latched = '1') else mem1_tagvalids;
mem_addressInstr <= FetchLastAddr when (mem1_request_latched = '1') else mem1_address;
mem_isData <= mem4_request;
mem_rnw <= mem4_rnw when mem4_request = '1' else '1';
mem_addressData <= mem4_address;
@@ -491,8 +496,9 @@ begin
elsif (ce = '1') then
if (mem1_request = '1') then
FetchLastAddr <= mem1_address;
FetchLastCache <= mem1_cacherequest;
FetchLastAddr <= mem1_address;
FetchLastCache <= mem1_cacherequest;
FetchLastTagvalids <= mem1_tagvalids;
if (mem4_request = '1' or memoryMuxBusy = '1') then
mem1_request_latched <= '1';
end if;
@@ -601,11 +607,8 @@ begin
tag_address_a <= std_logic_vector(writebackInvalidateCacheLine) when (writebackInvalidateCacheEna = '1') else std_logic_vector(FetchLastAddr(11 downto 4));
tag_data_a <= "0000" & std_logic_vector(FetchLastAddr(31 downto 12)) when (writebackInvalidateCacheEna = '1') else
"1000" & std_logic_vector(FetchLastAddr(31 downto 12)) when (FetchLastAddr(3 downto 2) = "11") else
"1100" & std_logic_vector(FetchLastAddr(31 downto 12)) when (FetchLastAddr(3 downto 2) = "10") else
"1110" & std_logic_vector(FetchLastAddr(31 downto 12)) when (FetchLastAddr(3 downto 2) = "01") else
"1111" & std_logic_vector(FetchLastAddr(31 downto 12));
tag_data_a <= "0000" & std_logic_vector(FetchLastAddr(31 downto 12)) when (writebackInvalidateCacheEna = '1') else
mem_tagvalids & std_logic_vector(FetchLastAddr(31 downto 12));
tag_address_b <= std_logic_vector(FetchAddr(11 downto 4));
@@ -658,6 +661,7 @@ begin
mem1_request <= '0';
cacheHitNext <= '0';
mem1_tagvalids <= "0000";
if (mem_done = '1' and memoryMuxStage4 = '0') then
case (to_integer(unsigned(FetchLastAddr(31 downto 29)))) is
@@ -696,6 +700,9 @@ begin
else
mem1_request <= '1';
stallNew1 <= '1';
if (unsigned(tag_q_b(19 downto 0)) = FetchAddr(31 downto 12)) then
mem1_tagvalids <= tag_q_b(23 downto 20);
end if;
end if;
when 5 =>

65
rtl/memorymux.vhd
View File

@@ -21,7 +21,6 @@ entity memorymux is
reset_exe : out std_logic := '0';
fastboot : in std_logic;
NOMEMWAIT : in std_logic;
PATCHSERIAL : in std_logic;
TURBO : in std_logic;
region_in : in std_logic_vector(1 downto 0);
@@ -40,7 +39,8 @@ entity memorymux is
mem_in_request : in std_logic;
mem_in_rnw : in std_logic;
mem_in_isData : in std_logic;
mem_in_isCache : in std_logic;
mem_in_isCache : in std_logic;
mem_in_oldtagvalids : in std_logic_vector(3 downto 0);
mem_in_addressInstr : in unsigned(31 downto 0);
mem_in_addressData : in unsigned(31 downto 0);
mem_in_reqsize : in unsigned(1 downto 0);
@@ -49,6 +49,7 @@ entity memorymux is
mem_dataRead : out std_logic_vector(31 downto 0);
mem_done : out std_logic;
mem_fifofull : out std_logic;
mem_tagvalids : out std_logic_vector(3 downto 0);
bios_memctrl : in unsigned(13 downto 0);
@@ -183,6 +184,7 @@ architecture arch of memorymux is
signal mem_rnw : std_logic;
signal mem_isData : std_logic;
signal mem_isCache : std_logic;
signal mem_oldtagvalids : std_logic_vector(3 downto 0);
signal mem_addressInstr : unsigned(31 downto 0);
signal mem_addressData : unsigned(31 downto 0);
signal mem_reqsize : unsigned(1 downto 0);
@@ -193,6 +195,7 @@ architecture arch of memorymux is
signal mem_save_rnw : std_logic := '0';
signal mem_save_isData : std_logic := '0';
signal mem_save_isCache : std_logic := '0';
signal mem_save_oldtagvalids : std_logic_vector(3 downto 0) := (others => '0');
signal mem_save_addressInstr : unsigned(31 downto 0) := (others => '0');
signal mem_save_addressData : unsigned(31 downto 0) := (others => '0');
signal mem_save_reqsize : unsigned(1 downto 0) := (others => '0');
@@ -208,6 +211,7 @@ architecture arch of memorymux is
signal writeFifo_busy : std_logic;
signal writeFifo_Wr_1 : std_logic;
signal bios_page_open : std_logic;
signal ram_page_open : std_logic;
signal ram_page_addr : unsigned(10 downto 0);
@@ -473,6 +477,7 @@ begin
mem_rnw <= '0' when writeFifo_Empty = '0' else mem_save_rnw when mem_save_request = '1' else mem_in_rnw ;
mem_isData <= '1' when writeFifo_Empty = '0' else mem_save_isData when mem_save_request = '1' else mem_in_isData ;
mem_isCache <= '0' when writeFifo_Empty = '0' else mem_save_isCache when mem_save_request = '1' else mem_in_isCache ;
mem_oldtagvalids <= "0000" when writeFifo_Empty = '0' else mem_save_oldtagvalids when mem_save_request = '1' else mem_in_oldtagvalids;
mem_addressInstr <= unsigned(writeFifo_Dout(63 downto 32)) when writeFifo_Empty = '0' else mem_save_addressInstr when mem_save_request = '1' else mem_in_addressInstr;
mem_addressData <= unsigned(writeFifo_Dout(63 downto 32)) when writeFifo_Empty = '0' else mem_save_addressData when mem_save_request = '1' else mem_in_addressData ;
mem_reqsize <= unsigned(writeFifo_Dout(65 downto 64)) when writeFifo_Empty = '0' else mem_save_reqsize when mem_save_request = '1' else mem_in_reqsize ;
@@ -513,6 +518,7 @@ begin
mem_save_rnw <= '1';
mem_save_isData <= mem_in_isData;
mem_save_isCache <= mem_in_isCache;
mem_save_oldtagvalids <= mem_in_oldtagvalids;
mem_save_addressInstr <= mem_in_addressInstr;
mem_save_addressData <= mem_in_addressData;
mem_save_reqsize <= mem_in_reqsize;
@@ -550,21 +556,36 @@ begin
readram <= '0';
writeram <= '0';
ram_page_open <= '0';
ram_page_open <= '0';
bios_page_open <= '0';
if (mem_isData = '0') then
if (mem_addressInstr(28 downto 0) < 16#800000#) then -- RAM
ram_ena <= '1';
ram_cache <= '0';
ram_cache <= mem_isCache;
ram_rnw <= '1';
ram_Adr <= "00" & std_logic_vector(mem_addressInstr(20 downto 2)) & "00";
state <= IDLE;
readram <= '1';
ram_rotate_bits <= "00";
if (mem_isCache = '1') then
ram_cache <= '1';
if (mem_isCache = '0') then
if (TURBO = '0') then
state <= WAITFORRAMREAD;
waitcnt <= 0;
ram_ena <= '0';
readram <= '0';
end if;
end if;
case (mem_addressInstr(3 downto 2)) is
when "00" => mem_tagvalids <= "1111";
when "01" => mem_tagvalids <= "1110";
when "10" => mem_tagvalids <= "1100";
when "11" => mem_tagvalids <= "1000";
when others => null;
end case;
elsif (mem_addressInstr(28 downto 0) >= 16#1FC00000# and mem_addressInstr(28 downto 0) < 16#1FC80000#) then -- BIOS
ram_ena <= '1';
ram_cache <= '0';
@@ -573,18 +594,21 @@ begin
state <= READBIOS;
addressBIOS_buf <= mem_addressInstr(18 downto 0);
ram_rotate_bits <= "00";
waitcnt <= 16;
if (mem_isCache = '1') then
ram_ena <= '0';
readram <= '0';
state <= WAITFORRAMREAD;
waitcnt <= 87;
ram_cache <= '1';
--if (NOMEMWAIT = '1') then
-- state <= IDLE;
-- readram <= '1';
--end if;
if (bios_page_open = '1') then
waitcnt <= 25;
else
waitcnt <= 26;
bios_page_open <= '1';
end if;
mem_tagvalids <= mem_oldtagvalids;
case (mem_addressInstr(3 downto 2)) is
when "00" => mem_tagvalids(0) <= '1';
when "01" => mem_tagvalids(1) <= '1';
when "10" => mem_tagvalids(2) <= '1';
when "11" => mem_tagvalids(3) <= '1';
when others => null;
end case;
else
report "should never happen" severity failure;
end if;
@@ -736,12 +760,7 @@ begin
mem_dataRead_buf <= data_ram_rotate;
end if;
if (NOMEMWAIT = '1') then
mem_done_buf <= '1';
state <= IDLE;
else
state <= WAITING;
end if;
state <= WAITING;
end if;
when BUSWRITE =>

2
rtl/psx_mister.vhd
View File

@@ -25,7 +25,6 @@ entity psx_mister is
exe_file_size : in unsigned(31 downto 0);
exe_stackpointer : in unsigned(31 downto 0);
fastboot : in std_logic;
FASTMEM : in std_logic;
TURBO_MEM : in std_logic;
TURBO_COMP : in std_logic;
TURBO_CACHE : in std_logic;
@@ -300,7 +299,6 @@ begin
exe_file_size => exe_file_size,
exe_stackpointer => exe_stackpointer,
fastboot => fastboot,
FASTMEM => FASTMEM,
TURBO_MEM => TURBO_MEM,
TURBO_COMP => TURBO_COMP,
TURBO_CACHE => TURBO_CACHE,

13
rtl/psx_top.vhd
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@@ -29,7 +29,6 @@ entity psx_top is
exe_file_size : in unsigned(31 downto 0);
exe_stackpointer : in unsigned(31 downto 0);
fastboot : in std_logic;
FASTMEM : in std_logic;
TURBO_MEM : in std_logic;
TURBO_COMP : in std_logic;
TURBO_CACHE : in std_logic;
@@ -404,6 +403,7 @@ architecture arch of psx_top is
signal mem_rnw : std_logic;
signal mem_isData : std_logic;
signal mem_isCache : std_logic;
signal mem_oldtagvalids : std_logic_vector(3 downto 0);
signal mem_addressInstr : unsigned(31 downto 0);
signal mem_addressData : unsigned(31 downto 0);
signal mem_reqsize : unsigned(1 downto 0);
@@ -412,6 +412,7 @@ architecture arch of psx_top is
signal mem_dataRead : std_logic_vector(31 downto 0);
signal mem_done : std_logic;
signal mem_fifofull : std_logic;
signal mem_tagvalids : std_logic_vector(3 downto 0);
signal ram_next_cpu : std_logic;
@@ -820,7 +821,6 @@ begin
end if;
debugmodeOn <= '0';
if (FASTMEM = '1') then debugmodeOn <= '1'; end if;
if (REPRODUCIBLEGPUTIMING = '1') then debugmodeOn <= '1'; end if;
if (DMABLOCKATONCE = '1') then debugmodeOn <= '1'; end if;
if (noTexture = '1') then debugmodeOn <= '1'; end if;
@@ -1670,7 +1670,6 @@ begin
reset_exe => reset_exe,
fastboot => fastboot,
NOMEMWAIT => FASTMEM,
TURBO => TURBO_MEM,
region_in => biosregion,
PATCHSERIAL => PATCHSERIAL,
@@ -1688,6 +1687,7 @@ begin
mem_in_rnw => mem_rnw,
mem_in_isData => mem_isData,
mem_in_isCache => mem_isCache,
mem_in_oldtagvalids => mem_oldtagvalids,
mem_in_addressInstr => mem_addressInstr,
mem_in_addressData => mem_addressData,
mem_in_reqsize => mem_reqsize,
@@ -1695,7 +1695,8 @@ begin
mem_in_dataWrite => mem_dataWrite,
mem_dataRead => mem_dataRead,
mem_done => mem_done,
mem_fifofull => mem_fifofull,
mem_fifofull => mem_fifofull,
mem_tagvalids => mem_tagvalids,
bios_memctrl => bios_memctrl,
@@ -1826,7 +1827,8 @@ begin
mem_request => mem_request,
mem_rnw => mem_rnw,
mem_isData => mem_isData,
mem_isCache => mem_isCache,
mem_isCache => mem_isCache,
mem_oldtagvalids => mem_oldtagvalids,
mem_addressInstr => mem_addressInstr,
mem_addressData => mem_addressData,
mem_reqsize => mem_reqsize,
@@ -1835,6 +1837,7 @@ begin
mem_dataRead => mem_dataRead,
mem_done => mem_done,
mem_fifofull => mem_fifofull,
mem_tagvalids => mem_tagvalids,
cache_wr => cache_wr,
cache_data => cache_data,

1
sim/system/src/tb/tb.vhd
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@@ -263,7 +263,6 @@ begin
exe_file_size => exe_file_size,
exe_stackpointer => exe_stackpointer,
fastboot => '1',
FASTMEM => '0',
TURBO_MEM => '0',
TURBO_COMP => '0',
TURBO_CACHE => '0',