Aitor Gómez García ebbecd6712 Fix HGC border display by calculating HBlank timing on correct clock domain ...

- Add std_hsyncwidth and vblank_border outputs to HGC module for border detection
- Connect CRTC hsync_width register (R3) to enable dynamic sync width detection
- Update HGC H_SYNCWIDTH to standard value (4'd15) per Hercules specifications
- Extend Peripherals.sv to multiplex HGC timing signals with CGA
- Fix critical bug: HBlank_fixed was calculated only in CGA clock domain
  In HGC mode, it was desynchronized, causing shifted display instead of proper border
- Add HBlank_fixed_hgc calculated on clk_57_272 (HGC clock) for correct timing
- Update LHBL logic to use appropriate HBlank_fixed for each video mode
- Border now properly reduces visible area in HGC mode with correct synchronization

2026-01-23 13:42:58 +01:00

..

8088

feat: update MCL86 to 10_4_2025 release

2025-10-25 12:36:46 +02:00

common

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

KFPC-XT

Fix HGC border display by calculating HBlank timing on correct clock domain

2026-01-23 13:42:58 +01:00

pll

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

pll_system

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

sound

C/MS Audio support and Sound Blaster FM compatibility

2022-11-24 14:21:11 +01:00

uart

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

video

Fix HGC border display by calculating HBlank timing on correct clock domain

2026-01-23 13:42:58 +01:00

hps_ext.v

Ported AO486 floppy controller.

2022-09-24 14:22:09 +09:00

pll_system.qip

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

pll_system.v

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

pll.qip

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

pll.v

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00