mirror of https://github.com/MiSTer-devel/PCXT_MiSTer.git synced 2026-04-19 03:04:47 +00:00

Files

Aitor Gómez García ebbecd6712 Fix HGC border display by calculating HBlank timing on correct clock domain

- Add std_hsyncwidth and vblank_border outputs to HGC module for border detection
- Connect CRTC hsync_width register (R3) to enable dynamic sync width detection
- Update HGC H_SYNCWIDTH to standard value (4'd15) per Hercules specifications
- Extend Peripherals.sv to multiplex HGC timing signals with CGA
- Fix critical bug: HBlank_fixed was calculated only in CGA clock domain
  In HGC mode, it was desynchronized, causing shifted display instead of proper border
- Add HBlank_fixed_hgc calculated on clk_57_272 (HGC clock) for correct timing
- Update LHBL logic to use appropriate HBlank_fixed for each video mode
- Border now properly reduces visible area in HGC mode with correct synchronization

2026-01-23 13:42:58 +01:00

DOC/img

Beta 0.3

2022-05-23 14:32:32 +02:00

HDL

Fix HGC border display by calculating HBlank timing on correct clock domain

2026-01-23 13:42:58 +01:00

TESTBENCH

Fix boot-only splash timing and status[0] VRAM clear

2025-12-27 11:35:15 +01:00

LICENSE

Beta 0.3