Beta 0.7

* 4.77Mhz CPU clock with 33% duty cycle, thanks to @MicroCoreLabs
* Peripheral clock now works at half cpu clock, for correct synchronisation with the 8253 timer, thanks to @kitune-san
* Turbo option is disabled for the moment, requires a redesign of the BIU... for the to-do list

PCXT.sv

@@ -207,7 +207,7 @@ localparam CONF_STR = {
 	"PCXT;;",
 	"-;",
 	"O3,Splash Screen,Yes,No;",
-	"O4,CPU Speed,4.77Mhz,7.16Mhz;",	
+	//"O4,CPU Speed,4.77Mhz,7.16Mhz;",	
 	"-;",
 	"OA,Adlib,On,Invisible;",
 	"-;",
@@ -315,9 +315,10 @@ wire clk_100;
 wire clk_28_636;
 wire clk_25;
 reg clk_14_318 = 1'b0;
-reg clk_7_16 = 1'b0;
+//reg clk_7_16 = 1'b0;
 wire clk_4_77;
 wire clk_cpu;
+wire peripheral_clock;
 
 pll pll
 (
@@ -344,14 +345,15 @@ wire ce_pix;
 assign CLK_VIDEO = clk_28_636;
 assign CE_PIXEL = 1'b1;
 
-assign clk_cpu = status[4] ? clk_7_16 : clk_4_77;
+//assign clk_cpu = status[4] ? clk_7_16 : clk_4_77;
+assign clk_cpu = clk_4_77;
 
 always @(posedge clk_28_636)
 	clk_14_318 <= ~clk_14_318; // 14.318Mhz
 	
 
-always @(posedge clk_14_318)
-	clk_7_16 <= ~clk_7_16; // 7.16Mhz
+//always @(posedge clk_14_318)
+//	clk_7_16 <= ~clk_7_16; // 7.16Mhz
 	
 	
 clk_div3 clk_normal // 4.77MHz
@@ -360,6 +362,10 @@ clk_div3 clk_normal // 4.77MHz
 	.clk_out(clk_4_77)
 );
 
+always @(posedge clk_4_77)
+	peripheral_clock <= ~peripheral_clock; // 2.385Mhz
+
+
 //////////////////////////////////////////////////////////////////
 
 	wire [5:0] r, g, b;	
@@ -462,7 +468,7 @@ clk_div3 clk_normal // 4.77MHz
    CHIPSET u_CHIPSET (
         .clock                              (clk_cpu),
 		  .clk_sys                            (CLK_50M),
-		  .peripheral_clock                   (clk_4_77),
+		  .peripheral_clock                   (peripheral_clock),
 		  
         .reset                              (reset || splashscreen),
         .cpu_address                        (cpu_address),

README.md

@@ -24,8 +24,16 @@ SN76489AN Compatible Implementation in VHDL Copyright (c) 2005, 2006, Arnim Laeu
     * EMS    
     * Others...
 
+* Turbo mode (7.16Mhz)
+
 # ChangeLog
 
+### Beta 0.7
+
+* 4.77Mhz CPU clock with 33% duty cycle, thanks to @MicroCoreLabs
+* Peripheral clock now works at half cpu clock, for correct synchronisation with the 8253 timer, thanks to @kitune-san
+* Turbo option is disabled for the moment, requires a redesign of the BIU... for the to-do list
+
 ### Beta 0.6
 
 * UART module implementation fix, thanks to @kitune-san

SW/splash.txt

@@ -5,7 +5,7 @@
           (_()((_|(_|_)) (_(_())/((_|()\  (_)) )\_____((_)(_(_())  
           |  \/  |(_) __||_   _(_))  ((_) | _ ((/ __\ \/ /|_   _|  
           | |\/| || \__ \  | | / -_)| '_| |  _/| (__ >  <   | |    
-          |_|  |_||_|___/  |_| \___||_|   |_|   \___/_/\_\  |_|  06/06/2022
+          |_|  |_||_|___/  |_| \___||_|   |_|   \___/_/\_\  |_|  07/06/2022
 
 
                         Port by @spark2k06, @naeloob
@@ -15,4 +15,4 @@
                                 Contributors
                                 ------------
 
-                       @JasonA, @gyurco, @kitune-san
+                @JasonA, @gyurco, @kitune-san, @MicroCoreLabs

rtl/KFPC-XT/HDL/Peripherals.sv

@@ -272,7 +272,7 @@ module PERIPHERALS #(
 	jtopl2 jtopl2_inst
 	(
 		.rst(reset),
-		.clk(peripheral_clock),
+		.clk(clock),
 		.cen(clk_en_opl2),
 		.din(internal_data_bus),
 		.dout(jtopl2_dout),
@@ -289,7 +289,7 @@ module PERIPHERALS #(
 	// Tandy sound
 	sn76489_top sn76489
 	(
-		.clock_i(peripheral_clock),
+		.clock_i(clock),
 		.clock_en_i(clk_en_opl2), // 3.579MHz
 		.res_n_i(reset),
 		.ce_n_i(tandy_chip_select_n),

rtl/common/clk_div3.v

@@ -1,20 +1,31 @@
 module clk_div3(clk, clk_out);
  
 input clk;
-output clk_out;
+output reg clk_out;
  
 reg [1:0] pos_count = 2'b00; 
 reg [1:0] neg_count = 2'b00;
 wire [1:0] r_nxt;
  
-always @(posedge clk)
-if (pos_count ==2) pos_count <= 0;
-else pos_count<= pos_count +1;
+//always @(posedge clk)
+//if (pos_count ==2) pos_count <= 0;
+//else pos_count<= pos_count +1;
  
-always @(negedge clk)
-if (neg_count ==2) neg_count <= 0;
-else neg_count<= neg_count +1;
+//always @(negedge clk)
+//if (neg_count ==2) neg_count <= 0;
+//else neg_count<= neg_count +1;
  
-assign clk_out = ((pos_count == 2) | (neg_count == 2));
+//assign clk_out = ((pos_count == 2) | (neg_count == 2));
 
-endmodule
+always @(posedge clk) begin
+	if (pos_count ==2) begin
+		pos_count <= 0;
+		clk_out <= 1'b1;
+	end
+	else begin
+		pos_count<= pos_count +1;
+		clk_out <= 1'b0;
+	end
+end
+
+endmodule