mirror of
https://github.com/MiSTer-devel/PCXT_MiSTer.git
synced 2026-04-26 03:04:30 +00:00
0d026a0fb0
* 4.77Mhz CPU clock with 33% duty cycle, thanks to @MicroCoreLabs * Peripheral clock now works at half cpu clock, for correct synchronisation with the 8253 timer, thanks to @kitune-san * Turbo option is disabled for the moment, requires a redesign of the BIU... for the to-do list
742 lines
20 KiB
Systemverilog
742 lines
20 KiB
Systemverilog
//============================================================================
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [47:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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//assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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//assign SDRAM_CLK = CLK_50M;
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//assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign HDMI_FREEZE = 0;
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assign AUDIO_S = 1;
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assign AUDIO_L = AUDIO_R;
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assign AUDIO_MIX = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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//led fdd_led(clk_cpu, |mgmt_req[7:6], LED_USER);
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//////////////////////////////////////////////////////////////////
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wire [1:0] ar = status[9:8];
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assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
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`include "build_id.v"
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localparam CONF_STR = {
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"PCXT;;",
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"-;",
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"O3,Splash Screen,Yes,No;",
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//"O4,CPU Speed,4.77Mhz,7.16Mhz;",
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"-;",
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"OA,Adlib,On,Invisible;",
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"-;",
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"O12,Video,Color,Green,Amber,B/W;",
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"O89,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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//"O78,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"-;",
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"F1,ROM,Load ROM;",
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"-;",
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"T0,Reset;",
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"R0,Reset and close OSD;",
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"V,v",`BUILD_DATE
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};
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wire forced_scandoubler;
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wire [1:0] buttons;
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wire [31:0] status;
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//wire [10:0] ps2_key;
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//VHD
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wire[ 0:0] usdRd = { vsdRd };
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wire[ 0:0] usdWr = { vsdWr };
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wire usdAck;
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wire[31:0] usdLba[1] = '{ vsdLba };
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wire usdBuffWr;
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wire[ 8:0] usdBuffA;
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wire[ 7:0] usdBuffD[1] = '{ vsdBuffD };
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wire[ 7:0] usdBuffQ;
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wire[63:0] usdImgSz;
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wire[ 0:0] usdImgMtd;
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//Keyboard Ps2
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//wire ps2_kbd_clk_out;
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//wire ps2_kbd_data_out;
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wire ps2_kbd_clk_in;
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wire ps2_kbd_data_in;
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//Mouse PS2
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wire ps2_mouse_clk_out;
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wire ps2_mouse_data_out;
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wire ps2_mouse_clk_in;
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wire ps2_mouse_data_in;
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wire ioctl_download;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_data;
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wire clk_uart;
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wire [21:0] gamma_bus;
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wire adlibhide = status[10];
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hps_io #(.CONF_STR(CONF_STR), .PS2DIV(2000), .PS2WE(1)) hps_io
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(
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.clk_sys(CLK_50M),
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.HPS_BUS(HPS_BUS),
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.EXT_BUS(),
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.gamma_bus(gamma_bus),
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.forced_scandoubler(forced_scandoubler),
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.buttons(buttons),
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.status(status),
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.status_menumask({status[5]}),
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//VHD
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.sd_rd (usdRd),
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.sd_wr (usdWr),
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.sd_ack (usdAck),
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.sd_lba (usdLba),
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.sd_buff_wr (usdBuffWr),
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.sd_buff_addr (usdBuffA),
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.sd_buff_din (usdBuffD),
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.sd_buff_dout (usdBuffQ),
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.img_mounted (usdImgMtd),
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.img_size (usdImgSz),
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.ps2_kbd_clk_in (1'b1),
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.ps2_kbd_data_in (1'b1),
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.ps2_kbd_clk_out (ps2_kbd_clk_in),
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.ps2_kbd_data_out (ps2_kbd_data_in),
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// .ps2_mouse_clk_in (ps2_mouse_clk_out),
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// .ps2_mouse_data_in (ps2_mouse_data_out),
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// .ps2_mouse_clk_out (ps2_mouse_clk_in),
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// .ps2_mouse_data_out (ps2_mouse_data_in),
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//.ps2_key(ps2_key),
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//ioctl
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.ioctl_download(ioctl_download),
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.ioctl_index(ioctl_index),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_data)
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);
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/////////////////////// CLOCKS ///////////////////////////////
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wire clk_sys;
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wire pll_locked;
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wire clk_100;
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wire clk_28_636;
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wire clk_25;
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reg clk_14_318 = 1'b0;
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//reg clk_7_16 = 1'b0;
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wire clk_4_77;
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wire clk_cpu;
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wire peripheral_clock;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_100),
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.outclk_1(clk_28_636),
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.outclk_2(clk_uart),
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.outclk_3(cen_opl2),
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.locked(pll_locked)
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);
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wire reset = RESET | status[0] | buttons[1] | !pll_locked | (status[14] && usdImgMtd) | (ioctl_download && ioctl_index == 0);
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//////////////////////////////////////////////////////////////////
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wire HBlank;
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wire HSync;
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wire VBlank;
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wire VSync;
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wire ce_pix;
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//wire [7:0] video;
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assign CLK_VIDEO = clk_28_636;
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assign CE_PIXEL = 1'b1;
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//assign clk_cpu = status[4] ? clk_7_16 : clk_4_77;
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assign clk_cpu = clk_4_77;
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always @(posedge clk_28_636)
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clk_14_318 <= ~clk_14_318; // 14.318Mhz
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//always @(posedge clk_14_318)
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// clk_7_16 <= ~clk_7_16; // 7.16Mhz
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clk_div3 clk_normal // 4.77MHz
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(
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.clk(clk_14_318),
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.clk_out(clk_4_77)
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);
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always @(posedge clk_4_77)
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peripheral_clock <= ~peripheral_clock; // 2.385Mhz
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//////////////////////////////////////////////////////////////////
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wire [5:0] r, g, b;
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reg [5:0] raux, gaux, baux;
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reg [5:0]red_weight[0:63] = '{ // 0.2126*R
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6'h00, 6'h01, 6'h01, 6'h01, 6'h01, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h04,
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6'h04, 6'h04, 6'h04, 6'h05, 6'h05, 6'h05, 6'h05, 6'h05, 6'h06, 6'h06, 6'h06, 6'h06, 6'h06, 6'h07, 6'h07, 6'h07,
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6'h07, 6'h08, 6'h08, 6'h08, 6'h08, 6'h08, 6'h09, 6'h09, 6'h09, 6'h09, 6'h09, 6'h0a, 6'h0a, 6'h0a, 6'h0a, 6'h0a,
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6'h0b, 6'h0b, 6'h0b, 6'h0b, 6'h0c, 6'h0c, 6'h0c, 6'h0c, 6'h0c, 6'h0d, 6'h0d, 6'h0d, 6'h0d, 6'h0d, 6'h0e, 6'h0e
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};
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reg [5:0]green_weight[0:63] = '{ // 0.7152*G
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6'h00, 6'h01, 6'h02, 6'h03, 6'h03, 6'h04, 6'h05, 6'h06, 6'h06, 6'h07, 6'h08, 6'h08, 6'h09, 6'h0a, 6'h0b, 6'h0b,
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6'h0c, 6'h0d, 6'h0d, 6'h0e, 6'h0f, 6'h10, 6'h10, 6'h11, 6'h12, 6'h12, 6'h13, 6'h14, 6'h15, 6'h15, 6'h16, 6'h17,
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6'h17, 6'h18, 6'h19, 6'h1a, 6'h1a, 6'h1b, 6'h1c, 6'h1c, 6'h1d, 6'h1e, 6'h1f, 6'h1f, 6'h20, 6'h21, 6'h21, 6'h22,
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6'h23, 6'h24, 6'h24, 6'h25, 6'h26, 6'h26, 6'h27, 6'h28, 6'h29, 6'h29, 6'h2a, 6'h2a, 6'h2a, 6'h2b, 6'h2b, 6'h2b
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};
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reg [5:0]blue_weight[0:63] = '{ // 0.0722*B
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6'h00, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h01, 6'h02, 6'h02,
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6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h02, 6'h03, 6'h03, 6'h03, 6'h03,
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6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h03, 6'h04, 6'h04, 6'h04, 6'h04, 6'h04, 6'h04,
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6'h04, 6'h04, 6'h04, 6'h04, 6'h04, 6'h04, 6'h04, 6'h04, 6'h05, 6'h05, 6'h05, 6'h05, 6'h05, 6'h05, 6'h05, 6'h05
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};
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wire de_o;
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reg [24:0] splash_cnt = 0;
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reg [3:0] splash_cnt2 = 0;
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reg splashscreen = 1;
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always @ (posedge clk_14_318) begin
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if (splashscreen) begin
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if (status[3])
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splashscreen <= 0;
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else if(splash_cnt2 == 5) // 5 seconds delay
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splashscreen <= 0;
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else if (splash_cnt == 14318000) begin // 1 second at 14.318Mhz
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splash_cnt2 <= splash_cnt2 + 1;
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splash_cnt <= 0;
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end
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else
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splash_cnt <= splash_cnt + 1;
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end
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end
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//
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// Input F/F PS2_CLK
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//
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logic device_clock_ff;
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logic device_clock;
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always_ff @(negedge clk_cpu, posedge reset)
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begin
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if (reset) begin
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device_clock_ff <= 1'b0;
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device_clock <= 1'b0;
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end
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else begin
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device_clock_ff <= ps2_kbd_clk_in;
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device_clock <= device_clock_ff ;
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end
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end
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//
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// Input F/F PS2_DAT
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//
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logic device_data_ff;
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logic device_data;
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always_ff @(negedge clk_cpu, posedge reset)
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begin
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|
if (reset) begin
|
|
device_data_ff <= 1'b0;
|
|
device_data <= 1'b0;
|
|
end
|
|
else begin
|
|
device_data_ff <= ps2_kbd_data_in;
|
|
device_data <= device_data_ff;
|
|
end
|
|
end
|
|
|
|
wire [7:0] data_bus;
|
|
wire INTA_n;
|
|
wire [19:0] cpu_ad_out;
|
|
reg [19:0] cpu_address;
|
|
wire [7:0] cpu_data_bus;
|
|
wire processor_ready;
|
|
wire interrupt_to_cpu;
|
|
wire address_latch_enable;
|
|
|
|
wire lock_n;
|
|
wire [2:0]processor_status;
|
|
|
|
CHIPSET u_CHIPSET (
|
|
.clock (clk_cpu),
|
|
.clk_sys (CLK_50M),
|
|
.peripheral_clock (peripheral_clock),
|
|
|
|
.reset (reset || splashscreen),
|
|
.cpu_address (cpu_address),
|
|
.cpu_data_bus (cpu_data_bus),
|
|
.processor_status (processor_status),
|
|
.processor_lock_n (lock_n),
|
|
// .processor_transmit_or_receive_n (processor_transmit_or_receive_n),
|
|
.processor_ready (processor_ready),
|
|
.interrupt_to_cpu (interrupt_to_cpu),
|
|
.splashscreen (splashscreen),
|
|
.clk_vga (clk_28_636),
|
|
.enable_cga (1'b1),
|
|
.de_o (VGA_DE),
|
|
.VGA_R (r),
|
|
.VGA_G (g),
|
|
.VGA_B (b),
|
|
.VGA_HSYNC (VGA_HS),
|
|
.VGA_VSYNC (VGA_VS),
|
|
// .address (address),
|
|
.address_ext (0),
|
|
// .address_direction (address_direction),
|
|
.data_bus (data_bus),
|
|
// .data_bus_ext (data_bus_ext),
|
|
// .data_bus_direction (data_bus_direction),
|
|
.address_latch_enable (address_latch_enable),
|
|
// .io_channel_check (),
|
|
.io_channel_ready (1'b1),
|
|
.interrupt_request (0), // use? -> It does not seem to be necessary.
|
|
// .io_read_n (io_read_n),
|
|
.io_read_n_ext (1'b1),
|
|
// .io_read_n_direction (io_read_n_direction),
|
|
// .io_write_n (io_write_n),
|
|
.io_write_n_ext (1'b1),
|
|
// .io_write_n_direction (io_write_n_direction),
|
|
// .memory_read_n (memory_read_n),
|
|
.memory_read_n_ext (1'b1),
|
|
// .memory_read_n_direction (memory_read_n_direction),
|
|
// .memory_write_n (memory_write_n),
|
|
.memory_write_n_ext (1'b1),
|
|
// .memory_write_n_direction (memory_write_n_direction),
|
|
.dma_request (0), // use? -> I don't know if it will ever be necessary, at least not during testing.
|
|
// .dma_acknowledge_n (dma_acknowledge_n),
|
|
// .address_enable_n (address_enable_n),
|
|
// .terminal_count_n (terminal_count_n)
|
|
.speaker_out (speaker_out),
|
|
.ps2_clock (ps2_kbd_clk_in),
|
|
.ps2_data (ps2_kbd_data_in),
|
|
.enable_sdram (0), // -> During the first tests, it shall not be used.
|
|
.clk_en_opl2 (cen_opl2), // clk_en_opl2
|
|
.jtopl2_snd_e (jtopl2_snd_e),
|
|
.adlibhide (adlibhide),
|
|
.tandy_snd_e (tandy_snd_e),
|
|
.ioctl_download (ioctl_download),
|
|
.ioctl_index (ioctl_index),
|
|
.ioctl_wr (ioctl_wr),
|
|
.ioctl_addr (ioctl_addr),
|
|
.ioctl_data (ioctl_data),
|
|
|
|
.clk_uart (clk_uart),
|
|
.uart_rx (uart_rx),
|
|
.uart_tx (uart_tx),
|
|
.uart_cts_n (uart_cts),
|
|
.uart_dcd_n (uart_dcd),
|
|
.uart_dsr_n (uart_dsr),
|
|
.uart_rts_n (uart_rts),
|
|
.uart_dtr_n (uart_dtr)
|
|
);
|
|
|
|
wire [15:0] jtopl2_snd_e;
|
|
wire [16:0]sndmix = (({jtopl2_snd_e[15], jtopl2_snd_e}) << 2) + (speaker_out << 15) + (tandy_snd_e << 8); // signed mixer
|
|
|
|
assign AUDIO_R = sndmix >> 1;
|
|
|
|
i8088 B1(
|
|
.CORE_CLK(clk_100),
|
|
.CLK(clk_cpu),
|
|
|
|
.RESET(reset || splashscreen),
|
|
.READY(processor_ready),
|
|
.NMI(1'b0),
|
|
.INTR(interrupt_to_cpu),
|
|
|
|
.ad_out(cpu_ad_out),
|
|
.dout(cpu_data_bus),
|
|
.din(data_bus),
|
|
|
|
.lock_n(lock_n),
|
|
.s6_3_mux(s6_3_mux),
|
|
.s2_s0_out(processor_status),
|
|
.SEGMENT(SEGMENT)
|
|
);
|
|
|
|
/// UART
|
|
|
|
|
|
assign USER_OUT = {1'b1, 1'b1, uart_dtr, 1'b1, uart_rts, uart_tx, 1'b1};
|
|
|
|
//
|
|
// Pin | USB Name | |Signal
|
|
// ----+----------+---+-------------
|
|
// 0 | D+ | I |RX
|
|
// 1 | D- | O |TX
|
|
// 2 | TX- | O |RTS
|
|
// 3 | GND_d | I |CTS
|
|
// 4 | RX+ | O |DTR
|
|
// 5 | RX- | I |DSR
|
|
// 6 | TX+ | I |DCD
|
|
//
|
|
|
|
wire uart_tx, uart_rts, uart_dtr;
|
|
|
|
wire uart_rx = USER_IN[0];
|
|
wire uart_cts = USER_IN[3];
|
|
wire uart_dsr = USER_IN[5];
|
|
wire uart_dcd = USER_IN[6];
|
|
|
|
always @(posedge clk_cpu) begin
|
|
if (address_latch_enable)
|
|
cpu_address <= cpu_ad_out;
|
|
else
|
|
cpu_address <= cpu_address;
|
|
end
|
|
|
|
/*
|
|
wire [1:0] scale = status[8:7];
|
|
assign VGA_SL = scale;
|
|
wire freeze_sync;
|
|
video_mixer #(640, 1) mixer
|
|
(
|
|
.*,
|
|
.hq2x(scale),
|
|
.scandoubler (scale || forced_scandoubler),
|
|
.R({raux, 2'b0}),
|
|
.G({gaux, 2'b0}),
|
|
.B({baux, 2'b0})
|
|
);
|
|
*/
|
|
|
|
always @ (status[2:1], r, g, b) begin
|
|
case(status[2:1])
|
|
// Verde
|
|
2'b01 : begin
|
|
raux = 6'b0;
|
|
gaux = red_weight[r] + green_weight[g] + blue_weight[b];
|
|
baux = 6'b0;
|
|
end
|
|
// Ambar
|
|
2'b10 : begin
|
|
raux = red_weight[r] + green_weight[g] + blue_weight[b];
|
|
gaux = (red_weight[r] + green_weight[g] + blue_weight[b]) >> 1;
|
|
baux = 6'b0;
|
|
end
|
|
// Blanco y negro
|
|
2'b11 : begin
|
|
raux = red_weight[r] + green_weight[g] + blue_weight[b];
|
|
gaux = red_weight[r] + green_weight[g] + blue_weight[b];
|
|
baux = red_weight[r] + green_weight[g] + blue_weight[b];
|
|
end
|
|
// Color
|
|
default: begin
|
|
raux = r;
|
|
gaux = g;
|
|
baux = b;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign VGA_R = {raux, 2'b0};
|
|
assign VGA_G = {gaux, 2'b0};
|
|
assign VGA_B = {baux, 2'b0};
|
|
|
|
/*
|
|
// SRAM management
|
|
wire sramOe = ~sramWe;
|
|
wire sramWe;
|
|
wire [20:0] sramA;
|
|
wire [ 7:0] sramDQ;
|
|
|
|
Mister_sRam sRam
|
|
( // .*,
|
|
//SDram interface
|
|
.SDRAM_A (SDRAM_A),
|
|
.SDRAM_DQ (SDRAM_DQ),
|
|
.SDRAM_BA (SDRAM_BA),
|
|
.SDRAM_nWE (SDRAM_nWE),
|
|
.SDRAM_nCAS (SDRAM_nCAS),
|
|
.SDRAM_nCS (SDRAM_nCS),
|
|
.SDRAM_CKE (SDRAM_CKE),
|
|
//Sram interface
|
|
.SRAM_A (sramA),
|
|
.SRAM_DQ (sramDQ),
|
|
.SRAM_nCE (1'b0),
|
|
.SRAM_nOE (sramOe),
|
|
.SRAM_nWE (sramWe)
|
|
);
|
|
*/
|
|
|
|
reg vsd = 0;
|
|
always @(posedge CLK_50M) if(usdImgMtd[0]) vsd <= |usdImgSz;
|
|
|
|
wire vsdRd;
|
|
wire vsdWr;
|
|
wire vsdAck = usdAck;
|
|
wire[31:0] vsdLba;
|
|
wire vsdBuffWr = usdBuffWr;
|
|
wire[ 8:0] vsdBuffA = usdBuffA;
|
|
wire[ 7:0] vsdBuffD;
|
|
wire[ 7:0] vsdBuffQ = usdBuffQ;
|
|
wire[63:0] vsdImgSz = usdImgSz;
|
|
wire vsdImgMtd = usdImgMtd[0];
|
|
|
|
wire vsdCs = usdCs | ~vsd;
|
|
wire vsdCk = usdCk;
|
|
wire vsdMosi = usdDo;
|
|
wire vsdMiso;
|
|
|
|
wire usdCs;
|
|
wire usdCk;
|
|
wire usdDo;
|
|
wire usdDi = vsd ? vsdMiso : SD_MISO;
|
|
|
|
assign SD_CS = usdCs | vsd;
|
|
assign SD_SCK = usdCk & ~vsd;
|
|
assign SD_MOSI = usdDo & ~vsd;
|
|
|
|
/*
|
|
sd_card sd_card
|
|
(
|
|
.clk_sys (CLK_50M ),
|
|
.reset (reset ),
|
|
.sdhc (status[4]),
|
|
.sd_rd (vsdRd ),
|
|
.sd_wr (vsdWr ),
|
|
.sd_ack (vsdAck ),
|
|
.sd_lba (vsdLba ),
|
|
.sd_buff_wr (vsdBuffWr),
|
|
.sd_buff_addr(vsdBuffA ),
|
|
.sd_buff_dout(vsdBuffQ ),
|
|
.sd_buff_din (vsdBuffD ),
|
|
.img_size (vsdImgSz ),
|
|
.img_mounted (vsdImgMtd),
|
|
.clk_spi (clk_25 ),
|
|
.ss (vsdCs ),
|
|
.sck (vsdCk ),
|
|
.mosi (vsdMosi ),
|
|
.miso (vsdMiso )
|
|
);
|
|
*/
|
|
|
|
endmodule
|
|
|
|
module led
|
|
(
|
|
input clk,
|
|
input in,
|
|
output reg out
|
|
);
|
|
|
|
integer counter = 0;
|
|
always @(posedge clk) begin
|
|
if(!counter) out <= 0;
|
|
else begin
|
|
counter <= counter - 1'b1;
|
|
out <= 1;
|
|
end
|
|
|
|
if(in) counter <= 4500000;
|
|
end
|
|
|
|
endmodule
|