36 Commits

Author	SHA1	Message	Date
David Hunter	ffc527951b	huc6261: Match huc6260.vhd pixel clock timings	2026-01-01 11:39:37 -08:00
David Hunter	aace72f0db	huc6270: Fix some sprites not rendered	2025-12-31 00:19:00 -08:00
David Hunter	a4562b4216	Add HuC6270.vhd and dependencies for FPGA testing	2025-12-30 22:58:19 -08:00
David Hunter	ba46cd758c	Fix multiple instabilities due to unplanned CDC ... Switch CPU and sys clocks over to a PLL 50 MHz output	2025-12-30 22:54:44 -08:00
David Hunter	01281bfd15	HuC6261: Add color palette RAM, sync gen, and VDC out mixer	2025-12-29 20:14:30 -08:00
David Hunter	3846996d1b	VDC0 is rendering sprites?	2025-12-28 11:43:06 -08:00
David Hunter	dd9c652112	Double VRAM to 128KB	2025-12-26 23:22:42 -08:00
David Hunter	eae59f2897	Fix upper halfword read from ROM	2025-12-26 23:21:09 -08:00
David Hunter	e91ea9e5b5	Add the SCSI controller and a fake CD drive	2025-12-26 16:19:59 -08:00
David Hunter	770ee2f7bf	Fix dpram read-during-write behavior	2025-12-24 14:47:37 -08:00
David Hunter	c3fb721a5f	Appease Verilator	2025-12-24 11:08:00 -08:00
David Hunter	e131762c66	Builds in Quartus	2025-12-24 10:58:50 -08:00
David Hunter	71a6401d72	Integrate the real HuC6270 from TurboGrafx16_MiSTer ... - Translate huc6270 from VHDL to SystemVerilog - Display each VDC's output as a bit-reversed color channel	2025-12-24 00:05:38 -08:00
David Hunter	72be3244f3	Pick up v810 update	2025-12-21 17:46:46 -08:00
David Hunter	68cb944d6c	Merge remote-tracking branch 'origin/main'	2025-12-20 22:51:57 -08:00
David Hunter	168f3fd9b3	huc6270: Clear ie on reset	2025-12-20 22:51:19 -08:00
David Hunter	dac69366d4	Fix SDRAM 8- and 16-bit writes ... SDRAM pins DQMH/L and A[12:11] are shorted on the SDRAM board. Top-level FPGA pins SDRAM_DQMH/L don't actually go to the SDRAM board.	2025-12-20 22:46:38 -08:00
David Hunter	068cdf37df	Add a fake Gate Array and HuC6270 ... Implements just enough registers in each IP to get VBlank interrupts working.	2025-12-15 22:34:41 -08:00
David Hunter	ca49b4fdfc	Pick up v810 update	2025-11-30 21:08:54 -08:00
David Hunter	45157b2623	Pick up v810 update	2025-11-30 20:28:03 -08:00
David Hunter	78d49e7f73	Add a fake HuC6121 w/ raster counter	2025-11-29 20:27:20 -08:00
David Hunter	36666d0144	Identify and report IO reads and writes	2025-11-29 14:49:39 -08:00
David Hunter	5825c14600	Handle reset during active SDRAM access	2025-11-28 12:33:34 -08:00
David Hunter	3817eb96c5	Use SDRAM to store 2MB RAM	2025-11-27 21:29:08 -08:00
David Hunter	91d46f49bd	Simulate full core with SDRAM memory	2025-11-26 20:18:16 -08:00
David Hunter	75ceea2ddc	Add copyright	2025-11-25 10:47:18 -08:00
David Hunter	8f2b1315b1	Reset CPU every 256 frames	2025-11-24 19:30:02 -08:00
David Hunter	99ac3353de	Use SDRAM to store ROM BIOS, download BIOS from HPS, cont.	2025-11-24 18:27:56 -08:00
David Hunter	fd372da527	Use SDRAM to store ROM BIOS, download BIOS from HPS	2025-11-23 21:52:27 -08:00
David Hunter	910087c034	Merge remote-tracking branch 'origin/main'	2025-11-23 21:40:17 -08:00
David Hunter	edc735fc28	Remove unneeded data bus resizer	2025-11-23 21:40:02 -08:00
David Hunter	cebe1843d2	Remove unused files	2025-11-23 20:19:49 -08:00
David Hunter	3a9e7e4dab	Get it to synthesize and implement	2025-11-23 15:18:20 -08:00
David Hunter	96c7021d21	Add v810 code as submodule	2025-11-23 15:17:57 -08:00
David Hunter	4d0ad2cf1e	Add the V810 CPU, memory interface, and RAMs	2025-11-23 15:13:17 -08:00
David Hunter	d6a9cbaa33	Copy Template_MiSTer ... Commit e0afd28	2025-11-22 14:26:51 -08:00