Remove unneeded data bus resizer

This commit is contained in:
David Hunter
2025-11-23 21:39:37 -08:00
parent 3a9e7e4dab
commit edc735fc28
2 changed files with 7 additions and 36 deletions

View File

@@ -2,7 +2,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/mycore.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mach.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/v810/v810_exec.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/v810/v810_mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/v810/tb/data_bus_resizer.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram.sv
set_global_assignment -name SDC_FILE Test_V810.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Test_V810.sv

View File

@@ -29,13 +29,8 @@ wire mem_bcystn;
wire mem_readyn;
wand mem_szrqn;
wire [31:0] rom_dbr_ctlr_di;
wire rom_dbr_readyn;
wire rom_dbr_szrqn;
int rom_ws, rom_dw;
logic rom_cen;
logic [31:0] rom_do;
logic [15:0] rom_do;
logic ram_cen;
wire [31:0] ram_do;
@@ -116,41 +111,24 @@ v810_mem dut_mem
always @* begin
if (~rom_cen)
mem_d_i = rom_dbr_ctlr_di;
mem_d_i = {16'b0, rom_do};
else if (~ram_cen)
mem_d_i = ram_do;
else
mem_d_i = '0;
end
assign mem_readyn = unk_cen & rom_dbr_readyn & ram_cen;
assign mem_szrqn = ~unk_cen | rom_dbr_szrqn;
assign mem_readyn = unk_cen & rom_cen & ram_cen;
assign mem_szrqn = ~unk_cen | rom_cen;
data_bus_resizer rom_dbr
(
.WS(rom_ws),
.DW(rom_dw),
.CLK(CLK),
.CE(CE),
.CTLR_DAn(mem_dan),
.CTLR_BEn(mem_ben),
.CTLR_READYn(rom_dbr_readyn),
.CTLR_SZRQn(rom_dbr_szrqn),
.CTLR_DI(rom_dbr_ctlr_di),
.CTLR_DO(),
.MEM_nCE(rom_cen),
.MEM_DI(),
.MEM_DO(rom_do)
);
ram #(4, 32) rombios
ram #(4, 16) rombios
(
.CLK(CLK),
.nCE(rom_cen),
.nWE('1),
.nOE('0),
.nBE(mem_ben),
.A(mem_a[5:2]),
.nBE('1),
.A(mem_a[4:1]),
.DI('Z),
.DO(rom_do)
);
@@ -171,12 +149,6 @@ assign ram_cen = ~(~mem_mrqn & ~mem_a[31]);
assign rom_cen = ~(~mem_mrqn & (mem_a[31:20] == 12'hFFF));
assign unk_cen = ~(ram_cen & rom_cen);
initial #0 begin
rom_ws = 0;
rom_dw = 16;
//rombios.load_hex16("pcfx.rom.hex");
end
assign A = mem_a;
endmodule