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https://github.com/MiSTer-devel/PCFX_MiSTer.git
synced 2026-05-31 03:04:28 +00:00
Remove unneeded data bus resizer
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@@ -2,7 +2,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/mycore.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/mach.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/v810/v810_exec.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/v810/v810_mem.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/v810/tb/data_bus_resizer.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram.sv
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set_global_assignment -name SDC_FILE Test_V810.sdc
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set_global_assignment -name SYSTEMVERILOG_FILE Test_V810.sv
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42
rtl/mach.sv
42
rtl/mach.sv
@@ -29,13 +29,8 @@ wire mem_bcystn;
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wire mem_readyn;
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wand mem_szrqn;
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wire [31:0] rom_dbr_ctlr_di;
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wire rom_dbr_readyn;
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wire rom_dbr_szrqn;
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int rom_ws, rom_dw;
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logic rom_cen;
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logic [31:0] rom_do;
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logic [15:0] rom_do;
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logic ram_cen;
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wire [31:0] ram_do;
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@@ -116,41 +111,24 @@ v810_mem dut_mem
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always @* begin
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if (~rom_cen)
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mem_d_i = rom_dbr_ctlr_di;
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mem_d_i = {16'b0, rom_do};
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else if (~ram_cen)
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mem_d_i = ram_do;
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else
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mem_d_i = '0;
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end
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assign mem_readyn = unk_cen & rom_dbr_readyn & ram_cen;
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assign mem_szrqn = ~unk_cen | rom_dbr_szrqn;
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assign mem_readyn = unk_cen & rom_cen & ram_cen;
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assign mem_szrqn = ~unk_cen | rom_cen;
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data_bus_resizer rom_dbr
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(
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.WS(rom_ws),
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.DW(rom_dw),
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.CLK(CLK),
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.CE(CE),
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.CTLR_DAn(mem_dan),
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.CTLR_BEn(mem_ben),
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.CTLR_READYn(rom_dbr_readyn),
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.CTLR_SZRQn(rom_dbr_szrqn),
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.CTLR_DI(rom_dbr_ctlr_di),
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.CTLR_DO(),
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.MEM_nCE(rom_cen),
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.MEM_DI(),
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.MEM_DO(rom_do)
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);
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ram #(4, 32) rombios
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ram #(4, 16) rombios
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(
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.CLK(CLK),
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.nCE(rom_cen),
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.nWE('1),
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.nOE('0),
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.nBE(mem_ben),
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.A(mem_a[5:2]),
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.nBE('1),
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.A(mem_a[4:1]),
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.DI('Z),
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.DO(rom_do)
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);
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@@ -171,12 +149,6 @@ assign ram_cen = ~(~mem_mrqn & ~mem_a[31]);
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assign rom_cen = ~(~mem_mrqn & (mem_a[31:20] == 12'hFFF));
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assign unk_cen = ~(ram_cen & rom_cen);
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initial #0 begin
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rom_ws = 0;
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rom_dw = 16;
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//rombios.load_hex16("pcfx.rom.hex");
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end
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assign A = mem_a;
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endmodule
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