mister-devel/NeoGeo_MiSTer
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Support for Metal Slug 5 Plus banking.

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This commit is contained in:
Sorgelig
2023-08-01 05:25:28 +08:00
parent ed666850b3
commit 8dad34e4e9
3 changed files with 24 additions and 21 deletions
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10
neogeo.sv
View File

@@ -674,6 +674,7 @@ parameter INDEX_CROMS = 64;
wire video_mode = status[3];
wire ms5p_bank = cfg[17];
wire xram = cfg[18];
wire adpcma_ext = cfg[19];
wire [2:0] cart_pchip = cfg[22:20];
@@ -1484,10 +1485,11 @@ begin
reg nPORTWEL_d;
nPORTWEL_d <= nPORTWEL;
if (!nRESET)
P_BANK <= 0;
else if (nPORTWEL & ~nPORTWEL_d)
if (!SYSTEM_CDx) P_BANK <= M68K_DATA[3:0];
if (!nRESET || SYSTEM_CDx) P_BANK <= 0;
else if (~nPORTWEL & nPORTWEL_d) begin
if(~ms5p_bank) P_BANK <= M68K_DATA[3:0];
else if(&M68K_ADDR[19:4] && M68K_ADDR[3:1] == 2) P_BANK <= M68K_DATA[7:4] - 1'd1;
end
end
// PRO-CT0 used as security chip

1
releases/romsets.xml
View File

@@ -311,6 +311,7 @@ https://lmgtfy.com/?q=darksoft+neo+geo+roll-up+pack
<romset name="mslug3b6,mslug6" pcm="1" altname="Metal Slug 6 (Metal Slug 3 bootleg)" publisher="Hack / Bootleg" year="2000" ram="2"/>
<romset name="mslug5" pvc="1" pcm="1" altname="Metal Slug 5" publisher="SNK Playmore" year="2003" ram="2"/>
<romset name="mslug5h" pvc="1" pcm="1" altname="Metal Slug 5 (NGH-2680)" publisher="SNK Playmore" year="2003" ram="2"/>
<romset name="ms5plus" ms5p="1" pcm="1" altname="Metal Slug 5 Plus (bootleg)" publisher="Bootleg" year="2003" ram="2"/>
<!-- Non-NeoGeo titles made for specific board. Do not work <romset name="ms5pcb" pcm="1" altname="Metal Slug 5 (PCB)" publisher="SNK Playmore" year="2003" ram="2"/> -->
<romset name="nblktigr" pcm="1" altname="Neo Black Tiger" publisher="OzzyOuzo" year="2020" ram="2"/>
<romset name="rotd" pcm="1" altname="Rage of the Dragons" publisher="Evoga" year="2002"/>

34
rtl/io/neo_c1.v
View File

@@ -74,31 +74,31 @@ module neo_c1(
c1_inputs C1INPUTS(nCTRL1_ZONE, nCTRL2_ZONE, nSTATUSB_ZONE, M68K_DATA, P1_IN, P2_IN,
nWP, nCD2, nCD1, SYSTEM_TYPE[0]);
// 000000~0FFFFF read/write
assign nROM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], M68K_ADDR[20]};
// 100000~1FFFFF read/write
assign nWRAM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], ~M68K_ADDR[20]};
// 200000~2FFFFF read/write
assign nPORT_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], M68K_ADDR[20]};
// 300000~3FFFFF read/write
assign nIO_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], ~M68K_ADDR[20]};
// 300000~3FFFFE even bytes read/write
assign nC1REGS_ZONE = nUDS | nIO_ZONE;
// 300000~31FFFE even bytes read only
assign nCTRL1_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]};
// 320000~33FFFE even bytes read/write
assign nICOM_ZONE = nC1REGS_ZONE | |{M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17]};
// 340000~35FFFE even bytes read only - Todo: MAME says A17 is used, see right below
assign nCTRL2_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]};
// 360000~37FFFF is not mapped ?
// 300000~3FFFFE even bytes read/write
assign nC1REGS_ZONE = nUDS | nIO_ZONE;
// 300000~31FFFE even bytes read only
assign nCTRL1_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]};
// 320000~33FFFE even bytes read/write
assign nICOM_ZONE = nC1REGS_ZONE | |{M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17]};
// 340000~35FFFE even bytes read only - Todo: MAME says A17 is used, see right below
assign nCTRL2_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]};
// 360000~37FFFF is not mapped ?
// 30xxxx 31xxxx odd bytes read only
assign nDIPRD0 = |{nIO_ZONE, M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17], ~RW, nLDS};