From 8dad34e4e903b2e1db0edebd0ba192ac0049fad2 Mon Sep 17 00:00:00 2001 From: Sorgelig Date: Tue, 1 Aug 2023 05:25:28 +0800 Subject: [PATCH] Support for Metal Slug 5 Plus banking. --- neogeo.sv | 10 ++++++---- releases/romsets.xml | 1 + rtl/io/neo_c1.v | 34 +++++++++++++++++----------------- 3 files changed, 24 insertions(+), 21 deletions(-) diff --git a/neogeo.sv b/neogeo.sv index 7dd3e15..40e0492 100644 --- a/neogeo.sv +++ b/neogeo.sv @@ -674,6 +674,7 @@ parameter INDEX_CROMS = 64; wire video_mode = status[3]; +wire ms5p_bank = cfg[17]; wire xram = cfg[18]; wire adpcma_ext = cfg[19]; wire [2:0] cart_pchip = cfg[22:20]; @@ -1484,10 +1485,11 @@ begin reg nPORTWEL_d; nPORTWEL_d <= nPORTWEL; - if (!nRESET) - P_BANK <= 0; - else if (nPORTWEL & ~nPORTWEL_d) - if (!SYSTEM_CDx) P_BANK <= M68K_DATA[3:0]; + if (!nRESET || SYSTEM_CDx) P_BANK <= 0; + else if (~nPORTWEL & nPORTWEL_d) begin + if(~ms5p_bank) P_BANK <= M68K_DATA[3:0]; + else if(&M68K_ADDR[19:4] && M68K_ADDR[3:1] == 2) P_BANK <= M68K_DATA[7:4] - 1'd1; + end end // PRO-CT0 used as security chip diff --git a/releases/romsets.xml b/releases/romsets.xml index 1f7393d..3795964 100644 --- a/releases/romsets.xml +++ b/releases/romsets.xml @@ -311,6 +311,7 @@ https://lmgtfy.com/?q=darksoft+neo+geo+roll-up+pack + diff --git a/rtl/io/neo_c1.v b/rtl/io/neo_c1.v index 17bcc58..721bafa 100644 --- a/rtl/io/neo_c1.v +++ b/rtl/io/neo_c1.v @@ -74,31 +74,31 @@ module neo_c1( c1_inputs C1INPUTS(nCTRL1_ZONE, nCTRL2_ZONE, nSTATUSB_ZONE, M68K_DATA, P1_IN, P2_IN, nWP, nCD2, nCD1, SYSTEM_TYPE[0]); - + // 000000~0FFFFF read/write assign nROM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], M68K_ADDR[20]}; - + // 100000~1FFFFF read/write assign nWRAM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], ~M68K_ADDR[20]}; - + // 200000~2FFFFF read/write assign nPORT_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], M68K_ADDR[20]}; - + // 300000~3FFFFF read/write assign nIO_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], ~M68K_ADDR[20]}; - - // 300000~3FFFFE even bytes read/write - assign nC1REGS_ZONE = nUDS | nIO_ZONE; - - // 300000~31FFFE even bytes read only - assign nCTRL1_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]}; - - // 320000~33FFFE even bytes read/write - assign nICOM_ZONE = nC1REGS_ZONE | |{M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17]}; - - // 340000~35FFFE even bytes read only - Todo: MAME says A17 is used, see right below - assign nCTRL2_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]}; - // 360000~37FFFF is not mapped ? + + // 300000~3FFFFE even bytes read/write + assign nC1REGS_ZONE = nUDS | nIO_ZONE; + + // 300000~31FFFE even bytes read only + assign nCTRL1_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]}; + + // 320000~33FFFE even bytes read/write + assign nICOM_ZONE = nC1REGS_ZONE | |{M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17]}; + + // 340000~35FFFE even bytes read only - Todo: MAME says A17 is used, see right below + assign nCTRL2_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]}; + // 360000~37FFFF is not mapped ? // 30xxxx 31xxxx odd bytes read only assign nDIPRD0 = |{nIO_ZONE, M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17], ~RW, nLDS};