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Podpora device a FW ROM

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Molekula
2024-08-28 00:37:47 +02:00
parent 8ef27816d3
commit d9b4e36624
11 changed files with 217 additions and 173 deletions
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6
MSX1.sv
View File

@@ -300,7 +300,7 @@ assign status_menumask[4] = ROM_B_load_hide;
assign status_menumask[5] = sram_A_select_hide;
assign status_menumask[6] = lookup_SRAM[0].size + lookup_SRAM[1].size + lookup_SRAM[2].size + lookup_SRAM[3].size == 0;
assign sdram_size = sdram_sz[15] ? sdram_sz[1:0] : 2'b00;
/*verilator tracing_off*/
hps_io #(.CONF_STR(CONF_STR),.VDNUM(VDNUM)) hps_io
(
.clk_sys(clk21m),
@@ -338,7 +338,7 @@ hps_io #(.CONF_STR(CONF_STR),.VDNUM(VDNUM)) hps_io
///////////////// CONFIG /////////////////
wire [5:0] mapper_A, mapper_B;
wire reload, sram_A_select_hide, fdc_enabled, ROM_A_load_hide, ROM_B_load_hide;
/*verilator tracing_off*/
msx_config msx_config
(
.clk(clk21m),
@@ -356,7 +356,7 @@ msx_config msx_config
.fdc_enabled(fdc_enabled),
.msxConfig(msxConfig)
);
/*verilator tracing_off*/
///////////////// CLOCKS /////////////////
wire clk21m, clk_sdram, locked_sdram;
wire ce_10m7_p, ce_10m7_n, ce_5m39_p, ce_5m39_n, ce_3m58_p, ce_3m58_n, ce_10hz;

2
rtl/msx.sv
View File

@@ -311,7 +311,7 @@ rtc rtc
.dbi(d_from_rtc),
.dbo(d_from_cpu)
);
/*verilator tracing_on*/
/*verilator tracing_off*/
// -----------------------------------------------------------------------------
// -- Video
// -----------------------------------------------------------------------------

9
rtl/package.sv
View File

@@ -5,15 +5,16 @@ typedef enum logic [2:0] {CART_TYP_ROM, CART_TYP_SCC, CART_TYP_SCC2, CART_TYP_FM
//typedef enum logic [4:0] {MAPPER_UNUSED, MAPPER_RAM, MAPPER_AUTO, MAPPER_NONE, MAPPER_ASCII8, MAPPER_ASCII16, MAPPER_KONAMI, MAPPER_KONAMI_SCC, MAPPER_KOEI, MAPPER_LINEAR, MAPPER_RTYPE, MAPPER_WIZARDY, /*NEXT INTERNAL*/ MAPPER_FMPAC,MAPPER_OFFSET, MAPPER_MFRSD1,MAPPER_MFRSD2, MAPPER_MFRSD3, MAPPER_GM2, MAPPER_HALNOTE} mapper_typ_t;
//typedef enum logic [3:0] {DEVICE_NONE, DEVICE_ROM, DEVICE_RAM, DEVICE_FDC, DEVICE_MFRSD0} device_typ_t;
typedef enum logic [3:0] {ROM_NONE, ROM_ROM, ROM_RAM, ROM_FDC, ROM_FMPAC, ROM_MFRSD, ROM_GM2 } data_ID_t;
typedef enum logic [3:0] {DEV_OPL3 } device_t;
typedef enum logic {MSX1,MSX2} MSX_typ_t;
typedef enum logic [3:0] {DEVICE_NONE, DEVICE_ROM} device_typ_t;
typedef enum logic [4:0] {MAPPER_NONE, MAPPER_OFFSET, MAPPER_ASCII16, MAPPER_RTYPE, MAPPER_ASCII8, MAPPER_KOEI, MAPPER_WIZARDY, MAPPER_UNUSED} mapper_typ_t;
typedef enum logic [3:0] {DEV_NONE, DEV_OPL3, DEV_SCC } device_t;
typedef enum logic [4:0] {MAPPER_NONE, MAPPER_OFFSET, MAPPER_ASCII16, MAPPER_RTYPE, MAPPER_ASCII8, MAPPER_KOEI, MAPPER_WIZARDY, MAPPER_KONAMI, MAPPER_FMPAC, MAPPER_UNUSED} mapper_typ_t;
typedef enum logic [3:0] {BLOCK_RAM, BLOCK_ROM, BLOCK_SRAM, BLOCK_DEVICE, BLOCK_MAPPER, BLOCK_CART, BLOCK_REF_MEM, BLOCK_REF_DEV} block_t;
typedef enum logic [2:0] {CONF_BLOCK, CONF_DEVICE, CONF_LAYOUT, CONF_CARTRIGE, CONF_BLOCK_FW, CONF_UNUSED5, CONF_UNUSED6, CONF_END} conf_t;
typedef enum logic [2:0] {ERR_NONE, ERR_BAD_MSX_CONF, ERR_NOT_SUPPORTED_CONF, ERR_NOT_SUPPORTED_BLOCK, ERR_BAD_MSX_FW_CONF, ERR_NOT_FW_CONF} error_t;
typedef enum logic [2:0] {ERR_NONE, ERR_BAD_MSX_CONF, ERR_NOT_SUPPORTED_CONF, ERR_NOT_SUPPORTED_BLOCK, ERR_BAD_MSX_FW_CONF, ERR_NOT_FW_CONF, ERR_DEVICE_MISSING} error_t;
typedef logic [15:0] dev_typ_t;
@@ -53,8 +54,8 @@ package MSX;
logic [3:0] ref_ram;
logic [1:0] ref_sram;
logic [1:0] offset_ram;
logic [1:0] device_num;
mapper_typ_t mapper;
device_typ_t device;
logic cart_num;
logic external;
} block_t;

183
rtl/peripheral/slots/fm_pac.sv
View File

@@ -1,142 +1,94 @@
/*verilator tracing_off*/
module cart_fm_pac
/*verilator tracing_on*/
module mapper_fm_pac
(
input clk,
input reset,
input [15:0] cpu_addr,
input [7:0] din,
output [7:0] mapper_dout,
input cs,
input cart_num,
input cpu_wr,
input cpu_rd,
input cpu_mreq,
output sram_we,
output sram_cs,
output mem_unmaped,
output [24:0] mem_addr,
output [1:0] opll_wr,
output [1:0] opll_io_enable
input cpu_rd,
input cpu_wr,
input [7:0] cpu_data,
input [15:0] cpu_addr,
input mapper_typ_t mapper,
input mapper_id,
output [7:0] data,
output [26:0] mem_addr,
output mem_rnw,
output ram_cs,
output sram_cs
// output [7:0] mapper_dout,
// input cs,
// input cart_num,
// output sram_we,
// output sram_cs,
// output mem_unmaped,
// output [1:0] opll_wr,
// output [1:0] opll_io_enable
);
wire [24:0] mem_addr_A, mem_addr_B;
wire [7:0] d_to_cpu_A, d_to_cpu_B;
wire sram_we_A, sram_we_B;
wire sram_cs_A, sram_cs_B;
wire cart_oe_A, cart_oe_B;
wire mem_unmaped_A, mem_unmaped_B;
wire opll_io_enable_A, opll_io_enable_B;
assign mem_addr = cart_num ? mem_addr_B : mem_addr_A;
assign sram_we = cart_num ? sram_we_B : sram_we_A;
assign sram_cs = cart_num ? sram_cs_B : sram_cs_A;
assign mem_unmaped = mem_unmaped_A | mem_unmaped_B;
assign mapper_dout = d_to_cpu_A & d_to_cpu_B;
assign opll_io_enable = {opll_io_enable_B, opll_io_enable_A};
fm_pac fm_pac_A
(
.d_to_cpu(d_to_cpu_A),
.cart_oe(cart_oe_A),
.mem_addr(mem_addr_A),
.sram_we(sram_we_A),
.sram_cs(sram_cs_A),
.cs(cs & ~cart_num),
.opll_io_enable(opll_io_enable_A),
.opll_wr(opll_wr[0]),
.mem_unmaped(mem_unmaped_A),
.*
);
fm_pac fm_pac_B
(
.d_to_cpu(d_to_cpu_B),
.cart_oe(cart_oe_B),
.mem_addr(mem_addr_B),
.sram_we(sram_we_B),
.sram_cs(sram_cs_B),
.cs(cs & cart_num),
.opll_io_enable(opll_io_enable_B),
.opll_wr(opll_wr[1]),
.mem_unmaped(mem_unmaped_B),
.*
);
endmodule
// Signály a logika pro mapování paměti
wire cs, mapped, mapper_en, sramEnable;
module fm_pac
(
input clk,
input reset,
input [15:0] cpu_addr,
input [7:0] din,
output [7:0] d_to_cpu,
input cs,
input cpu_wr,
input cpu_rd,
input cpu_mreq,
output logic opll_wr,
output opll_io_enable,
output cart_oe,
output sram_we,
output sram_cs,
output [24:0] mem_addr,
output mem_unmaped
);
/*verilator tracing_off*/
initial begin
opll_wr = 0;
end
assign mapped = cpu_addr[15:14] == 2'b01; // Adresa je platná pouze 0x4000 - 0x7FFF
assign mapper_en = (mapper == MAPPER_FMPAC);
assign cs = mapper_en & cpu_mreq;
assign sramEnable = {magicHi[mapper_id],magicLo[mapper_id]} == 16'h694D;
logic [7:0] enable = 8'h00;
logic [1:0] bank = 2'b00;
logic [7:0] magicLo = 8'h00;
logic [7:0] magicHi = 8'h00;
assign data = mapper_en & cpu_addr[13:0] == 14'h3FF6 ? enable[mapper_id] :
mapper_en & cpu_addr[13:0] == 14'h3FF7 ? {6'b000000, bank[mapper_id]} :
mapper_en & cpu_addr[13:0] == 14'h1FFE & sramEnable ? magicLo[mapper_id] :
mapper_en & cpu_addr[13:0] == 14'h1FFF & sramEnable ? magicHi[mapper_id] :
8'hFF ;
logic [7:0] enable[2];
logic [1:0] bank[2];
logic [7:0] magicLo[2];
logic [7:0] magicHi[2];
logic last_mreq;
wire sramEnable = {magicHi,magicLo} == 16'h694D;
initial begin
opll_wr = '0;
enable = '{default: '0};
bank = '{default: '0};
magicLo = '{default: '0};
magicHi = '{default: '0};
end
assign mem_unmaped = cs & ((cpu_addr < 16'h4000 | cpu_addr >= 16'h8000)) & cart_oe;
//assign opll_io_enable = enable[0]; // Zápis OPL
logic opll_wr; // Write to OPL
assign {cart_oe, d_to_cpu} = ~cs ? {cs, 8'hFF} :
cpu_addr[13:0] == 14'h3FF6 ? {cs, enable} :
cpu_addr[13:0] == 14'h3FF7 ? {cs, 6'b000000, bank} :
cpu_addr[13:0] == 14'h1FFE & sramEnable ? {cs, magicLo} :
cpu_addr[13:0] == 14'h1FFF & sramEnable ? {cs, magicHi} :
{cs, 8'hFF} ;
assign opll_io_enable = enable[0];
always @(posedge clk) begin
if (reset) begin
enable <= 8'h00;
bank <= 2'b00;
magicLo <= 8'h00;
magicHi <= 8'h00;
enable <= '{default: '0};
bank <= '{default: '0};
magicLo <= '{default: '0};
magicHi <= '{default: '0};
end else begin
opll_wr <= 1'b0;
if (cs & cpu_wr & cpu_mreq) begin
if (mapper_en & cpu_wr & cpu_mreq) begin
case (cpu_addr[13:0])
14'h1FFE:
if (~enable[4])
magicLo <= din;
if (~enable[mapper_id][4])
magicLo[mapper_id] <= cpu_data;
14'h1FFF:
if (~enable[4])
magicHi <= din;
if (~enable[mapper_id][4])
magicHi[mapper_id] <= cpu_data;
14'h3FF4,
14'h3FF5: begin
opll_wr <= 1'b1;
end
14'h3FF6: begin
enable <= din & 8'h11;
if (enable[4]) begin
magicLo <= 0;
magicHi <= 0;
enable[mapper_id] <= cpu_data & 8'h11;
if (enable[mapper_id][4]) begin
magicLo[mapper_id] <= 0;
magicHi[mapper_id] <= 0;
end
end
14'h3FF7: begin
bank <=din[1:0];
bank[mapper_id] <=cpu_data[1:0];
end
default: ;
endcase
@@ -145,8 +97,13 @@ always @(posedge clk) begin
last_mreq <= cpu_mreq & (cpu_rd | cpu_wr);
end
assign sram_cs = cs & sramEnable & ~cpu_addr[13] & ((~last_mreq & cpu_wr) | cpu_mreq & cpu_rd);
assign sram_we = sram_cs & cpu_wr & cpu_mreq;
assign mem_addr = sram_cs ? 25'(cpu_addr[12:0]) : 25'({bank, cpu_addr[13:0]});
wire sram_en = sramEnable & ~cpu_addr[13] & ((~last_mreq & cpu_wr) | cpu_mreq & cpu_rd);
wire [26:0] sram_addr = 27'(cpu_addr[12:0]);
wire [26:0] ram_addr = 27'({bank[mapper_id], cpu_addr[13:0]});
assign sram_cs = cs & sram_en;
assign ram_cs = cs & ~sram_en & cpu_rd & mapped;
assign mem_rnw = ~(sram_cs & cpu_wr);
assign mem_addr = cs ? (sram_cs ? sram_addr : ram_addr) : {27{1'b1}};
endmodule

24
rtl/peripheral/slots/mappers.sv
View File

@@ -11,17 +11,18 @@ module mappers(
input [1:0] offset_ram,
input mapper_typ_t mapper,
input mapper_id,
output [7:0] data, //Data z mapperu. Pokud není aktivován tak FF
output [24:0] mem_addr, //Adresa požadované paměti (obecná)
output mem_rnw, //Požadavek RD/WR (obecný)
output ram_cs, //Požadovaná RAM/ROM
output sram_cs //Požadovaná SRAM
);
assign mem_addr = ascii8_addr & ascii16_addr & offset_addr;
assign mem_rnw = ascii8_rnw & ascii16_rnw & offset_rnw;
assign ram_cs = ascii8_ram_cs | ascii16_ram_cs | offset_ram_cs;
assign sram_cs = ascii8_sram_cs | ascii16_sram_cs;
assign mem_addr = ascii8_addr & ascii16_addr & offset_addr & fm_pac_addr;
assign mem_rnw = ascii8_rnw & ascii16_rnw & offset_rnw & fm_pac_rnw;
assign ram_cs = ascii8_ram_cs | ascii16_ram_cs | offset_ram_cs | fm_pac_ram_cs;
assign sram_cs = ascii8_sram_cs | ascii16_sram_cs | fm_pac_sram_cs;
assign data = fm_pac_data;
wire [24:0] ascii8_addr;
wire ascii8_sram_cs, ascii8_ram_cs, ascii8_rnw;
@@ -56,4 +57,17 @@ mapper_offset offset
.*
);
wire [26:0] fm_pac_addr;
wire [7:0] fm_pac_data;
wire fm_pac_ram_cs, fm_pac_sram_cs, fm_pac_rnw;
mapper_fm_pac fm_pac
(
.mem_addr(fm_pac_addr),
.mem_rnw(fm_pac_rnw),
.ram_cs(fm_pac_ram_cs),
.sram_cs(fm_pac_sram_cs),
.data(fm_pac_data),
.*
);
endmodule

132
rtl/peripheral/slots/memory_upload.sv
View File

@@ -39,7 +39,7 @@ module memory_upload
);
// Parametry
localparam DDR3_BASE_ADDR = 28'h300000;
localparam DDR3_BASE_FW_ADDR = 28'h300000;
localparam DDR3_CRC32_TABLE_ADDR = 28'h1600000;
// Stavový signál, který indikuje, zda je modul resetován
@@ -105,7 +105,7 @@ module memory_upload
typedef enum logic [3:0] {
STATE_IDLE,
STATE_CLEAN,
STATE_READ_FW_CONF,
STATE_READ_ADRFILL_FW_ROM,
STATE_READ_CONF,
STATE_CHECK_FW_CONF,
STATE_CHECK_CONF,
@@ -133,11 +133,12 @@ module memory_upload
logic [7:0] temp[8];
logic [5:0] block_num;
logic [2:0] head_addr, read_cnt;
logic [27:0] save_addr;
logic [27:0] save_addr, save_addr2;
logic ref_add, ref_sram_add, fw_space;
logic [1:0] slot, subslot, block, size, offset, ref_sram;
logic [1:0] slot, subslot, block, size, offset, ref_sram, device_num;
logic [15:0] rom_fw_table;
mapper_typ_t mapper;
mapper_typ_t mapper;
device_t device;
if (load) begin
state <= STATE_CLEAN;
@@ -164,18 +165,21 @@ module memory_upload
STATE_IDLE: begin
block_num <= '0;
ddr3_request <= '0;
ref_add <= '0;
ref_add <= '0;
ref_sram_add <= '0;
ref_ram <= '0;
ram_addr <= '0;
crc_en <= '0;
fw_space <= '0;
save_addr <= '0;
save_addr2 <= '0;
kbd_request <= '0;
end
STATE_CLEAN: begin
error_t error = ERR_NONE;
ddr3_request <= '1;
slot_layout[block_num].mapper <= MAPPER_NONE;
slot_layout[block_num].device <= DEVICE_NONE;
slot_layout[block_num].device_num <= '0;
slot_layout[block_num].ref_ram <= '0;
slot_layout[block_num].offset_ram <= block_num[1:0];
slot_layout[block_num].cart_num <= '0;
@@ -196,13 +200,13 @@ module memory_upload
if (ioctl_size[1] > 0) begin
state <= STATE_READ_CONF;
next_state <= STATE_CHECK_FW_CONF;
ddr3_addr <= DDR3_BASE_ADDR;
ddr3_addr <= DDR3_BASE_FW_ADDR;
fw_space <= '1; // Čtení firmware oblasti
end
end
end
STATE_READ_CONF: begin // Přečte požadovaný počet bytů do konfigurace
if (fw_space ? ioctl_size[1] > (ddr3_addr - DDR3_BASE_ADDR) : ioctl_size[0] > (ddr3_addr)) begin // Kontrola konce dat
if (fw_space ? ioctl_size[1] > (ddr3_addr - DDR3_BASE_FW_ADDR) : ioctl_size[0] > (ddr3_addr)) begin // Kontrola konce dat
conf[head_addr] <= ddr3_dout;
ddr3_rd <= '1;
if (head_addr == read_cnt) begin
@@ -214,7 +218,7 @@ module memory_upload
end else begin
state <= STATE_IDLE;
end
kbd_request <= '1;
kbd_request <= '0;
end
STATE_CHECK_FW_CONF: begin
if ({conf[0], conf[1], conf[2]} == {"M", "s", "X"}) begin
@@ -274,6 +278,7 @@ module memory_upload
block <= conf[1][3:2];
size <= conf[1][1:0];
mapper <= MAPPER_NONE;
device <= DEV_NONE;
next_state <= STATE_READ_CONF;
case(block_t'(conf[2]))
BLOCK_RAM: begin
@@ -289,35 +294,62 @@ module memory_upload
state <= STATE_FILL_RAM;
end
BLOCK_ROM: begin
$display("BLOCK ROM ref_RAM:%x addr:%x size %d ", ref_ram, ram_addr, {conf[3],14'd0});
lookup_RAM[ref_ram].addr <= ram_addr; // Uložíme adresu ROM
lookup_RAM[ref_ram].size <= {conf[3],14'd0}; // Uložíme velikost ROM
lookup_RAM[ref_ram].ro <= '1; // Uložíme ochranu paměti ROM
mapper <= MAPPER_OFFSET;
offset <= '0; // Offset posunu RAM
ref_add <= '1; // Bude potřeba zvednout referenci
data_size <= {conf[3],14'd0}; // Velikost nahrávaných dat
pattern <= PATTERN_DDR;
state <= STATE_FILL_RAM;
if (fw_space) begin // Pokud se bude jednat o ROM z FW musíme dle indexu najít adresu v DDR
$display("BLOCK FW ROM ID: %x ref_RAM:%x addr:%x size %d ", conf[3], ref_ram, ram_addr, {conf[4],conf[5],14'd0});
lookup_RAM[ref_ram].size <= {conf[4],conf[5]}; // Uložíme velikost ROM
data_size <= {conf[4],conf[5],14'd0};
save_addr2 <= ddr3_addr - 1'b1; // Uložíme adresu pokračování -1 kvůli prefetch
ddr3_addr <= DDR3_BASE_FW_ADDR + rom_fw_table + {conf[3],2'b00};
ddr3_rd <= '1;
state <= STATE_READ_CONF; // Jdeme přečíst ROM ADDR
next_state <= STATE_READ_ADRFILL_FW_ROM; // Pokračujeme nastavením ROM
end else begin
$display("BLOCK ROM ref_RAM:%x addr:%x size %d ", ref_ram, ram_addr, {conf[3],14'd0});
lookup_RAM[ref_ram].size <= {conf[3],14'd0}; // Uložíme velikost ROM
data_size <= {conf[3],14'd0}; // Velikost nahrávaných dat
state <= STATE_FILL_RAM;
end
end
BLOCK_CART: begin
next_state <= STATE_LOAD_CONF; // Defaultně neděláme nic
state <= STATE_READ_CONF;
$display("BLOCK CART %d", conf[3][0]);
if (ioctl_size[conf[3][0] ? 3 : 2] > '0) begin
$display("BLOCK CART %d LOAD START ref: %d addr:%x size:%x - %x", conf[3][0], ref_ram, ram_addr, ioctl_size[conf[3][0] ? 3 : 2], ioctl_size[conf[3][0] ? 3 : 2][26:14]);
lookup_RAM[ref_ram].addr <= ram_addr; // Uložíme adresu ROM
lookup_RAM[ref_ram].size <= ioctl_size[conf[3][0] ? 3 : 2][26:14]; // Uložíme velikost ROM
lookup_RAM[ref_ram].ro <= '1; // Uložíme ochranu paměti ROM
state <= STATE_FILL_RAM; // Načítáme ROM
next_state <= STATE_SEARCH_CRC32_INIT; // Po nahrání budeme hledat CRC
save_addr <= ddr3_addr - 1'b1; // Uchováme adresu -1 kvůli již načtenému prefetch bajtu
ddr3_addr <= conf[3][0] ? 28'h1100000 : 28'hC00000; // Adresa ROM v DDR
data_size <= ioctl_size[conf[3][0] ? 3 : 2][24:0]; // Velikost ROM
ddr3_rd <= '1; // Prefetch
ref_add <= '1; // Ukládáme referenci
crc_en <= '1; // Počítáme CRC
pattern <= PATTERN_DDR; // Ukládáme z ROM
$display("BLOCK CART ID:%d CONF:%x", conf[3][0], cart_conf[conf[3][0]]);
if (cart_conf[conf[3][0]].typ == CART_TYP_ROM) begin
if (ioctl_size[conf[3][0] ? 3 : 2] > '0) begin
$display("BLOCK CART %d LOAD START ref: %d addr:%x size:%x - %x", conf[3][0], ref_ram, ram_addr, ioctl_size[conf[3][0] ? 3 : 2], ioctl_size[conf[3][0] ? 3 : 2][26:14]);
lookup_RAM[ref_ram].addr <= ram_addr; // Uložíme adresu ROM
lookup_RAM[ref_ram].size <= ioctl_size[conf[3][0] ? 3 : 2][26:14]; // Uložíme velikost ROM
lookup_RAM[ref_ram].ro <= '1; // Uložíme ochranu paměti ROM
state <= STATE_FILL_RAM; // Načítáme ROM
next_state <= STATE_SEARCH_CRC32_INIT; // Po nahrání budeme hledat CRC
save_addr <= ddr3_addr - 1'b1; // Uchováme adresu -1 kvůli již načtenému prefetch bajtu
ddr3_addr <= conf[3][0] ? 28'h1100000 : 28'hC00000; // Adresa ROM v DDR
data_size <= ioctl_size[conf[3][0] ? 3 : 2][24:0]; // Velikost ROM
ddr3_rd <= '1; // Prefetch
ref_add <= '1; // Ukládáme referenci
crc_en <= '1; // Počítáme CRC
pattern <= PATTERN_DDR; // Ukládáme z ROM
end
end else begin // Neni ROM jdeme do FW
if (ioctl_size[1] > '0) begin // Máme FW?
save_addr <= ddr3_addr - 1'b1; // Uchováme adresu -1 kvůli již načtenému prefetch bajtu
ddr3_addr <= 'h300010 + {cart_conf[conf[3][0]].typ,2'b00}; // FW Area + ID zařízení
ddr3_rd <= '1; // Preferch
read_cnt <= 4;
fw_space <= '1;
state <= STATE_READ_CONF; // Zahájíme LOAD
next_state <= STATE_GET_FW_ADDR;
end else begin
error <= ERR_NOT_FW_CONF; // FW není k dispozici
state <= STATE_IDLE;
end
end
end
BLOCK_MAPPER: begin
@@ -325,6 +357,28 @@ module memory_upload
mapper <= mapper_typ_t'(conf[3]);
state <= STATE_SET_LAYOUT;
end
BLOCK_DEVICE: begin
state <= STATE_SET_LAYOUT;
device <= device_t'(conf[3]);
if (~dev_enable[device_t'(conf[3])][0]) begin
dev_enable[device_t'(conf[3])][0] = '1;
device_num <= 0;
$display("DEVICE NUM: %d ENABLE", 1);
end else if (~dev_enable[device_t'(conf[3])][1]) begin
dev_enable[device_t'(conf[3])][1] = '1;
device_num <= 1;
$display("DEVICE NUM: %d ENABLE", 2);
end else if (~dev_enable[device_t'(conf[3])][2]) begin
dev_enable[device_t'(conf[3])][2] = '1;
device_num <= 2;
$display("DEVICE NUM: %d ENABLE", 3);
end else begin
error <= ERR_DEVICE_MISSING; // DEVICE JIZ NENI K DISPOZICI
state <= STATE_IDLE;
$display("DEVICE JIZ NENI K DISPOZICI");
device <= DEV_NONE;
end
end
default: begin
$display("BLOCK UNKNOWN");
error <= ERR_NOT_SUPPORTED_BLOCK;
@@ -332,6 +386,12 @@ module memory_upload
end
endcase
end
STATE_READ_ADRFILL_FW_ROM:begin
ddr3_addr <= DDR3_BASE_FW_ADDR + {conf[3],conf[2],conf[1],conf[0]};
ddr3_rd <= '1;
next_state <= STATE_READ_CONF;
state <= STATE_FILL_RAM;
end
STATE_FILL_RAM: begin
if (sdram_ready) begin // RAM je připravená
data_size <= data_size - 25'd1; // Snížíme velikost dat
@@ -345,12 +405,19 @@ module memory_upload
STATE_SET_LAYOUT: begin
if (size == 2'b00) begin // Kontrola, zda jsme na konci
if (ref_add) begin
ref_ram <= ref_ram + 1'd1; // Zvýšíme referenci o 1
ref_ram <= ref_ram + 1'd1; // Zvýšíme referenci o 1
end
if (save_addr2 != '0) begin // Pokud jsme jeli v ROM FW uložíme
ddr3_addr <= save_addr2;
save_addr2 <= '0;
ddr3_rd <= '1;
end
ref_add <= '0;
ref_sram_add <= '0;
state <= next_state;
next_state <= STATE_LOAD_CONF;
end
block <= block + 2'b01; // Další blok
@@ -378,7 +445,10 @@ module memory_upload
slot_layout[{slot, subslot, block}].ref_sram <= ref_sram;
end
// slot_layout[{slotSubslot, i[1:0]}].device
if (device != DEV_NONE) begin
slot_layout[{slot, subslot, block}].device_num <= device_num;
$display("BLOCK slot:%x subslot:%x block:%x < device:%x(id:%d) ", slot, subslot, block, device, device_num );
end
// slot_layout[{slotSubslot, i[1:0]}].external
if (subslot != 2'b00) begin
bios_config.slot_expander_en[slot] <= 1'b1;

9
rtl/peripheral/slots/msx_slots.sv
View File

@@ -79,7 +79,8 @@ wire [1:0] ref_sram = slot_layout[layout_id].ref_sram;
wire [1:0] offset_ram = slot_layout[layout_id].offset_ram;
wire cart_num = slot_layout[layout_id].cart_num;
wire external = slot_layout[layout_id].external;
assign device = slot_layout[layout_id].device;
wire [1:0] device_num = slot_layout[layout_id].device_num;
//assign device = slot_layout[layout_id].device;
assign mapper = selected_mapper[cart_num] == MAPPER_UNUSED & device == DEVICE_ROM & external ? MAPPER_UNUSED : slot_layout[layout_id].mapper;
wire [26:0] base_ram = lookup_RAM[ref_ram].addr;
@@ -89,7 +90,7 @@ wire [17:0] base_sram = lookup_SRAM[ref_sram].addr;
wire [15:0] sram_size = lookup_SRAM[ref_sram].size;
assign data = mapper_subslot_cs ? subslot_data : ram_dout;
assign data = mapper_subslot_cs ? subslot_data : ram_dout & mapper_data;
assign ram_din = cpu_data;
assign bram_ce = (sdram_size == 2'd0 & ram_cs) | sram_cs;
@@ -112,6 +113,7 @@ subslot subsloot
);
wire sram_cs, ram_cs, mem_rnw;
wire [7:0] mapper_data;
wire [26:0] mem_addr;
mappers mappers
(
@@ -130,7 +132,8 @@ mappers mappers
.mem_addr(mem_addr),
.mem_rnw(mem_rnw),
.ram_cs(ram_cs),
.sram_cs(sram_cs)
.sram_cs(sram_cs),
.data(mapper_data)
);
endmodule

2
rtl/video/vdp18v/vdp18_core.sv
View File

@@ -69,7 +69,7 @@
// you have the latest version of this file.
//
//-------------------------------------------------------------------------------
/*verilator tracing_on*/
/*verilator tracing_off*/
import vdp18_pack::*;
module vdp18_core #(

13
tools/CreateMSXpack/cart_device.json
View File

@@ -1,11 +1,8 @@
{
"KonamiSCC": 0,
"MEGA_FLASH_ROMs": 1,
"FM_PAC": 2,
"DEVICE": 3,
"MAPPER": 4,
"SLOT": 5,
"KonamiSCCs": 99,
"KonamiSCC+s": 99,
"RTYPE": 10,
"REF_DEV": 7,
"KonamiSCC+": 8
"FM_PAC": 3,
"GM2s": 99,
"MEGA_FLASH_ROMs": 99
}

5
tools/CreateMSXpack/createDev.py
View File

@@ -56,8 +56,9 @@ def parse_fw_block(root: ET.Element, subslot: int, files_with_sha1: dict, consta
if 'device' in block:
if block['device'] in constants['device']:
param1 = block.get('device_param', 0)
result.append(create_block_entry(constants, 'DEVICE', address, param1=param1))
param_dev = block.get('device_param', 0)
device_id = constants['device'][block['device']]
result.append(create_block_entry(constants, 'DEVICE', address, param1=device_id, param2 = param_dev))
else:
logger.warning(f"Unknown device type: {block['device']}")

5
tools/CreateMSXpack/device.json
View File

@@ -1,4 +1,5 @@
{
"SCC": 0,
"OPL3": 1
"NONE": 0,
"OPL3": 1,
"SCC": 2
}