mirror of
https://github.com/MiSTer-devel/MSX1_MiSTer.git
synced 2026-05-24 03:03:50 +00:00
543 lines
15 KiB
Systemverilog
543 lines
15 KiB
Systemverilog
module msx
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(
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input reset,
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//Clock
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input clk21m,
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input ce_10m7_p,
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input ce_3m58_p,
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input ce_3m58_n,
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input ce_5m39_n,
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input ce_10hz,
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input clk_sdram,
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//Video
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output [7:0] R,
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output [7:0] G,
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output [7:0] B,
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output DE,
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output HS,
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output VS,
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output hblank,
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output vblank,
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output ce_pix,
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//I/O
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output [15:0] audio,
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input [ 10:0] ps2_key,
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input [5:0] joy0,
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input [5:0] joy1,
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//Cassete
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output cas_motor,
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input cas_audio_in,
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//MSX config
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input [64:0] rtc_time,
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input MSX::bios_config_t bios_config,
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input MSX::user_config_t msxConfig,
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input dev_typ_t cart_device[2],
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input dev_typ_t msx_device,
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input [3:0] msx_dev_ref_ram[8],
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input mapper_typ_t selected_mapper[2],
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input sram_save,
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input sram_load,
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input [2:0] dev_enable[0:(1 << $bits(device_t))-1],
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//IOCTL
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input ioctl_download,
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input [15:0] ioctl_index,
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input [26:0] ioctl_addr,
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//SDRAM/BRAM
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output [26:0] ram_addr,
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output [7:0] ram_din,
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output ram_rnw,
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output sdram_ce,
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output bram_ce,
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input [7:0] ram_dout,
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input [1:0] sdram_size,
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input MSX::block_t slot_layout[64],
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input MSX::lookup_RAM_t lookup_RAM[16],
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input MSX::lookup_SRAM_t lookup_SRAM[4],
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//KBD
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input kbd_request,
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input [8:0] kbd_addr,
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input [7:0] kbd_din,
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input kbd_we,
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output [26:0] flash_addr,
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output [7:0] flash_din,
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output flash_req,
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input flash_ready,
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input flash_done,
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//SD FDC
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input img_mounted,
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input [31:0] img_size,
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input img_readonly,
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output [31:0] sd_lba,
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output sd_rd,
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output sd_wr,
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input sd_ack,
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input [13:0] sd_buff_addr,
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input [7:0] sd_buff_dout,
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output [7:0] sd_buff_din,
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input sd_buff_wr,
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output [7:0] d_to_sd,
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input [7:0] d_from_sd,
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output sd_tx,
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output sd_rx
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);
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/*verilator tracing_off*/
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// -----------------------------------------------------------------------------
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// -- Audio MIX
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// -----------------------------------------------------------------------------
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wire [15:0] compr[7:0];
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wire [9:0] audioPSG = ay_ch_mix + {keybeep,5'b00000} + {(cas_audio_in & ~cas_motor),4'b0000};
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wire [16:0] fm = {3'b00, audioPSG, 4'b0000};
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wire [16:0] audio_mix = {cart_sound[15], cart_sound} + fm;
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assign compr = '{ {1'b1, audio_mix[13:0], 1'b0}, 16'h8000, 16'h8000, 16'h8000, 16'h7FFF, 16'h7FFF, 16'h7FFF, {1'b0, audio_mix[13:0], 1'b0}};
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assign audio = compr[audio_mix[16:14]];
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// -----------------------------------------------------------------------------
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// -- T80 CPU
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// -----------------------------------------------------------------------------
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wire [15:0] a;
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wire [7:0] d_to_cpu, d_from_cpu;
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wire mreq_n, wr_n, m1_n, iorq_n, rd_n, rfrsh_n;
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/*
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t80pa #(.Mode(0)) T80
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(
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.RESET_n(~reset),
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.CLK(clk21m),
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.CEN_p(ce_3m58_p),
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.CEN_n(ce_3m58_n),
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.WAIT_n(wait_n),
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.INT_n(vdp_int_n),
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.NMI_n(1),
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.BUSRQ_n(1),
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.M1_n(m1_n),
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.MREQ_n(mreq_n),
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.IORQ_n(iorq_n),
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.RD_n(rd_n),
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.WR_n(wr_n),
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.RFSH_n(rfrsh_n),
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.HALT_n(1),
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.BUSAK_n(),
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.A(a),
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.DI(d_to_cpu),
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.DO(d_from_cpu)
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);
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*/
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/*verilator tracing_on*/
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tv80n Z80
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(
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.reset_n(~reset),
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.clk(ce_3m58_n),
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.wait_n(wait_n),
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.int_n(vdp_int_n),
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.nmi_n(1'b1),
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.busrq_n(1'b1),
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.m1_n(m1_n),
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.mreq_n(mreq_n),
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.iorq_n(iorq_n),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.rfsh_n(rfrsh_n),
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.halt_n(),
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.busak_n(),
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.A(a),
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.di(d_to_cpu),
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.dout(d_from_cpu)
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);
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/*verilator tracing_off*/
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// -----------------------------------------------------------------------------
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// -- WAIT CPU
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// -----------------------------------------------------------------------------
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wire exwait_n = 1;
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logic wait_n = 1'b0;
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always @(posedge clk21m, negedge exwait_n, negedge u1_2_q) begin
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if (~exwait_n)
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wait_n <= 1'b0;
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else if (~u1_2_q)
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wait_n <= 1'b1;
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else if (ce_3m58_p)
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wait_n <= m1_n;
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end
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logic u1_2_q = 1'b0;
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always @(posedge clk21m, negedge exwait_n) begin
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if (~exwait_n)
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u1_2_q <= 1'b1;
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else if (ce_3m58_p)
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u1_2_q <= wait_n;
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end
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logic map_valid = 0;
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wire ppi_en = ~ppi_n;
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wire [1:0] slot;
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always @(posedge reset, posedge clk21m) begin
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if (reset)
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map_valid = 0;
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else if (ppi_en)
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map_valid = 1;
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end
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assign slot = ~map_valid ? 2'b00 :
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a[15:14] == 2'b00 ? ppi_out_a[1:0] :
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a[15:14] == 2'b01 ? ppi_out_a[3:2] :
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a[15:14] == 2'b10 ? ppi_out_a[5:4] :
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ppi_out_a[7:6] ;
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// -----------------------------------------------------------------------------
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// -- IO Decoder
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// -----------------------------------------------------------------------------
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wire psg_n = ~((a[7:3] == 5'b10100) & ~iorq_n & m1_n);
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wire ppi_n = ~((a[7:3] == 5'b10101) & ~iorq_n & m1_n);
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wire vdp_en = (a[7:3] == 5'b10011) & ~iorq_n & m1_n ;
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wire rtc_en = (a[7:1] == 7'b1011010) & ~iorq_n & m1_n & bios_config.MSX_typ == MSX2;
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// -----------------------------------------------------------------------------
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// -- 82C55 PPI
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// -----------------------------------------------------------------------------
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wire [7:0] d_from_8255;
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wire [7:0] ppi_out_a, ppi_out_c;
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wire keybeep = ppi_out_c[7];
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assign cas_motor = ppi_out_c[4];
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jt8255 PPI
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(
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.rst(reset),
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.clk(clk21m),
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.addr(a[1:0]),
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.din(d_from_cpu),
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.dout(d_from_8255),
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.rdn(rd_n),
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.wrn(wr_n),
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.csn(ppi_n),
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.porta_din(8'h0),
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.portb_din(d_from_kb),
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.portc_din(8'h0),
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.porta_dout(ppi_out_a),
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.portb_dout(),
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.portc_dout(ppi_out_c)
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);
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// -----------------------------------------------------------------------------
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// -- CPU data multiplex
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// -----------------------------------------------------------------------------
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assign d_to_cpu = rd_n ? 8'hFF :
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vdp_en ? d_to_cpu_vdp :
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rtc_en ? d_from_rtc :
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~psg_n ? d_from_psg :
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~ppi_n ? d_from_8255 :
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d_from_slots ;
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// -----------------------------------------------------------------------------
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// -- Keyboard decoder
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// -----------------------------------------------------------------------------
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/*verilator tracing_on*/
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wire [7:0] d_from_kb;
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keyboard msx_key
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(
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.reset(reset),
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.clk(clk21m),
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.ps2_key(ps2_key),
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.kb_row(ppi_out_c[3:0]),
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.kb_data(d_from_kb),
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.kbd_addr(kbd_addr),
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.kbd_din(kbd_din),
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.kbd_we(kbd_we),
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.kbd_request(kbd_request)
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);
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/*verilator tracing_off*/
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// -----------------------------------------------------------------------------
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// -- Sound AY-3-8910
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// -----------------------------------------------------------------------------
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wire [7:0] d_from_psg, psg_ioa, psg_iob;
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wire [5:0] joy_a = psg_iob[4] ? 6'b111111 : {~joy0[5], ~joy0[4], ~joy0[0], ~joy0[1], ~joy0[2], ~joy0[3]};
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wire [5:0] joy_b = psg_iob[5] ? 6'b111111 : {~joy1[5], ~joy1[4], ~joy1[0], ~joy1[1], ~joy1[2], ~joy1[3]};
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wire [5:0] joyA = joy_a & {psg_iob[0], psg_iob[1], 4'b1111};
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wire [5:0] joyB = joy_b & {psg_iob[2], psg_iob[3], 4'b1111};
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assign psg_ioa = {cas_audio_in,1'b0, psg_iob[6] ? joyB : joyA};
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wire [9:0] ay_ch_mix;
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logic u21_1_q = 1'b0;
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always @(posedge clk21m, posedge psg_n) begin
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if (psg_n)
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u21_1_q <= 1'b0;
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else if (ce_3m58_p)
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u21_1_q <= ~psg_n;
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end
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logic u21_2_q = 1'b0;
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always @(posedge clk21m, posedge psg_n) begin
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if (psg_n)
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u21_2_q <= 1'b0;
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else if (ce_3m58_p)
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u21_2_q <= u21_1_q;
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end
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wire psg_e = !(!u21_2_q | ce_3m58_p) | psg_n;
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wire psg_bc = !(a[0] | psg_e);
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wire psg_bdir = !(a[1] | psg_e);
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jt49_bus PSG
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(
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.rst_n(~reset),
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.clk(clk21m),
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.clk_en(ce_3m58_p),
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.bdir(psg_bdir),
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.bc1(psg_bc),
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.din(d_from_cpu),
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.sel(0),
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.dout(d_from_psg),
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.sound(ay_ch_mix),
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.A(),
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.B(),
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.C(),
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.IOA_in(psg_ioa),
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.IOA_out(),
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.IOB_in(8'hFF),
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.IOB_out(psg_iob)
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);
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// -----------------------------------------------------------------------------
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// -- RTC
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// -----------------------------------------------------------------------------
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wire [7:0] d_from_rtc;
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rtc rtc
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(
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.clk21m(clk21m),
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.reset(reset),
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.setup(reset),
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.rt(rtc_time),
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.clkena(ce_10hz),
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.req(req & rtc_en),
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.ack(),
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.wrt(~wr_n),
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.adr(a),
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.dbi(d_from_rtc),
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.dbo(d_from_cpu)
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);
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/*verilator tracing_off*/
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// -----------------------------------------------------------------------------
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// -- Video
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// -----------------------------------------------------------------------------
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wire VRAM_we_lo_vdp, VRAM_we_hi_vdp, vdp18, vdp ;
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wire vdp_int_n;
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wire [7:0] d_to_cpu_vdp;
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assign vdp18 = bios_config.MSX_typ == MSX1;
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assign vdp = bios_config.MSX_typ == MSX2;
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//CPU access
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assign d_to_cpu_vdp = vdp18 ? d_from_vdp18 : d_from_vdp;
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assign vdp_int_n = vdp18 ? int_n_vdp18 : int_n_vdp;
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//Video access
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assign R = vdp18 ? R_vdp18 : {R_vdp,R_vdp[5:4]};
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assign G = vdp18 ? G_vdp18 : {G_vdp,G_vdp[5:4]};
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assign B = vdp18 ? B_vdp18 : {B_vdp,B_vdp[5:4]};
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assign HS = vdp18 ? ~HS_n_vdp18 : ~HS_n_vdp;
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assign VS = vdp18 ? ~VS_n_vdp18 : ~VS_n_vdp;
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assign DE = vdp18 ? DE_vdp18 : DE_vdp;
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assign hblank = vdp18 ? hblank_vdp18 : hblank_vdp_cor;
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assign vblank = vdp18 ? vblank_vdp18 : vblank_vdp;
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assign ce_pix = vdp18 ? ce_5m39_n : ~DHClk_vdp;
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logic hblank_vdp_cor;
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always @(posedge clk21m) begin
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if (hblank_vdp)
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hblank_vdp_cor <= 1'b1;
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else
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if (DHClk_vdp & DLClk_vdp)
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hblank_vdp_cor <= 1'b0;
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end
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//VRAM access
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assign VRAM_address = vdp18 ? {2'b00, VRAM_address_vdp18} : VRAM_address_vdp[15:0];
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assign VRAM_we_lo = vdp18 ? VRAM_we_vdp18 : VRAM_we_lo_vdp;
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assign VRAM_we_hi = vdp18 ? 1'b0 : VRAM_we_hi_vdp;
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assign VRAM_do = vdp18 ? VRAM_do_vdp18 : VRAM_do_vdp;
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assign VRAM_we_lo_vdp = ~VRAM_we_n_vdp & DLClk_vdp & ~VRAM_address_vdp[16];
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assign VRAM_we_hi_vdp = ~VRAM_we_n_vdp & DLClk_vdp & VRAM_address_vdp[16];
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logic iack;
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always @(posedge clk21m) begin
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if (reset) iack <= 0;
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else begin
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if (iorq_n & mreq_n)
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iack <= 0;
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else
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if (req)
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iack <= 1;
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end
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end
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wire req = ~((iorq_n & mreq_n) | (wr_n & rd_n) | iack);
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wire int_n_vdp18;
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wire [7:0] d_from_vdp18;
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wire [7:0] R_vdp18, G_vdp18, B_vdp18;
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wire HS_n_vdp18, VS_n_vdp18, DE_vdp18, DLClk_vdp18, hblank_vdp18, vblank_vdp18, Blank_vdp18;
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wire [13:0] VRAM_address_vdp18;
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wire [7:0] VRAM_do_vdp18;
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wire VRAM_we_vdp18;
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vdp18_core #(.compat_rgb_g(0)) vdp_vdp18
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(
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.clk_i(clk21m),
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.clk_en_10m7_i(ce_10m7_p),
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.reset_n_i(~reset),
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.csr_n_i(~(vdp_en & vdp18) | rd_n),
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.csw_n_i(~(vdp_en & vdp18) | wr_n),
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.mode_i(a[0]),
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.cd_i(d_from_cpu),
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.cd_o(d_from_vdp18),
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.int_n_o(int_n_vdp18),
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.vram_we_o(VRAM_we_vdp18),
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.vram_a_o(VRAM_address_vdp18),
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.vram_d_o(VRAM_do_vdp18),
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.vram_d_i(VRAM_di_lo),
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.border_i(msxConfig.border),
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.rgb_r_o(R_vdp18),
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.rgb_g_o(G_vdp18),
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.rgb_b_o(B_vdp18),
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.hsync_n_o(HS_n_vdp18),
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.vsync_n_o(VS_n_vdp18),
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.hblank_o(hblank_vdp18),
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.vblank_o(vblank_vdp18),
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.blank_n_o(DE_vdp18),
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.is_pal_i(msxConfig.video_mode == PAL)
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);
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/*verilator tracing_off*/
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wire int_n_vdp;
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wire [7:0] d_from_vdp;
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wire [5:0] R_vdp, G_vdp, B_vdp;
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wire HS_n_vdp, VS_n_vdp, DE_vdp, DLClk_vdp, DHClk_vdp, Blank_vdp, hblank_vdp, vblank_vdp;
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wire [16:0] VRAM_address_vdp;
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wire [7:0] VRAM_do_vdp;
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wire VRAM_we_n_vdp;
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vdp vdp_vdp
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(
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.CLK21M(clk21m),
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.RESET(reset),
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.REQ(req & vdp_en & vdp),
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.ACK(),
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.WRT(~wr_n),
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.ADR(a),
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.DBI(d_from_vdp),
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.DBO(d_from_cpu),
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.INT_N(int_n_vdp),
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.PRAMOE_N(),
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.PRAMWE_N(VRAM_we_n_vdp),
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.PRAMADR(VRAM_address_vdp),
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.PRAMDBI({VRAM_di_hi, VRAM_di_lo}),
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.PRAMDBO(VRAM_do_vdp),
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.VDPSPEEDMODE(0),
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.CENTERYJK_R25_N(0),
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.PVIDEOR(R_vdp),
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.PVIDEOG(G_vdp),
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.PVIDEOB(B_vdp),
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.PVIDEODE(DE_vdp),
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.BLANK_O(Blank_vdp),
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.HBLANK(hblank_vdp),
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.VBLANK(vblank_vdp),
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.PVIDEOHS_N(HS_n_vdp),
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.PVIDEOVS_N(VS_n_vdp),
|
|
.PVIDEOCS_N(),
|
|
.PVIDEODHCLK(DHClk_vdp),
|
|
.PVIDEODLCLK(DLClk_vdp),
|
|
.DISPRESO(/*msxConfig.scandoubler*/ 0),
|
|
.LEGACY_VGA(1),
|
|
.RATIOMODE(3'b000),
|
|
.NTSC_PAL_TYPE(msxConfig.video_mode == AUTO),
|
|
.FORCED_V_MODE(msxConfig.video_mode == PAL),
|
|
.BORDER(msxConfig.border)
|
|
);
|
|
|
|
wire [15:0] VRAM_address;
|
|
wire [7:0] VRAM_do, VRAM_di_lo, VRAM_di_hi;
|
|
wire VRAM_we_lo, VRAM_we_hi;
|
|
spram #(.addr_width(16),.mem_name("VRA2")) vram_lo
|
|
(
|
|
.clock(clk21m),
|
|
.address(VRAM_address),
|
|
.wren(VRAM_we_lo),
|
|
.data(VRAM_do),
|
|
.q(VRAM_di_lo)
|
|
);
|
|
spram #(.addr_width(16),.mem_name("VRA3")) vram_hi
|
|
(
|
|
.clock(clk21m),
|
|
.address(VRAM_address),
|
|
.wren(VRAM_we_hi),
|
|
.data(VRAM_do),
|
|
.q(VRAM_di_hi)
|
|
);
|
|
|
|
devices devices
|
|
(
|
|
.clk(clk21m),
|
|
.clk_en(ce_3m58_p),
|
|
.reset(reset),
|
|
.dev_enable(dev_enable), //Konfigurace zařízení z load. Povoluje jednotlivé zařízení
|
|
.device(),
|
|
.device_num(),
|
|
.dev_addr(),
|
|
.dev_din(),
|
|
.dev_dout(),
|
|
.dev_wr(),
|
|
.dev_rd(),
|
|
.sound()
|
|
);
|
|
|
|
/*verilator tracing_on*/
|
|
|
|
wire [7:0] d_from_slots;
|
|
wire signed [15:0] cart_sound;
|
|
msx_slots msx_slots
|
|
(
|
|
.clk(clk21m),
|
|
.clk_en(ce_3m58_p),
|
|
.reset(reset),
|
|
.cpu_addr(a),
|
|
.data(d_from_slots),
|
|
.cpu_data(d_from_cpu),
|
|
.cpu_iorq(~iorq_n),
|
|
.cpu_m1(~m1_n),
|
|
.cpu_mreq(~mreq_n),
|
|
.cpu_rd(~rd_n),
|
|
.cpu_wr(~wr_n),
|
|
.sound(cart_sound),
|
|
.ram_addr(ram_addr),
|
|
.ram_din(ram_din),
|
|
.ram_rnw(ram_rnw),
|
|
.ram_dout(ram_dout),
|
|
.sdram_ce(sdram_ce),
|
|
.bram_ce(bram_ce),
|
|
.sdram_size(sdram_size),
|
|
.flash_addr(flash_addr),
|
|
.flash_din(flash_din),
|
|
.flash_req(flash_req),
|
|
.flash_ready(flash_ready),
|
|
.flash_done(flash_ready),
|
|
.slot_layout(slot_layout),
|
|
.img_mounted(img_mounted),
|
|
.img_size(img_size),
|
|
.img_readonly(img_readonly),
|
|
.sd_lba(sd_lba),
|
|
.sd_rd(sd_rd),
|
|
.sd_wr(sd_wr),
|
|
.sd_ack(sd_ack),
|
|
.sd_buff_addr(sd_buff_addr),
|
|
.sd_buff_dout(sd_buff_dout),
|
|
.sd_buff_din(sd_buff_din),
|
|
.sd_buff_wr(sd_buff_wr),
|
|
.active_slot(slot),
|
|
.lookup_RAM(lookup_RAM),
|
|
.lookup_SRAM(lookup_SRAM),
|
|
.bios_config(bios_config),
|
|
.cart_device(cart_device),
|
|
.msx_device(msx_device),
|
|
.msx_dev_ref_ram(msx_dev_ref_ram),
|
|
.selected_mapper(selected_mapper),
|
|
.sd_tx(sd_tx),
|
|
.sd_rx(sd_rx),
|
|
.d_to_sd(d_to_sd),
|
|
.d_from_sd(d_from_sd)
|
|
);
|
|
|
|
endmodule |