mister-devel/Gameboy_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/Gameboy_MiSTer.git synced 2026-04-19 03:04:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

T80: fixed rst xx timing (16 cycles)

Browse Source
This commit is contained in:
Bruno Duarte Gouveia
2019-02-12 22:10:43 +00:00
committed by Bruno Gouveia
parent c02fced876
commit 6922b95fee
1 changed files with 33 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
t80/T80_MCode.vhd
View File

@@ -1364,25 +1364,41 @@ begin
-- RST p
if Mode = 3 then
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 3 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 4 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
else
MCycles <= "011";
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
end if;
-- INPUT AND OUTPUT GROUP
when "11011011" =>