From 6922b95feec2dbf27b1580340bd2efeddd8e5b42 Mon Sep 17 00:00:00 2001
From: Bruno Duarte Gouveia <bgouveia@gmail.com>
Date: Tue, 12 Feb 2019 22:10:43 +0000
Subject: [PATCH] T80: fixed rst xx timing (16 cycles)

---
 t80/T80_MCode.vhd | 50 +++++++++++++++++++++++++++++++----------------
 1 file changed, 33 insertions(+), 17 deletions(-)

diff --git a/t80/T80_MCode.vhd b/t80/T80_MCode.vhd
index 60bfa01..3df2a17 100644
--- a/t80/T80_MCode.vhd
+++ b/t80/T80_MCode.vhd
@@ -1364,25 +1364,41 @@ begin
 			-- RST p
 			if Mode = 3 then
 				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 3 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 4 =>
+					Write <= '1';
+					RstP <= '1';
+				when others => null;
+				end case;
 			else
 				MCycles <= "011";
-			end if;
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					Write <= '1';
+					RstP <= '1';
+				when others => null;
+				end case;
+		   end if;
 
 -- INPUT AND OUTPUT GROUP
 		when "11011011" =>