Andre Zeps f7bd5d3d73 FMV: Improved frame pacing ...

- 25 fps hard coded for experiments
- Presentation time utilized to define start of playback
  - Makes use of FIFO structure for stable frame rate
- Firmware
  - Provides all 3 planar framebuffers to hardware for playback

2025-09-15 16:09:35 +02:00

..

.clang-format

First public release

2024-07-08 19:22:59 +02:00

.gitignore

Added simulatable MPEG video decoder

2025-09-08 23:46:32 +02:00

analysis.gtkw

FMV: Improved P and B frames

2025-09-12 16:36:04 +02:00

byte_word_test.asm

Boot fixes and video implementation

2024-08-17 22:32:51 +02:00

cdic_audiomap.asm

CDIC: Rewritten audio state machine

2025-03-17 21:58:10 +01:00

cdic_cdda_play.asm

CDIC: Rewritten audio state machine

2025-03-17 21:58:10 +01:00

cdic_data.asm

CDIC: Add audiomap and related features

2024-11-15 12:18:55 +01:00

cdic_sector_send.asm

CDIC: Add Seek command and subchannel data frame

2024-12-23 02:04:45 +01:00

cdic_xa_play.asm

AD7528: Reduces volume of input to 56%

2025-03-28 19:27:09 +01:00

crc.h

MPEG video decoder synthesizable for MiSTer

2025-09-09 00:06:42 +02:00

create_wav.sh

MPEG Audio is working

2025-07-15 20:49:26 +02:00

hle.h

Boot fixes and video implementation

2024-08-17 22:32:51 +02:00

memtest.asm

DVC test with SkyWays

2025-06-11 18:48:11 +02:00

memzero.asm

DVC test with SkyWays

2025-06-11 18:48:11 +02:00

nvram_backup_restore.asm

HPS: Added NvRAM backup and restore

2024-12-12 07:29:13 +01:00

nvramsender.asm

HPS: Added NvRAM backup and restore

2024-12-12 07:29:13 +01:00

pl_mpeg_pc.h

Added simulatable MPEG video decoder

2025-09-08 23:46:32 +02:00

produce_cdi_rom.sh

DVC test with SkyWays

2025-06-11 18:48:11 +02:00

produce_test_rom.sh

MPEG video decoder synthesizable for MiSTer

2025-09-09 00:06:42 +02:00

ramsender.asm

DVC test with SkyWays

2025-06-11 18:48:11 +02:00

rc5_joy_upwards.csv

68HC05: Added Input Capture registers and adjusted clock frequency

2025-04-14 09:54:22 +02:00

romsender.asm

DVC test with SkyWays

2025-06-11 18:48:11 +02:00

scramble.h

MPEG video decoder synthesizable for MiSTer

2025-09-09 00:06:42 +02:00

sim_slave.cpp

First public release

2024-07-08 19:22:59 +02:00

sim_slave.sh

First public release

2024-07-08 19:22:59 +02:00

sim_top.cpp

FMV: Improved frame pacing

2025-09-15 16:09:35 +02:00

sim_top.sh

Added simulatable MPEG video decoder

2025-09-08 23:46:32 +02:00

slavetest.asm

68HC05: Added Input Capture registers and adjusted clock frequency

2025-04-14 09:54:22 +02:00

table_of_contents.h

MPEG video decoder synthesizable for MiSTer

2025-09-09 00:06:42 +02:00

tb_slave.sv

First public release

2024-07-08 19:22:59 +02:00

tg68kdotc_verilog_wrapper.v

SCC68070: Timing accuracy of multiplication and bit shift

2025-02-23 21:03:00 +01:00

uarttest.asm

SCC68070: Fixed UART IRQ handling

2024-11-20 19:33:10 +01:00

unaligned_video_test.asm

MCD212: Added video plane visibility debug option

2024-12-12 17:36:15 +01:00

ur6805.v

moved generated code to verilator folder

2024-09-09 13:34:13 +02:00

videosim_top.cpp

MCD212: Display Active flag adapted to measured timing

2025-04-06 12:13:03 +02:00

videosim.sh

Utilized PES PTS for playback start

2025-07-20 19:20:19 +02:00

vmpegtest.asm

MPEG video decoder synthesizable for MiSTer

2025-09-09 00:06:42 +02:00