mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-05-24 03:03:09 +00:00
FMV: Improved frame pacing
- 25 fps hard coded for experiments - Presentation time utilized to define start of playback - Makes use of FIFO structure for stable frame rate - Firmware - Provides all 3 planar framebuffers to hardware for playback
This commit is contained in:
Andre Zeps
@@ -33,9 +33,9 @@ CD images can be stored as CHD or CUE/BIN format.
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Core Utilization:
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Logic utilization (in ALMs) 24,631 / 41,910 ( 59 % )
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Total registers 29008
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Total block memory bits 1,896,711 / 5,662,720 ( 33 % )
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Logic utilization (in ALMs) 24,331 / 41,910 ( 58 % )
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Total registers 28509
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Total block memory bits 1,897,911 / 5,662,720 ( 34 % )
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Total DSP Blocks 92 / 112 ( 82 % )
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Expected synthesis times with Quartus 17.0.2
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@@ -30,6 +30,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/mpeg/fmv/mpeg_input_stream_fi
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/mpeg/fmv/mpeg_video_start_code_decoder.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/mpeg/fmv/mpeg_video.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/mpeg/fmv/worker_firmware_memory.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/mpeg/fmv/yuv_frame_adr_fifo.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/mpeg/VexiiRiscv.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/pointing_device.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/resetdelay.sv
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@@ -49,4 +50,4 @@ set_global_assignment -name VHDL_FILE tg68k/tg68dotc_verilog_wrapper.vhd
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set_global_assignment -name VHDL_FILE tg68k/TG68K_ALU.vhd
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set_global_assignment -name VHDL_FILE tg68k/TG68K_Pack.vhd
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set_global_assignment -name VHDL_FILE tg68k/TG68K.vhd
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set_global_assignment -name VHDL_FILE tg68k/TG68KdotC_Kernel.vhd
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set_global_assignment -name VHDL_FILE tg68k/TG68KdotC_Kernel.vhd
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@@ -1243,9 +1243,6 @@ module mcd212 (
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end
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vsd = backdrop_pixel && image_coding_method_register.ev;
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`ifdef VERILATOR
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vsd = 1;
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`endif
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end
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// Implementation of Table 5-13 Register Map
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@@ -8,48 +8,49 @@ module mpeg_demuxer (
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output bit signed [32:0] system_clock_reference_start_time,
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output bit system_clock_reference_start_time_valid
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);
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parameter string unit = "";
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enum bit [4:0] {
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FMA_IDLE,
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FMA_MAGIC0,
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FMA_MAGIC1,
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FMA_MAGIC2,
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FMA_MAGIC3,
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FMA_MAGIC_MATCH,
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FMA_PACK0,
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FMA_PACK1,
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FMA_PACK2,
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FMA_PACK3,
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FMA_PACK4,
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FMA_PACK5,
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FMA_PES0,
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FMA_PES1,
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FMA_PES2,
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FMA_PES3,
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FMA_PES4,
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FMA_PES5,
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FMA_PES6,
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FMA_PES7,
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FMA_PES8,
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FMA_PES_DTS0,
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FMA_PES_DTS1,
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FMA_PES_DTS2,
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FMA_PES_DTS3,
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FMA_PES_DTS4
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IDLE,
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MAGIC0,
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MAGIC1,
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MAGIC2,
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MAGIC3,
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MAGIC_MATCH,
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PACK0,
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PACK1,
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PACK2,
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PACK3,
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PACK4,
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PACK5,
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PES0,
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PES1,
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PES2,
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PES3,
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PES4,
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PES5,
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PES6,
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PES7,
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PES8,
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PES_DTS0,
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PES_DTS1,
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PES_DTS2,
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PES_DTS3,
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PES_DTS4
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} demux_state = FMA_IDLE;
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} demux_state = IDLE;
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bit packet_length_decreasing;
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bit [15:0] packet_length;
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bit signed [32:0] system_clock_reference;
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bit [9:0] pack_cnt = 0;
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bit [32:0] presentation_time_stamp;
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bit [32:0] decoding_time_stamp;
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bit signed [32:0] presentation_time_stamp;
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bit signed [32:0] decoding_time_stamp;
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bit dts_present;
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always_ff @(posedge clk) begin
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if (reset) begin
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demux_state <= FMA_IDLE;
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demux_state <= IDLE;
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system_clock_reference_start_time_valid <= 0;
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end else if (data_valid) begin
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@@ -64,140 +65,144 @@ module mpeg_demuxer (
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casez ({
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demux_state, mpeg_data
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})
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// verilog_format: off
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{FMA_PACK5, 8'h??}: begin
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demux_state <= FMA_IDLE;
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$display ("FMA PACK %x %d",mpeg_data,system_clock_reference);
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{PACK5, 8'h??}: begin
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demux_state <= IDLE;
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$display ("%s PACK %d", unit, system_clock_reference);
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end
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{FMA_PACK4, 8'h??}: begin
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demux_state <= FMA_PACK5;
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{PACK4, 8'h??}: begin
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demux_state <= PACK5;
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system_clock_reference[6:0] <= mpeg_data[7:1];
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pack_cnt <= pack_cnt +1;
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end
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{FMA_PACK3, 8'h??}: begin
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demux_state <= FMA_PACK4;
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{PACK3, 8'h??}: begin
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demux_state <= PACK4;
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system_clock_reference[14:7] <= mpeg_data;
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end
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{FMA_PACK2, 8'h??}: begin
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demux_state <= FMA_PACK3;
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{PACK2, 8'h??}: begin
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demux_state <= PACK3;
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system_clock_reference[21:15] <= mpeg_data[7:1];
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end
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{FMA_PACK1, 8'h??}: begin
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demux_state <= FMA_PACK2;
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{PACK1, 8'h??}: begin
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demux_state <= PACK2;
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system_clock_reference[29:22] <= mpeg_data;
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end
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{FMA_PACK0, 8'h??}: begin
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demux_state <= FMA_PACK1;
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{PACK0, 8'h??}: begin
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demux_state <= PACK1;
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system_clock_reference[32:30] <= mpeg_data[3:1];
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end
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{FMA_PES8, 8'h??}: begin
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demux_state <= FMA_IDLE;
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$display ("FMA PES %x %d",mpeg_data,presentation_time_stamp);
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{PES8, 8'h??}: begin
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demux_state <= IDLE;
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if (dts_present)
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$display ("%s PES %d %d", unit, presentation_time_stamp, decoding_time_stamp);
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else
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$display ("%s PES %d", unit, presentation_time_stamp);
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// verilog_format: on
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if (!system_clock_reference_start_time_valid) begin
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system_clock_reference_start_time_valid <= 1;
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system_clock_reference_start_time[32:1] <= dclk + presentation_time_stamp[32:1] - system_clock_reference[32:1];
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end
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// verilog_format: off
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end
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{FMA_PES_DTS4, 8'b???????1}: begin // DTS
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{PES_DTS4, 8'b???????1}: begin // DTS
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decoding_time_stamp[6:0] <= mpeg_data[7:1];
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mpeg_packet_body <= 1;
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demux_state <= FMA_PES8;
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demux_state <= PES8;
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end
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{FMA_PES_DTS3, 8'h??}: begin // DTS
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demux_state <= FMA_PES_DTS4;
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{PES_DTS3, 8'h??}: begin // DTS
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demux_state <= PES_DTS4;
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decoding_time_stamp[14:7] <= mpeg_data;
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end
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{FMA_PES_DTS2, 8'b???????1}: begin // DTS
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{PES_DTS2, 8'b???????1}: begin // DTS
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decoding_time_stamp[21:15] <= mpeg_data[7:1];
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demux_state <= FMA_PES_DTS3;
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demux_state <= PES_DTS3;
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end
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{FMA_PES_DTS1, 8'h??}: begin // DTS
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demux_state <= FMA_PES_DTS2;
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{PES_DTS1, 8'h??}: begin // DTS
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demux_state <= PES_DTS2;
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decoding_time_stamp[29:22] <= mpeg_data;
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end
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{FMA_PES_DTS0, 8'b0001???1}: begin // DTS
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{PES_DTS0, 8'b0001???1}: begin // DTS
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decoding_time_stamp[32:30] <= mpeg_data[3:1];
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demux_state <= FMA_PES_DTS1;
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demux_state <= PES_DTS1;
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end
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{FMA_PES7, 8'b???????1}: begin // PTS
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{PES7, 8'b???????1}: begin // PTS
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presentation_time_stamp[6:0] <= mpeg_data[7:1];
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if (dts_present) begin
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demux_state <= FMA_PES_DTS0;
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demux_state <= PES_DTS0;
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end else begin
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mpeg_packet_body <= 1;
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demux_state <= FMA_PES8;
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demux_state <= PES8;
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end
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end
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{FMA_PES6, 8'h??}: begin // PTS
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demux_state <= FMA_PES7;
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{PES6, 8'h??}: begin // PTS
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demux_state <= PES7;
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presentation_time_stamp[14:7] <= mpeg_data;
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end
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{FMA_PES5, 8'b???????1}: begin // PTS
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{PES5, 8'b???????1}: begin // PTS
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presentation_time_stamp[21:15] <= mpeg_data[7:1];
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demux_state <= FMA_PES6;
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demux_state <= PES6;
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end
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{FMA_PES4, 8'h??}: begin // PTS
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demux_state <= FMA_PES5;
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{PES4, 8'h??}: begin // PTS
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demux_state <= PES5;
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presentation_time_stamp[29:22] <= mpeg_data;
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end
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{FMA_PES2, 8'b0010???1}: begin // PTS (no DTS)
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{PES2, 8'b0010???1}: begin // PTS (no DTS)
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presentation_time_stamp[32:30] <= mpeg_data[3:1];
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dts_present <= 0;
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demux_state <= FMA_PES4;
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demux_state <= PES4;
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end
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{FMA_PES2, 8'b0011???1}: begin // PTS and DTS
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{PES2, 8'b0011???1}: begin // PTS and DTS
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presentation_time_stamp[32:30] <= mpeg_data[3:1];
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dts_present <= 1;
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demux_state <= FMA_PES4;
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demux_state <= PES4;
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end
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{FMA_PES2, 8'b00001111}: begin // Neither PTS nor DTS
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demux_state <= FMA_IDLE;
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{PES2, 8'b00001111}: begin // Neither PTS nor DTS
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demux_state <= IDLE;
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mpeg_packet_body <= 1;
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$display ("%s PES ...", unit);
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end
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{FMA_PES3, 8'h??}: begin
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{PES3, 8'h??}: begin
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// just ignore STD buffer size second byte
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demux_state <= FMA_PES2;
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demux_state <= PES2;
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end
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{FMA_PES2, 8'b01??????}: begin // STD buffer size
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demux_state <= FMA_PES3;
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{PES2, 8'b01??????}: begin // STD buffer size
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demux_state <= PES3;
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end
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{FMA_PES2, 8'hff}: begin // stuffing byte
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demux_state <= FMA_PES2;
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{PES2, 8'hff}: begin // stuffing byte
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demux_state <= PES2;
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end
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{FMA_PES1, 8'h??}: begin
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demux_state <= FMA_PES2;
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{PES1, 8'h??}: begin
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demux_state <= PES2;
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packet_length[7:0] <= mpeg_data;
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packet_length_decreasing <= 1;
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end
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{FMA_PES0, 8'h??}: begin
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demux_state <= FMA_PES1;
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{PES0, 8'h??}: begin
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demux_state <= PES1;
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packet_length[15:8] <= mpeg_data;
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end
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{FMA_MAGIC_MATCH, 8'hba} : begin
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demux_state <= FMA_PACK0;
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{MAGIC_MATCH, 8'hba} : begin
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demux_state <= PACK0;
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end
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{FMA_MAGIC_MATCH, 8'hC?} : begin
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demux_state <= FMA_PES0;
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{MAGIC_MATCH, 8'hC?} : begin
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demux_state <= PES0;
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end
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{FMA_MAGIC_MATCH, 8'hE?} : begin
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demux_state <= FMA_PES0;
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{MAGIC_MATCH, 8'hE?} : begin
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demux_state <= PES0;
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end
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{FMA_MAGIC2, 8'h01} : demux_state <= FMA_MAGIC_MATCH;
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{FMA_MAGIC2, 8'h00} : demux_state <= FMA_MAGIC2;
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{FMA_MAGIC0, 8'h00} : demux_state <= FMA_MAGIC2;
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{FMA_IDLE, 8'h00} : demux_state <= FMA_MAGIC0;
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default: demux_state <= FMA_IDLE;
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{MAGIC2, 8'h01} : demux_state <= MAGIC_MATCH;
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{MAGIC2, 8'h00} : demux_state <= MAGIC2;
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{MAGIC0, 8'h00} : demux_state <= MAGIC2;
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{IDLE, 8'h00} : demux_state <= MAGIC0;
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default: demux_state <= IDLE;
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// verilog_format: on
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endcase
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@@ -21,13 +21,13 @@ module mpeg_audiofifo (
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bit indizes_equal_during_write_d;
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bit indizes_equal_during_write_q;
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assign out.write = count != 0 && !reset && !indizes_equal_during_write_q;
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assign in.strobe = count < 510 && !reset && in.write;
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assign out.write = count != 0 && !reset && !indizes_equal_during_write_q;
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assign in.strobe = count < 510 && !reset && in.write;
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// Every MPEG synthesis will create 32 samples
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// Let's have at least 70 samples to not starve during frame change
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assign nearly_full = count >= 510;
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assign half_full = count >= 70;
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assign half_full = count >= 70;
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always_comb begin
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read_index_d = read_index_q;
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@@ -60,4 +60,4 @@ module dual_port_videoram #(
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assign data_out2 = data_reg2;
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endmodule : dual_port_videoram
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endmodule : dual_port_videoram
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@@ -1,25 +1,25 @@
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00003117
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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@@ -173,11 +179,11 @@ cb158a32
|
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00230731
|
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640900d7
|
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|
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|
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|
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@@ -274,7 +280,7 @@ fee78de3
|
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|
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|
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|
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|
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|
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|
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|
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@@ -296,7 +302,7 @@ c50348a1
|
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471cc71c
|
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|
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85936589
|
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@@ -391,14 +397,14 @@ d78ccfc8
|
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610506a8
|
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|
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|
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@@ -407,9 +413,9 @@ f1c58593
|
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|
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|
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@@ -424,7 +430,7 @@ fe851ee3
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|
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|
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@@ -527,19 +533,19 @@ df934017
|
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|
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|
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|
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@@ -553,15 +559,15 @@ c15001c5
|
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|
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|
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|
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|
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|
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@@ -678,18 +684,18 @@ ce62d05e
|
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|
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|
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|
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|
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|
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|
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|
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@@ -764,7 +770,7 @@ ac2342c7
|
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|
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|
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|
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|
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|
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|
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|
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@@ -802,8 +808,8 @@ c7901000
|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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@@ -866,15 +872,15 @@ c7637ff0
|
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|
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|
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|
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@@ -957,7 +963,7 @@ c86e019a
|
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@@ -976,11 +982,11 @@ bdd197b2
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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@@ -1072,7 +1078,7 @@ cad1d43c
|
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|
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|
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|
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|
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|
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|
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|
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|
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@@ -1457,8 +1463,8 @@ ff010113
|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
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@@ -1470,8 +1476,8 @@ ff010113
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
@@ -1616,9 +1622,9 @@ fed70fa3
|
||||
00158593
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@@ -1850,9 +1856,9 @@ fff50000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000002
|
||||
00000004
|
||||
00000006
|
||||
|
||||
@@ -16,19 +16,19 @@ module frameplayer (
|
||||
input hblank,
|
||||
input vblank,
|
||||
|
||||
input [28:0] frame_adr,
|
||||
input planar_yuv_s frame,
|
||||
input latch_frame
|
||||
);
|
||||
|
||||
assign ddrif.byteenable = 8'hff;
|
||||
assign ddrif.write = 0;
|
||||
|
||||
bit [28:0] latched_frame_adr = 0;
|
||||
planar_yuv_s latched_frame;
|
||||
|
||||
always_ff @(posedge clkddr) begin
|
||||
if (latch_frame) begin
|
||||
latched_frame_adr <= frame_adr;
|
||||
$display("Latched frame %x", latched_frame_adr);
|
||||
latched_frame <= frame;
|
||||
//$display("Latched frame %x", latched_frame);
|
||||
end
|
||||
end
|
||||
|
||||
@@ -173,9 +173,9 @@ module frameplayer (
|
||||
|
||||
if (reset_clkddr || vblank_clkddr) begin
|
||||
fetchstate <= IDLE;
|
||||
address_y <= latched_frame_adr + 29'h0;
|
||||
address_v <= latched_frame_adr + 29'h15900; // 368*240 = 88320
|
||||
address_u <= latched_frame_adr + 29'h1af40; // 368*240 + 88320/4
|
||||
address_y <= latched_frame.y_adr;
|
||||
address_u <= latched_frame.u_adr;
|
||||
address_v <= latched_frame.v_adr;
|
||||
target_y <= 0;
|
||||
target_u <= 0;
|
||||
target_v <= 0;
|
||||
|
||||
@@ -19,4 +19,4 @@ module mpeg_input_stream_fifo_32k (
|
||||
always_ff @(posedge clkr) begin
|
||||
q <= ram[raddr];
|
||||
end
|
||||
endmodule : mpeg_input_stream_fifo_32k
|
||||
endmodule : mpeg_input_stream_fifo_32k
|
||||
|
||||
@@ -6,6 +6,7 @@ module mpeg_video (
|
||||
input clk60,
|
||||
input reset,
|
||||
input dsp_enable,
|
||||
input playback_active,
|
||||
|
||||
input [7:0] data_byte,
|
||||
input data_strobe,
|
||||
@@ -698,12 +699,9 @@ module mpeg_video (
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// Assuming 90 MHz clock rate and 25 Hz frame rate
|
||||
localparam TICKS_PER_FRAME = 1200000 * 3;
|
||||
planar_yuv_s just_decoded;
|
||||
|
||||
bit signed [15:0] shared_buffer_level = 0;
|
||||
|
||||
@@ -761,6 +759,12 @@ module mpeg_video (
|
||||
4'd4: begin // Shared SRAM region
|
||||
end
|
||||
4'd1: begin
|
||||
if (dmem_cmd_payload_address_1[15:0] == 16'h3000)
|
||||
just_decoded.y_adr <= dmem_cmd_payload_data_1[28:0];
|
||||
if (dmem_cmd_payload_address_1[15:0] == 16'h3004)
|
||||
just_decoded.u_adr <= dmem_cmd_payload_data_1[28:0];
|
||||
if (dmem_cmd_payload_address_1[15:0] == 16'h3008)
|
||||
just_decoded.v_adr <= dmem_cmd_payload_data_1[28:0];
|
||||
end
|
||||
4'd0: begin
|
||||
end
|
||||
@@ -1021,6 +1025,55 @@ module mpeg_video (
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
planar_yuv_s for_display;
|
||||
wire just_decoded_commit = dmem_cmd_payload_write_1 && dmem_cmd_valid_1 && dmem_cmd_ready_1 && dmem_cmd_payload_address_1==32'h10003010;
|
||||
wire for_display_valid;
|
||||
bit for_display_strobe;
|
||||
bit latch_frame_for_display;
|
||||
wire latch_frame_for_display_clk60;
|
||||
|
||||
// Assuming 30 MHz clock rate and 25 Hz frame rate
|
||||
localparam bit [23:0] TICKS_PER_FRAME = 24'(int'(30e6) / 25);
|
||||
bit [23:0] playback_frame_cnt;
|
||||
|
||||
// In theory this machine could run with clk60.
|
||||
// But I'm not so sure about the final frequency and timing is vital
|
||||
always_ff @(posedge clk30) begin
|
||||
latch_frame_for_display <= 0;
|
||||
|
||||
if (!playback_active) playback_frame_cnt <= 0;
|
||||
else begin
|
||||
playback_frame_cnt <= playback_frame_cnt + 1;
|
||||
|
||||
// Only for simulation. Ensure that frames are always available - no underflow
|
||||
if (playback_frame_cnt == 0) assert (for_display_valid);
|
||||
|
||||
if (playback_frame_cnt == TICKS_PER_FRAME - 1) playback_frame_cnt <= 0;
|
||||
if (playback_frame_cnt == 0 && for_display_valid) latch_frame_for_display <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
flag_cross_domain cross_latch_frame (
|
||||
.clk_a(clk30),
|
||||
.clk_b(clk60),
|
||||
.flag_in_clk_a(latch_frame_for_display),
|
||||
.flag_out_clk_b(latch_frame_for_display_clk60)
|
||||
);
|
||||
|
||||
|
||||
yuv_frame_adr_fifo readyframes (
|
||||
.clk_in(clk60),
|
||||
.reset_in(reset_dsp_enabled_clk60),
|
||||
.wdata(just_decoded),
|
||||
.we(just_decoded_commit),
|
||||
.reset_out(reset_dsp_enabled_clk60),
|
||||
.clk_out(clk60),
|
||||
.strobe(latch_frame_for_display_clk60),
|
||||
.valid(for_display_valid),
|
||||
.q(for_display)
|
||||
);
|
||||
|
||||
frameplayer frameplayer (
|
||||
.clk(clk30),
|
||||
.clkddr(clk60),
|
||||
@@ -1031,8 +1084,8 @@ module mpeg_video (
|
||||
.vsync,
|
||||
.hblank,
|
||||
.vblank,
|
||||
.frame_adr(dmem_cmd_payload_data_1[28:0]),
|
||||
.latch_frame(expose_frame_y_adr_clk60)
|
||||
.frame(for_display),
|
||||
.latch_frame(latch_frame_for_display)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -11,11 +11,13 @@ module mpeg_video_start_code_decoder (
|
||||
output bit [31:0] timecode
|
||||
);
|
||||
|
||||
bit [9:0] temperal_sequence_number;
|
||||
bit [9:0] temporal_sequence_number;
|
||||
bit [9:0] next_sequence_number;
|
||||
bit [9:0] gop_cnt = 0;
|
||||
bit [2:0] coding_type;
|
||||
bit [15:0] vbv_delay;
|
||||
|
||||
enum bit [3:0] {
|
||||
enum bit [4:0] {
|
||||
IDLE,
|
||||
MAGIC0,
|
||||
MAGIC1,
|
||||
@@ -30,6 +32,7 @@ module mpeg_video_start_code_decoder (
|
||||
PIC1,
|
||||
PIC2,
|
||||
PIC3,
|
||||
PIC4,
|
||||
SLICE0,
|
||||
SEQHDR
|
||||
} finder_state = IDLE;
|
||||
@@ -46,29 +49,38 @@ module mpeg_video_start_code_decoder (
|
||||
})
|
||||
// verilog_format: off
|
||||
|
||||
{PIC3, 8'h??}: begin finder_state <= IDLE;
|
||||
$display ("PIC3 %x",mpeg_data);
|
||||
{PIC4, 8'h??}: begin
|
||||
finder_state <= IDLE;
|
||||
$display ("PIC4 %d %d %d", temporal_sequence_number, coding_type, vbv_delay);
|
||||
event_picture <= 1;
|
||||
end
|
||||
{PIC3, 8'h??}: begin
|
||||
finder_state <= PIC4;
|
||||
//$display ("PIC3");
|
||||
vbv_delay[4:0] <= mpeg_data[7:3];
|
||||
end
|
||||
{PIC2, 8'h??}: begin
|
||||
finder_state <= PIC3;
|
||||
if (next_sequence_number == temperal_sequence_number)
|
||||
if (next_sequence_number == temporal_sequence_number)
|
||||
begin
|
||||
tmpref[11:2] <= temperal_sequence_number;
|
||||
$display ("PIC2 %x %d",mpeg_data,temperal_sequence_number);
|
||||
tmpref[11:2] <= temporal_sequence_number;
|
||||
$display ("PIC2 %d", temporal_sequence_number);
|
||||
next_sequence_number <= next_sequence_number + 1;
|
||||
end
|
||||
end
|
||||
vbv_delay[12:5] <= mpeg_data;
|
||||
end
|
||||
{PIC1, 8'h??}: begin
|
||||
finder_state <= PIC2;
|
||||
//$display ("PIC1 %x",mpeg_data);
|
||||
temperal_sequence_number[1:0] <= mpeg_data[7:6];
|
||||
end
|
||||
temporal_sequence_number[1:0] <= mpeg_data[7:6];
|
||||
coding_type <= mpeg_data[5:3];
|
||||
vbv_delay[15:13] <= mpeg_data[2:0];
|
||||
end
|
||||
{PIC0, 8'h??}: begin
|
||||
finder_state <= PIC1;
|
||||
//$display ("PIC0 %x",mpeg_data);
|
||||
temperal_sequence_number[9:2] <= mpeg_data;
|
||||
end
|
||||
temporal_sequence_number[9:2] <= mpeg_data;
|
||||
end
|
||||
{GOP3, 8'h??}: begin
|
||||
finder_state <= IDLE;
|
||||
$display ("GOP3 %x",mpeg_data);
|
||||
|
||||
@@ -64,4 +64,4 @@ module worker_firmware_memory #(
|
||||
|
||||
assign data_out2 = data_reg2;
|
||||
|
||||
endmodule : worker_firmware_memory
|
||||
endmodule : worker_firmware_memory
|
||||
|
||||
80
rtl/mpeg/fmv/yuv_frame_adr_fifo.sv
Normal file
80
rtl/mpeg/fmv/yuv_frame_adr_fifo.sv
Normal file
@@ -0,0 +1,80 @@
|
||||
`include "../util.svh"
|
||||
|
||||
module yuv_frame_adr_fifo (
|
||||
// Input
|
||||
input clk_in,
|
||||
input reset_in,
|
||||
input planar_yuv_s wdata,
|
||||
input we,
|
||||
// Output
|
||||
input reset_out,
|
||||
input clk_out,
|
||||
input strobe,
|
||||
output bit valid,
|
||||
output planar_yuv_s q
|
||||
);
|
||||
|
||||
planar_yuv_s ram[16];
|
||||
|
||||
// Clock domain of output
|
||||
bit [3:0] raddr; // 512 x 8
|
||||
|
||||
// Clock domain of input
|
||||
bit [3:0] waddr; // 64 x 64
|
||||
|
||||
// verilog_format: off
|
||||
// Transfer waddr from clk_in to clk_out
|
||||
bit [3:0] waddr_gray;
|
||||
b2g_converter #(.WIDTH(4)) waddr_to_gray1 (.binary(waddr),.gray(waddr_gray));
|
||||
bit [3:0] waddr_q;
|
||||
bit [3:0] waddr_q2;
|
||||
bit [3:0] waddr_q3;
|
||||
always @(posedge clk_in) waddr_q <= waddr_gray;
|
||||
always @(posedge clk_out) waddr_q2 <= waddr_q;
|
||||
always @(posedge clk_out) waddr_q3 <= waddr_q2;
|
||||
bit [3:0] waddr_clkout;
|
||||
g2b_converter #(.WIDTH(4)) waddr_to_binary1 (.binary(waddr_clkout),.gray(waddr_q3));
|
||||
|
||||
// Transfer raddr from clk_out to clk_in
|
||||
bit [3:0] raddr_gray;
|
||||
b2g_converter #(.WIDTH(4)) raddr_to_gray2 (.binary(raddr),.gray(raddr_gray));
|
||||
bit [3:0] raddr_q;
|
||||
bit [3:0] raddr_q2;
|
||||
bit [3:0] raddr_q3;
|
||||
always @(posedge clk_out) raddr_q <= raddr_gray;
|
||||
always @(posedge clk_in) raddr_q2 <= raddr_q;
|
||||
always @(posedge clk_in) raddr_q3 <= raddr_q2;
|
||||
bit [3:0] raddr_clkin;
|
||||
g2b_converter #(.WIDTH(4)) raddr_to_binary2 (.binary(raddr_clkin),.gray(raddr_q3));
|
||||
|
||||
// verilog_format: on
|
||||
|
||||
wire [3:0] cnt_clkin = waddr - raddr_clkin;
|
||||
wire [3:0] cnt_clkout = waddr_clkout - raddr;
|
||||
|
||||
always_ff @(posedge clk_in) begin
|
||||
if (reset_in) waddr <= 0;
|
||||
else if (we) begin
|
||||
ram[waddr] <= wdata;
|
||||
waddr <= waddr + 1;
|
||||
|
||||
assert (cnt_clkout < 10);
|
||||
assert (cnt_clkin < 10);
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_out) begin
|
||||
if (reset_out) raddr <= 0;
|
||||
else if (strobe) begin
|
||||
raddr <= raddr + 1;
|
||||
|
||||
assert (cnt_clkout > 0);
|
||||
assert (cnt_clkin > 0);
|
||||
end
|
||||
|
||||
q <= ram[raddr];
|
||||
valid <= cnt_clkout != 0;
|
||||
end
|
||||
|
||||
endmodule : yuv_frame_adr_fifo
|
||||
|
||||
@@ -1,6 +1,12 @@
|
||||
`ifndef HEADER_UTIL
|
||||
`define HEADER_UTIL
|
||||
|
||||
typedef struct {
|
||||
bit [28:0] y_adr;
|
||||
bit [28:0] u_adr;
|
||||
bit [28:0] v_adr;
|
||||
} planar_yuv_s;
|
||||
|
||||
function [31:0] ones_mask(bit [4:0] n);
|
||||
begin
|
||||
ones_mask = (32'h1 << n) - 1; // n ones at LSB
|
||||
|
||||
33
rtl/vmpeg.sv
33
rtl/vmpeg.sv
@@ -99,12 +99,14 @@ module vmpeg (
|
||||
// [5:0] 6 Bit Minutes? Not BCD
|
||||
// Where are the hours?
|
||||
wire [31:0] fmv_timecode;
|
||||
bit fmv_playback_active;
|
||||
|
||||
mpeg_video video (
|
||||
.clk30(clk),
|
||||
.clk60(clk_mpeg),
|
||||
.reset,
|
||||
.dsp_enable(1'b1),
|
||||
.playback_active(fmv_playback_active),
|
||||
.data_byte(mpeg_data),
|
||||
.data_strobe(fmv_data_valid && fmv_packet_body),
|
||||
.fifo_full(video_fifo_full),
|
||||
@@ -134,29 +136,35 @@ module vmpeg (
|
||||
);
|
||||
|
||||
bit dsp_enable = 0;
|
||||
wire signed [32:0] system_clock_reference_start_time;
|
||||
wire system_clock_reference_start_time_valid;
|
||||
wire signed [32:0] fma_system_clock_reference_start_time;
|
||||
wire fma_system_clock_reference_start_time_valid;
|
||||
wire signed [32:0] fmv_system_clock_reference_start_time;
|
||||
wire fmv_system_clock_reference_start_time_valid;
|
||||
|
||||
mpeg_demuxer audio_demuxer (
|
||||
mpeg_demuxer #(
|
||||
.unit("FMA")
|
||||
) audio_demuxer (
|
||||
.clk,
|
||||
.reset(reset || (fma_command_register == 1)),
|
||||
.mpeg_data(mpeg_data),
|
||||
.data_valid(fma_data_valid),
|
||||
.mpeg_packet_body(fma_packet_body),
|
||||
.dclk(fma_dclk),
|
||||
.system_clock_reference_start_time(system_clock_reference_start_time),
|
||||
.system_clock_reference_start_time_valid(system_clock_reference_start_time_valid)
|
||||
.system_clock_reference_start_time(fma_system_clock_reference_start_time),
|
||||
.system_clock_reference_start_time_valid(fma_system_clock_reference_start_time_valid)
|
||||
);
|
||||
|
||||
mpeg_demuxer video_demuxer (
|
||||
mpeg_demuxer #(
|
||||
.unit("FMV")
|
||||
) video_demuxer (
|
||||
.clk,
|
||||
.reset(reset),
|
||||
.mpeg_data(mpeg_data),
|
||||
.data_valid(fmv_data_valid),
|
||||
.mpeg_packet_body(fmv_packet_body),
|
||||
.dclk(fma_dclk),
|
||||
.system_clock_reference_start_time(),
|
||||
.system_clock_reference_start_time_valid()
|
||||
.system_clock_reference_start_time(fmv_system_clock_reference_start_time),
|
||||
.system_clock_reference_start_time_valid(fmv_system_clock_reference_start_time_valid)
|
||||
);
|
||||
|
||||
typedef struct packed {
|
||||
@@ -328,6 +336,8 @@ module vmpeg (
|
||||
mpeg_ram_enabled_cnt <= 0;
|
||||
timer_cnt <= 0;
|
||||
dma_active <= 0;
|
||||
dsp_enable <= 0;
|
||||
fmv_playback_active <= 0;
|
||||
end else begin
|
||||
if (vsync && !vsync_q) interrupt_status_register.vsync <= 1;
|
||||
|
||||
@@ -370,9 +380,14 @@ module vmpeg (
|
||||
timer_cnt <= timer_cnt + 1;
|
||||
end
|
||||
|
||||
if (system_clock_reference_start_time_valid && fma_dclk == system_clock_reference_start_time[32:1] && !dsp_enable) begin
|
||||
if (fma_system_clock_reference_start_time_valid && fma_dclk == fma_system_clock_reference_start_time[32:1] && !dsp_enable) begin
|
||||
dsp_enable <= 1;
|
||||
end
|
||||
|
||||
if (fmv_system_clock_reference_start_time_valid && fma_dclk == fmv_system_clock_reference_start_time[32:1] && !fmv_playback_active) begin
|
||||
fmv_playback_active <= 1;
|
||||
end
|
||||
|
||||
end else begin
|
||||
fma_dclk_shadow_cnt <= fma_dclk_shadow_cnt + 1;
|
||||
end
|
||||
|
||||
@@ -4,4 +4,4 @@
|
||||
cd "$(dirname "$0")/../rtl"
|
||||
|
||||
verible-verilog-format --inplace --indentation_spaces 4 \
|
||||
../rtl/*.v ../rtl/*.sv ../*.v ../*.sv
|
||||
../rtl/*.v ../rtl/*.sv ../rtl/*/*.sv ../rtl/*/*/*.sv ../*.v ../*.sv
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
|
||||
#define SCC68070
|
||||
#define SLAVE
|
||||
#define TRACE
|
||||
// #define TRACE
|
||||
// #define SIMULATE_RC5
|
||||
|
||||
#define PL_MPEG_IMPLEMENTATION
|
||||
@@ -638,10 +638,13 @@ class CDi {
|
||||
|
||||
} else {
|
||||
// PAL
|
||||
|
||||
if (frame_index == 144) { // Skip Philips Logo
|
||||
if ((frame_index % 25) == 20)
|
||||
press_button_signal = true;
|
||||
|
||||
if (frame_index == 137) { // Skip Philips Logo
|
||||
press_button_signal = true;
|
||||
}
|
||||
|
||||
if (frame_index == 430) { // Skip Dragons Lair Intro
|
||||
press_button_signal = true;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -869,7 +872,7 @@ class CDi {
|
||||
|
||||
start = std::chrono::system_clock::now();
|
||||
#ifdef TRACE
|
||||
//do_trace = false;
|
||||
do_trace = false;
|
||||
fprintf(stderr, "Trace off!\n");
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user