- 25 fps hard coded for experiments
- Presentation time utilized to define start of playback
- Makes use of FIFO structure for stable frame rate
- Firmware
- Provides all 3 planar framebuffers to hardware for playback
- Added detection of MPEG stream overflows (for debugging)
- Reduced PLL for worker to 80 MHz (was 90 MHz before)
- Decoder core now running at worker speed (80 MHz instead of 30 MHz)
- MPEG Firmware
- Readded better FIFO level checks to avoid underflows
- Better buffer management to ensure immutability of decoded frames
- Frameplayer now switches framebuffer address when frame was decoded
- Added MPEG optimized data cache for DDR3 access to store 8 macroblock lines
Shows Dragon's Lair intro with less artefacts now.
Timing is not correct as the presentation time is not utilized
Skyways playable again
Dragon's Lair can enter gameplay again
In case of FMA this was done in software but
pl_mpeg doesn't really provide this info and
it can be done easily in hardware.
Replaced memory arrays of video decoder with dual port RAM for FPGA usage
Added planar YCbCr frame player to display decoded frames
Added DDR3 interface for frame player and pixel worker
Added DDR3 interface mux for multiple masters
MCD212: Added EV bit usage to replace backdrop with external video
Shows Dragon's Lair intro with artefacts on MiSTer
because the worker currently cannot read from DDR3
For some reason, the EV bit is not working correctly
- MPEG video decoder based on pl_mpeg, executed
on 3 VexiiRiscv cores. One for decoding the stream and
two for pixel workings and IDCT.
- Added additional clock for MPEG workers
- Added hardware accelerated DCT coefficient huffman decoder
- Generalized MPEG demuxer design for video and audio
- Removed fake startcode decoder for video stream (for now)
- Expanded Verilator testbench with YUV to RGB conversion
to extract decoded MPEG frames
- Dragon's Lair Intro can be decoded with this (vmpeg.asm)
Design cannot be synthesized
- Added clock divider to get 0.5 MHz from 30 MHz system clock
The system timer tick now occurs every 8.1ms like it does on a 210/05
- Added reset delay mechanism to fix the resulting time out when polling
for the PAL/NTSC status.
This occurs when the m68k is overclocked
- Added captured RC5 test data to confirm compatibility with the
Thumbstick remote controller in a simulated environment
- Approximates the clipping behavior of a CDI 210/05
- Required to fit the theoretical 17 bit output
into the 16 bit PCM signal of the MiSTer
- Fixes sound distortion in Hotel Mario
- Changes based on findings of the CDIC_BlackBoxAnalyzer project
- Removed side channel for audio coding
- A real CDIC reads the audio coding always from RAM
- Removed the concept of the audio tick found in MAME
- A real CDIC performs audio playback asynchronous to the CD reading
- Seek time now 19 sectors
- Fixes audio glitch in "Help cutscene" in "Zelda - Wand of Gamelon"
"Remember, tools can only be used..."
- Fixes audio regression during "Hotel Mario" score screen
- Fixed spurious IRQ caused by sector data interrupt after reading stopped
- Should fix hang on shopkeeper cutscene in "Zelda - Wand of Gamelon"
(Cannot be reproduced or is very unlikely now)
- The new behavior based on 210/05 measurements
added in 20250214 is hidden in the debug menu
- Original video timing from before is restored
- Fixes boot of "The Flowers of Robert Mapplethorpe"
- Allows NTSC material being usable on PAL modes.
- Reduces horizontal resolution from 384 to 360 pixels
and vertical resolution from 280 to 240.
- Fixes glitched graphics in Flashback intro.
Game is still hanging after intro.
- Added state management for audiomap usage
- Added coding dependent sector playback delay
- Basic seeking time simulation and constant data rate
- Removed debugging option to disable MODE2 filters
- Added a lot documentation about expectations of
the CDIC to the code
- Splitted off all audio playback into seperate file
- Added DC bias filter to reduce pops between playbacks
- Fixed wrong sample during underflow of FIFO
- Added two sample delay for ADPCM
Fixes frequent clicks and pops due to latency of ADPCM calculation
- Buffer management now equal to CDIC emulation of MAME
Uses internal bank switching to avoid ADPCM overwrite
Stabilizes intro of "Zelda's Adventure" and "Hotel Mario"
SCC68070: DMA support for transfer to CDIC memory
Added additional test roms to verify the additions
Known issues:
- Hotel Mario hangs during score screen
- Frog Feast hangs ingame
- Implement data reading state machine in CDIC
- Implement required interface to HPS for reading
cd sector data
- Add DMA support to CPU which is required
by the CDIC driver to get sector data into main
memory
- Add INT1 and INT2 to SCC68070
- Can boot into the demo of Frog Feast
- Servo HLE fixed to closed tray with
inserted CDi medium
- Add video IRQ
- Added servo controller SPI fake communication
Behaves as a closed but empty tray
- Added pointing device emulation
MiSTer joystick data used as input
Behaves like a maneuvering device
- Added SCI IRQ to 6805 cpu core
- Added SPI and SCI to 6805 uC
- Fixed spurious 68k chip select for slave
- Added documentation about I2C to the Front LCD
- Simulated U3090MG no longer causes front panel button presses
Lead to spurious IRQs before
- Removal of slave memory patches
- Added ICA1 and FILE1
- CLUT implemented as True Dual-Port RAM to allow
writing and reading with two video channels
- Added weight calculations
- Mouse cursor
- Attach display file and ICA to SDRAM
- Fixed byte order of 8 bit accesses by CPU
- Added SDRAM burst mode to fix video timing
- Fixed missing reset behavior of some components
- Added optional SDRAM zeroing
- Added SDRAM refresh during ROM download
- Added OS aware syscall parser to simulation
- Fixed SCC68070 on-chip interrupt autovector
- Fixed SCC68070 Timer0 frequency
- Added video pixel data FIFO
- Changed SDRAM auto refresh command
- SDRAM controller added
- fixed 6805 bus timing with clk enable signal
- fixed 6805 latch warnings in quartus
- added 6805 reset logic
- added 6805 ram zeroing after reset
- fixed synthesis and timing of CDIC memory
- MCD212 cpu bridge interfaces with SDRAM
- fixed NvRAM memory timing
- fixed spurious sdram access in reset
- removed fake display_active flag
- added SDRAM refresh logic
- added real UART to SCC68070
- switched simulation top level to real MiSTer core
video is corrupted and needs fixes
- CLUT7 RLE
- Video timing according to datasheet
- Example framebuffer in block ram
as SDRAM interface is not finished yet
- simulation can export video signal to PNG
- design can be synthesized and fitted but CPU parts are not functional
- SCC68070 is booting cdi200.rom
- SLAVE is communicating with the CPU
- MCD212 only implements memory map
- IRQs incomplete
- CDIC missing
- MiSTer interface missing
