Commit Graph

11 Commits

Author SHA1 Message Date
Andre Zeps
09778e02a0 Removed git submodules
Copy of tg68k added to rtl subfolder

Last revision
https://github.com/Slamy/TG68K.C.git
a1c18a18a073b33f49aaf092509da06bc14f47ed

This should make merges with mainline easier
2025-11-13 20:12:20 +01:00
Andre Zeps
62319d342b FMV: Added support for Hide/Show Video Command
- Fixes mv_hide() and mv_show()
2025-11-13 20:12:20 +01:00
Andre Zeps
413b8f78bb VMPEG: Interlocked MPEG system clock reference with CD sector time
Fixes desynchronisation in fmvdrv after 18 minutes of Top Gun

Thanks to cdifan for pointing this out
Source:
http://icdia.co.uk/notes/technote097.pdf
TN #097 - The Full Motion System for CD-I,
section 4. ARCHITECTURE OF FULL MOTION CD-I PLAYER
VMPEG can be disabled via OSD
WIP
FMV: Increased soft core clock rate to 92 MHz

Was 80 MHz before, which wasn't enough
Fixes Top Gun CPU overload at timecode ~15:48
2025-11-02 13:11:42 +01:00
Andre Zeps
f7bd5d3d73 FMV: Improved frame pacing
- 25 fps hard coded for experiments
- Presentation time utilized to define start of playback
  - Makes use of FIFO structure for stable frame rate
- Firmware
  - Provides all 3 planar framebuffers to hardware for playback
2025-09-15 16:09:35 +02:00
Andre Zeps
a2a856226d Audiodecoder now processes elementary data instead of muxed
Saves lots of memory
Fixes support for very short MPEG files
pl_mpeg seems to be not able to demux short streams

Lucky Luke seems fine now
2025-07-27 19:47:21 +02:00
Andre Zeps
b9d9678654 moved generated code to verilator folder 2024-09-09 13:34:13 +02:00
Andre Zeps
d05f1fb295 Slave controller features
- Added servo controller SPI fake communication
  Behaves as a closed but empty tray
- Added pointing device emulation
  MiSTer joystick data used as input
  Behaves like a maneuvering device
- Added SCI IRQ to 6805 cpu core
- Added SPI and SCI to 6805 uC
- Fixed spurious 68k chip select for slave
- Added documentation about I2C to the Front LCD
- Simulated U3090MG no longer causes front panel button presses
  Lead to spurious IRQs before
- Removal of slave memory patches
2024-09-03 11:58:26 +02:00
Andre Zeps
74bff4c5ce Removed slave rom from FPGA bitstream
Added ioctl_download for slave rom
boot0.rom is expected to be the main cpu rom
boot1.rom is expected to be the slave rom
2024-08-18 20:02:33 +02:00
Andre Zeps
738bd44379 Boot fixes and video implementation
- Attach display file and ICA to SDRAM
- Fixed byte order of 8 bit accesses by CPU
- Added SDRAM burst mode to fix video timing
- Fixed missing reset behavior of some components
- Added optional SDRAM zeroing
- Added SDRAM refresh during ROM download
- Added OS aware syscall parser to simulation
- Fixed SCC68070 on-chip interrupt autovector
- Fixed SCC68070 Timer0 frequency
- Added video pixel data FIFO
- Changed SDRAM auto refresh command
2024-08-17 22:32:51 +02:00
Andre Zeps
3cbdbea097 Added more comments to the code 2024-07-10 18:41:12 +02:00
Andre Zeps
b99ab86b09 First public release
- SCC68070 is booting cdi200.rom
- SLAVE is communicating with the CPU
- MCD212 only implements memory map
- IRQs incomplete
- CDIC missing
- MiSTer interface missing
2024-07-08 19:22:59 +02:00