mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-04-19 03:04:19 +00:00
- Attach display file and ICA to SDRAM - Fixed byte order of 8 bit accesses by CPU - Added SDRAM burst mode to fix video timing - Fixed missing reset behavior of some components - Added optional SDRAM zeroing - Added SDRAM refresh during ROM download - Added OS aware syscall parser to simulation - Fixed SCC68070 on-chip interrupt autovector - Fixed SCC68070 Timer0 frequency - Added video pixel data FIFO - Changed SDRAM auto refresh command