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Update sys.

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sorgelig
2019-02-01 19:40:40 +08:00
parent fa058ca816
commit 4ab9fa8efb
3 changed files with 14 additions and 6 deletions
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1
C64-vip.qsf
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@@ -354,6 +354,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_global_assignment -name SDC_FILE sys/vip.sdc
set_global_assignment -name QIP_FILE sid6581/sid.qip
set_global_assignment -name QIP_FILE sid8580/sid.qip
set_global_assignment -name QIP_FILE opl3/opl3.qip

7
sys/sys_top.sdc
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@@ -14,10 +14,6 @@ create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|alt
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
@@ -34,7 +30,7 @@ set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRA
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
@@ -43,7 +39,6 @@ set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE
set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}]
# Put constraints on input ports
set_false_path -from [get_ports {KEY*}] -to *
set_false_path -from [get_ports {BTN_*}] -to *

12
sys/vip.sdc Normal file
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@@ -0,0 +1,12 @@
# Specify root clocks
# Specify PLL-generated clock(s)
create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}]