From 4ab9fa8efb16b5dc30d0fb3ef065ff808397dae6 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Fri, 1 Feb 2019 19:40:40 +0800 Subject: [PATCH] Update sys. --- C64-vip.qsf | 1 + sys/sys_top.sdc | 7 +------ sys/vip.sdc | 12 ++++++++++++ 3 files changed, 14 insertions(+), 6 deletions(-) create mode 100644 sys/vip.sdc diff --git a/C64-vip.qsf b/C64-vip.qsf index 5b9c5d2..298ce16 100644 --- a/C64-vip.qsf +++ b/C64-vip.qsf @@ -354,6 +354,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" set_global_assignment -name CDF_FILE jtag.cdf set_global_assignment -name QIP_FILE sys/sys.qip set_global_assignment -name QSYS_FILE sys/vip.qsys +set_global_assignment -name SDC_FILE sys/vip.sdc set_global_assignment -name QIP_FILE sid6581/sid.qip set_global_assignment -name QIP_FILE sid8580/sid.qip set_global_assignment -name QIP_FILE opl3/opl3.qip diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 34b884a..01cc3cc 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -14,10 +14,6 @@ create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|alt create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ -name HDMI_CLK [get_ports HDMI_TX_CLK] -create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ - -name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}] - - derive_clock_uncertainty # Set acceptable delays for SDRAM chip (See correspondent chip datasheet) @@ -34,7 +30,7 @@ set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRA # Decouple different clock groups (to simplify routing) set_clock_groups -asynchronous \ -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \ - -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \ + -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ -group [get_clocks { *|h2f_user0_clk}] \ -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}] @@ -43,7 +39,6 @@ set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}] - # Put constraints on input ports set_false_path -from [get_ports {KEY*}] -to * set_false_path -from [get_ports {BTN_*}] -to * diff --git a/sys/vip.sdc b/sys/vip.sdc new file mode 100644 index 0000000..701f346 --- /dev/null +++ b/sys/vip.sdc @@ -0,0 +1,12 @@ +# Specify root clocks + +# Specify PLL-generated clock(s) +create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ + -name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}] + + +derive_clock_uncertainty + +# Decouple different clock groups (to simplify routing) +set_clock_groups -asynchronous \ + -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}]