mirror of
https://github.com/MiSTer-devel/AcornAtom_MiSTer.git
synced 2026-04-19 03:01:39 +00:00
Video and Timing Fixes New Sys (#5)
* new sys * timing fixes * Working on 15khz
This commit is contained in:
Alan Steremberg
GitHub
15
.gitignore
vendored
Normal file
15
.gitignore
vendored
Normal file
@@ -0,0 +1,15 @@
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db
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incremental_db
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output_files
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build_id.v
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c5_pin_model_dump.txt
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jtag.cdf
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*.zip
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*.bak
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/*.qws
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greybox_tmp/cbx_args.txt
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*/greybox_tmp/cbx_args.txt
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.idea
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output_files
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incremental_db
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@@ -13,7 +13,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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@@ -37,6 +37,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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@@ -49,13 +50,15 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
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set_global_assignment -name SEED 1
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#set_global_assignment -name VERILOG_MACRO "ARCADE_SYS=1"
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#set_global_assignment -name VERILOG_MACRO "USE_FB=1"
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#set_global_assignment -name VERILOG_MACRO "USE_SDRAM=1"
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#set_global_assignment -name VERILOG_MACRO "USE_DDRAM=1"
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
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#enable it only if 8bit indexed mode is used in core
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
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#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
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#do not enable DEBUG_NOHDMI in release!
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#set_global_assignment -name VERILOG_MACRO "DEBUG_NOHDMI=1"
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#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
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source sys/sys.tcl
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source sys/sys_analog.tcl
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244
AcornAtom.sv
244
AcornAtom.sv
@@ -17,6 +17,7 @@
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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@@ -27,7 +28,7 @@ module emu
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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inout [47:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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@@ -37,8 +38,9 @@ module emu
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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@@ -46,8 +48,42 @@ module emu
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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@@ -62,16 +98,16 @@ module emu
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, //24.576 MHz
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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// SD-SPI
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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@@ -102,24 +138,38 @@ module emu
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..5 - USR1..USR4
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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assign ADC_BUS = 'Z;
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@@ -134,10 +184,14 @@ assign LED_DISK = {1'b1,~vsd_sel & sd_act};
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
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assign VGA_SCALER = 0;
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assign HDMI_FREEZE = 0;
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wire [1:0] ar = status[12:11];
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assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
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wire [1:0] scale = status[3:2];
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`include "build_id.v"
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parameter CONF_STR = {
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@@ -145,8 +199,8 @@ parameter CONF_STR = {
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"-;",
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"S,VHD;",
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"-;",
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"O1,Aspect ratio,4:3,16:9;",
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"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"OBC,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"O13,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
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"-;",
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"O45,Audio,Atom,SID,TAPE,off;",
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"O67,Keyboard,UK,US,orig,game;",
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@@ -160,23 +214,48 @@ parameter CONF_STR = {
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};
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///////////////// CLOCKS ////////////////////////
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wire clk_sys;
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wire clk_main = clk_sys;
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wire clk_sys = clk_32;
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//wire clk_100;
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wire clk_16;
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wire clk_32;
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wire clk_25;
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//wire clk_25;
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wire clk_42;
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wire pll_locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys),
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.outclk_1(clk_16),
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.outclk_2(clk_25),
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.outclk_3(clk_32)
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.outclk_0(clk_42),
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.outclk_1(clk_32),
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.outclk_2(clk_16)
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);
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reg clk_14M318_ena ;
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reg [1:0] count;
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always @(posedge clk_42)
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begin
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if (reset)
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count<=0;
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else
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begin
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clk_14M318_ena <= 0;
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if (count == 'd2)
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begin
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clk_14M318_ena <= 1;
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count <= 0;
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end
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else
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begin
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count<=count+1;
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end
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end
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end
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///////////////// HPS ///////////////////////////
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@@ -197,35 +276,35 @@ wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire forced_scandoubler;
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wire [21:0] gamma_bus;
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wire direct_video;
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wire [31:0] sd_lba;
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wire [31:0] sd_lba[1];
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wire sd_rd;
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wire sd_wr;
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wire sd_ack;
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire [7:0] sd_buff_din;
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wire [7:0] sd_buff_din[1];
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wire sd_buff_wr;
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wire img_mounted;
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wire img_readonly;
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wire [63:0] img_size;
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wire sd_ack_conf;
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wire [64:0] RTC;
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wire ps2_clk,ps2_data;
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hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.buttons(buttons),
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.status(status),
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.forced_scandoubler(forced_scandoubler),
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.gamma_bus(gamma_bus),
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.direct_video(direct_video),
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.RTC(RTC),
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@@ -240,13 +319,13 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.uart_mode(16'b000_11111_000_11111),
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//.uart_mode(16'b000_11111_000_11111),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_ack_conf(sd_ack_conf),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
|
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@@ -257,8 +336,8 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
|
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|
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.joystick_0(joy1),
|
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.joystick_1(joy2),
|
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.joystick_analog_0({joy1_y,joy1_x}),
|
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.joystick_analog_1({joy2_y,joy2_x})
|
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.joystick_l_analog_0({joy1_y,joy1_x}),
|
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.joystick_l_analog_1({joy2_y,joy2_x})
|
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);
|
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|
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///////////////// RESET /////////////////////////
|
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@@ -327,7 +406,7 @@ wire [7:0] mem_din,mem_dout;
|
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|
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spram #(8, 18, 196608, "roms/ATOM192k.mif") rom
|
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(
|
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.clock(clk_sys),
|
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.clock(clk_main),
|
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.address(mem_addr),
|
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.data(mem_din),
|
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.wren(mem_we),
|
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@@ -340,14 +419,19 @@ spram #(8, 18, 196608, "roms/ATOM192k.mif") rom
|
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wire charset = status[8];
|
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|
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wire tape_out;
|
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|
||||
wire pixel_clock;
|
||||
AtomFpga_Core AcornAtom
|
||||
(
|
||||
// clocks
|
||||
.clk_vga(clk_25),
|
||||
.clk_main(clk_32),
|
||||
|
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.clk_vid(clk_42),
|
||||
.clk_vid_en(clk_14M318_ena),
|
||||
.clk_main(clk_main),
|
||||
.clk_dac(clk_sys),
|
||||
.clk_avr(clk_16),
|
||||
//.clk_avr(clk_16),
|
||||
.clk_avr(clk_main),
|
||||
|
||||
.pixel_clock(pixel_clock),
|
||||
|
||||
// Keyboard
|
||||
.ps2_key(ps2_key),
|
||||
@@ -435,42 +519,41 @@ assign AUDIO_R = status[5:4] == 2'b00 ? {{16{a_audio}}} : status[5:4] == 2'b01 ?
|
||||
assign AUDIO_MIX = 0;
|
||||
assign AUDIO_S = 1'b0;
|
||||
|
||||
wire hs, vs, hblank, vblank, ce_pix, clk_sel;
|
||||
wire hs, vs, hblank, vblank, clk_sel;
|
||||
wire [1:0] r,g,b;
|
||||
|
||||
assign CLK_VIDEO = clk_25;
|
||||
video_mixer #(640, 0) mixer
|
||||
(
|
||||
.clk_vid(CLK_VIDEO),
|
||||
|
||||
.ce_pix(1'b1),
|
||||
.ce_pix_out(CE_PIXEL),
|
||||
assign CLK_VIDEO = clk_42;// clk_25;
|
||||
wire freeze_sync;
|
||||
|
||||
|
||||
|
||||
video_mixer #(.GAMMA(1)) video_mixer
|
||||
(
|
||||
.*,
|
||||
|
||||
.CLK_VIDEO(CLK_VIDEO),
|
||||
.ce_pix(pixel_clock),
|
||||
|
||||
.hq2x(scale==1),
|
||||
|
||||
.hq2x(scale == 1),
|
||||
.scanlines(0),
|
||||
.scandoubler(scale),
|
||||
|
||||
.R({r[1],r[1],r[1],r[0],r[0],r[0],r}),
|
||||
.G({g[1],g[1],g[1],g[0],g[0],g[0],g}),
|
||||
.B({b[1],b[1],b[1],b[0],b[0],b[0],b}),
|
||||
|
||||
.mono(0),
|
||||
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.HBlank(hblank),
|
||||
.VBlank(vblank),
|
||||
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.VGA_DE(VGA_DE)
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.HBlank(hblank),
|
||||
.VBlank(vblank)
|
||||
);
|
||||
|
||||
|
||||
|
||||
assign VGA_F1 = 0;
|
||||
assign VGA_SL = scale ? scale - 1'd1 : 2'd0;
|
||||
wire [2:0] scale = status[3:1];
|
||||
wire [2:0] sl = scale ? scale - 1'd1 : 3'd0;
|
||||
wire scandoubler = (scale || forced_scandoubler);
|
||||
assign VGA_SL = sl[1:0];
|
||||
|
||||
////////////////// SD ///////////////////
|
||||
|
||||
@@ -487,6 +570,9 @@ sd_card #(0) sd_card
|
||||
(
|
||||
.*,
|
||||
|
||||
.sd_lba(sd_lba[0]),
|
||||
.sd_buff_din(sd_buff_din[0]),
|
||||
|
||||
.clk_spi(clk_sys),
|
||||
.sdhc(1),
|
||||
.sck(sdclk),
|
||||
|
||||
204
pll.xml
Normal file
204
pll.xml
Normal file
@@ -0,0 +1,204 @@
|
||||
<?xml version="1.0"?>
|
||||
<instance entity-name="altera_pll" version="17.0" >
|
||||
<generic name="debug_print_output" value="false" />
|
||||
<generic name="debug_use_rbc_taf_method" value="false" />
|
||||
<generic name="device_family" value="Cyclone V" />
|
||||
<generic name="device" value="5CEBA2F17A7" />
|
||||
<generic name="gui_device_speed_grade" value="2" />
|
||||
<generic name="gui_pll_mode" value="Integer-N PLL" />
|
||||
<generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
<generic name="gui_channel_spacing" value="0.0" />
|
||||
<generic name="gui_operation_mode" value="direct" />
|
||||
<generic name="gui_feedback_clock" value="Global Clock" />
|
||||
<generic name="gui_fractional_cout" value="32" />
|
||||
<generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
<generic name="gui_use_locked" value="true" />
|
||||
<generic name="gui_en_adv_params" value="false" />
|
||||
<generic name="gui_number_of_clocks" value="3" />
|
||||
<generic name="gui_multiply_factor" value="1" />
|
||||
<generic name="gui_frac_multiply_factor" value="1" />
|
||||
<generic name="gui_divide_factor_n" value="1" />
|
||||
<generic name="gui_cascade_counter0" value="false" />
|
||||
<generic name="gui_output_clock_frequency0" value="42.954" />
|
||||
<generic name="gui_divide_factor_c0" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
<generic name="gui_ps_units0" value="ps" />
|
||||
<generic name="gui_phase_shift0" value="0" />
|
||||
<generic name="gui_phase_shift_deg0" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift0" value="0" />
|
||||
<generic name="gui_duty_cycle0" value="50" />
|
||||
<generic name="gui_cascade_counter1" value="false" />
|
||||
<generic name="gui_output_clock_frequency1" value="32.0" />
|
||||
<generic name="gui_divide_factor_c1" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
<generic name="gui_ps_units1" value="ps" />
|
||||
<generic name="gui_phase_shift1" value="0" />
|
||||
<generic name="gui_phase_shift_deg1" value="-60.0" />
|
||||
<generic name="gui_actual_phase_shift1" value="0" />
|
||||
<generic name="gui_duty_cycle1" value="50" />
|
||||
<generic name="gui_cascade_counter2" value="false" />
|
||||
<generic name="gui_output_clock_frequency2" value="16.0" />
|
||||
<generic name="gui_divide_factor_c2" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
<generic name="gui_ps_units2" value="ps" />
|
||||
<generic name="gui_phase_shift2" value="0" />
|
||||
<generic name="gui_phase_shift_deg2" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift2" value="0" />
|
||||
<generic name="gui_duty_cycle2" value="50" />
|
||||
<generic name="gui_cascade_counter3" value="false" />
|
||||
<generic name="gui_output_clock_frequency3" value="32.0" />
|
||||
<generic name="gui_divide_factor_c3" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
<generic name="gui_ps_units3" value="ps" />
|
||||
<generic name="gui_phase_shift3" value="0" />
|
||||
<generic name="gui_phase_shift_deg3" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift3" value="0" />
|
||||
<generic name="gui_duty_cycle3" value="50" />
|
||||
<generic name="gui_cascade_counter4" value="false" />
|
||||
<generic name="gui_output_clock_frequency4" value="42.954" />
|
||||
<generic name="gui_divide_factor_c4" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
<generic name="gui_ps_units4" value="ps" />
|
||||
<generic name="gui_phase_shift4" value="0" />
|
||||
<generic name="gui_phase_shift_deg4" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift4" value="0" />
|
||||
<generic name="gui_duty_cycle4" value="50" />
|
||||
<generic name="gui_cascade_counter5" value="false" />
|
||||
<generic name="gui_output_clock_frequency5" value="100.0" />
|
||||
<generic name="gui_divide_factor_c5" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
<generic name="gui_ps_units5" value="ps" />
|
||||
<generic name="gui_phase_shift5" value="0" />
|
||||
<generic name="gui_phase_shift_deg5" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift5" value="0" />
|
||||
<generic name="gui_duty_cycle5" value="50" />
|
||||
<generic name="gui_cascade_counter6" value="false" />
|
||||
<generic name="gui_output_clock_frequency6" value="100.0" />
|
||||
<generic name="gui_divide_factor_c6" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
<generic name="gui_ps_units6" value="ps" />
|
||||
<generic name="gui_phase_shift6" value="0" />
|
||||
<generic name="gui_phase_shift_deg6" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift6" value="0" />
|
||||
<generic name="gui_duty_cycle6" value="50" />
|
||||
<generic name="gui_cascade_counter7" value="false" />
|
||||
<generic name="gui_output_clock_frequency7" value="100.0" />
|
||||
<generic name="gui_divide_factor_c7" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
<generic name="gui_ps_units7" value="ps" />
|
||||
<generic name="gui_phase_shift7" value="0" />
|
||||
<generic name="gui_phase_shift_deg7" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift7" value="0" />
|
||||
<generic name="gui_duty_cycle7" value="50" />
|
||||
<generic name="gui_cascade_counter8" value="false" />
|
||||
<generic name="gui_output_clock_frequency8" value="100.0" />
|
||||
<generic name="gui_divide_factor_c8" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
<generic name="gui_ps_units8" value="ps" />
|
||||
<generic name="gui_phase_shift8" value="0" />
|
||||
<generic name="gui_phase_shift_deg8" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift8" value="0" />
|
||||
<generic name="gui_duty_cycle8" value="50" />
|
||||
<generic name="gui_cascade_counter9" value="false" />
|
||||
<generic name="gui_output_clock_frequency9" value="100.0" />
|
||||
<generic name="gui_divide_factor_c9" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
<generic name="gui_ps_units9" value="ps" />
|
||||
<generic name="gui_phase_shift9" value="0" />
|
||||
<generic name="gui_phase_shift_deg9" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift9" value="0" />
|
||||
<generic name="gui_duty_cycle9" value="50" />
|
||||
<generic name="gui_cascade_counter10" value="false" />
|
||||
<generic name="gui_output_clock_frequency10" value="100.0" />
|
||||
<generic name="gui_divide_factor_c10" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
<generic name="gui_ps_units10" value="ps" />
|
||||
<generic name="gui_phase_shift10" value="0" />
|
||||
<generic name="gui_phase_shift_deg10" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift10" value="0" />
|
||||
<generic name="gui_duty_cycle10" value="50" />
|
||||
<generic name="gui_cascade_counter11" value="false" />
|
||||
<generic name="gui_output_clock_frequency11" value="100.0" />
|
||||
<generic name="gui_divide_factor_c11" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
<generic name="gui_ps_units11" value="ps" />
|
||||
<generic name="gui_phase_shift11" value="0" />
|
||||
<generic name="gui_phase_shift_deg11" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift11" value="0" />
|
||||
<generic name="gui_duty_cycle11" value="50" />
|
||||
<generic name="gui_cascade_counter12" value="false" />
|
||||
<generic name="gui_output_clock_frequency12" value="100.0" />
|
||||
<generic name="gui_divide_factor_c12" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
<generic name="gui_ps_units12" value="ps" />
|
||||
<generic name="gui_phase_shift12" value="0" />
|
||||
<generic name="gui_phase_shift_deg12" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift12" value="0" />
|
||||
<generic name="gui_duty_cycle12" value="50" />
|
||||
<generic name="gui_cascade_counter13" value="false" />
|
||||
<generic name="gui_output_clock_frequency13" value="100.0" />
|
||||
<generic name="gui_divide_factor_c13" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
<generic name="gui_ps_units13" value="ps" />
|
||||
<generic name="gui_phase_shift13" value="0" />
|
||||
<generic name="gui_phase_shift_deg13" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift13" value="0" />
|
||||
<generic name="gui_duty_cycle13" value="50" />
|
||||
<generic name="gui_cascade_counter14" value="false" />
|
||||
<generic name="gui_output_clock_frequency14" value="100.0" />
|
||||
<generic name="gui_divide_factor_c14" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
<generic name="gui_ps_units14" value="ps" />
|
||||
<generic name="gui_phase_shift14" value="0" />
|
||||
<generic name="gui_phase_shift_deg14" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift14" value="0" />
|
||||
<generic name="gui_duty_cycle14" value="50" />
|
||||
<generic name="gui_cascade_counter15" value="false" />
|
||||
<generic name="gui_output_clock_frequency15" value="100.0" />
|
||||
<generic name="gui_divide_factor_c15" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
<generic name="gui_ps_units15" value="ps" />
|
||||
<generic name="gui_phase_shift15" value="0" />
|
||||
<generic name="gui_phase_shift_deg15" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift15" value="0" />
|
||||
<generic name="gui_duty_cycle15" value="50" />
|
||||
<generic name="gui_cascade_counter16" value="false" />
|
||||
<generic name="gui_output_clock_frequency16" value="100.0" />
|
||||
<generic name="gui_divide_factor_c16" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
<generic name="gui_ps_units16" value="ps" />
|
||||
<generic name="gui_phase_shift16" value="0" />
|
||||
<generic name="gui_phase_shift_deg16" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift16" value="0" />
|
||||
<generic name="gui_duty_cycle16" value="50" />
|
||||
<generic name="gui_cascade_counter17" value="false" />
|
||||
<generic name="gui_output_clock_frequency17" value="100.0" />
|
||||
<generic name="gui_divide_factor_c17" value="1" />
|
||||
<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
<generic name="gui_ps_units17" value="ps" />
|
||||
<generic name="gui_phase_shift17" value="0" />
|
||||
<generic name="gui_phase_shift_deg17" value="0.0" />
|
||||
<generic name="gui_actual_phase_shift17" value="0" />
|
||||
<generic name="gui_duty_cycle17" value="50" />
|
||||
<generic name="gui_pll_auto_reset" value="On" />
|
||||
<generic name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
<generic name="gui_en_reconf" value="false" />
|
||||
<generic name="gui_en_dps_ports" value="false" />
|
||||
<generic name="gui_en_phout_ports" value="false" />
|
||||
<generic name="gui_phout_division" value="1" />
|
||||
<generic name="gui_mif_generate" value="false" />
|
||||
<generic name="gui_enable_mif_dps" value="false" />
|
||||
<generic name="gui_dps_cntr" value="C0" />
|
||||
<generic name="gui_dps_num" value="1" />
|
||||
<generic name="gui_dps_dir" value="Positive" />
|
||||
<generic name="gui_refclk_switch" value="false" />
|
||||
<generic name="gui_refclk1_frequency" value="100.0" />
|
||||
<generic name="gui_switchover_mode" value="Automatic Switchover" />
|
||||
<generic name="gui_switchover_delay" value="0" />
|
||||
<generic name="gui_active_clk" value="false" />
|
||||
<generic name="gui_clk_bad" value="false" />
|
||||
<generic name="gui_enable_cascade_out" value="false" />
|
||||
<generic name="gui_cascade_outclk_index" value="0" />
|
||||
<generic name="gui_enable_cascade_in" value="false" />
|
||||
<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
|
||||
</instance>
|
||||
@@ -22,10 +22,12 @@ use ieee.numeric_std.all;
|
||||
entity AtomFpga_Core is
|
||||
port (
|
||||
-- Clocking
|
||||
clk_vga : in std_logic; -- nominally 25.175MHz VGA clock
|
||||
clk_vid : in std_logic; -- nominally 25.175MHz VGA clock
|
||||
clk_vid_en : in std_logic; -- nominally 25.175MHz VGA clock
|
||||
clk_main : in std_logic; -- clock for the main system
|
||||
clk_dac : in std_logic; -- fast clock for the 1-bit DAC
|
||||
clk_avr : in std_logic; -- clock for the AtoMMC AVR
|
||||
pixel_clock : out std_logic;
|
||||
|
||||
-- Keyboard/mouse
|
||||
ps2_key : in std_logic_vector (10 downto 0);
|
||||
@@ -257,7 +259,7 @@ architecture BEHAVIORAL of AtomFpga_Core is
|
||||
|
||||
signal clk_sid_1MHz : std_logic;
|
||||
|
||||
|
||||
signal reset_vid : std_logic;
|
||||
|
||||
--------------------------------------------------------------------
|
||||
-- here it begin :)
|
||||
@@ -329,7 +331,13 @@ begin
|
||||
not_cpu_R_W_n <= not cpu_R_W_n;
|
||||
|
||||
-- reset logic
|
||||
RSTn <= key_break and ext_reset_n;
|
||||
process (clk_main)
|
||||
begin
|
||||
if rising_edge(clk_main) then
|
||||
RSTn <= key_break and ext_reset_n;
|
||||
reset_vid <=not ext_reset_n;
|
||||
end if;
|
||||
end process;
|
||||
reset <= not RSTn;
|
||||
-- process(clk_main)
|
||||
-- begin
|
||||
@@ -346,24 +354,16 @@ begin
|
||||
|
||||
video_ram_we <= not_cpu_R_W_n and vid_cs;
|
||||
|
||||
|
||||
|
||||
process (clk_vga)
|
||||
begin
|
||||
if rising_edge(clk_vga) then
|
||||
clock_vga_en <= not clock_vga_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Motorola MC6847
|
||||
-- Original version: https://svn.pacedev.net/repos/pace/sw/src/component/video/mc6847.vhd
|
||||
-- Updated by AlanD for his Atom FPGA: http://stardot.org.uk/forums/viewtopic.php?f=3&t=6313
|
||||
-- A further few bugs fixed by myself
|
||||
Inst_mc6847 : entity work.mc6847
|
||||
port map (
|
||||
clk => clk_vga,
|
||||
clk_ena => clock_vga_en,
|
||||
reset => not ext_reset_n,
|
||||
clk => clk_vid,
|
||||
clk_ena => clk_vid_en,
|
||||
reset => reset_vid,
|
||||
da0 => open,
|
||||
videoaddr => vid_addr,
|
||||
dd => vid_data,
|
||||
@@ -388,7 +388,8 @@ begin
|
||||
cvbs => open,
|
||||
black_backgnd => BLACK_BACKGND,
|
||||
char_a => char_a,
|
||||
char_d_o => char_d_o
|
||||
char_d_o => char_d_o,
|
||||
pixel_clock => pixel_clock
|
||||
);
|
||||
|
||||
-- 8Kx8 Dual port video RAM
|
||||
@@ -401,7 +402,7 @@ begin
|
||||
addra => cpu_addr(12 downto 0),
|
||||
dina => cpu_dout,
|
||||
douta => vid_dout,
|
||||
clkb => clk_vga,
|
||||
clkb => clk_vid,
|
||||
web => '0',
|
||||
addrb => vid_addr,
|
||||
dinb => (others => '0'),
|
||||
@@ -412,7 +413,7 @@ begin
|
||||
---- ram for char generator
|
||||
charrom_inst : entity work.CharRom
|
||||
port map(
|
||||
CLK => clk_vga,
|
||||
CLK => clk_vid,
|
||||
ADDR => char_a,
|
||||
DATA => char_do
|
||||
);
|
||||
@@ -420,7 +421,7 @@ begin
|
||||
---- ram for xtra char generator
|
||||
charromx_inst : entity work.CharRomx
|
||||
port map(
|
||||
CLK => clk_vga,
|
||||
CLK => clk_vid,
|
||||
ADDR => char_a,
|
||||
DATA => charx_do
|
||||
);
|
||||
@@ -488,9 +489,9 @@ begin
|
||||
vga_blank <= (vga_vblank or vga_hblank);
|
||||
-- Making this a synchronous process should improve the timing
|
||||
-- and potentially make the pixels more defined
|
||||
process (clk_vga)
|
||||
process (clk_vid)
|
||||
begin
|
||||
if rising_edge(clk_vga) then
|
||||
if rising_edge(clk_vid) then
|
||||
if vga_blank = '1' then
|
||||
physical_colour <= (others => '0');
|
||||
else
|
||||
|
||||
@@ -7,7 +7,7 @@ entity mc6847 is
|
||||
generic
|
||||
(
|
||||
T1_VARIANT : boolean := false;
|
||||
CVBS_NOT_VGA : boolean := false);
|
||||
CVBS_NOT_VGA : boolean := true);
|
||||
port
|
||||
(
|
||||
clk : in std_logic;
|
||||
@@ -37,7 +37,8 @@ entity mc6847 is
|
||||
cvbs : out std_logic_vector(7 downto 0);
|
||||
black_backgnd : in std_logic;
|
||||
char_a : out std_logic_vector(11 downto 0);
|
||||
char_d_o : in std_logic_vector(7 downto 0)
|
||||
char_d_o : in std_logic_vector(7 downto 0);
|
||||
pixel_clock : out std_logic
|
||||
);
|
||||
end mc6847;
|
||||
|
||||
@@ -67,14 +68,25 @@ architecture SYN of mc6847 is
|
||||
-- constant H_RIGHT_BORDER : integer := H_VIDEO + 54;---3; -- tweak to get to 60hz exactly
|
||||
-- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
|
||||
|
||||
constant H_FRONT_PORCH : integer := 8;
|
||||
constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48;
|
||||
constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24;
|
||||
constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6
|
||||
constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16;
|
||||
constant H_VIDEO : integer := H_LEFT_BORDER + 256;
|
||||
constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- "
|
||||
constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
|
||||
|
||||
|
||||
constant H_FRONT_PORCH : integer := 11-1+1;
|
||||
constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 35+2;
|
||||
constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 34+1+2; -- AJS
|
||||
constant H_LEFT_BORDER : integer := H_BACK_PORCH + 61+1+3 ; -- adjust for hblank de-assert @sys_count=6
|
||||
constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16 +8;
|
||||
constant H_VIDEO : integer := H_LEFT_BORDER + 256;
|
||||
constant H_RIGHT_BORDER : integer := H_VIDEO + 61+1-3; -- "
|
||||
constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
|
||||
|
||||
-- constant H_FRONT_PORCH : integer := 8;
|
||||
-- constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48;
|
||||
-- constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24;
|
||||
-- constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6
|
||||
-- constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16;
|
||||
-- constant H_VIDEO : integer := H_LEFT_BORDER + 256;
|
||||
-- constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- "
|
||||
-- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
|
||||
|
||||
constant V2_FRONT_PORCH : integer := 2;
|
||||
constant V2_VERTICAL_SYNC : integer := V2_FRONT_PORCH + 2;
|
||||
@@ -93,6 +105,7 @@ architecture SYN of mc6847 is
|
||||
signal inv_s : std_logic;
|
||||
|
||||
-- VGA signals
|
||||
signal vga_clk_ena : std_logic;
|
||||
signal vga_hsync : std_logic;
|
||||
signal vga_vsync : std_logic;
|
||||
signal vga_hblank : std_logic;
|
||||
@@ -213,6 +226,7 @@ begin
|
||||
cvbs_clk_ena <= toggle;
|
||||
toggle := not toggle;
|
||||
end if;
|
||||
vga_clk_ena <= clk_ena;
|
||||
end if;
|
||||
end process PROC_CLOCKS;
|
||||
|
||||
@@ -229,7 +243,7 @@ begin
|
||||
vga_vsync <= '1';
|
||||
vga_hblank <= '0';
|
||||
|
||||
elsif rising_edge (clk) and clk_ena = '1' then
|
||||
elsif rising_edge (clk) and vga_clk_ena = '1' then
|
||||
|
||||
-- start hsync when cvbs comes out of vblank
|
||||
if vga_vblank_r = '1' and vga_vblank = '0' then
|
||||
@@ -273,7 +287,7 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- generate horizontal timing for CVBS
|
||||
-- generate horizontal timing f or CVBS
|
||||
-- generate line buffer address for writing CVBS char_d_o
|
||||
PROC_CVBS : process (clk, reset)
|
||||
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
|
||||
@@ -387,9 +401,9 @@ begin
|
||||
active_h_count := (others => '0');
|
||||
elsif h_count = H_LEFT_BORDER then
|
||||
cvbs_hblank <= '0';
|
||||
active_h_start <= '1';
|
||||
elsif h_count = H_VIDEO then
|
||||
cvbs_hblank <= '1';
|
||||
active_h_start <= '1';
|
||||
active_h_count := active_h_count + 1;
|
||||
elsif h_count = H_RIGHT_BORDER then
|
||||
null;
|
||||
@@ -421,15 +435,15 @@ begin
|
||||
cvbs_hblank_r := cvbs_hblank;
|
||||
|
||||
if an_g_s = '0' then
|
||||
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
|
||||
lookup(4 downto 0) <= active_h_count(7 downto 3);
|
||||
videoaddr <= videoaddr_base(12 downto 5) & lookup(4 downto 0);
|
||||
else
|
||||
case gm is --lookupaddr
|
||||
when "000" | "001" | "011" | "101" =>
|
||||
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
|
||||
lookup(3 downto 0) <= active_h_count(7 downto 4);
|
||||
videoaddr <= videoaddr_base(12 downto 4) & lookup(3 downto 0);
|
||||
when "010" | "100" | "110" | "111" =>
|
||||
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
|
||||
lookup(4 downto 0) <= active_h_count(7 downto 3);
|
||||
videoaddr <= videoaddr_base(12 downto 5) & lookup(4 downto 0);
|
||||
when others =>
|
||||
null;
|
||||
@@ -615,7 +629,8 @@ begin
|
||||
if CVBS_NOT_VGA then
|
||||
if cvbs_clk_ena = '1' then
|
||||
if cvbs_hblank = '0' and cvbs_vblank = '0' then
|
||||
map_palette (vga_char_d_o, r, g, b);
|
||||
--map_palette (vga_char_d_o, r, g, b);
|
||||
map_palette (pixel_char_d_o,r,g,b);
|
||||
else
|
||||
r := (others => '0');
|
||||
g := (others => '0');
|
||||
@@ -670,11 +685,13 @@ begin
|
||||
vsync <= cvbs_vsync;
|
||||
hblank <= cvbs_hblank;
|
||||
vblank <= cvbs_vblank;
|
||||
pixel_clock<=cvbs_clk_ena;
|
||||
else
|
||||
hsync <= vga_hsync;
|
||||
vsync <= vga_vsync;
|
||||
hblank <= not vga_hborder;
|
||||
vblank <= not cvbs_vborder;
|
||||
pixel_clock<=vga_clk_ena;
|
||||
end if;
|
||||
|
||||
end process PROC_OUTPUT;
|
||||
|
||||
@@ -1,6 +1,10 @@
|
||||
-- ****
|
||||
-- T65(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
-- Ver 315 SzGy April 2020
|
||||
-- Reduced the IRQ detection delay when RDY is not asserted (NMI?)
|
||||
-- Undocumented opcodes behavior change during not RDY and page boundary crossing (VICE tests - cpu/sha, cpu/shs, cpu/shxy)
|
||||
--
|
||||
-- Ver 313 WoS January 2015
|
||||
-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
|
||||
-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
|
||||
@@ -130,6 +134,8 @@ library IEEE;
|
||||
entity T65 is
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
|
||||
BCD_en : in std_logic := '1'; -- '0' => 2A03/2A07, '1' => others
|
||||
|
||||
Res_n : in std_logic;
|
||||
Enable : in std_logic;
|
||||
Clk : in std_logic;
|
||||
@@ -152,7 +158,8 @@ entity T65 is
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
|
||||
Regs : out std_logic_vector(63 downto 0);
|
||||
DEBUG : out T_t65_dbg
|
||||
DEBUG : out T_t65_dbg;
|
||||
NMI_ack : out std_logic
|
||||
);
|
||||
end T65;
|
||||
|
||||
@@ -175,7 +182,10 @@ architecture rtl of T65 is
|
||||
signal IR : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
|
||||
signal DO_r : std_logic_vector(7 downto 0);
|
||||
|
||||
signal Mode_r : std_logic_vector(1 downto 0);
|
||||
signal BCD_en_r : std_logic;
|
||||
signal ALU_Op_r : T_ALU_Op;
|
||||
signal Write_Data_r : T_Write_Data;
|
||||
signal Set_Addr_To_r : T_Set_Addr_To;
|
||||
@@ -208,6 +218,7 @@ architecture rtl of T65 is
|
||||
signal Write_Data : T_Write_Data;
|
||||
signal Jump : std_logic_vector(1 downto 0);
|
||||
signal BAAdd : std_logic_vector(1 downto 0);
|
||||
signal BAQuirk : std_logic_vector(1 downto 0);
|
||||
signal BreakAtNA : std_logic;
|
||||
signal ADAdd : std_logic;
|
||||
signal AddY : std_logic;
|
||||
@@ -230,12 +241,15 @@ architecture rtl of T65 is
|
||||
signal Res_n_i : std_logic;
|
||||
signal Res_n_d : std_logic;
|
||||
|
||||
signal rdy_mod : std_logic; -- RDY signal turned off during the instruction
|
||||
signal really_rdy : std_logic;
|
||||
signal WRn_i : std_logic;
|
||||
|
||||
signal NMI_entered : std_logic;
|
||||
|
||||
begin
|
||||
NMI_ack <= NMIAct;
|
||||
|
||||
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
|
||||
really_rdy <= Rdy or not(WRn_i);
|
||||
Sync <= '1' when MCycle = "000" else '0';
|
||||
@@ -265,6 +279,7 @@ begin
|
||||
IR => IR,
|
||||
MCycle => MCycle,
|
||||
P => P,
|
||||
Rdy_mod => rdy_mod,
|
||||
--outputs
|
||||
LCycle => LCycle,
|
||||
ALU_Op => ALU_Op,
|
||||
@@ -273,6 +288,7 @@ begin
|
||||
Write_Data => Write_Data,
|
||||
Jump => Jump,
|
||||
BAAdd => BAAdd,
|
||||
BAQuirk => BAQuirk,
|
||||
BreakAtNA => BreakAtNA,
|
||||
ADAdd => ADAdd,
|
||||
AddY => AddY,
|
||||
@@ -296,6 +312,7 @@ begin
|
||||
alu : entity work.T65_ALU
|
||||
port map(
|
||||
Mode => Mode_r,
|
||||
BCD_en => BCD_en_r,
|
||||
Op => ALU_Op_r,
|
||||
BusA => BusA_r,
|
||||
BusB => BusB,
|
||||
@@ -327,6 +344,7 @@ begin
|
||||
DBR <= (others => '0');
|
||||
|
||||
Mode_r <= (others => '0');
|
||||
BCD_en_r <= '1';
|
||||
ALU_Op_r <= ALU_OP_BIT;
|
||||
Write_Data_r <= Write_Data_DL;
|
||||
Set_Addr_To_r <= Set_Addr_To_PBR;
|
||||
@@ -338,6 +356,13 @@ begin
|
||||
|
||||
elsif Clk'event and Clk = '1' then
|
||||
if (Enable = '1') then
|
||||
-- some instructions behavior changed by the Rdy line. Detect this at the correct cycles.
|
||||
if MCycle = "000" then
|
||||
rdy_mod <= '0';
|
||||
elsif ((MCycle = "011" and IR /= x"93") or (MCycle = "100" and IR = x"93")) and Rdy = '0' then
|
||||
rdy_mod <= '1';
|
||||
end if;
|
||||
|
||||
if (really_rdy = '1') then
|
||||
WRn_i <= not Write or RstCycle;
|
||||
|
||||
@@ -349,6 +374,7 @@ begin
|
||||
|
||||
if MCycle = "000" then
|
||||
Mode_r <= Mode;
|
||||
BCD_en_r <= BCD_en;
|
||||
|
||||
if IRQCycle = '0' and NMICycle = '0' then
|
||||
PC <= PC + 1;
|
||||
@@ -376,7 +402,7 @@ begin
|
||||
if Inc_S = '1' then
|
||||
S <= S + 1;
|
||||
end if;
|
||||
if Dec_S = '1' and RstCycle = '0' then
|
||||
if Dec_S = '1' and (RstCycle = '0' or Mode="00") then -- 6502 only?
|
||||
S <= S - 1;
|
||||
end if;
|
||||
|
||||
@@ -463,9 +489,6 @@ begin
|
||||
--This should happen after P has been pushed to stack
|
||||
tmpP(Flag_I) := '1';
|
||||
end if;
|
||||
if SO_n_o = '1' and SO_n = '0' then
|
||||
tmpP(Flag_V) := '1';
|
||||
end if;
|
||||
if RstCycle = '1' then
|
||||
tmpP(Flag_I) := '1';
|
||||
tmpP(Flag_D) := '0';
|
||||
@@ -474,16 +497,24 @@ begin
|
||||
|
||||
P<=tmpP;--new way
|
||||
|
||||
SO_n_o <= SO_n;
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
|
||||
IRQ_n_o <= IRQ_n;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- detect irq even if not rdy
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" or really_rdy = '0' then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
|
||||
IRQ_n_o <= IRQ_n;
|
||||
end if;
|
||||
-- detect nmi even if not rdy
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
|
||||
NMI_n_o <= NMI_n;
|
||||
end if;
|
||||
end if;
|
||||
-- act immediately on SO pin change
|
||||
-- The signal is sampled on the trailing edge of phi1 and must be externally synchronized (from datasheet)
|
||||
SO_n_o <= SO_n;
|
||||
if SO_n_o = '1' and SO_n = '0' then
|
||||
P(Flag_V) <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
@@ -505,8 +536,8 @@ begin
|
||||
DL <= (others => '0');
|
||||
elsif Clk'event and Clk = '1' then
|
||||
if (Enable = '1') then
|
||||
NMI_entered <= '0';
|
||||
if (really_rdy = '1') then
|
||||
NMI_entered <= '0';
|
||||
BusA_r <= BusA;
|
||||
BusB <= DI;
|
||||
|
||||
@@ -526,7 +557,13 @@ begin
|
||||
when "11" =>
|
||||
-- BA Adj
|
||||
if BAL(8) = '1' then
|
||||
BAH <= std_logic_vector(unsigned(BAH) + 1);
|
||||
-- Handle quirks with some undocumented opcodes crossing page boundary
|
||||
case BAQuirk is
|
||||
when "00" => BAH <= std_logic_vector(unsigned(BAH) + 1); -- no quirk
|
||||
when "01" => BAH <= std_logic_vector(unsigned(BAH) + 1) and DO_r;
|
||||
when "10" => BAH <= DO_r;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
@@ -604,8 +641,10 @@ begin
|
||||
-- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
|
||||
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
|
||||
|
||||
DO <= DO_r;
|
||||
|
||||
with Write_Data_r select
|
||||
DO <=
|
||||
DO_r <=
|
||||
DL when Write_Data_DL,
|
||||
ABC(7 downto 0) when Write_Data_ABC,
|
||||
X(7 downto 0) when Write_Data_X,
|
||||
|
||||
@@ -57,6 +57,7 @@ use work.T65_Pack.all;
|
||||
entity T65_ALU is
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
|
||||
BCD_en : in std_logic;
|
||||
Op : in T_ALU_OP;
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
@@ -83,7 +84,7 @@ architecture rtl of T65_ALU is
|
||||
|
||||
begin
|
||||
|
||||
process (P_In, BusA, BusB)
|
||||
process (P_In, BusA, BusB, BCD_en)
|
||||
variable AL : unsigned(6 downto 0);
|
||||
variable AH : unsigned(6 downto 0);
|
||||
variable C : std_logic;
|
||||
@@ -102,7 +103,7 @@ begin
|
||||
ADC_Z <= '0';
|
||||
end if;
|
||||
|
||||
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
|
||||
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
|
||||
AL(6 downto 1) := AL(6 downto 1) + 6;
|
||||
end if;
|
||||
|
||||
@@ -116,7 +117,7 @@ begin
|
||||
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
|
||||
-- pragma translate_on
|
||||
|
||||
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
|
||||
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
|
||||
AH(6 downto 1) := AH(6 downto 1) + 6;
|
||||
end if;
|
||||
|
||||
@@ -125,7 +126,7 @@ begin
|
||||
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
|
||||
end process;
|
||||
|
||||
process (Op, P_In, BusA, BusB)
|
||||
process (Op, P_In, BusA, BusB, BCD_en)
|
||||
variable AL : unsigned(6 downto 0);
|
||||
variable AH : unsigned(5 downto 0);
|
||||
variable C : std_logic;
|
||||
@@ -165,7 +166,7 @@ begin
|
||||
|
||||
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
|
||||
|
||||
if P_In(Flag_D) = '1' then
|
||||
if P_In(Flag_D) = '1' and BCD_en = '1' then
|
||||
if AL(5) = '1' then
|
||||
AL(5 downto 1) := AL(5 downto 1) - 6;
|
||||
end if;
|
||||
@@ -180,16 +181,16 @@ begin
|
||||
|
||||
process (Op, P_In, BusA, BusB,
|
||||
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
|
||||
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
|
||||
SBX_Q)
|
||||
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
|
||||
SBX_Q, BCD_en)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable Q2_t : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
|
||||
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
|
||||
P_Out <= P_In;
|
||||
Q_t := BusA;
|
||||
Q2_t := BusA;
|
||||
Q_t := BusA;
|
||||
Q2_t := BusA;
|
||||
case Op is
|
||||
when ALU_OP_OR=>
|
||||
Q_t := BusA or BusB;
|
||||
@@ -226,7 +227,7 @@ begin
|
||||
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
|
||||
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
|
||||
Q2_t := Q_t;
|
||||
if P_In(Flag_D)='1' then
|
||||
if P_In(Flag_D)='1' and BCD_en = '1' then
|
||||
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
|
||||
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
|
||||
end if;
|
||||
|
||||
@@ -61,6 +61,7 @@ entity T65_MCode is
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
MCycle : in T_Lcycle;
|
||||
P : in std_logic_vector(7 downto 0);
|
||||
Rdy_mod : in std_logic;
|
||||
LCycle : out T_Lcycle;
|
||||
ALU_Op : out T_ALU_Op;
|
||||
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
|
||||
@@ -68,6 +69,7 @@ entity T65_MCode is
|
||||
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
|
||||
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
|
||||
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
|
||||
BAQuirk : out std_logic_vector(1 downto 0); -- None,And,Copy
|
||||
BreakAtNA : out std_logic;
|
||||
ADAdd : out std_logic;
|
||||
AddY : out std_logic;
|
||||
@@ -106,7 +108,7 @@ begin
|
||||
not P(Flag_Z) when "110",
|
||||
P(Flag_Z) when others;
|
||||
|
||||
process (IR, MCycle, P, Branch, Mode)
|
||||
process (IR, MCycle, P, Branch, Mode, Rdy_mod)
|
||||
begin
|
||||
lCycle <= Cycle_1;
|
||||
Set_BusA_To <= Set_BusA_To_ABC;
|
||||
@@ -114,6 +116,7 @@ begin
|
||||
Write_Data <= Write_Data_DL;
|
||||
Jump <= (others => '0');
|
||||
BAAdd <= "00";
|
||||
BAQuirk <= "00";
|
||||
BreakAtNA <= '0';
|
||||
ADAdd <= '0';
|
||||
PCAdd <= '0';
|
||||
@@ -140,14 +143,22 @@ begin
|
||||
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
|
||||
Set_BusA_To <= Set_BusA_To_Y;
|
||||
if IR(4 downto 2)="111" then -- SYA ($9C)
|
||||
Write_Data <= Write_Data_YB;
|
||||
if Rdy_mod = '0' then
|
||||
Write_Data <= Write_Data_YB;
|
||||
else
|
||||
Write_Data <= Write_Data_Y;
|
||||
end if;
|
||||
else
|
||||
Write_Data <= Write_Data_Y;
|
||||
end if;
|
||||
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
|
||||
Set_BusA_To <= Set_BusA_To_X;
|
||||
if IR(4 downto 2)="111" then -- SXA ($9E)
|
||||
Write_Data <= Write_Data_XB;
|
||||
if Rdy_mod = '0' then
|
||||
Write_Data <= Write_Data_XB;
|
||||
else
|
||||
Write_Data <= Write_Data_X;
|
||||
end if;
|
||||
else
|
||||
Write_Data <= Write_Data_X;
|
||||
end if;
|
||||
@@ -159,7 +170,11 @@ begin
|
||||
Set_BusA_To <= Set_BusA_To_ABC;
|
||||
end if;
|
||||
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
|
||||
Write_Data <= Write_Data_AXB;
|
||||
if Rdy_mod = '0' then
|
||||
Write_Data <= Write_Data_AXB;
|
||||
else
|
||||
Write_Data <= Write_Data_AX;
|
||||
end if;
|
||||
else
|
||||
Write_Data <= Write_Data_AX;
|
||||
end if;
|
||||
@@ -843,6 +858,9 @@ begin
|
||||
BAAdd <= "11"; -- BA Adj
|
||||
if IR(7 downto 5) = "100" then
|
||||
Write <= '1';
|
||||
if IR(3 downto 0) = x"3" then
|
||||
BAQuirk <= "10"; -- COPY
|
||||
end if;
|
||||
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
|
||||
BreakAtNA <= '1';
|
||||
end if;
|
||||
@@ -956,6 +974,9 @@ begin
|
||||
BAAdd <= "11"; -- BA adj
|
||||
if IR(7 downto 5) = "100" then--99/9b
|
||||
Write <= '1';
|
||||
if IR(3 downto 0) = x"B" then
|
||||
BAQuirk <= "01"; -- AND
|
||||
end if;
|
||||
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
|
||||
BreakAtNA <= '1';
|
||||
end if;
|
||||
@@ -1045,8 +1066,13 @@ begin
|
||||
Set_Addr_To <= Set_Addr_To_BA;
|
||||
when Cycle_3 =>
|
||||
BAAdd <= "11"; -- BA adj
|
||||
if IR(7 downto 5) = "100" then -- ($9E,$9F)
|
||||
if IR(7 downto 5) = "100" then -- ($9C,$9D,$9E,$9F)
|
||||
Write <= '1';
|
||||
case IR(1 downto 0) is
|
||||
when "00"|"10" => BAQuirk <= "01"; -- AND
|
||||
when "11" => BAQuirk <= "10"; -- COPY
|
||||
when others => null;
|
||||
end case;
|
||||
else
|
||||
BreakAtNA <= '1';
|
||||
end if;
|
||||
|
||||
@@ -177,4 +177,4 @@ package body T65_Pack is
|
||||
end case;
|
||||
end CycleNext;
|
||||
|
||||
end T65_Pack;
|
||||
end T65_Pack;
|
||||
4
rtl/T65/t65.qip
Normal file
4
rtl/T65/t65.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_Pack.vhd ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_ALU.vhd ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_MCode.vhd ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65.vhd ]
|
||||
104
rtl/pll.bsf
Normal file
104
rtl/pll.bsf
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel MegaCore Function License Agreement, or other
|
||||
applicable license agreement, including, without limitation,
|
||||
that your use is for the sole purpose of programming logic
|
||||
devices manufactured by Intel and sold by Intel or its
|
||||
authorized distributors. Please refer to the applicable
|
||||
agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 224)
|
||||
(text "pll" (rect 74 -1 81 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 208 20 220)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
|
||||
(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
|
||||
(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 48 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
|
||||
(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 112 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 112)
|
||||
(output)
|
||||
(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
|
||||
(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 112)(pt 112 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 152)
|
||||
(output)
|
||||
(text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8)))
|
||||
(text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 152)(pt 112 152)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 192)
|
||||
(output)
|
||||
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
|
||||
(text "locked" (rect 127 181 163 192)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 192)(pt 112 192)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
|
||||
(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
|
||||
(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
|
||||
(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
|
||||
(text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0)))
|
||||
(text "locked" (rect 113 163 262 339)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 82 187 200 384)(font "Arial" (color 0 0 0)))
|
||||
(text " altera_pll " (rect 118 208 308 426)(font "Arial" ))
|
||||
(line (pt 48 32)(pt 112 32)(line_width 1))
|
||||
(line (pt 112 32)(pt 112 208)(line_width 1))
|
||||
(line (pt 48 208)(pt 112 208)(line_width 1))
|
||||
(line (pt 48 32)(pt 48 208)(line_width 1))
|
||||
(line (pt 49 52)(pt 49 76)(line_width 1))
|
||||
(line (pt 50 52)(pt 50 76)(line_width 1))
|
||||
(line (pt 49 92)(pt 49 116)(line_width 1))
|
||||
(line (pt 50 92)(pt 50 116)(line_width 1))
|
||||
(line (pt 111 52)(pt 111 76)(line_width 1))
|
||||
(line (pt 110 52)(pt 110 76)(line_width 1))
|
||||
(line (pt 111 92)(pt 111 116)(line_width 1))
|
||||
(line (pt 110 92)(pt 110 116)(line_width 1))
|
||||
(line (pt 111 132)(pt 111 156)(line_width 1))
|
||||
(line (pt 110 132)(pt 110 156)(line_width 1))
|
||||
(line (pt 111 172)(pt 111 196)(line_width 1))
|
||||
(line (pt 110 172)(pt 110 196)(line_width 1))
|
||||
(line (pt 0 0)(pt 160 0)(line_width 1))
|
||||
(line (pt 160 0)(pt 160 224)(line_width 1))
|
||||
(line (pt 0 224)(pt 160 224)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 224)(line_width 1))
|
||||
)
|
||||
)
|
||||
11
rtl/pll.cmp
Normal file
11
rtl/pll.cmp
Normal file
@@ -0,0 +1,11 @@
|
||||
component pll is
|
||||
port (
|
||||
refclk : in std_logic := 'X'; -- clk
|
||||
rst : in std_logic := 'X'; -- reset
|
||||
outclk_0 : out std_logic; -- clk
|
||||
outclk_1 : out std_logic; -- clk
|
||||
outclk_2 : out std_logic; -- clk
|
||||
locked : out std_logic -- export
|
||||
);
|
||||
end component pll;
|
||||
|
||||
15
rtl/pll.ppf
Normal file
15
rtl/pll.ppf
Normal file
@@ -0,0 +1,15 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<pinplan
|
||||
variation_name="pll"
|
||||
megafunction_name="ALTERA_PLL"
|
||||
intended_family="Cyclone V"
|
||||
specifies="all_ports">
|
||||
<global>
|
||||
<pin name="refclk" direction="input" scope="external" />
|
||||
<pin name="rst" direction="input" scope="external" />
|
||||
<pin name="outclk_0" direction="output" scope="external" />
|
||||
<pin name="outclk_1" direction="output" scope="external" />
|
||||
<pin name="outclk_2" direction="output" scope="external" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
</global>
|
||||
</pinplan>
|
||||
55
rtl/pll.qip
55
rtl/pll.qip
@@ -1,5 +1,5 @@
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
@@ -11,19 +11,18 @@ set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NA
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
@@ -36,17 +35,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NDIuOTU0::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjIw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@@ -54,11 +53,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MzAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@@ -66,11 +65,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MzI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NTkw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@@ -80,9 +79,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@@ -90,11 +89,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::NDIuOTU0::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MjIw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
@@ -257,16 +256,16 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NDIuOTU0NTQ1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MzEuNTAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MjUuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTYuMDE2OTQ5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MzIuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
|
||||
@@ -318,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw4LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjUsMjUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTYsMTYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTMsMTIsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxLDIwLDQwMDAsODAwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OTUsOTQsNSw1LGZhbHNlLGZhbHNlLHRydWUsZmFsc2UsMTEsMTEsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTUsMTUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMzAsMjksMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxLDIwLDEyMDAwLDk0NS4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
@@ -334,5 +333,5 @@ set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qi
|
||||
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||
|
||||
6
rtl/pll.sip
Normal file
6
rtl/pll.sip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "lib_pll" -name SPD_FILE [file join $::quartus(sip_path) "pll.spd"]
|
||||
|
||||
set_global_assignment -library "lib_pll" -name MISC_FILE [file join $::quartus(sip_path) "pll_sim/pll.vo"]
|
||||
6
rtl/pll.spd
Normal file
6
rtl/pll.spd
Normal file
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<simPackage>
|
||||
<file path="pll_sim/pll.vo" type="VERILOG" />
|
||||
<topLevel name="pll" />
|
||||
<deviceFamily name="cyclonev" />
|
||||
</simPackage>
|
||||
22
rtl/pll.v
22
rtl/pll.v
@@ -1,8 +1,8 @@
|
||||
// megafunction wizard: %Altera PLL v17.1%
|
||||
// megafunction wizard: %Altera PLL v17.0%
|
||||
// GENERATION: XML
|
||||
// pll.v
|
||||
|
||||
// Generated using ACDS version 17.1 593
|
||||
// Generated using ACDS version 17.0 602
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll (
|
||||
@@ -11,7 +11,6 @@ module pll (
|
||||
output wire outclk_0, // outclk0.clk
|
||||
output wire outclk_1, // outclk1.clk
|
||||
output wire outclk_2, // outclk2.clk
|
||||
output wire outclk_3, // outclk3.clk
|
||||
output wire locked // locked.export
|
||||
);
|
||||
|
||||
@@ -21,7 +20,6 @@ module pll (
|
||||
.outclk_0 (outclk_0), // outclk0.clk
|
||||
.outclk_1 (outclk_1), // outclk1.clk
|
||||
.outclk_2 (outclk_2), // outclk2.clk
|
||||
.outclk_3 (outclk_3), // outclk3.clk
|
||||
.locked (locked) // locked.export
|
||||
);
|
||||
|
||||
@@ -32,7 +30,7 @@ endmodule
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2020 Altera Corporation
|
||||
// Copyright (C) 1991-2022 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
@@ -52,11 +50,11 @@ endmodule
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.1" >
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="Unknown" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
@@ -67,12 +65,12 @@ endmodule
|
||||
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
// Retrieval info: <generic name="gui_use_locked" value="true" />
|
||||
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="4" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="3" />
|
||||
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency0" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency0" value="42.954" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
|
||||
@@ -81,7 +79,7 @@ endmodule
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency1" value="16.0" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency1" value="32.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
@@ -90,7 +88,7 @@ endmodule
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency2" value="25.0" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency2" value="16.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
|
||||
@@ -108,7 +106,7 @@ endmodule
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency4" value="42.954" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
|
||||
|
||||
@@ -16,9 +16,6 @@ module pll_0002(
|
||||
// interface 'outclk2'
|
||||
output wire outclk_2,
|
||||
|
||||
// interface 'outclk3'
|
||||
output wire outclk_3,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked
|
||||
);
|
||||
@@ -27,17 +24,17 @@ module pll_0002(
|
||||
.fractional_vco_multiplier("false"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(4),
|
||||
.output_clock_frequency0("100.000000 MHz"),
|
||||
.number_of_clocks(3),
|
||||
.output_clock_frequency0("42.954545 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("16.000000 MHz"),
|
||||
.output_clock_frequency1("31.500000 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("25.000000 MHz"),
|
||||
.output_clock_frequency2("16.016949 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
.duty_cycle2(50),
|
||||
.output_clock_frequency3("32.000000 MHz"),
|
||||
.output_clock_frequency3("0 MHz"),
|
||||
.phase_shift3("0 ps"),
|
||||
.duty_cycle3(50),
|
||||
.output_clock_frequency4("0 MHz"),
|
||||
@@ -86,7 +83,7 @@ module pll_0002(
|
||||
.pll_subtype("General")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
|
||||
.outclk ({outclk_2, outclk_1, outclk_0}),
|
||||
.locked (locked),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
|
||||
1
rtl/pll_sim.f
Normal file
1
rtl/pll_sim.f
Normal file
@@ -0,0 +1 @@
|
||||
pll_sim/pll.vo
|
||||
278
rtl/pll_sim/aldec/rivierapro_setup.tcl
Normal file
278
rtl/pll_sim/aldec/rivierapro_setup.tcl
Normal file
@@ -0,0 +1,278 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Altera simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "aldec.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog -sv2k5 <your compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "pll"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/17.0/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
||||
} else {
|
||||
}
|
||||
|
||||
set Aldec "Riviera"
|
||||
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
|
||||
set Aldec "Active"
|
||||
}
|
||||
|
||||
if { [ string match "Active" $Aldec ] } {
|
||||
scripterconf -tcl
|
||||
createdesign "$TOP_LEVEL_NAME" "."
|
||||
opendesign "$TOP_LEVEL_NAME"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries
|
||||
ensure_lib ./libraries/work
|
||||
vmap work ./libraries/work
|
||||
ensure_lib ./libraries/altera_ver
|
||||
vmap altera_ver ./libraries/altera_ver
|
||||
ensure_lib ./libraries/lpm_ver
|
||||
vmap lpm_ver ./libraries/lpm_ver
|
||||
ensure_lib ./libraries/sgate_ver
|
||||
vmap sgate_ver ./libraries/sgate_ver
|
||||
ensure_lib ./libraries/altera_mf_ver
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver
|
||||
ensure_lib ./libraries/altera_lnsim_ver
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
|
||||
ensure_lib ./libraries/cyclonev_ver
|
||||
vmap cyclonev_ver ./libraries/cyclonev_ver
|
||||
ensure_lib ./libraries/cyclonev_hssi_ver
|
||||
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
|
||||
ensure_lib ./libraries/cyclonev_pcie_hip_ver
|
||||
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
echo "\[exec\] dev_com"
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
echo "\[exec\] com"
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll.vo"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
echo "\[exec\] elab"
|
||||
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -dbg -O2 option
|
||||
alias elab_debug {
|
||||
echo "\[exec\] elab_debug"
|
||||
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -dbg -O2
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Qsys base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
19
rtl/pll_sim/cadence/cds.lib
Normal file
19
rtl/pll_sim/cadence/cds.lib
Normal file
@@ -0,0 +1,19 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
DEFINE work ./libraries/work/
|
||||
DEFINE altera_ver ./libraries/altera_ver/
|
||||
DEFINE lpm_ver ./libraries/lpm_ver/
|
||||
DEFINE sgate_ver ./libraries/sgate_ver/
|
||||
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
|
||||
DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
|
||||
DEFINE cyclonev_ver ./libraries/cyclonev_ver/
|
||||
DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
|
||||
DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
|
||||
2
rtl/pll_sim/cadence/hdl.var
Normal file
2
rtl/pll_sim/cadence/hdl.var
Normal file
@@ -0,0 +1,2 @@
|
||||
|
||||
DEFINE WORK work
|
||||
195
rtl/pll_sim/cadence/ncsim_setup.sh
Normal file
195
rtl/pll_sim/cadence/ncsim_setup.sh
Normal file
@@ -0,0 +1,195 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
|
||||
# ----------------------------------------
|
||||
# ncsim - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated files
|
||||
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
|
||||
# # into the location from which you launch the simulator, or incorporate
|
||||
# # into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/cadence/ncsim_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# ncvlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/cadence/ncsim_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="pll"
|
||||
QSYS_SIMDIR="./../"
|
||||
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/17.0/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
mkdir -p ./libraries/work/
|
||||
mkdir -p ./libraries/altera_ver/
|
||||
mkdir -p ./libraries/lpm_ver/
|
||||
mkdir -p ./libraries/sgate_ver/
|
||||
mkdir -p ./libraries/altera_mf_ver/
|
||||
mkdir -p ./libraries/altera_lnsim_ver/
|
||||
mkdir -p ./libraries/cyclonev_ver/
|
||||
mkdir -p ./libraries/cyclonev_hssi_ver/
|
||||
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll.vo"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
export GENERIC_PARAM_COMPAT_CHECK=1
|
||||
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
272
rtl/pll_sim/mentor/msim_setup.tcl
Normal file
272
rtl/pll_sim/mentor/msim_setup.tcl
Normal file
@@ -0,0 +1,272 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Altera simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "mentor.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run -a
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "pll"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/17.0/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
||||
} else {
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work/
|
||||
vmap work ./libraries/work/
|
||||
vmap work_lib ./libraries/work/
|
||||
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
|
||||
ensure_lib ./libraries/altera_ver/
|
||||
vmap altera_ver ./libraries/altera_ver/
|
||||
ensure_lib ./libraries/lpm_ver/
|
||||
vmap lpm_ver ./libraries/lpm_ver/
|
||||
ensure_lib ./libraries/sgate_ver/
|
||||
vmap sgate_ver ./libraries/sgate_ver/
|
||||
ensure_lib ./libraries/altera_mf_ver/
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver/
|
||||
ensure_lib ./libraries/altera_lnsim_ver/
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
|
||||
ensure_lib ./libraries/cyclonev_ver/
|
||||
vmap cyclonev_ver ./libraries/cyclonev_ver/
|
||||
ensure_lib ./libraries/cyclonev_hssi_ver/
|
||||
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
|
||||
ensure_lib ./libraries/cyclonev_pcie_hip_ver/
|
||||
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
echo "\[exec\] dev_com"
|
||||
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
echo "\[exec\] com"
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll.vo"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
echo "\[exec\] elab"
|
||||
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with novopt option
|
||||
alias elab_debug {
|
||||
echo "\[exec\] elab_debug"
|
||||
eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -novopt
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with novopt option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Qsys base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
303
rtl/pll_sim/pll.vo
Normal file
303
rtl/pll_sim/pll.vo
Normal file
@@ -0,0 +1,303 @@
|
||||
//IP Functional Simulation Model
|
||||
//VERSION_BEGIN 17.0 cbx_mgl 2017:07:19:18:10:29:SJ cbx_simgen 2017:07:19:18:07:03:SJ VERSION_END
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
|
||||
// Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel MegaCore Function License Agreement, or other
|
||||
// applicable license agreement, including, without limitation,
|
||||
// that your use is for the sole purpose of programming logic
|
||||
// devices manufactured by Intel and sold by Intel or its
|
||||
// authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
// You may only use these simulation model output files for simulation
|
||||
// purposes and expressly not for synthesis or any other purposes (in which
|
||||
// event Intel disclaims all warranties of any kind).
|
||||
|
||||
|
||||
//synopsys translate_off
|
||||
|
||||
//synthesis_resources = altera_pll 1
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll
|
||||
(
|
||||
locked,
|
||||
outclk_0,
|
||||
outclk_1,
|
||||
outclk_2,
|
||||
refclk,
|
||||
rst) /* synthesis synthesis_clearbox=1 */;
|
||||
output locked;
|
||||
output outclk_0;
|
||||
output outclk_1;
|
||||
output outclk_2;
|
||||
input refclk;
|
||||
input rst;
|
||||
|
||||
wire wire_pll_altera_pll_altera_pll_i_1557_locked;
|
||||
wire [2:0] wire_pll_altera_pll_altera_pll_i_1557_outclk;
|
||||
|
||||
altera_pll pll_altera_pll_altera_pll_i_1557
|
||||
(
|
||||
.fbclk(1'b0),
|
||||
.locked(wire_pll_altera_pll_altera_pll_i_1557_locked),
|
||||
.outclk(wire_pll_altera_pll_altera_pll_i_1557_outclk),
|
||||
.refclk(refclk),
|
||||
.rst(rst));
|
||||
defparam
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en0 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en1 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en10 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en11 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en12 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en13 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en14 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en15 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en16 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en17 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en2 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en3 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en4 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en5 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en6 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en7 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en8 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_bypass_en9 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div0 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div1 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div10 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div11 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div12 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div13 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div14 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div15 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div16 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div17 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div2 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div3 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div4 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div5 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div6 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div7 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div8 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_hi_div9 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src0 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src1 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src10 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src11 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src12 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src13 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src14 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src15 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src16 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src17 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src2 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src3 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src4 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src5 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src6 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src7 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src8 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_in_src9 = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div0 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div1 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div10 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div11 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div12 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div13 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div14 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div15 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div16 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div17 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div2 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div3 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div4 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div5 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div6 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div7 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div8 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_lo_div9 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en0 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en1 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en10 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en11 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en12 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en13 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en14 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en15 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en16 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en17 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en2 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en3 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en4 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en5 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en6 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en7 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en8 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_odd_div_duty_en9 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst0 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst1 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst10 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst11 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst12 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst13 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst14 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst15 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst16 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst17 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst2 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst3 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst4 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst5 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst6 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst7 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst8 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_ph_mux_prst9 = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst0 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst1 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst10 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst11 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst12 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst13 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst14 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst15 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst16 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst17 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst2 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst3 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst4 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst5 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst6 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst7 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst8 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.c_cnt_prst9 = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_0 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_1 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_2 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_3 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_4 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_5 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_6 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_7 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_8 = "UNUSED",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_0 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_1 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_2 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_3 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_4 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_5 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_6 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_7 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.clock_name_global_8 = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.data_rate = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.deserialization_factor = 4,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle0 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle1 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle10 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle11 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle12 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle13 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle14 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle15 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle16 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle17 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle2 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle3 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle4 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle5 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle6 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle7 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle8 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.duty_cycle9 = 50,
|
||||
pll_altera_pll_altera_pll_i_1557.fractional_vco_multiplier = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.m_cnt_bypass_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.m_cnt_hi_div = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.m_cnt_lo_div = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.m_cnt_odd_div_duty_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.mimic_fbclk_type = "gclk",
|
||||
pll_altera_pll_altera_pll_i_1557.n_cnt_bypass_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.n_cnt_hi_div = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.n_cnt_lo_div = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.n_cnt_odd_div_duty_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.number_of_clocks = 3,
|
||||
pll_altera_pll_altera_pll_i_1557.operation_mode = "direct",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency0 = "42.954545 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency1 = "31.500000 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency10 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency11 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency12 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency13 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency14 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency15 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency16 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency17 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency2 = "16.016949 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency3 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency4 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency5 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency6 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency7 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency8 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.output_clock_frequency9 = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift0 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift1 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift10 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift11 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift12 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift13 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift14 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift15 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift16 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift17 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift2 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift3 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift4 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift5 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift6 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift7 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift8 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.phase_shift9 = "0 ps",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_auto_clk_sw_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_bw_sel = "low",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_bwctrl = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.pll_clk_loss_sw_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_clk_sw_dly = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.pll_clkin_0_src = "clk_0",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_clkin_1_src = "clk_0",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_cp_current = 0,
|
||||
pll_altera_pll_altera_pll_i_1557.pll_dsm_out_sel = "1st_order",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_fbclk_mux_1 = "glb",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_fbclk_mux_2 = "fb_1",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_fractional_cout = 24,
|
||||
pll_altera_pll_altera_pll_i_1557.pll_fractional_division = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.pll_m_cnt_in_src = "ph_mux_clk",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_manu_clk_sw_en = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_output_clk_frequency = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_slf_rst = "false",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_subtype = "General",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_type = "General",
|
||||
pll_altera_pll_altera_pll_i_1557.pll_vco_div = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.pll_vcoph_div = 1,
|
||||
pll_altera_pll_altera_pll_i_1557.refclk1_frequency = "0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.reference_clock_frequency = "50.0 MHz",
|
||||
pll_altera_pll_altera_pll_i_1557.sim_additional_refclk_cycles_to_lock = 0;
|
||||
assign
|
||||
locked = wire_pll_altera_pll_altera_pll_i_1557_locked,
|
||||
outclk_0 = wire_pll_altera_pll_altera_pll_i_1557_outclk[0],
|
||||
outclk_1 = wire_pll_altera_pll_altera_pll_i_1557_outclk[1],
|
||||
outclk_2 = wire_pll_altera_pll_altera_pll_i_1557_outclk[2];
|
||||
endmodule //pll
|
||||
//synopsys translate_on
|
||||
//VALID FILE
|
||||
152
rtl/pll_sim/synopsys/vcs/vcs_setup.sh
Normal file
152
rtl/pll_sim/synopsys/vcs/vcs_setup.sh
Normal file
@@ -0,0 +1,152 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
|
||||
# ----------------------------------------
|
||||
# vcs - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, follow the guidelines below.
|
||||
#
|
||||
# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
|
||||
# below into a new file, e.g. named "vcs_sim.sh".
|
||||
#
|
||||
# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
|
||||
# a separate file, e.g. named "filelist.f".
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
|
||||
# # set the top-level simulation or testbench module/entity name.
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# # Source the Quartus-generated IP simulation script and do the following:
|
||||
# # - Compile the Quartus EDA simulation library and IP simulation files.
|
||||
# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
|
||||
# # - Compile the design and top-level simulation module/entity using
|
||||
# # information specified in "filelist.f".
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# # - Run the simulation.
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# +systemverilogext+.sv
|
||||
# <design and testbench files, compile-time options, elaboration options>
|
||||
# #
|
||||
# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="pll"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/17.0/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
|
||||
$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
|
||||
$QSYS_SIMDIR/pll.vo \
|
||||
-top $TOP_LEVEL_NAME
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
13
rtl/pll_sim/synopsys/vcsmx/synopsys_sim.setup
Normal file
13
rtl/pll_sim/synopsys/vcsmx/synopsys_sim.setup
Normal file
@@ -0,0 +1,13 @@
|
||||
|
||||
WORK > DEFAULT
|
||||
DEFAULT: ./libraries/work/
|
||||
work: ./libraries/work/
|
||||
altera_ver: ./libraries/altera_ver/
|
||||
lpm_ver: ./libraries/lpm_ver/
|
||||
sgate_ver: ./libraries/sgate_ver/
|
||||
altera_mf_ver: ./libraries/altera_mf_ver/
|
||||
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
|
||||
cyclonev_ver: ./libraries/cyclonev_ver/
|
||||
cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
|
||||
cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
|
||||
LIBRARY_SCAN = TRUE
|
||||
195
rtl/pll_sim/synopsys/vcsmx/vcsmx_setup.sh
Normal file
195
rtl/pll_sim/synopsys/vcsmx/vcsmx_setup.sh
Normal file
@@ -0,0 +1,195 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
|
||||
# ----------------------------------------
|
||||
# vcsmx - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated library
|
||||
# # setup "synopsys_sim.setup" into the location from which you launch the
|
||||
# # simulator, or incorporate into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# #
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# vlogan <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME="'-top <simulation top>'" \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 17.0 602 win32 2022.01.09.09:43:02
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="pll"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/17.0/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
mkdir -p ./libraries/work/
|
||||
mkdir -p ./libraries/altera_ver/
|
||||
mkdir -p ./libraries/lpm_ver/
|
||||
mkdir -p ./libraries/sgate_ver/
|
||||
mkdir -p ./libraries/altera_mf_ver/
|
||||
mkdir -p ./libraries/altera_lnsim_ver/
|
||||
mkdir -p ./libraries/cyclonev_ver/
|
||||
mkdir -p ./libraries/cyclonev_hssi_ver/
|
||||
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll.vo"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
@@ -112,9 +112,9 @@ wire scandoubler = fx || forced_scandoubler;
|
||||
|
||||
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
|
||||
(
|
||||
.clk_vid(CLK_VIDEO),
|
||||
.CLK_VIDEO(CLK_VIDEO),
|
||||
.ce_pix(CE),
|
||||
.ce_pix_out(CE_PIXEL),
|
||||
.CE_PIXEL(CE_PIXEL),
|
||||
|
||||
.scandoubler(scandoubler),
|
||||
.hq2x(fx==1),
|
||||
@@ -174,15 +174,16 @@ module screen_rotate
|
||||
|
||||
input rotate_ccw,
|
||||
input no_rotate,
|
||||
input flip,
|
||||
|
||||
output FB_EN,
|
||||
output [4:0] FB_FORMAT,
|
||||
output [11:0] FB_WIDTH,
|
||||
output [11:0] FB_HEIGHT,
|
||||
output [31:0] FB_BASE,
|
||||
output [13:0] FB_STRIDE,
|
||||
input FB_VBL,
|
||||
input FB_LL,
|
||||
output FB_EN,
|
||||
output [4:0] FB_FORMAT,
|
||||
output reg [11:0] FB_WIDTH,
|
||||
output reg [11:0] FB_HEIGHT,
|
||||
output [31:0] FB_BASE,
|
||||
output [13:0] FB_STRIDE,
|
||||
input FB_VBL,
|
||||
input FB_LL,
|
||||
|
||||
output DDRAM_CLK,
|
||||
input DDRAM_BUSY,
|
||||
@@ -196,6 +197,8 @@ module screen_rotate
|
||||
|
||||
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
|
||||
|
||||
reg do_flip;
|
||||
|
||||
assign DDRAM_CLK = CLK_VIDEO;
|
||||
assign DDRAM_BURSTCNT = 1;
|
||||
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
|
||||
@@ -204,11 +207,9 @@ assign DDRAM_DIN = {ram_data,ram_data};
|
||||
assign DDRAM_WE = ram_wr;
|
||||
assign DDRAM_RD = 0;
|
||||
|
||||
assign FB_EN = ~no_rotate;
|
||||
assign FB_EN = fb_en[2];
|
||||
assign FB_FORMAT = 5'b00110;
|
||||
assign FB_BASE = {MEM_BASE,o_fb,23'd0};
|
||||
assign FB_WIDTH = vsz;
|
||||
assign FB_HEIGHT = hsz;
|
||||
assign FB_STRIDE = stride;
|
||||
|
||||
function [1:0] buf_next;
|
||||
@@ -220,6 +221,17 @@ function [1:0] buf_next;
|
||||
end
|
||||
endfunction
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
do_flip <= no_rotate && flip;
|
||||
if( do_flip ) begin
|
||||
FB_WIDTH <= hsz;
|
||||
FB_HEIGHT <= vsz;
|
||||
end else begin
|
||||
FB_WIDTH <= vsz;
|
||||
FB_HEIGHT <= hsz;
|
||||
end
|
||||
end
|
||||
|
||||
reg [1:0] i_fb,o_fb;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_vbl,old_vs;
|
||||
@@ -236,6 +248,11 @@ always @(posedge CLK_VIDEO) begin
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
fb_en = 0;
|
||||
end
|
||||
|
||||
reg [2:0] fb_en = 0;
|
||||
reg [11:0] hsz = 320, vsz = 240;
|
||||
reg [11:0] bwidth;
|
||||
reg [22:0] bufsize;
|
||||
@@ -246,19 +263,23 @@ always @(posedge CLK_VIDEO) begin
|
||||
if(CE_PIXEL) begin
|
||||
old_vs <= VGA_VS;
|
||||
old_de <= VGA_DE;
|
||||
|
||||
|
||||
hcnt <= hcnt + 1'd1;
|
||||
if(~old_de & VGA_DE) begin
|
||||
hcnt <= 1;
|
||||
vcnt <= vcnt + 1'd1;
|
||||
end
|
||||
if(old_de & ~VGA_DE) hsz <= hcnt;
|
||||
if(old_de & ~VGA_DE) begin
|
||||
hsz <= hcnt;
|
||||
if( do_flip ) bwidth <= hcnt + 2'd3;
|
||||
end
|
||||
if(~old_vs & VGA_VS) begin
|
||||
vsz <= vcnt;
|
||||
bwidth <= vcnt + 2'd3;
|
||||
if( !do_flip ) bwidth <= vcnt + 2'd3;
|
||||
vcnt <= 0;
|
||||
fb_en <= {fb_en[1:0], ~no_rotate | flip};
|
||||
end
|
||||
if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
|
||||
if(old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz ) * stride;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -272,21 +293,25 @@ always @(posedge CLK_VIDEO) begin
|
||||
reg old_vs, old_de;
|
||||
|
||||
ram_wr <= 0;
|
||||
if(CE_PIXEL) begin
|
||||
if(CE_PIXEL && FB_EN) begin
|
||||
old_vs <= VGA_VS;
|
||||
old_de <= VGA_DE;
|
||||
|
||||
if(~old_vs & VGA_VS) begin
|
||||
next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
|
||||
next_addr <=
|
||||
do_flip ? bufsize-3'd4 :
|
||||
rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
|
||||
hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
|
||||
end
|
||||
if(VGA_DE) begin
|
||||
ram_wr <= 1;
|
||||
ram_data <= {VGA_B,VGA_G,VGA_R};
|
||||
ram_data <= {8'd0,VGA_B,VGA_G,VGA_R};
|
||||
ram_addr <= next_addr;
|
||||
next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
|
||||
next_addr <=
|
||||
do_flip ? next_addr-3'd4 :
|
||||
rotate_ccw ? (next_addr - stride) : (next_addr + stride);
|
||||
end
|
||||
if(old_de & ~VGA_DE) begin
|
||||
if(old_de & ~VGA_DE & ~do_flip) begin
|
||||
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
|
||||
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
|
||||
end
|
||||
|
||||
257
sys/ascal.vhd
257
sys/ascal.vhd
@@ -151,6 +151,7 @@ ENTITY ascal IS
|
||||
o_vs : OUT std_logic; -- V sync
|
||||
o_de : OUT std_logic; -- Display Enable
|
||||
o_vbl : OUT std_logic; -- V blank
|
||||
o_brd : OUT std_logic; -- border enable
|
||||
o_ce : IN std_logic; -- Clock Enable
|
||||
o_clk : IN std_logic; -- Output clock
|
||||
|
||||
@@ -382,8 +383,9 @@ ARCHITECTURE rtl OF ascal IS
|
||||
SIGNAL avl_o_vs_sync,avl_o_vs : std_logic;
|
||||
SIGNAL avl_fb_ena : std_logic;
|
||||
|
||||
FUNCTION buf_next(a,b : natural RANGE 0 TO 2) RETURN natural IS
|
||||
FUNCTION buf_next(a,b : natural RANGE 0 TO 2; freeze : std_logic := '0') RETURN natural IS
|
||||
BEGIN
|
||||
IF (freeze='1') THEN RETURN a; END IF;
|
||||
IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF;
|
||||
IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF;
|
||||
RETURN 1;
|
||||
@@ -400,6 +402,7 @@ ARCHITECTURE rtl OF ascal IS
|
||||
----------------------------------------------------------
|
||||
-- Output
|
||||
SIGNAL o_run : std_logic;
|
||||
SIGNAL o_freeze : std_logic;
|
||||
SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
|
||||
SIGNAL o_format : unsigned(5 DOWNTO 0);
|
||||
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
|
||||
@@ -429,7 +432,7 @@ ARCHITECTURE rtl OF ascal IS
|
||||
SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic;
|
||||
SIGNAL o_copyv : unsigned(0 TO 8);
|
||||
SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address
|
||||
SIGNAL o_adrs_pre : natural RANGE 0 TO 2**23-1;
|
||||
SIGNAL o_adrs_pre : natural RANGE 0 TO 2**24-1;
|
||||
SIGNAL o_stride : unsigned(13 DOWNTO 0);
|
||||
SIGNAL o_adrsa,o_adrsb,o_rline : std_logic;
|
||||
SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1;
|
||||
@@ -456,14 +459,15 @@ ARCHITECTURE rtl OF ascal IS
|
||||
SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
|
||||
SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 5);
|
||||
SIGNAL o_hsp,o_vss : std_logic;
|
||||
SIGNAL o_vcarrym,o_prim : boolean;
|
||||
SIGNAL o_read,o_read_pre : std_logic;
|
||||
SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2;
|
||||
SIGNAL o_hburst,o_hbcpt : natural RANGE 0 TO 31;
|
||||
SIGNAL o_fload : natural RANGE 0 TO 3;
|
||||
SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO
|
||||
SIGNAL o_dshi : natural RANGE 0 TO 3;
|
||||
SIGNAL o_first,o_last,o_last1,o_last2,o_last3 : std_logic;
|
||||
SIGNAL o_lastt1,o_lastt2,o_lastt3 : std_logic;
|
||||
SIGNAL o_first,o_last,o_last1,o_last2 : std_logic;
|
||||
SIGNAL o_lastt1,o_lastt2,o_lastt3,o_lastt4 : std_logic;
|
||||
SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0);
|
||||
SIGNAL o_hdown,o_vdown : std_logic;
|
||||
SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2);
|
||||
@@ -483,6 +487,7 @@ ARCHITECTURE rtl OF ascal IS
|
||||
SIGNAL o_divstart : std_logic;
|
||||
SIGNAL o_divrun : std_logic;
|
||||
SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0);
|
||||
SIGNAL o_vacptl : unsigned(1 DOWNTO 0);
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
FUNCTION shift_ishift(shift : unsigned(0 TO 119);
|
||||
@@ -703,8 +708,10 @@ ARCHITECTURE rtl OF ascal IS
|
||||
RETURN x;
|
||||
END FUNCTION;
|
||||
|
||||
SIGNAL o_h_frac2,o_v_frac : unsigned(FRAC-1 DOWNTO 0);
|
||||
SIGNAL o_h_near_frac,o_v_near_frac : unsigned(FRAC-1 DOWNTO 0);
|
||||
SIGNAL o_h_bil_frac,o_v_bil_frac : unsigned(FRAC-1 DOWNTO 0);
|
||||
SIGNAL o_h_bil_pix,o_v_bil_pix : type_pix;
|
||||
SIGNAL o_h_near_pix,o_v_near_pix : type_pix;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Nearest + Bilinear + Sharp Bilinear
|
||||
@@ -716,6 +723,7 @@ ARCHITECTURE rtl OF ascal IS
|
||||
TYPE type_bil_t IS RECORD
|
||||
r,g,b : unsigned(8+FRAC DOWNTO 0);
|
||||
END RECORD;
|
||||
|
||||
FUNCTION bil_calc(f : unsigned(FRAC-1 DOWNTO 0);
|
||||
p : arr_pix(0 TO 3)) RETURN type_bil_t IS
|
||||
VARIABLE fp,fn : unsigned(FRAC DOWNTO 0);
|
||||
@@ -723,7 +731,7 @@ ARCHITECTURE rtl OF ascal IS
|
||||
VARIABLE x : type_bil_t;
|
||||
CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0');
|
||||
BEGIN
|
||||
fp:='0' & f;
|
||||
fp:=('0' & f) + (Z & f(FRAC-1));
|
||||
fn:=('1' & Z) - fp;
|
||||
u:=p(2).r * fp + p(1).r * fn;
|
||||
x.r:=u;
|
||||
@@ -733,7 +741,27 @@ ARCHITECTURE rtl OF ascal IS
|
||||
x.b:=u;
|
||||
RETURN x;
|
||||
END FUNCTION;
|
||||
|
||||
FUNCTION near_calc(f : unsigned(FRAC-1 DOWNTO 0);
|
||||
p : arr_pix(0 TO 3)) RETURN type_bil_t IS
|
||||
VARIABLE fp,fn : unsigned(FRAC DOWNTO 0);
|
||||
VARIABLE u : unsigned(8+FRAC DOWNTO 0);
|
||||
VARIABLE x : type_bil_t;
|
||||
CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0');
|
||||
BEGIN
|
||||
IF f(FRAC-1)='0' THEN
|
||||
x.r := '0' & p(1).r & Z;
|
||||
x.g := '0' & p(1).g & Z;
|
||||
x.b := '0' & p(1).b & Z;
|
||||
ELSE
|
||||
x.r := '0' & p(2).r & Z;
|
||||
x.g := '0' & p(2).g & Z;
|
||||
x.b := '0' & p(2).b & Z;
|
||||
END IF;
|
||||
RETURN x;
|
||||
END FUNCTION;
|
||||
SIGNAL o_h_bil_t,o_v_bil_t : type_bil_t;
|
||||
SIGNAL o_h_near_t,o_v_near_t : type_bil_t;
|
||||
SIGNAL i_h_bil_t : type_bil_t;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
@@ -1519,7 +1547,7 @@ BEGIN
|
||||
avl_read_sync<=o_read; -- <ASYNC>
|
||||
avl_read_sync2<=avl_read_sync;
|
||||
avl_read_pulse<=avl_read_sync XOR avl_read_sync2;
|
||||
avl_radrs <=o_adrs AND (RAMSIZE - 1); -- <ASYNC>
|
||||
avl_radrs <=o_adrs; -- <ASYNC>
|
||||
avl_rline <=o_rline; -- <ASYNC>
|
||||
|
||||
--------------------------------------------
|
||||
@@ -1730,28 +1758,61 @@ BEGIN
|
||||
-- Triple buffering.
|
||||
-- For intelaced video, half frames are updated independently
|
||||
-- Input : Toggle buffer at end of input frame
|
||||
o_freeze <= freeze;
|
||||
o_inter <=i_inter; -- <ASYNC>
|
||||
o_iendframe0<=i_endframe0; -- <ASYNC>
|
||||
o_iendframe02<=o_iendframe0;
|
||||
IF o_iendframe0='1' AND o_iendframe02='0' THEN
|
||||
o_ibuf0<=buf_next(o_ibuf0,o_obuf0);
|
||||
o_ibuf0<=buf_next(o_ibuf0,o_obuf0,o_freeze);
|
||||
o_bufup0<='1';
|
||||
END IF;
|
||||
o_iendframe1<=i_endframe1; -- <ASYNC>
|
||||
o_iendframe12<=o_iendframe1;
|
||||
IF o_iendframe1='1' AND o_iendframe12='0' THEN
|
||||
o_ibuf1<=buf_next(o_ibuf1,o_obuf1);
|
||||
o_ibuf1<=buf_next(o_ibuf1,o_obuf1,o_freeze);
|
||||
o_bufup1<='1';
|
||||
END IF;
|
||||
|
||||
-- Output : Change framebuffer, and image properties, at VS falling edge
|
||||
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
|
||||
o_obuf0<=buf_next(o_obuf0,o_ibuf0,o_freeze);
|
||||
o_bufup0<='0';
|
||||
END IF;
|
||||
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN
|
||||
o_obuf1<=buf_next(o_obuf1,o_ibuf1);
|
||||
o_obuf1<=buf_next(o_obuf1,o_ibuf1,o_freeze);
|
||||
o_bufup1<='0';
|
||||
o_ihsize<=i_hrsize; -- <ASYNC>
|
||||
o_ivsize<=i_vrsize; -- <ASYNC>
|
||||
o_hdown<=i_hdown; -- <ASYNC>
|
||||
o_vdown<=i_vdown; -- <ASYNC>
|
||||
END IF;
|
||||
|
||||
-- Simultaneous change of input and output framebuffers
|
||||
IF o_vsv(1)='1' AND o_vsv(0)='0' AND
|
||||
o_iendframe0='1' AND o_iendframe02='0' THEN
|
||||
o_bufup0<='0';
|
||||
o_obuf0<=o_ibuf0;
|
||||
END IF;
|
||||
IF o_vsv(1)='1' AND o_vsv(0)='0' AND
|
||||
o_iendframe1='1' AND o_iendframe12='0' THEN
|
||||
o_bufup1<='0';
|
||||
o_obuf1<=o_ibuf1;
|
||||
END IF;
|
||||
|
||||
-- Non-interlaced, use same buffer for even and odd lines
|
||||
IF o_inter='0' THEN
|
||||
o_ibuf1<=o_ibuf0;
|
||||
o_obuf1<=o_obuf0;
|
||||
END IF;
|
||||
|
||||
-- Triple buffer disabled
|
||||
IF o_mode(3)='0' THEN
|
||||
o_obuf0<=0;
|
||||
o_obuf1<=0;
|
||||
o_ibuf0<=0;
|
||||
o_ibuf1<=0;
|
||||
END IF;
|
||||
|
||||
-- Framebuffer mode.
|
||||
IF o_fb_ena='1' THEN
|
||||
o_ihsize<=o_fb_hsize;
|
||||
@@ -1771,25 +1832,6 @@ BEGIN
|
||||
o_stride<=to_unsigned(o_ihsize_temp2,14);
|
||||
o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0');
|
||||
END IF;
|
||||
|
||||
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
|
||||
o_obuf0<=buf_next(o_obuf0,o_ibuf0);
|
||||
o_bufup0<='0';
|
||||
END IF;
|
||||
|
||||
IF o_inter='0' THEN
|
||||
o_ibuf1<=o_ibuf0;
|
||||
o_obuf1<=o_obuf0;
|
||||
END IF;
|
||||
|
||||
-- Triple buffer disabled
|
||||
IF o_mode(3)='0' THEN
|
||||
o_obuf0<=0;
|
||||
o_obuf1<=0;
|
||||
o_ibuf0<=0;
|
||||
o_ibuf1<=0;
|
||||
END IF;
|
||||
|
||||
------------------------------------------------------
|
||||
o_hmode<=o_mode;
|
||||
IF o_hdown='1' AND DOWNSCALE THEN
|
||||
@@ -1848,35 +1890,51 @@ BEGIN
|
||||
o_state<=sHSYNC;
|
||||
o_hsp<='0';
|
||||
END IF;
|
||||
o_prim<=true;
|
||||
o_vcarrym<=false;
|
||||
|
||||
--------------------------------------------------
|
||||
WHEN sHSYNC =>
|
||||
dif_v:=(o_vacc_next - 2*o_vsize + 16384) MOD 16384;
|
||||
dif_v :=(o_vacc_next - 2*o_vsize + 16384) MOD 16384;
|
||||
IF o_prim THEN
|
||||
IF dif_v>=8192 THEN
|
||||
o_vacc <=o_vacc_next;
|
||||
ELSE
|
||||
o_vacc <=dif_v;
|
||||
END IF;
|
||||
END IF;
|
||||
IF dif_v>=8192 THEN
|
||||
o_vacc <=o_vacc_next;
|
||||
o_vacc_next<=(o_vacc_next + 2*o_ivsize) MOD 8192;
|
||||
vcarry_v:=false;
|
||||
ELSE
|
||||
o_vacc <=dif_v;
|
||||
o_vacc_next<=(dif_v + 2*o_ivsize + 8192) MOD 8192;
|
||||
o_vacc_next<=dif_v;
|
||||
vcarry_v:=true;
|
||||
END IF;
|
||||
o_divstart<='1';
|
||||
|
||||
IF o_vcpt_pre2=o_vmin THEN
|
||||
o_vacc <=o_vacc_ini;
|
||||
o_vacc_next<=o_vacc_ini + 2*o_ivsize;
|
||||
o_vacpt<=x"001";
|
||||
o_vacpt <=x"001";
|
||||
o_vacptl<="01";
|
||||
vcarry_v:=false;
|
||||
END IF;
|
||||
|
||||
IF vcarry_v THEN
|
||||
o_vacpt<=o_vacpt+1;
|
||||
END IF;
|
||||
IF vcarry_v AND o_prim THEN
|
||||
o_vacptl<=o_vacptl+1;
|
||||
END IF;
|
||||
o_vcarrym <= o_vcarrym OR vcarry_v;
|
||||
o_prim <= false;
|
||||
o_hbcpt<=0; -- Clear burst counter on line
|
||||
IF (o_vpe='1' AND vcarry_v) OR o_fload>0 THEN
|
||||
o_state<=sREAD;
|
||||
ELSE
|
||||
o_state<=sDISP;
|
||||
o_divstart<=to_std_logic(NOT vcarry_v);
|
||||
IF NOT vcarry_v OR o_fload>0 THEN
|
||||
IF (o_vpe='1' AND o_vcarrym) OR o_fload>0 THEN
|
||||
o_state<=sREAD;
|
||||
ELSE
|
||||
o_state<=sDISP;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
WHEN sREAD =>
|
||||
@@ -1926,7 +1984,7 @@ BEGIN
|
||||
o_alt<="0100";
|
||||
ELSE
|
||||
o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32);
|
||||
o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1);
|
||||
o_alt<=altx(o_vacptl + 1);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
@@ -2029,7 +2087,8 @@ BEGIN
|
||||
o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3;
|
||||
o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2;
|
||||
o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3;
|
||||
o_lastt1<=o_last; o_lastt2<=o_lastt1; o_lastt3<=o_lastt2;
|
||||
o_lastt1<=o_last; o_lastt2<=o_lastt1;
|
||||
o_lastt3<=o_lastt2; o_lastt4<=o_lastt3;
|
||||
|
||||
------------------------------------------------------
|
||||
IF o_sh3='1' THEN
|
||||
@@ -2059,7 +2118,7 @@ BEGIN
|
||||
o_hpix2<=hpix_v;
|
||||
o_first<='0';
|
||||
END IF;
|
||||
IF o_lastt3='1' THEN
|
||||
IF o_lastt4='1' THEN
|
||||
-- Right edge. Keep last pixel.
|
||||
o_hpix0<=o_hpix0;
|
||||
END IF;
|
||||
@@ -2259,33 +2318,38 @@ BEGIN
|
||||
|
||||
o_hpixq<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0);
|
||||
|
||||
-- NEAREST / BILINEAR / SHARP BILINEAR ---------------
|
||||
-- NEAREST -------------------------------------------
|
||||
-- C2
|
||||
o_h_near_frac<=near_frac(o_hfrac2);
|
||||
|
||||
-- C3
|
||||
o_h_near_t<=near_calc(o_h_near_frac,o_hpixq);
|
||||
|
||||
-- C4 : Nearest
|
||||
o_h_near_pix.r<=o_h_near_t.r(7+FRAC DOWNTO FRAC);
|
||||
o_h_near_pix.g<=o_h_near_t.g(7+FRAC DOWNTO FRAC);
|
||||
o_h_near_pix.b<=o_h_near_t.b(7+FRAC DOWNTO FRAC);
|
||||
|
||||
-- BILINEAR / SHARP BILINEAR ---------------
|
||||
-- C1 : Pre-calc Sharp Bilinear
|
||||
o_h_sbil_t<=sbil_frac1(o_hfrac1);
|
||||
|
||||
-- C2 : Select
|
||||
o_h_frac2<=(OTHERS =>'0');
|
||||
CASE o_hmode(1 DOWNTO 0) IS
|
||||
WHEN "00" => -- Nearest
|
||||
IF MASK(MASK_NEAREST)='1' THEN
|
||||
o_h_frac2<=near_frac(o_hfrac2);
|
||||
END IF;
|
||||
WHEN "01" => -- Bilinear
|
||||
IF MASK(MASK_BILINEAR)='1' THEN
|
||||
o_h_frac2<=bil_frac(o_hfrac2);
|
||||
END IF;
|
||||
WHEN "10" => -- Sharp Bilinear
|
||||
IF MASK(MASK_SHARP_BILINEAR)='1' THEN
|
||||
o_h_frac2<=sbil_frac2(o_hfrac2,o_h_sbil_t);
|
||||
END IF;
|
||||
WHEN OTHERS =>
|
||||
NULL;
|
||||
END CASE;
|
||||
|
||||
o_h_bil_frac<=(OTHERS =>'0');
|
||||
IF o_hmode(0)='1' THEN -- Bilinear
|
||||
IF MASK(MASK_BILINEAR)='1' THEN
|
||||
o_h_bil_frac<=bil_frac(o_hfrac2);
|
||||
END IF;
|
||||
ELSE -- Sharp Bilinear
|
||||
IF MASK(MASK_SHARP_BILINEAR)='1' THEN
|
||||
o_h_bil_frac<=sbil_frac2(o_hfrac2,o_h_sbil_t);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
-- C3 : Opposite frac
|
||||
o_h_bil_t<=bil_calc(o_h_frac2,o_hpixq);
|
||||
o_h_bil_t<=bil_calc(o_h_bil_frac,o_hpixq);
|
||||
|
||||
-- C4 : Nearest / Bilinear / Sharp Bilinear
|
||||
-- C4 : Bilinear / Sharp Bilinear
|
||||
o_h_bil_pix.r<=bound(o_h_bil_t.r,8+FRAC);
|
||||
o_h_bil_pix.g<=bound(o_h_bil_t.g,8+FRAC);
|
||||
o_h_bil_pix.b<=bound(o_h_bil_t.b,8+FRAC);
|
||||
@@ -2323,9 +2387,12 @@ BEGIN
|
||||
o_ldw<=(x"00",x"00",x"00");
|
||||
|
||||
CASE o_hmode(2 DOWNTO 0) IS
|
||||
WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear
|
||||
IF MASK(MASK_NEAREST)='1' OR
|
||||
MASK(MASK_BILINEAR)='1' OR
|
||||
WHEN "000" => -- Nearest
|
||||
IF MASK(MASK_NEAREST)='1' THEN
|
||||
o_ldw<=o_h_near_pix;
|
||||
END IF;
|
||||
WHEN "001" | "010" => -- Bilinear | Sharp Bilinear
|
||||
IF MASK(MASK_BILINEAR)='1' OR
|
||||
MASK(MASK_SHARP_BILINEAR)='1' THEN
|
||||
o_ldw<=o_h_bil_pix;
|
||||
END IF;
|
||||
@@ -2424,7 +2491,7 @@ BEGIN
|
||||
|
||||
-- CYCLE 2 -----------------------------------------
|
||||
-- Lines reordering
|
||||
CASE o_vacpt(1 DOWNTO 0) IS
|
||||
CASE o_vacptl IS
|
||||
WHEN "10" => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3);
|
||||
WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0);
|
||||
WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1);
|
||||
@@ -2444,31 +2511,37 @@ BEGIN
|
||||
|
||||
o_vpixq1<=o_vpixq;
|
||||
|
||||
-- NEAREST / BILINEAR / SHARP BILINEAR -------------
|
||||
-- NEAREST -----------------------------------------
|
||||
-- C4
|
||||
o_v_near_frac<=near_frac(o_vfrac);
|
||||
|
||||
-- C5
|
||||
o_v_near_t<=near_calc(o_v_near_frac,o_vpixq1);
|
||||
|
||||
-- C6 : Nearest
|
||||
o_v_near_pix.r<=o_v_near_t.r(7+FRAC DOWNTO FRAC);
|
||||
o_v_near_pix.g<=o_v_near_t.g(7+FRAC DOWNTO FRAC);
|
||||
o_v_near_pix.b<=o_v_near_t.b(7+FRAC DOWNTO FRAC);
|
||||
|
||||
-- BILINEAR / SHARP BILINEAR -----------------------
|
||||
-- C3 : Pre-calc Sharp Bilinear
|
||||
o_v_sbil_t<=sbil_frac1(o_vfrac);
|
||||
|
||||
-- C4 : Select
|
||||
o_v_frac<=(OTHERS =>'0');
|
||||
CASE o_vmode(1 DOWNTO 0) IS
|
||||
WHEN "00" => -- Nearest
|
||||
IF MASK(MASK_NEAREST)='1' THEN
|
||||
o_v_frac<=near_frac(o_vfrac);
|
||||
END IF;
|
||||
WHEN "01" => -- Bilinear
|
||||
IF MASK(MASK_BILINEAR)='1' THEN
|
||||
o_v_frac<=bil_frac(o_vfrac);
|
||||
END IF;
|
||||
WHEN "10" => -- Sharp Bilinear
|
||||
IF MASK(MASK_SHARP_BILINEAR)='1' THEN
|
||||
o_v_frac<=sbil_frac2(o_vfrac,o_v_sbil_t);
|
||||
END IF;
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
o_v_bil_frac<=(OTHERS =>'0');
|
||||
IF o_vmode(0)='1' THEN -- Bilinear
|
||||
IF MASK(MASK_BILINEAR)='1' THEN
|
||||
o_v_bil_frac<=bil_frac(o_vfrac);
|
||||
END IF;
|
||||
ELSE -- Sharp Bilinear
|
||||
IF MASK(MASK_SHARP_BILINEAR)='1' THEN
|
||||
o_v_bil_frac<=sbil_frac2(o_vfrac,o_v_sbil_t);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
o_v_bil_t<=bil_calc(o_v_frac,o_vpixq1);
|
||||
o_v_bil_t<=bil_calc(o_v_bil_frac,o_vpixq1);
|
||||
|
||||
-- C6 : Nearest / Bilinear / Sharp Bilinear
|
||||
-- C6 : Bilinear / Sharp Bilinear
|
||||
o_v_bil_pix.r<=bound(o_v_bil_t.r,8+FRAC);
|
||||
o_v_bil_pix.g<=bound(o_v_bil_t.g,8+FRAC);
|
||||
o_v_bil_pix.b<=bound(o_v_bil_t.b,8+FRAC);
|
||||
@@ -2507,11 +2580,17 @@ BEGIN
|
||||
o_r<=x"00";
|
||||
o_g<=x"00";
|
||||
o_b<=x"00";
|
||||
o_brd<= not o_pev(5);
|
||||
|
||||
CASE o_vmode(2 DOWNTO 0) IS
|
||||
WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear
|
||||
IF MASK(MASK_NEAREST)='1' OR
|
||||
MASK(MASK_BILINEAR)='1' OR
|
||||
WHEN "000" => -- Nearest
|
||||
IF MASK(MASK_NEAREST)='1' THEN
|
||||
o_r<=o_v_near_pix.r;
|
||||
o_g<=o_v_near_pix.g;
|
||||
o_b<=o_v_near_pix.b;
|
||||
END IF;
|
||||
WHEN "001" | "010" => -- Bilinear | Sharp Bilinear
|
||||
IF MASK(MASK_BILINEAR)='1' OR
|
||||
MASK(MASK_SHARP_BILINEAR)='1' THEN
|
||||
o_r<=o_v_bil_pix.r;
|
||||
o_g<=o_v_bil_pix.g;
|
||||
|
||||
250
sys/f2sdram_safe_terminator.sv
Normal file
250
sys/f2sdram_safe_terminator.sv
Normal file
@@ -0,0 +1,250 @@
|
||||
// ============================================================================
|
||||
//
|
||||
// f2sdram_safe_terminator for MiSTer platform
|
||||
//
|
||||
// ============================================================================
|
||||
// Copyright (c) 2021 bellwood420
|
||||
//
|
||||
// Background:
|
||||
//
|
||||
// Terminating a transaction of burst writing(/reading) in its midstream
|
||||
// seems to cause an illegal state to f2sdram interface.
|
||||
//
|
||||
// Forced reset request that occurs when loading other core is inevitable.
|
||||
//
|
||||
// So if it happens exactly within the transaction period,
|
||||
// unexpected issues with accessing to f2sdram interface will be caused
|
||||
// in next loaded core.
|
||||
//
|
||||
// It seems that only way to reset broken f2sdram interface is to reset
|
||||
// whole SDRAM Controller Subsystem from HPS via permodrst register
|
||||
// in Reset Manager.
|
||||
// But it cannot be done safely while Linux is running.
|
||||
// It is usually done when cold or warm reset is issued in HPS.
|
||||
//
|
||||
// Main_MiSTer is issuing reset for FPGA <> HPS bridges
|
||||
// via brgmodrst register in Reset Manager when loading rbf.
|
||||
// But it has no effect on f2sdram interface.
|
||||
// f2sdram interface seems to belong to SDRAM Controller Subsystem
|
||||
// rather than FPGA-to-HPS bridge.
|
||||
//
|
||||
// Main_MiSTer is also trying to issuing reset for f2sdram ports
|
||||
// via fpgaportrst register in SDRAM Controller Subsystem when loading rbf.
|
||||
// But according to the Intel's document, fpgaportrst register can be
|
||||
// used to stretch the port reset.
|
||||
// It seems that it cannot be used to assert the port reset.
|
||||
//
|
||||
// According to the Intel's document, there seems to be a reset port on
|
||||
// Avalon-MM slave interface, but it cannot be found in Qsys generated HDL.
|
||||
//
|
||||
// To conclude, the only thing FPGA can do is not to break the transaction.
|
||||
// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
//
|
||||
// Purpose:
|
||||
// To prevent the issue, this module completes ongoing transaction
|
||||
// on behalf of user logic, when reset is asserted.
|
||||
//
|
||||
// Usage:
|
||||
// Insert this module into the bus line between
|
||||
// f2sdram (Avalon-MM slave) and user logic (Avalon-MM master).
|
||||
//
|
||||
// Notice:
|
||||
// Asynchronous reset request is not supported.
|
||||
// Please feed reset request synchronized to clock.
|
||||
//
|
||||
module f2sdram_safe_terminator #(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter BURSTCOUNT_WIDTH = 8
|
||||
) (
|
||||
// clk should be the same as one provided to f2sdram port
|
||||
// clk should not be stop when reset is asserted
|
||||
input clk,
|
||||
// rst_req_sync should be synchronized to clk
|
||||
// Asynchronous reset request is not supported
|
||||
input rst_req_sync,
|
||||
|
||||
// Master port: connecting to Alavon-MM slave(f2sdram)
|
||||
input waitrequest_master,
|
||||
output [BURSTCOUNT_WIDTH-1:0] burstcount_master,
|
||||
output [ADDRESS_WITDH-1:0] address_master,
|
||||
input [DATA_WIDTH-1:0] readdata_master,
|
||||
input readdatavalid_master,
|
||||
output read_master,
|
||||
output [DATA_WIDTH-1:0] writedata_master,
|
||||
output [BYTEENABLE_WIDTH-1:0] byteenable_master,
|
||||
output write_master,
|
||||
|
||||
// Slave port: connecting to Alavon-MM master(user logic)
|
||||
output waitrequest_slave,
|
||||
input [BURSTCOUNT_WIDTH-1:0] burstcount_slave,
|
||||
input [ADDRESS_WITDH-1:0] address_slave,
|
||||
output [DATA_WIDTH-1:0] readdata_slave,
|
||||
output readdatavalid_slave,
|
||||
input read_slave,
|
||||
input [DATA_WIDTH-1:0] writedata_slave,
|
||||
input [BYTEENABLE_WIDTH-1:0] byteenable_slave,
|
||||
input write_slave
|
||||
);
|
||||
|
||||
localparam BYTEENABLE_WIDTH = DATA_WIDTH/8;
|
||||
localparam ADDRESS_WITDH = 32-$clog2(BYTEENABLE_WIDTH);
|
||||
|
||||
/*
|
||||
* Capture init reset deaseert
|
||||
*/
|
||||
reg init_reset_deasserted = 1'b0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_req_sync) begin
|
||||
init_reset_deasserted <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Lock stage
|
||||
*/
|
||||
reg lock_stage = 1'b0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst_req_sync) begin
|
||||
// Reset assert
|
||||
if (init_reset_deasserted) begin
|
||||
lock_stage <= 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
// Reset deassert
|
||||
lock_stage <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Write burst transaction observer
|
||||
*/
|
||||
reg state_write = 1'b0;
|
||||
wire next_state_write;
|
||||
|
||||
wire burst_write_start = !state_write && next_state_write;
|
||||
wire valid_write_data = state_write && !waitrequest_master;
|
||||
wire burst_write_end = state_write && (write_burstcounter == write_burstcount_latch - 1'd1);
|
||||
wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master;
|
||||
|
||||
reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter = 0;
|
||||
reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0;
|
||||
reg [ADDRESS_WITDH-1:0] write_address_latch = 0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_write <= next_state_write;
|
||||
|
||||
if (burst_write_start) begin
|
||||
write_burstcounter <= waitrequest_master ? 1'd0 : 1'd1;
|
||||
write_burstcount_latch <= burstcount_slave;
|
||||
write_address_latch <= address_slave;
|
||||
end
|
||||
else if (valid_write_data) begin
|
||||
write_burstcounter <= write_burstcounter + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
if (!state_write) begin
|
||||
if (valid_non_burst_write)
|
||||
next_state_write = 1'b0;
|
||||
else if (write_slave)
|
||||
next_state_write = 1'b1;
|
||||
else
|
||||
next_state_write = 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (burst_write_end)
|
||||
next_state_write = 1'b0;
|
||||
else
|
||||
next_state_write = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0;
|
||||
reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch = 0;
|
||||
reg [ADDRESS_WITDH-1:0] address_latch = 0;
|
||||
|
||||
reg terminating = 0;
|
||||
reg read_terminating = 0;
|
||||
reg write_terminating = 0;
|
||||
|
||||
wire on_write_transaction = state_write && next_state_write;
|
||||
wire on_start_write_transaction = !state_write && next_state_write;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst_req_sync) begin
|
||||
// Reset assert
|
||||
if (init_reset_deasserted) begin
|
||||
if (!lock_stage) begin
|
||||
// Even not knowing reading is in progress or not,
|
||||
// if it is in progress, it will finish at some point, and no need to do anything.
|
||||
// Assume that reading is in progress when we are not on write transaction.
|
||||
burstcount_latch <= burstcount_slave;
|
||||
address_latch <= address_slave;
|
||||
terminating <= 1;
|
||||
|
||||
if (on_write_transaction) begin
|
||||
write_terminating <= 1;
|
||||
burstcount_latch <= write_burstcount_latch;
|
||||
address_latch <= write_address_latch;
|
||||
write_terminate_counter <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1;
|
||||
end
|
||||
else if (on_start_write_transaction) begin
|
||||
if (!valid_non_burst_write) begin
|
||||
write_terminating <= 1;
|
||||
write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1;
|
||||
end
|
||||
end
|
||||
else if (read_slave && waitrequest_master) begin
|
||||
// Need to keep read signal, burstcount and address until waitrequest_master deasserted
|
||||
read_terminating <= 1;
|
||||
end
|
||||
end
|
||||
else if (!waitrequest_master) begin
|
||||
read_terminating <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
// Reset deassert
|
||||
if (!write_terminating) terminating <= 0;
|
||||
read_terminating <= 0;
|
||||
end
|
||||
|
||||
if (write_terminating) begin
|
||||
// Continue write transaction until the end
|
||||
if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1;
|
||||
if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Bus mux depending on the stage.
|
||||
*/
|
||||
always_comb begin
|
||||
if (terminating) begin
|
||||
burstcount_master = burstcount_latch;
|
||||
address_master = address_latch;
|
||||
read_master = read_terminating;
|
||||
write_master = write_terminating;
|
||||
byteenable_master = 0;
|
||||
end
|
||||
else begin
|
||||
burstcount_master = burstcount_slave;
|
||||
address_master = address_slave;
|
||||
read_master = read_slave;
|
||||
byteenable_master = byteenable_slave;
|
||||
write_master = write_slave;
|
||||
end
|
||||
end
|
||||
|
||||
// Just passing master <-> slave
|
||||
assign writedata_master = writedata_slave;
|
||||
assign readdata_slave = readdata_master;
|
||||
assign readdatavalid_slave = readdatavalid_master;
|
||||
assign waitrequest_slave = waitrequest_master;
|
||||
|
||||
endmodule
|
||||
@@ -32,8 +32,10 @@ always @(posedge clk_vid) begin
|
||||
reg [7:0] R_gamma, G_gamma;
|
||||
reg hs,vs,hb,vb;
|
||||
reg [1:0] ctr = 0;
|
||||
reg old_ce;
|
||||
|
||||
if(ce_pix) begin
|
||||
old_ce <= ce_pix;
|
||||
if(~old_ce & ce_pix) begin
|
||||
{R_in,G_in,B_in} <= RGB_in;
|
||||
hs <= HSync; vs <= VSync;
|
||||
hb <= HBlank; vb <= VBlank;
|
||||
|
||||
@@ -111,32 +111,32 @@ wire [15:0] init_data[82] =
|
||||
|
||||
{8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
|
||||
|
||||
{8'h18, ypbpr ? 8'h88 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited.
|
||||
{8'h19, ypbpr ? 8'h2E : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide.
|
||||
{8'h1A, ypbpr ? 8'h18 : 8'h00}, // CSC Channel A.
|
||||
{8'h1B, ypbpr ? 8'h93 : 8'h00},
|
||||
{8'h1C, ypbpr ? 8'h1F : 8'h00},
|
||||
{8'h1D, ypbpr ? 8'h3F : 8'h00},
|
||||
{8'h1E, ypbpr ? 8'h08 : 8'h01},
|
||||
{8'h1F, 8'h00},
|
||||
{8'h18, ypbpr ? 8'h86 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited.
|
||||
{8'h19, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide.
|
||||
{8'h1A, ypbpr ? 8'h1A : 8'h00}, // CSC Channel A.
|
||||
{8'h1B, ypbpr ? 8'h3F : 8'h00},
|
||||
{8'h1C, ypbpr ? 8'h1E : 8'h00},
|
||||
{8'h1D, ypbpr ? 8'hE2 : 8'h00},
|
||||
{8'h1E, ypbpr ? 8'h07 : 8'h01},
|
||||
{8'h1F, ypbpr ? 8'hE7 : 8'h00},
|
||||
|
||||
{8'h20, ypbpr ? 8'h03 : 8'h00}, // CSC Channel B.
|
||||
{8'h21, ypbpr ? 8'h67 : 8'h00},
|
||||
{8'h22, ypbpr ? 8'h0B : limited[0] ? 8'h0D : 8'h0E},
|
||||
{8'h23, ypbpr ? 8'h71 : limited[0] ? 8'hBC : 8'hFE},
|
||||
{8'h20, ypbpr ? 8'h04 : 8'h00}, // CSC Channel B.
|
||||
{8'h21, ypbpr ? 8'h1C : 8'h00},
|
||||
{8'h22, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
|
||||
{8'h23, ypbpr ? 8'h11 : limited[0] ? 8'hBC : 8'hFE},
|
||||
{8'h24, ypbpr ? 8'h01 : 8'h00},
|
||||
{8'h25, ypbpr ? 8'h28 : 8'h00},
|
||||
{8'h26, ypbpr ? 8'h00 : 8'h01},
|
||||
{8'h25, ypbpr ? 8'h91 : 8'h00},
|
||||
{8'h26, ypbpr ? 8'h01 : 8'h01},
|
||||
{8'h27, 8'h00},
|
||||
|
||||
{8'h28, ypbpr ? 8'h1E : 8'h00}, // CSC Channel C.
|
||||
{8'h29, ypbpr ? 8'h21 : 8'h00},
|
||||
{8'h2A, ypbpr ? 8'h19 : 8'h00},
|
||||
{8'h2B, ypbpr ? 8'hB2 : 8'h00},
|
||||
{8'h2C, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
|
||||
{8'h2D, ypbpr ? 8'h2D : limited[0] ? 8'hBC : 8'hFE},
|
||||
{8'h2E, ypbpr ? 8'h08 : 8'h01},
|
||||
{8'h2F, 8'h00},
|
||||
{8'h28, ypbpr ? 8'h1D : 8'h00}, // CSC Channel C.
|
||||
{8'h29, ypbpr ? 8'hAE : 8'h00},
|
||||
{8'h2A, ypbpr ? 8'h1B : 8'h00},
|
||||
{8'h2B, ypbpr ? 8'h73 : 8'h00},
|
||||
{8'h2C, ypbpr ? 8'h06 : limited[0] ? 8'h0D : 8'h0E},
|
||||
{8'h2D, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE},
|
||||
{8'h2E, ypbpr ? 8'h07 : 8'h01},
|
||||
{8'h2F, ypbpr ? 8'hE7 : 8'h00},
|
||||
|
||||
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
|
||||
|
||||
|
||||
978
sys/hps_io.sv
Normal file
978
sys/hps_io.sv
Normal file
@@ -0,0 +1,978 @@
|
||||
//
|
||||
// hps_io.v
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017-2020 Alexey Melnikov
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// altera message_off 10665
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
//
|
||||
// WIDE=1 for 16 bit file I/O
|
||||
// VDNUM 1..10
|
||||
// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
|
||||
//
|
||||
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
|
||||
(
|
||||
input clk_sys,
|
||||
inout [47:0] HPS_BUS,
|
||||
|
||||
// buttons up to 32
|
||||
output reg [31:0] joystick_0,
|
||||
output reg [31:0] joystick_1,
|
||||
output reg [31:0] joystick_2,
|
||||
output reg [31:0] joystick_3,
|
||||
output reg [31:0] joystick_4,
|
||||
output reg [31:0] joystick_5,
|
||||
|
||||
// analog -127..+127, Y: [15:8], X: [7:0]
|
||||
output reg [15:0] joystick_l_analog_0,
|
||||
output reg [15:0] joystick_l_analog_1,
|
||||
output reg [15:0] joystick_l_analog_2,
|
||||
output reg [15:0] joystick_l_analog_3,
|
||||
output reg [15:0] joystick_l_analog_4,
|
||||
output reg [15:0] joystick_l_analog_5,
|
||||
|
||||
output reg [15:0] joystick_r_analog_0,
|
||||
output reg [15:0] joystick_r_analog_1,
|
||||
output reg [15:0] joystick_r_analog_2,
|
||||
output reg [15:0] joystick_r_analog_3,
|
||||
output reg [15:0] joystick_r_analog_4,
|
||||
output reg [15:0] joystick_r_analog_5,
|
||||
|
||||
// paddle 0..255
|
||||
output reg [7:0] paddle_0,
|
||||
output reg [7:0] paddle_1,
|
||||
output reg [7:0] paddle_2,
|
||||
output reg [7:0] paddle_3,
|
||||
output reg [7:0] paddle_4,
|
||||
output reg [7:0] paddle_5,
|
||||
|
||||
// spinner [7:0] -128..+127, [8] - toggle with every update
|
||||
output reg [8:0] spinner_0,
|
||||
output reg [8:0] spinner_1,
|
||||
output reg [8:0] spinner_2,
|
||||
output reg [8:0] spinner_3,
|
||||
output reg [8:0] spinner_4,
|
||||
output reg [8:0] spinner_5,
|
||||
|
||||
output [1:0] buttons,
|
||||
output forced_scandoubler,
|
||||
output direct_video,
|
||||
|
||||
output reg [63:0] status,
|
||||
input [63:0] status_in,
|
||||
input status_set,
|
||||
input [15:0] status_menumask,
|
||||
|
||||
input info_req,
|
||||
input [7:0] info,
|
||||
|
||||
//toggle to force notify of video mode change
|
||||
input new_vmode,
|
||||
|
||||
// SD config
|
||||
output reg [VD:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted
|
||||
output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba[VDNUM],
|
||||
input [5:0] sd_blk_cnt[VDNUM], // number of blocks-1, total size ((sd_blk_cnt+1)*(1<<(BLKSZ+7))) must be <= 16384!
|
||||
input [VD:0] sd_rd,
|
||||
input [VD:0] sd_wr,
|
||||
output reg [VD:0] sd_ack,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [AW:0] sd_buff_addr,
|
||||
output reg [DW:0] sd_buff_dout,
|
||||
input [DW:0] sd_buff_din[VDNUM],
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ARM -> FPGA download
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [15:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr,
|
||||
output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2
|
||||
output reg [DW:0] ioctl_dout,
|
||||
output reg ioctl_upload = 0, // signal indicating an active upload
|
||||
input ioctl_upload_req,
|
||||
input [DW:0] ioctl_din,
|
||||
output reg ioctl_rd,
|
||||
output reg [31:0] ioctl_file_ext,
|
||||
input ioctl_wait,
|
||||
|
||||
// [15]: 0 - unset, 1 - set. [1:0]: 0 - none, 1 - 32MB, 2 - 64MB, 3 - 128MB
|
||||
// [14]: debug mode: [8]: 1 - phase up, 0 - phase down. [7:0]: amount of shift.
|
||||
output reg [15:0] sdram_sz,
|
||||
|
||||
// RTC MSM6242B layout
|
||||
output reg [64:0] RTC,
|
||||
|
||||
// Seconds since 1970-01-01 00:00:00
|
||||
output reg [32:0] TIMESTAMP,
|
||||
|
||||
// UART flags
|
||||
output reg [7:0] uart_mode,
|
||||
output reg [31:0] uart_speed,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk_out,
|
||||
output ps2_kbd_data_out,
|
||||
input ps2_kbd_clk_in,
|
||||
input ps2_kbd_data_in,
|
||||
|
||||
input [2:0] ps2_kbd_led_status,
|
||||
input [2:0] ps2_kbd_led_use,
|
||||
|
||||
output ps2_mouse_clk_out,
|
||||
output ps2_mouse_data_out,
|
||||
input ps2_mouse_clk_in,
|
||||
input ps2_mouse_data_in,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
|
||||
|
||||
inout [21:0] gamma_bus,
|
||||
|
||||
// for core-specific extensions
|
||||
inout [35:0] EXT_BUS
|
||||
);
|
||||
|
||||
assign EXT_BUS[31:16] = HPS_BUS[31:16];
|
||||
assign EXT_BUS[35:33] = HPS_BUS[35:33];
|
||||
|
||||
localparam DW = (WIDE) ? 15 : 7;
|
||||
localparam AW = (WIDE) ? 12 : 13;
|
||||
localparam VD = VDNUM-1;
|
||||
|
||||
wire io_strobe= HPS_BUS[33];
|
||||
wire io_enable= HPS_BUS[34];
|
||||
wire fp_enable= HPS_BUS[35];
|
||||
wire io_wide = (WIDE) ? 1'b1 : 1'b0;
|
||||
wire [15:0] io_din = HPS_BUS[31:16];
|
||||
reg [15:0] io_dout;
|
||||
|
||||
assign HPS_BUS[37] = ioctl_wait;
|
||||
assign HPS_BUS[36] = clk_sys;
|
||||
assign HPS_BUS[32] = io_wide;
|
||||
assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : fp_enable ? fp_dout : io_dout;
|
||||
|
||||
reg [15:0] cfg;
|
||||
assign buttons = cfg[1:0];
|
||||
//cfg[2] - vga_scaler handled in sys_top
|
||||
//cfg[3] - csync handled in sys_top
|
||||
assign forced_scandoubler = cfg[4];
|
||||
//cfg[5] - ypbpr handled in sys_top
|
||||
assign direct_video = cfg[10];
|
||||
|
||||
reg [3:0] sdn;
|
||||
reg [3:0] sd_rrb = 0;
|
||||
always_comb begin
|
||||
int n, i;
|
||||
|
||||
sdn = 0;
|
||||
for(i = VDNUM - 1; i >= 0; i = i - 1) begin
|
||||
n = i + sd_rrb;
|
||||
if(n >= VDNUM) n = n - VDNUM;
|
||||
if(sd_wr[n] | sd_rd[n]) sdn = n[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
wire [15:0] vc_dout;
|
||||
video_calc video_calc
|
||||
(
|
||||
.clk_100(HPS_BUS[43]),
|
||||
.clk_vid(HPS_BUS[42]),
|
||||
.clk_sys(clk_sys),
|
||||
.ce_pix(HPS_BUS[41]),
|
||||
.de(HPS_BUS[40]),
|
||||
.hs(HPS_BUS[39]),
|
||||
.vs(HPS_BUS[38]),
|
||||
.vs_hdmi(HPS_BUS[44]),
|
||||
.f1(HPS_BUS[45]),
|
||||
.new_vmode(new_vmode),
|
||||
|
||||
.par_num(byte_cnt[3:0]),
|
||||
.dout(vc_dout)
|
||||
);
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
localparam STRLEN = $size(CONF_STR)>>3;
|
||||
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
|
||||
|
||||
wire [7:0] conf_byte;
|
||||
generate
|
||||
if(CONF_STR_BRAM) begin
|
||||
confstr_rom #(CONF_STR, STRLEN) confstr_rom(.*, .conf_addr(byte_cnt - 1'd1));
|
||||
end
|
||||
else begin
|
||||
assign conf_byte = CONF_STR[{(STRLEN - byte_cnt),3'b000} +:8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign gamma_bus[20:0] = {clk_sys, gamma_en, gamma_wr, gamma_wr_addr, gamma_value};
|
||||
reg gamma_en;
|
||||
reg gamma_wr;
|
||||
reg [9:0] gamma_wr_addr;
|
||||
reg [7:0] gamma_value;
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
reg [MAX_W:0] byte_cnt;
|
||||
reg [3:0] sdn_ack;
|
||||
wire [15:0] disk = 16'd1 << io_din[11:8];
|
||||
|
||||
always@(posedge clk_sys) begin : uio_block
|
||||
reg [15:0] cmd;
|
||||
reg [2:0] b_wr;
|
||||
reg [3:0] stick_idx;
|
||||
reg [3:0] pdsp_idx;
|
||||
reg ps2skip = 0;
|
||||
reg [3:0] stflg = 0;
|
||||
reg [63:0] status_req;
|
||||
reg old_status_set = 0;
|
||||
reg old_upload_req = 0;
|
||||
reg upload_req = 0;
|
||||
reg old_info = 0;
|
||||
reg [7:0] info_n = 0;
|
||||
reg [15:0] tmp1;
|
||||
reg [7:0] tmp2;
|
||||
reg [3:0] sdn_r;
|
||||
|
||||
old_status_set <= status_set;
|
||||
if(~old_status_set & status_set) begin
|
||||
stflg <= stflg + 1'd1;
|
||||
status_req <= status_in;
|
||||
end
|
||||
|
||||
old_upload_req <= ioctl_upload_req;
|
||||
if(~old_upload_req & ioctl_upload_req) upload_req <= 1;
|
||||
|
||||
old_info <= info_req;
|
||||
if(~old_info & info_req) info_n <= info;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(PS2DIV) {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
|
||||
|
||||
gamma_wr <= 0;
|
||||
|
||||
if(~io_enable) begin
|
||||
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5 && !ps2skip) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
if(cmd == 'h22) RTC[64] <= ~RTC[64];
|
||||
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
|
||||
cmd <= 0;
|
||||
byte_cnt <= 0;
|
||||
sd_ack <= 0;
|
||||
io_dout <= 0;
|
||||
ps2skip <= 0;
|
||||
img_mounted <= 0;
|
||||
end
|
||||
else if(io_strobe) begin
|
||||
|
||||
io_dout <= 0;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
|
||||
|
||||
if(byte_cnt == 0) begin
|
||||
cmd <= io_din;
|
||||
|
||||
casex(io_din)
|
||||
'h16: begin io_dout <= {1'b1, sd_blk_cnt[sdn], BLKSZ[2:0], sdn, sd_wr[sdn], sd_rd[sdn]}; sdn_r <= sdn; end
|
||||
'h0X17,
|
||||
'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end
|
||||
'h29: io_dout <= {4'hA, stflg};
|
||||
'h2B: io_dout <= {HPS_BUS[47:46],4'b0010};
|
||||
'h2F: io_dout <= 1;
|
||||
'h32: io_dout <= gamma_bus[21];
|
||||
'h36: begin io_dout <= info_n; info_n <= 0; end
|
||||
'h39: io_dout <= 1;
|
||||
'h3C: if(upload_req) begin io_dout <= 1; upload_req <= 0; end
|
||||
'h3E: io_dout <= 1; // shadow mask
|
||||
endcase
|
||||
|
||||
sd_buff_addr <= 0;
|
||||
if(io_din == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
casex(cmd)
|
||||
// buttons and switches
|
||||
'h01: cfg <= io_din;
|
||||
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
|
||||
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
|
||||
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
|
||||
'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
|
||||
'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
|
||||
'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
|
||||
|
||||
// store incoming ps2 mouse bytes
|
||||
'h04: begin
|
||||
if(PS2DIV) begin
|
||||
mouse_data <= io_din[7:0];
|
||||
mouse_we <= 1;
|
||||
end
|
||||
if(&io_din[15:8]) ps2skip <= 1;
|
||||
if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: ps2_mouse[7:0] <= io_din[7:0];
|
||||
2: ps2_mouse[15:8] <= io_din[7:0];
|
||||
3: ps2_mouse[23:16] <= io_din[7:0];
|
||||
endcase
|
||||
case(byte_cnt[1:0])
|
||||
1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
|
||||
2: ps2_mouse_ext[11:8] <= io_din[11:8];
|
||||
3: ps2_mouse_ext[15:12]<= io_din[11:8];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
'h05: begin
|
||||
if(&io_din[15:8]) ps2skip <= 1;
|
||||
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
|
||||
if(PS2DIV) begin
|
||||
kbd_data <= io_din[7:0];
|
||||
kbd_we <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
// reading config string, returning a byte from string
|
||||
'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_byte;
|
||||
|
||||
// reading sd card status
|
||||
'h16: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: sd_rrb <= (sd_rrb == VD) ? 4'd0 : (sd_rrb + 1'd1);
|
||||
2: io_dout <= sd_lba[sdn_r][15:0];
|
||||
3: io_dout <= sd_lba[sdn_r][31:16];
|
||||
endcase
|
||||
end
|
||||
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
'h0X17: begin
|
||||
sd_buff_dout <= io_din[DW:0];
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// reading sd card write data
|
||||
'h0X18: begin
|
||||
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
io_dout <= sd_buff_din[sdn_ack];
|
||||
end
|
||||
|
||||
// joystick left analog
|
||||
'h1a: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
|
||||
2: case(stick_idx)
|
||||
0: joystick_l_analog_0 <= io_din;
|
||||
1: joystick_l_analog_1 <= io_din;
|
||||
2: joystick_l_analog_2 <= io_din;
|
||||
3: joystick_l_analog_3 <= io_din;
|
||||
4: joystick_l_analog_4 <= io_din;
|
||||
5: joystick_l_analog_5 <= io_din;
|
||||
15: case(pdsp_idx)
|
||||
0: paddle_0 <= io_din[7:0];
|
||||
1: paddle_1 <= io_din[7:0];
|
||||
2: paddle_2 <= io_din[7:0];
|
||||
3: paddle_3 <= io_din[7:0];
|
||||
4: paddle_4 <= io_din[7:0];
|
||||
5: paddle_5 <= io_din[7:0];
|
||||
8: spinner_0 <= {~spinner_0[8],io_din[7:0]};
|
||||
9: spinner_1 <= {~spinner_1[8],io_din[7:0]};
|
||||
10: spinner_2 <= {~spinner_2[8],io_din[7:0]};
|
||||
11: spinner_3 <= {~spinner_3[8],io_din[7:0]};
|
||||
12: spinner_4 <= {~spinner_4[8],io_din[7:0]};
|
||||
13: spinner_5 <= {~spinner_5[8],io_din[7:0]};
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
|
||||
// joystick right analog
|
||||
'h3d: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: stick_idx <= io_din[3:0]; // first byte is joystick index
|
||||
2: case(stick_idx)
|
||||
0: joystick_r_analog_0 <= io_din;
|
||||
1: joystick_r_analog_1 <= io_din;
|
||||
2: joystick_r_analog_2 <= io_din;
|
||||
3: joystick_r_analog_3 <= io_din;
|
||||
4: joystick_r_analog_4 <= io_din;
|
||||
5: joystick_r_analog_5 <= io_din;
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
'h1c: begin
|
||||
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
|
||||
img_readonly <= io_din[7];
|
||||
end
|
||||
|
||||
// send image info
|
||||
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
|
||||
|
||||
// status, 64bit version
|
||||
'h1e: if(!byte_cnt[MAX_W:3]) begin
|
||||
case(byte_cnt[2:0])
|
||||
1: status[15:00] <= io_din;
|
||||
2: status[31:16] <= io_din;
|
||||
3: status[47:32] <= io_din;
|
||||
4: status[63:48] <= io_din;
|
||||
endcase
|
||||
end
|
||||
|
||||
// reading keyboard LED status
|
||||
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
|
||||
|
||||
// reading ps2 keyboard/mouse control
|
||||
'h21: if(PS2DIV) begin
|
||||
if(byte_cnt == 1) begin
|
||||
io_dout <= kbd_data_host;
|
||||
kbd_rd <= 1;
|
||||
end
|
||||
else
|
||||
if(byte_cnt == 2) begin
|
||||
io_dout <= mouse_data_host;
|
||||
mouse_rd <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
//RTC
|
||||
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||
|
||||
//Video res.
|
||||
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
|
||||
|
||||
//RTC
|
||||
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||
|
||||
//status set
|
||||
'h29: if(!byte_cnt[MAX_W:3]) begin
|
||||
case(byte_cnt[2:0])
|
||||
1: io_dout <= status_req[15:00];
|
||||
2: io_dout <= status_req[31:16];
|
||||
3: io_dout <= status_req[47:32];
|
||||
4: io_dout <= status_req[63:48];
|
||||
endcase
|
||||
end
|
||||
|
||||
//menu mask
|
||||
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
|
||||
|
||||
//sdram size set
|
||||
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
|
||||
|
||||
// Gamma
|
||||
'h32: gamma_en <= io_din[0];
|
||||
'h33: begin
|
||||
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
|
||||
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
|
||||
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
|
||||
end
|
||||
|
||||
// UART
|
||||
'h3b: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: tmp2 <= io_din[7:0];
|
||||
2: tmp1 <= io_din;
|
||||
3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2};
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
generate
|
||||
if(PS2DIV) begin
|
||||
reg clk_ps2;
|
||||
always @(posedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [7:0] kbd_data;
|
||||
reg kbd_we;
|
||||
wire [8:0] kbd_data_host;
|
||||
reg kbd_rd;
|
||||
|
||||
ps2_device keyboard
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.wdata(kbd_data),
|
||||
.we(kbd_we),
|
||||
|
||||
.ps2_clk(clk_ps2),
|
||||
.ps2_clk_out(ps2_kbd_clk_out),
|
||||
.ps2_dat_out(ps2_kbd_data_out),
|
||||
|
||||
.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
|
||||
.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
|
||||
|
||||
.rdata(kbd_data_host),
|
||||
.rd(kbd_rd)
|
||||
);
|
||||
|
||||
reg [7:0] mouse_data;
|
||||
reg mouse_we;
|
||||
wire [8:0] mouse_data_host;
|
||||
reg mouse_rd;
|
||||
|
||||
ps2_device mouse
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.wdata(mouse_data),
|
||||
.we(mouse_we),
|
||||
|
||||
.ps2_clk(clk_ps2),
|
||||
.ps2_clk_out(ps2_mouse_clk_out),
|
||||
.ps2_dat_out(ps2_mouse_data_out),
|
||||
|
||||
.ps2_clk_in(ps2_mouse_clk_in || !PS2WE),
|
||||
.ps2_dat_in(ps2_mouse_data_in || !PS2WE),
|
||||
|
||||
.rdata(mouse_data_host),
|
||||
.rd(mouse_rd)
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign ps2_kbd_clk_out = 0;
|
||||
assign ps2_kbd_data_out = 0;
|
||||
assign ps2_mouse_clk_out = 0;
|
||||
assign ps2_mouse_data_out = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
localparam FIO_FILE_TX = 8'h53;
|
||||
localparam FIO_FILE_TX_DAT = 8'h54;
|
||||
localparam FIO_FILE_INDEX = 8'h55;
|
||||
localparam FIO_FILE_INFO = 8'h56;
|
||||
|
||||
reg [15:0] fp_dout;
|
||||
always@(posedge clk_sys) begin : fio_block
|
||||
reg [15:0] cmd;
|
||||
reg [2:0] cnt;
|
||||
reg has_cmd;
|
||||
reg [26:0] addr;
|
||||
reg wr;
|
||||
|
||||
ioctl_rd <= 0;
|
||||
ioctl_wr <= wr;
|
||||
wr <= 0;
|
||||
|
||||
if(~fp_enable) has_cmd <= 0;
|
||||
else begin
|
||||
if(io_strobe) begin
|
||||
|
||||
if(!has_cmd) begin
|
||||
cmd <= io_din;
|
||||
has_cmd <= 1;
|
||||
cnt <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
FIO_FILE_INFO:
|
||||
if(~cnt[1]) begin
|
||||
case(cnt)
|
||||
0: ioctl_file_ext[31:16] <= io_din;
|
||||
1: ioctl_file_ext[15:00] <= io_din;
|
||||
endcase
|
||||
cnt <= cnt + 1'd1;
|
||||
end
|
||||
|
||||
FIO_FILE_INDEX:
|
||||
begin
|
||||
ioctl_index <= io_din[15:0];
|
||||
end
|
||||
|
||||
FIO_FILE_TX:
|
||||
begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
0: if(io_din[7:0] == 8'hAA) begin
|
||||
ioctl_addr <= 0;
|
||||
ioctl_upload <= 1;
|
||||
ioctl_rd <= 1;
|
||||
end
|
||||
else if(io_din[7:0]) begin
|
||||
addr <= 0;
|
||||
ioctl_download <= 1;
|
||||
end
|
||||
else begin
|
||||
if(ioctl_download) ioctl_addr <= addr;
|
||||
ioctl_download <= 0;
|
||||
ioctl_upload <= 0;
|
||||
end
|
||||
|
||||
1: begin
|
||||
ioctl_addr[15:0] <= io_din;
|
||||
addr[15:0] <= io_din;
|
||||
end
|
||||
|
||||
2: begin
|
||||
ioctl_addr[26:16] <= io_din[10:0];
|
||||
addr[26:16] <= io_din[10:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
FIO_FILE_TX_DAT:
|
||||
if(ioctl_download) begin
|
||||
ioctl_addr <= addr;
|
||||
ioctl_dout <= io_din[DW:0];
|
||||
wr <= 1;
|
||||
addr <= addr + (WIDE ? 2'd2 : 2'd1);
|
||||
end
|
||||
else begin
|
||||
ioctl_addr <= ioctl_addr + (WIDE ? 2'd2 : 2'd1);
|
||||
fp_dout <= ioctl_din;
|
||||
ioctl_rd <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ps2_device #(parameter PS2_FIFO_BITS=5)
|
||||
(
|
||||
input clk_sys,
|
||||
|
||||
input [7:0] wdata,
|
||||
input we,
|
||||
|
||||
input ps2_clk,
|
||||
output reg ps2_clk_out,
|
||||
output reg ps2_dat_out,
|
||||
output reg tx_empty,
|
||||
|
||||
input ps2_clk_in,
|
||||
input ps2_dat_in,
|
||||
|
||||
output [8:0] rdata,
|
||||
input rd
|
||||
);
|
||||
|
||||
|
||||
(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
|
||||
|
||||
reg [PS2_FIFO_BITS-1:0] wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] rptr;
|
||||
|
||||
reg [2:0] rx_state = 0;
|
||||
reg [3:0] tx_state = 0;
|
||||
|
||||
reg has_data;
|
||||
reg [7:0] data;
|
||||
assign rdata = {has_data, data};
|
||||
|
||||
always@(posedge clk_sys) begin
|
||||
reg [7:0] tx_byte;
|
||||
reg parity;
|
||||
reg r_inc;
|
||||
reg old_clk;
|
||||
reg [1:0] timeout;
|
||||
|
||||
reg [3:0] rx_cnt;
|
||||
|
||||
reg c1,c2,d1;
|
||||
|
||||
tx_empty <= ((wptr == rptr) && (tx_state == 0));
|
||||
|
||||
if(we && !has_data) begin
|
||||
fifo[wptr] <= wdata;
|
||||
wptr <= wptr + 1'd1;
|
||||
end
|
||||
|
||||
if(rd) has_data <= 0;
|
||||
|
||||
c1 <= ps2_clk_in;
|
||||
c2 <= c1;
|
||||
d1 <= ps2_dat_in;
|
||||
if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
|
||||
rx_state <= rx_state + 1'b1;
|
||||
ps2_dat_out <= 1;
|
||||
end
|
||||
|
||||
old_clk <= ps2_clk;
|
||||
if(~old_clk & ps2_clk) begin
|
||||
|
||||
if(rx_state) begin
|
||||
case(rx_state)
|
||||
1: begin
|
||||
rx_state <= rx_state + 1'b1;
|
||||
rx_cnt <= 0;
|
||||
end
|
||||
|
||||
2: begin
|
||||
if(rx_cnt <= 7) data <= {d1, data[7:1]};
|
||||
else rx_state <= rx_state + 1'b1;
|
||||
rx_cnt <= rx_cnt + 1'b1;
|
||||
end
|
||||
|
||||
3: if(d1) begin
|
||||
rx_state <= rx_state + 1'b1;
|
||||
ps2_dat_out <= 0;
|
||||
end
|
||||
|
||||
4: begin
|
||||
ps2_dat_out <= 1;
|
||||
has_data <= 1;
|
||||
rx_state <= 0;
|
||||
rptr <= 0;
|
||||
wptr <= 0;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
|
||||
// transmitter is idle?
|
||||
if(tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(c2 && c1 && d1 && wptr != rptr) begin
|
||||
|
||||
timeout <= timeout - 1'd1;
|
||||
if(!timeout) begin
|
||||
tx_byte <= fifo[rptr];
|
||||
rptr <= rptr + 1'd1;
|
||||
|
||||
// reset parity
|
||||
parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_dat_out <= 0; // start bit is 0
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((tx_state >= 1)&&(tx_state < 9)) begin
|
||||
ps2_dat_out <= tx_byte[0]; // data bits
|
||||
tx_byte[6:0] <= tx_byte[7:1]; // shift down
|
||||
if(tx_byte[0])
|
||||
parity <= !parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(tx_state == 9) ps2_dat_out <= parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(tx_state < 11) tx_state <= tx_state + 1'd1;
|
||||
else tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if(~old_clk & ps2_clk) ps2_clk_out <= 1;
|
||||
if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
///////////////// calc video parameters //////////////////
|
||||
module video_calc
|
||||
(
|
||||
input clk_100,
|
||||
input clk_vid,
|
||||
input clk_sys,
|
||||
|
||||
input ce_pix,
|
||||
input de,
|
||||
input hs,
|
||||
input vs,
|
||||
input vs_hdmi,
|
||||
input f1,
|
||||
input new_vmode,
|
||||
|
||||
input [3:0] par_num,
|
||||
output reg [15:0] dout
|
||||
);
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
case(par_num)
|
||||
1: dout <= {|vid_int, vid_nres};
|
||||
2: dout <= vid_hcnt[15:0];
|
||||
3: dout <= vid_hcnt[31:16];
|
||||
4: dout <= vid_vcnt[15:0];
|
||||
5: dout <= vid_vcnt[31:16];
|
||||
6: dout <= vid_htime[15:0];
|
||||
7: dout <= vid_htime[31:16];
|
||||
8: dout <= vid_vtime[15:0];
|
||||
9: dout <= vid_vtime[31:16];
|
||||
10: dout <= vid_pix[15:0];
|
||||
11: dout <= vid_pix[31:16];
|
||||
12: dout <= vid_vtime_hdmi[15:0];
|
||||
13: dout <= vid_vtime_hdmi[31:16];
|
||||
default dout <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [31:0] vid_hcnt = 0;
|
||||
reg [31:0] vid_vcnt = 0;
|
||||
reg [7:0] vid_nres = 0;
|
||||
reg [1:0] vid_int = 0;
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
integer hcnt;
|
||||
integer vcnt;
|
||||
reg old_vs= 0, old_de = 0, old_vmode = 0;
|
||||
reg [3:0] resto = 0;
|
||||
reg calch = 0;
|
||||
|
||||
if(ce_pix) begin
|
||||
old_vs <= vs;
|
||||
old_de <= de;
|
||||
|
||||
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
|
||||
if(calch & de) hcnt <= hcnt + 1;
|
||||
if(old_de & ~de) calch <= 0;
|
||||
|
||||
if(old_vs & ~vs) begin
|
||||
vid_int <= {vid_int[0],f1};
|
||||
if(~f1) begin
|
||||
if(hcnt && vcnt) begin
|
||||
old_vmode <= new_vmode;
|
||||
|
||||
//report new resolution after timeout
|
||||
if(resto) resto <= resto + 1'd1;
|
||||
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
|
||||
if(&resto) vid_nres <= vid_nres + 1'd1;
|
||||
vid_hcnt <= hcnt;
|
||||
vid_vcnt <= vcnt;
|
||||
end
|
||||
vcnt <= 0;
|
||||
hcnt <= 0;
|
||||
calch <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] vid_htime = 0;
|
||||
reg [31:0] vid_vtime = 0;
|
||||
reg [31:0] vid_pix = 0;
|
||||
|
||||
always @(posedge clk_100) begin
|
||||
integer vtime, htime, hcnt;
|
||||
reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
|
||||
reg calch = 0;
|
||||
|
||||
old_vs <= vs;
|
||||
old_hs <= hs;
|
||||
|
||||
old_vs2 <= old_vs;
|
||||
old_hs2 <= old_hs;
|
||||
|
||||
vtime <= vtime + 1'd1;
|
||||
htime <= htime + 1'd1;
|
||||
|
||||
if(~old_vs2 & old_vs) begin
|
||||
vid_pix <= hcnt;
|
||||
vid_vtime <= vtime;
|
||||
vtime <= 0;
|
||||
hcnt <= 0;
|
||||
end
|
||||
|
||||
if(old_vs2 & ~old_vs) calch <= 1;
|
||||
|
||||
if(~old_hs2 & old_hs) begin
|
||||
vid_htime <= htime;
|
||||
htime <= 0;
|
||||
end
|
||||
|
||||
old_de <= de;
|
||||
old_de2 <= old_de;
|
||||
|
||||
if(calch & old_de) hcnt <= hcnt + 1;
|
||||
if(old_de2 & ~old_de) calch <= 0;
|
||||
end
|
||||
|
||||
reg [31:0] vid_vtime_hdmi;
|
||||
always @(posedge clk_100) begin
|
||||
integer vtime;
|
||||
reg old_vs, old_vs2;
|
||||
|
||||
old_vs <= vs_hdmi;
|
||||
old_vs2 <= old_vs;
|
||||
|
||||
vtime <= vtime + 1'd1;
|
||||
|
||||
if(~old_vs2 & old_vs) begin
|
||||
vid_vtime_hdmi <= vtime;
|
||||
vtime <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module confstr_rom #(parameter CONF_STR, STRLEN)
|
||||
(
|
||||
input clk_sys,
|
||||
input [$clog2(STRLEN+1)-1:0] conf_addr,
|
||||
output reg [7:0] conf_byte
|
||||
);
|
||||
|
||||
wire [7:0] rom[STRLEN];
|
||||
initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
|
||||
always @ (posedge clk_sys) conf_byte <= rom[conf_addr];
|
||||
|
||||
endmodule
|
||||
19
sys/i2c.v
19
sys/i2c.v
@@ -37,13 +37,23 @@ always @(posedge CLK) begin
|
||||
end
|
||||
end
|
||||
|
||||
assign I2C_SCL = SCLK | I2C_CLOCK;
|
||||
assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0;
|
||||
assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
|
||||
|
||||
reg SCLK = 1;
|
||||
reg [3:0] SDO = 4'b1111;
|
||||
reg SCLK;
|
||||
reg [3:0] SDO;
|
||||
reg [0:7] rdata;
|
||||
|
||||
reg [5:0] SD_COUNTER;
|
||||
reg [0:31] SD;
|
||||
|
||||
initial begin
|
||||
SD_COUNTER = 'b111111;
|
||||
SD = 'hFFFF;
|
||||
SCLK = 1;
|
||||
SDO = 4'b1111;
|
||||
end
|
||||
|
||||
assign I2C_RDATA = rdata;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
@@ -51,9 +61,6 @@ always @(posedge CLK) begin
|
||||
reg old_st;
|
||||
reg rd,len;
|
||||
|
||||
reg [5:0] SD_COUNTER = 'b111111;
|
||||
reg [0:31] SD;
|
||||
|
||||
old_clk <= I2C_CLOCK;
|
||||
old_st <= START;
|
||||
|
||||
|
||||
109
sys/math.sv
Normal file
109
sys/math.sv
Normal file
@@ -0,0 +1,109 @@
|
||||
|
||||
// result = num/div
|
||||
module sys_udiv
|
||||
#(
|
||||
parameter NB_NUM,
|
||||
parameter NB_DIV
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input start,
|
||||
output busy,
|
||||
|
||||
input [NB_NUM-1:0] num,
|
||||
input [NB_DIV-1:0] div,
|
||||
output reg [NB_NUM-1:0] result,
|
||||
output reg [NB_DIV-1:0] remainder
|
||||
);
|
||||
|
||||
reg run;
|
||||
assign busy = run;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [5:0] cpt;
|
||||
reg [NB_NUM+NB_DIV+1:0] rem;
|
||||
|
||||
if (start) begin
|
||||
cpt <= 0;
|
||||
run <= 1;
|
||||
rem <= num;
|
||||
end
|
||||
else if (run) begin
|
||||
cpt <= cpt + 1'd1;
|
||||
run <= (cpt != NB_NUM + 1'd1);
|
||||
remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1];
|
||||
if (!rem[NB_DIV + NB_NUM + 1'd1])
|
||||
rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0};
|
||||
else
|
||||
rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0};
|
||||
result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// result = mul1*mul2
|
||||
module sys_umul
|
||||
#(
|
||||
parameter NB_MUL1,
|
||||
parameter NB_MUL2
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input start,
|
||||
output busy,
|
||||
|
||||
input [NB_MUL1-1:0] mul1,
|
||||
input [NB_MUL2-1:0] mul2,
|
||||
output reg [NB_MUL1+NB_MUL2-1:0] result
|
||||
);
|
||||
|
||||
reg run;
|
||||
assign busy = run;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [NB_MUL1+NB_MUL2-1:0] add;
|
||||
reg [NB_MUL2-1:0] map;
|
||||
|
||||
if (start) begin
|
||||
run <= 1;
|
||||
result <= 0;
|
||||
add <= mul1;
|
||||
map <= mul2;
|
||||
end
|
||||
else if (run) begin
|
||||
if(!map) run <= 0;
|
||||
if(map[0]) result <= result + add;
|
||||
add <= add << 1;
|
||||
map <= map >> 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// result = (mul1*mul2)/div
|
||||
module sys_umuldiv
|
||||
#(
|
||||
parameter NB_MUL1,
|
||||
parameter NB_MUL2,
|
||||
parameter NB_DIV
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input start,
|
||||
output busy,
|
||||
|
||||
input [NB_MUL1-1:0] mul1,
|
||||
input [NB_MUL2-1:0] mul2,
|
||||
input [NB_DIV-1:0] div,
|
||||
output [NB_MUL1+NB_MUL2-1:0] result,
|
||||
output [NB_DIV-1:0] remainder
|
||||
);
|
||||
|
||||
wire mul_run;
|
||||
wire [NB_MUL1+NB_MUL2-1:0] mul_res;
|
||||
sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res);
|
||||
|
||||
sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder);
|
||||
|
||||
endmodule
|
||||
283
sys/mt32pi.sv
Normal file
283
sys/mt32pi.sv
Normal file
@@ -0,0 +1,283 @@
|
||||
//
|
||||
// Communication module to MT32-pi (external MIDI emulator on RPi)
|
||||
// (C) 2020 Sorgelig, Kitrinx
|
||||
//
|
||||
// https://github.com/dwhinham/mt32-pi
|
||||
//
|
||||
|
||||
module mt32pi
|
||||
(
|
||||
input CLK_AUDIO,
|
||||
|
||||
input CLK_VIDEO,
|
||||
input CE_PIXEL,
|
||||
input VGA_VS,
|
||||
input VGA_DE,
|
||||
|
||||
input [6:0] USER_IN,
|
||||
output [6:0] USER_OUT,
|
||||
|
||||
input reset,
|
||||
input midi_tx,
|
||||
output midi_rx,
|
||||
|
||||
output reg [15:0] mt32_i2s_r,
|
||||
output reg [15:0] mt32_i2s_l,
|
||||
|
||||
output reg mt32_available,
|
||||
|
||||
input mt32_mode_req,
|
||||
input [1:0] mt32_rom_req,
|
||||
input [7:0] mt32_sf_req,
|
||||
|
||||
output reg [7:0] mt32_mode,
|
||||
output reg [7:0] mt32_rom,
|
||||
output reg [7:0] mt32_sf,
|
||||
output reg mt32_newmode,
|
||||
|
||||
output reg mt32_lcd_en,
|
||||
output reg mt32_lcd_pix,
|
||||
output reg mt32_lcd_update
|
||||
);
|
||||
|
||||
//
|
||||
// Pin | USB Name | Signal
|
||||
// ----+----------+--------------
|
||||
// 0 | D+ | I/O I2C_SDA / RX (midi in)
|
||||
// 1 | D- | O TX (midi out)
|
||||
// 2 | TX- | I I2S_WS (1 == right)
|
||||
// 3 | GND_d | I I2C_SCL
|
||||
// 4 | RX+ | I I2S_BCLK
|
||||
// 5 | RX- | I I2S_DAT
|
||||
// 6 | TX+ | - none
|
||||
//
|
||||
|
||||
assign USER_OUT[0] = sda_out;
|
||||
assign USER_OUT[1] = midi_tx;
|
||||
assign USER_OUT[6:2] = '1;
|
||||
|
||||
|
||||
//
|
||||
// crossed/straight cable selection
|
||||
//
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for(i = 0; i<2; i++) begin : clk_rate
|
||||
wire clk_in = i ? USER_IN[6] : USER_IN[4];
|
||||
reg [4:0] cnt;
|
||||
always @(posedge CLK_AUDIO) begin : clkr
|
||||
reg clk_sr, clk, old_clk;
|
||||
reg [4:0] cnt_tmp;
|
||||
|
||||
clk_sr <= clk_in;
|
||||
if (clk_sr == clk_in) clk <= clk_sr;
|
||||
|
||||
if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1;
|
||||
else cnt <= '1;
|
||||
|
||||
old_clk <= clk;
|
||||
if(~old_clk & clk) begin
|
||||
cnt <= cnt_tmp;
|
||||
cnt_tmp <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg crossed;
|
||||
always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt);
|
||||
endgenerate
|
||||
|
||||
wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5];
|
||||
wire i2s_data = crossed ? USER_IN[5] : USER_IN[2];
|
||||
wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6];
|
||||
assign midi_rx = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4];
|
||||
|
||||
|
||||
//
|
||||
// i2s receiver
|
||||
//
|
||||
|
||||
always @(posedge CLK_AUDIO) begin : i2s_proc
|
||||
reg [15:0] i2s_buf = 0;
|
||||
reg [4:0] i2s_cnt = 0;
|
||||
reg clk_sr;
|
||||
reg i2s_clk = 0;
|
||||
reg old_clk, old_ws;
|
||||
reg i2s_next = 0;
|
||||
|
||||
// Debounce clock
|
||||
clk_sr <= i2s_bclk;
|
||||
if (clk_sr == i2s_bclk) i2s_clk <= clk_sr;
|
||||
|
||||
// Latch data and ws on rising edge
|
||||
old_clk <= i2s_clk;
|
||||
if (i2s_clk && ~old_clk) begin
|
||||
|
||||
if (~i2s_cnt[4]) begin
|
||||
i2s_cnt <= i2s_cnt + 1'd1;
|
||||
i2s_buf[~i2s_cnt[3:0]] <= i2s_data;
|
||||
end
|
||||
|
||||
// Word Select will change 1 clock before the new word starts
|
||||
old_ws <= i2s_ws;
|
||||
if (old_ws != i2s_ws) i2s_next <= 1;
|
||||
end
|
||||
|
||||
if (i2s_next) begin
|
||||
i2s_next <= 0;
|
||||
i2s_cnt <= 0;
|
||||
i2s_buf <= 0;
|
||||
|
||||
if (i2s_ws) mt32_i2s_l <= i2s_buf;
|
||||
else mt32_i2s_r <= i2s_buf;
|
||||
end
|
||||
|
||||
if (reset) begin
|
||||
i2s_buf <= 0;
|
||||
mt32_i2s_l <= 0;
|
||||
mt32_i2s_r <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// i2c slave
|
||||
//
|
||||
|
||||
reg sda_out;
|
||||
reg [7:0] lcd_data[1024];
|
||||
reg lcd_sz;
|
||||
|
||||
reg reset_r = 0;
|
||||
wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1;
|
||||
wire [7:0] rom_req = {6'd0, mt32_rom_req};
|
||||
|
||||
always @(posedge CLK_AUDIO) begin : i2c_slave
|
||||
reg sda_sr, scl_sr;
|
||||
reg old_sda, old_scl;
|
||||
reg sda, scl;
|
||||
reg [7:0] tmp;
|
||||
reg [3:0] cnt = 0;
|
||||
reg [10:0] bcnt = 0;
|
||||
reg ack;
|
||||
reg i2c_rw;
|
||||
reg disp, dispdata;
|
||||
reg [2:0] div;
|
||||
reg old_reset;
|
||||
|
||||
old_reset <= reset;
|
||||
if(old_reset & ~reset) sda_out <= 1;
|
||||
|
||||
div <= div + 1'd1;
|
||||
if(!div) begin
|
||||
sda_sr <= USER_IN[0];
|
||||
if(sda_sr == USER_IN[0]) sda <= sda_sr;
|
||||
old_sda <= sda;
|
||||
|
||||
scl_sr <= USER_IN[3];
|
||||
if(scl_sr == USER_IN[3]) scl <= scl_sr;
|
||||
old_scl <= scl;
|
||||
|
||||
//start
|
||||
if(old_scl & scl & old_sda & ~sda) begin
|
||||
cnt <= 9;
|
||||
bcnt <= 0;
|
||||
ack <= 0;
|
||||
i2c_rw <= 0;
|
||||
disp <= 0;
|
||||
dispdata <= 0;
|
||||
end
|
||||
|
||||
//stop
|
||||
if(old_scl & scl & ~old_sda & sda) begin
|
||||
cnt <= 0;
|
||||
if(dispdata) begin
|
||||
lcd_sz <= ~bcnt[9];
|
||||
mt32_lcd_update <= ~mt32_lcd_update;
|
||||
end
|
||||
end
|
||||
|
||||
//data latch
|
||||
if(~old_scl && scl && cnt) begin
|
||||
tmp <= {tmp[6:0], sda};
|
||||
cnt <= cnt - 1'd1;
|
||||
end
|
||||
|
||||
if(!cnt) sda_out <= 1;
|
||||
|
||||
//data set
|
||||
if(old_scl && ~scl) begin
|
||||
sda_out <= 1;
|
||||
if(cnt == 1) begin
|
||||
if(!bcnt) begin
|
||||
if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin
|
||||
disp <= (tmp[7:1] == 'h3c);
|
||||
sda_out <= 0;
|
||||
mt32_available <= 1;
|
||||
ack <= 1;
|
||||
i2c_rw <= tmp[0];
|
||||
bcnt <= bcnt + 1'd1;
|
||||
cnt <= 10;
|
||||
end
|
||||
else begin
|
||||
// wrong address, stop
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
else if(ack) begin
|
||||
if(~i2c_rw) begin
|
||||
if(disp) begin
|
||||
if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01);
|
||||
else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp;
|
||||
end
|
||||
else begin
|
||||
if(bcnt == 1) mt32_mode <= tmp;
|
||||
if(bcnt == 2) mt32_rom <= tmp;
|
||||
if(bcnt == 3) mt32_sf <= tmp;
|
||||
if(bcnt == 3) mt32_newmode <= ~mt32_newmode;
|
||||
end
|
||||
end
|
||||
if(~&bcnt) bcnt <= bcnt + 1'd1;
|
||||
sda_out <= 0;
|
||||
cnt <= 10;
|
||||
end
|
||||
end
|
||||
else if(i2c_rw && ack && cnt && ~disp) begin
|
||||
if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2];
|
||||
if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2];
|
||||
if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2];
|
||||
if(bcnt == 3) reset_r <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if(reset) begin
|
||||
reset_r <= 1;
|
||||
mt32_available <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_de, old_vs;
|
||||
reg [7:0] hcnt;
|
||||
reg [6:0] vcnt;
|
||||
reg [7:0] sh;
|
||||
|
||||
if(CE_PIXEL) begin
|
||||
old_de <= VGA_DE;
|
||||
old_vs <= VGA_VS;
|
||||
|
||||
if(~&hcnt) hcnt <= hcnt + 1'd1;
|
||||
sh <= (sh << 1) | (~old_de & VGA_DE);
|
||||
if(sh[7]) hcnt <= 0;
|
||||
|
||||
if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1;
|
||||
if(~old_vs & VGA_VS) vcnt <= 0;
|
||||
|
||||
mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]);
|
||||
mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -72,7 +72,7 @@ always@(posedge clk_sys) begin
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(io_din[7:4] == 4) begin
|
||||
if(!io_din[0]) {osd_status,highres} <= 0;
|
||||
else {osd_status,info} <= {~io_din[2],io_din[2]};
|
||||
else {osd_status,info} <= {~io_din[2] & ~io_din[3],io_din[2]};
|
||||
bcnt <= 0;
|
||||
end
|
||||
// command 0x20: OSDCMDWRITE
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
@@ -11,19 +11,18 @@ set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONEN
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlvXzAwMDI="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
@@ -334,5 +333,5 @@ set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quar
|
||||
set_global_assignment -library "pll_audio" -name QIP_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
// megafunction wizard: %Altera PLL v17.1%
|
||||
// megafunction wizard: %Altera PLL v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_audio.v
|
||||
|
||||
// Generated using ACDS version 17.1 593
|
||||
// Generated using ACDS version 17.0 602
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_audio (
|
||||
@@ -45,12 +45,12 @@ endmodule
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.1" >
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="Unknown" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
|
||||
@@ -1,17 +1,17 @@
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2NmZw=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
||||
@@ -24,7 +24,7 @@ set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
|
||||
@@ -38,8 +38,7 @@ set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_std_synchronizer.v"]
|
||||
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
// megafunction wizard: %Altera PLL Reconfig v17.1%
|
||||
// megafunction wizard: %Altera PLL Reconfig v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_cfg.v
|
||||
|
||||
// Generated using ACDS version 17.1 593
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_cfg #(
|
||||
@@ -56,7 +56,7 @@ endmodule
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2020 Altera Corporation
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
@@ -76,7 +76,7 @@ endmodule
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.1" >
|
||||
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
|
||||
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
// (C) 2001-2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
// (C) 2001-2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
@@ -11,19 +11,18 @@ set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
@@ -480,5 +479,5 @@ set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quart
|
||||
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
// megafunction wizard: %Altera PLL v17.1%
|
||||
// megafunction wizard: %Altera PLL v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_hdmi.v
|
||||
|
||||
// Generated using ACDS version 17.1 593
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_hdmi (
|
||||
@@ -29,7 +29,7 @@ endmodule
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2020 Altera Corporation
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
@@ -49,11 +49,11 @@ endmodule
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.1" >
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="Unknown" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017-2019 Sorgelig
|
||||
// Copyright (c) 2017-2021 Alexey Melnikov
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
@@ -23,23 +23,20 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_vid,
|
||||
input ce_pix,
|
||||
output ce_pix_out,
|
||||
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input ce_pix,
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input hb_in,
|
||||
input vb_in,
|
||||
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
input mono,
|
||||
|
||||
// output interface
|
||||
output ce_pix_out,
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output hb_out,
|
||||
@@ -109,7 +106,6 @@ Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
|
||||
.ce_in(ce_x4i),
|
||||
.inputpixel({b_d,g_d,r_d}),
|
||||
.mono(mono),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vb_in),
|
||||
.reset_line(req_line_reset),
|
||||
|
||||
798
sys/sd_card.sv
798
sys/sd_card.sv
@@ -23,52 +23,55 @@
|
||||
|
||||
//
|
||||
// Made module syncrhronous. Total code refactoring. (Sorgelig)
|
||||
// clk_spi must be at least 4 x sck for proper work.
|
||||
// clk_spi must be at least 2 x sck for proper work.
|
||||
|
||||
module sd_card #(parameter WIDE = 0)
|
||||
module sd_card #(parameter WIDE = 0, OCTAL=0)
|
||||
(
|
||||
input clk_sys,
|
||||
input reset,
|
||||
input clk_sys,
|
||||
input reset,
|
||||
|
||||
input sdhc,
|
||||
|
||||
output [31:0] sd_lba,
|
||||
output reg sd_rd,
|
||||
output reg sd_wr,
|
||||
input sd_ack,
|
||||
input sd_ack_conf,
|
||||
input sdhc,
|
||||
input img_mounted,
|
||||
input [63:0] img_size,
|
||||
|
||||
input [AW:0] sd_buff_addr,
|
||||
input [DW:0] sd_buff_dout,
|
||||
output [DW:0] sd_buff_din,
|
||||
input sd_buff_wr,
|
||||
output reg [31:0] sd_lba,
|
||||
output reg sd_rd,
|
||||
output reg sd_wr,
|
||||
input sd_ack,
|
||||
|
||||
input [AW:0] sd_buff_addr,
|
||||
input [DW:0] sd_buff_dout,
|
||||
output [DW:0] sd_buff_din,
|
||||
input sd_buff_wr,
|
||||
|
||||
// SPI interface
|
||||
input clk_spi,
|
||||
input clk_spi,
|
||||
|
||||
input ss,
|
||||
input sck,
|
||||
input mosi,
|
||||
output reg miso
|
||||
input ss,
|
||||
input sck,
|
||||
input [SW:0] mosi,
|
||||
output reg [SW:0] miso
|
||||
);
|
||||
|
||||
localparam AW = WIDE ? 7 : 8;
|
||||
localparam DW = WIDE ? 15 : 7;
|
||||
localparam AW = WIDE ? 7 : 8;
|
||||
localparam DW = WIDE ? 15 : 7;
|
||||
localparam SZ = OCTAL ? 8 : 1;
|
||||
localparam SW = SZ-1;
|
||||
|
||||
assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]};
|
||||
|
||||
wire[31:0] OCR = { 1'b1, sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished
|
||||
wire [7:0] READ_DATA_TOKEN = 8'hfe;
|
||||
wire [7:0] DATA_TOKEN_CMD25 = 8'hfc;
|
||||
wire [7:0] STOP_TRAN = 8'hfd;
|
||||
wire [7:0] DATA_TOKEN = 8'hfe;
|
||||
wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
|
||||
|
||||
// number of bytes to wait after a command before sending the reply
|
||||
localparam NCR=3;
|
||||
localparam NCR = 5+3; // 5 bytes are required (command length)
|
||||
|
||||
localparam RD_STATE_IDLE = 0;
|
||||
localparam RD_STATE_WAIT_IO = 1;
|
||||
localparam RD_STATE_SEND_TOKEN = 2;
|
||||
localparam RD_STATE_SEND_DATA = 3;
|
||||
localparam RD_STATE_WAIT_M = 4;
|
||||
localparam RD_STATE_START = 1;
|
||||
localparam RD_STATE_WAIT_IO = 2;
|
||||
localparam RD_STATE_SEND_TOKEN = 3;
|
||||
localparam RD_STATE_SEND_DATA = 4;
|
||||
localparam RD_STATE_WAIT_M = 5;
|
||||
|
||||
localparam WR_STATE_IDLE = 0;
|
||||
localparam WR_STATE_EXP_DTOKEN = 1;
|
||||
@@ -78,460 +81,383 @@ localparam WR_STATE_RECV_CRC1 = 4;
|
||||
localparam WR_STATE_SEND_DRESP = 5;
|
||||
localparam WR_STATE_BUSY = 6;
|
||||
|
||||
sdbuf #(WIDE) buffer
|
||||
localparam PREF_STATE_IDLE = 0;
|
||||
localparam PREF_STATE_RD = 1;
|
||||
localparam PREF_STATE_FINISH = 2;
|
||||
|
||||
altsyncram sdbuf
|
||||
(
|
||||
.clock_a(clk_sys),
|
||||
.address_a(sd_buff_addr),
|
||||
.data_a(sd_buff_dout),
|
||||
.wren_a(sd_ack & sd_buff_wr),
|
||||
.q_a(sd_buff_din),
|
||||
.clock0 (clk_sys),
|
||||
.address_a ({sd_buf,sd_buff_addr}),
|
||||
.data_a (sd_buff_dout),
|
||||
.wren_a (sd_ack & sd_buff_wr),
|
||||
.q_a (sd_buff_din),
|
||||
|
||||
.clock_b(clk_spi),
|
||||
.address_b(buffer_ptr),
|
||||
.data_b(buffer_din),
|
||||
.wren_b(buffer_wr),
|
||||
.q_b(buffer_dout)
|
||||
.clock1 (clk_spi),
|
||||
.address_b ({spi_buf,buffer_ptr}),
|
||||
.data_b (buffer_din),
|
||||
.wren_b (buffer_wr),
|
||||
.q_b (buffer_dout),
|
||||
|
||||
.aclr0(1'b0),
|
||||
.aclr1(1'b0),
|
||||
.addressstall_a(1'b0),
|
||||
.addressstall_b(1'b0),
|
||||
.byteena_a(1'b1),
|
||||
.byteena_b(1'b1),
|
||||
.clocken0(1'b1),
|
||||
.clocken1(1'b1),
|
||||
.clocken2(1'b1),
|
||||
.clocken3(1'b1),
|
||||
.eccstatus(),
|
||||
.rden_a(1'b1),
|
||||
.rden_b(1'b1)
|
||||
);
|
||||
defparam
|
||||
sdbuf.numwords_a = 1<<(AW+3),
|
||||
sdbuf.widthad_a = AW+3,
|
||||
sdbuf.width_a = DW+1,
|
||||
sdbuf.numwords_b = 2048,
|
||||
sdbuf.widthad_b = 11,
|
||||
sdbuf.width_b = 8,
|
||||
sdbuf.address_reg_b = "CLOCK1",
|
||||
sdbuf.clock_enable_input_a = "BYPASS",
|
||||
sdbuf.clock_enable_input_b = "BYPASS",
|
||||
sdbuf.clock_enable_output_a = "BYPASS",
|
||||
sdbuf.clock_enable_output_b = "BYPASS",
|
||||
sdbuf.indata_reg_b = "CLOCK1",
|
||||
sdbuf.intended_device_family = "Cyclone V",
|
||||
sdbuf.lpm_type = "altsyncram",
|
||||
sdbuf.operation_mode = "BIDIR_DUAL_PORT",
|
||||
sdbuf.outdata_aclr_a = "NONE",
|
||||
sdbuf.outdata_aclr_b = "NONE",
|
||||
sdbuf.outdata_reg_a = "UNREGISTERED",
|
||||
sdbuf.outdata_reg_b = "UNREGISTERED",
|
||||
sdbuf.power_up_uninitialized = "FALSE",
|
||||
sdbuf.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
|
||||
sdbuf.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
|
||||
sdbuf.width_byteena_a = 1,
|
||||
sdbuf.width_byteena_b = 1,
|
||||
sdbuf.wrcontrol_wraddress_reg_b = "CLOCK1";
|
||||
|
||||
sdbuf #(WIDE) conf
|
||||
(
|
||||
.clock_a(clk_sys),
|
||||
.address_a(sd_buff_addr),
|
||||
.data_a(sd_buff_dout),
|
||||
.wren_a(sd_ack_conf & sd_buff_wr),
|
||||
reg [26:0] csd_size;
|
||||
reg csd_sdhc;
|
||||
always @(posedge clk_sys) begin
|
||||
if (img_mounted) begin
|
||||
csd_sdhc <= sdhc;
|
||||
if (sdhc) begin
|
||||
csd_size[0] <= 0;
|
||||
csd_size[22:1] <= img_size[40:19]; // in 512K units
|
||||
csd_size[26:23] <= 0;
|
||||
end
|
||||
else begin
|
||||
csd_size[2:0] <= 7; // C_SIZE_MULT
|
||||
csd_size[14:3] <= 12'b101101101101;
|
||||
csd_size[26:15] <= img_size[29:18]; // in 256K units ((2**(C_SIZE_MULT+2))*512)
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
.clock_b(clk_spi),
|
||||
.address_b(buffer_ptr),
|
||||
.q_b(config_dout)
|
||||
);
|
||||
wire [127:0] CSD = {1'b0,csd_sdhc,6'h00,8'h0e,8'h00,8'h32,8'h5b,8'h59,6'h00,csd_size,7'h7f,8'h80,8'h0a,8'h40,8'h40,8'hf1};
|
||||
wire [127:0] CID = {8'hcd,8'hc7,8'h00,8'h93,8'h6f,8'h2f,8'h73,8'h00,8'h00,8'h44,8'h32,8'h38,8'h34,8'h00,8'h00,8'h3e};
|
||||
|
||||
reg [31:0] lba, new_lba;
|
||||
reg [8:0] buffer_ptr;
|
||||
reg [7:0] buffer_din;
|
||||
wire [7:0] buffer_dout;
|
||||
wire [7:0] config_dout;
|
||||
reg buffer_wr;
|
||||
|
||||
always @(posedge clk_spi) begin
|
||||
reg [2:0] read_state;
|
||||
reg [2:0] write_state;
|
||||
reg [6:0] sbuf;
|
||||
reg cmd55;
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt;
|
||||
reg [3:0] byte_cnt;
|
||||
reg [7:0] reply;
|
||||
reg [7:0] reply0, reply1, reply2, reply3;
|
||||
reg [3:0] reply_len;
|
||||
reg tx_finish;
|
||||
reg rx_finish;
|
||||
reg old_sck;
|
||||
reg synced;
|
||||
reg [5:0] ack;
|
||||
reg io_ack;
|
||||
reg [4:0] idle_cnt = 0;
|
||||
reg [2:0] wait_m_cnt;
|
||||
reg [1:0] sd_buf, spi_buf;
|
||||
|
||||
reg [6:0] sbuf;
|
||||
reg [2:0] bit_cnt;
|
||||
|
||||
wire last_bit = &bit_cnt || OCTAL;
|
||||
wire [7:0] ibuf = OCTAL ? mosi : {sbuf,mosi[0]};
|
||||
|
||||
always @(posedge clk_spi) begin
|
||||
reg [2:0] read_state;
|
||||
reg [2:0] write_state;
|
||||
reg [1:0] pref_state;
|
||||
reg [5:0] cmd;
|
||||
reg cmd55;
|
||||
reg [39:0] reply;
|
||||
reg [3:0] byte_cnt;
|
||||
reg old_sck;
|
||||
reg [2:0] ack;
|
||||
reg [2:0] wait_m_cnt;
|
||||
reg [31:0] arg;
|
||||
|
||||
ack[1:0] <= {ack[0],sd_ack};
|
||||
if(ack[1] == ack[0]) ack[2] <= ack[1];
|
||||
|
||||
if(~ack[2] & ack[1]) {sd_rd,sd_wr} <= 0;
|
||||
if( ack[2] & ~ack[1]) begin
|
||||
sd_buf <= sd_buf + 1'd1;
|
||||
sd_lba <= sd_lba + 1;
|
||||
end
|
||||
|
||||
if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
|
||||
buffer_wr <= 0;
|
||||
|
||||
ack <= {ack[4:0], sd_ack};
|
||||
if(ack[5:4] == 2'b10) io_ack <= 1;
|
||||
if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0;
|
||||
|
||||
old_sck <= sck;
|
||||
|
||||
if(~ss) idle_cnt <= 31;
|
||||
else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1;
|
||||
|
||||
if(reset || !idle_cnt) begin
|
||||
if(reset) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 15;
|
||||
synced <= 0;
|
||||
miso <= 1;
|
||||
sbuf <= 7'b1111111;
|
||||
tx_finish <= 0;
|
||||
rx_finish <= 0;
|
||||
byte_cnt <= '1;
|
||||
miso <= '1;
|
||||
cmd <= 0;
|
||||
sd_wr <= 0;
|
||||
sd_rd <= 0;
|
||||
read_state <= RD_STATE_IDLE;
|
||||
write_state <= WR_STATE_IDLE;
|
||||
pref_state <= PREF_STATE_IDLE;
|
||||
end
|
||||
else begin
|
||||
|
||||
if(old_sck & ~sck & ~ss) begin
|
||||
tx_finish <= 0;
|
||||
miso <= 1; // default: send 1's (busy/wait)
|
||||
|
||||
if(byte_cnt == 5+NCR) begin
|
||||
miso <= reply[~bit_cnt];
|
||||
|
||||
if(bit_cnt == 7) begin
|
||||
// these three commands all have a reply_len of 0 and will thus
|
||||
// not send more than a single reply byte
|
||||
|
||||
// CMD9: SEND_CSD
|
||||
// CMD10: SEND_CID
|
||||
if((cmd == 'h49) | (cmd == 'h4a))
|
||||
read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission
|
||||
|
||||
// CMD17/CMD18
|
||||
if((cmd == 'h51) | (cmd == 'h52)) begin
|
||||
io_ack <= 0;
|
||||
read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller
|
||||
lba <= new_lba;
|
||||
sd_rd <= 1; // trigger request to io controller
|
||||
end
|
||||
if(buffer_wr) begin
|
||||
if(~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
|
||||
else begin
|
||||
spi_buf <= spi_buf + 1'd1;
|
||||
sd_wr <= 1;
|
||||
end
|
||||
end
|
||||
else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt];
|
||||
else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt];
|
||||
else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt];
|
||||
else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt];
|
||||
else begin
|
||||
if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1;
|
||||
end
|
||||
|
||||
// ---------- read state machine processing -------------
|
||||
|
||||
case(read_state)
|
||||
RD_STATE_IDLE: ; // do nothing
|
||||
|
||||
|
||||
// waiting for io controller to return data
|
||||
RD_STATE_WAIT_IO: begin
|
||||
if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN;
|
||||
end
|
||||
|
||||
// send data token
|
||||
RD_STATE_SEND_TOKEN: begin
|
||||
miso <= READ_DATA_TOKEN[~bit_cnt];
|
||||
|
||||
if(bit_cnt == 7) begin
|
||||
read_state <= RD_STATE_SEND_DATA; // next: send data
|
||||
buffer_ptr <= 0;
|
||||
if(cmd == 'h49) buffer_ptr <= 16;
|
||||
case(pref_state)
|
||||
PREF_STATE_IDLE:
|
||||
if(((sd_buf - spi_buf) <= 1) && (read_state != RD_STATE_IDLE) && (cmd == 17 || cmd == 18)) begin
|
||||
sd_rd <= 1;
|
||||
pref_state <= PREF_STATE_RD;
|
||||
end
|
||||
end
|
||||
|
||||
// send data
|
||||
RD_STATE_SEND_DATA: begin
|
||||
|
||||
miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt];
|
||||
|
||||
if(bit_cnt == 7) begin
|
||||
|
||||
// sent 512 sector data bytes?
|
||||
if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE;
|
||||
else if((cmd == 'h52) & &buffer_ptr) begin
|
||||
read_state <= RD_STATE_WAIT_M;
|
||||
wait_m_cnt <= 0;
|
||||
end
|
||||
|
||||
// sent 16 cid/csd data bytes?
|
||||
else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE;
|
||||
|
||||
// not done yet -> trigger read of next data byte
|
||||
else buffer_ptr <= buffer_ptr + 1'd1;
|
||||
PREF_STATE_RD:
|
||||
if(read_state == RD_STATE_IDLE) begin
|
||||
pref_state <= PREF_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
RD_STATE_WAIT_M: begin
|
||||
if(bit_cnt == 7) begin
|
||||
wait_m_cnt <= wait_m_cnt + 1'd1;
|
||||
if(&wait_m_cnt) begin
|
||||
lba <= lba + 1;
|
||||
io_ack <= 0;
|
||||
sd_rd <= 1;
|
||||
read_state <= RD_STATE_WAIT_IO;
|
||||
end
|
||||
else if(ack[2] & ~ack[1]) begin
|
||||
pref_state <= (cmd == 18) ? PREF_STATE_IDLE : PREF_STATE_FINISH;
|
||||
end
|
||||
|
||||
PREF_STATE_FINISH:
|
||||
if(read_state == RD_STATE_IDLE) begin
|
||||
pref_state <= PREF_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// ------------------ write support ----------------------
|
||||
// send write data response
|
||||
if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt];
|
||||
|
||||
// busy after write until the io controller sends ack
|
||||
if(write_state == WR_STATE_BUSY) miso <= 0;
|
||||
end
|
||||
|
||||
if(~old_sck & sck & ~ss) begin
|
||||
|
||||
if(synced) bit_cnt <= bit_cnt + 1'd1;
|
||||
|
||||
// assemble byte
|
||||
if(bit_cnt != 7) begin
|
||||
sbuf[6:0] <= { sbuf[5:0], mosi };
|
||||
|
||||
// resync while waiting for token
|
||||
if(write_state==WR_STATE_EXP_DTOKEN) begin
|
||||
if(cmd == 'h58) begin
|
||||
if({sbuf,mosi} == 8'hfe) begin
|
||||
write_state <= WR_STATE_RECV_DATA;
|
||||
buffer_ptr <= 0;
|
||||
bit_cnt <= 0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if({sbuf,mosi} == 8'hfc) begin
|
||||
write_state <= WR_STATE_RECV_DATA;
|
||||
buffer_ptr <= 0;
|
||||
bit_cnt <= 0;
|
||||
end
|
||||
if({sbuf,mosi} == 8'hfd) begin
|
||||
write_state <= WR_STATE_IDLE;
|
||||
rx_finish <= 1;
|
||||
bit_cnt <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
old_sck <= sck;
|
||||
if(ss) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= '1;
|
||||
miso <= '1;
|
||||
end
|
||||
else begin
|
||||
// finished reading one byte
|
||||
// byte counter runs against 15 byte boundary
|
||||
if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1;
|
||||
else if(old_sck & ~sck) begin
|
||||
miso <= '1; // default: send 1's (busy/wait)
|
||||
if(byte_cnt >= NCR) {miso,reply} <= {reply, {SZ{1'b1}}};
|
||||
|
||||
// byte_cnt > 6 -> complete command received
|
||||
// first byte of valid command is 01xxxxxx
|
||||
// don't accept new commands once a write or read command has been accepted
|
||||
if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin
|
||||
byte_cnt <= 0;
|
||||
cmd <= { sbuf, mosi};
|
||||
// ---------- read state machine processing -------------
|
||||
case(read_state)
|
||||
RD_STATE_IDLE: ;
|
||||
|
||||
// set cmd55 flag if previous command was 55
|
||||
cmd55 <= (cmd == 'h77);
|
||||
end
|
||||
RD_STATE_START: begin
|
||||
if(byte_cnt == NCR && last_bit) read_state <= (cmd == 9 || cmd == 10) ? RD_STATE_SEND_TOKEN : RD_STATE_WAIT_IO;
|
||||
end
|
||||
|
||||
if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin
|
||||
byte_cnt <= 0;
|
||||
rx_finish <= 0;
|
||||
cmd <= {sbuf, mosi};
|
||||
read_state <= RD_STATE_IDLE;
|
||||
end
|
||||
// waiting for io controller to return data
|
||||
RD_STATE_WAIT_IO: begin
|
||||
if(sd_buf != spi_buf && last_bit) read_state <= RD_STATE_SEND_TOKEN;
|
||||
end
|
||||
|
||||
// parse additional command bytes
|
||||
if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi};
|
||||
if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi};
|
||||
if(byte_cnt == 2) new_lba[15:8] <= { sbuf, mosi};
|
||||
if(byte_cnt == 3) new_lba[7:0] <= { sbuf, mosi};
|
||||
|
||||
// last byte (crc) received, evaluate
|
||||
if(byte_cnt == 4) begin
|
||||
|
||||
// default:
|
||||
reply <= 4; // illegal command
|
||||
reply_len <= 0; // no extra reply bytes
|
||||
rx_finish <= 1;
|
||||
|
||||
case(cmd)
|
||||
// CMD0: GO_IDLE_STATE
|
||||
'h40: reply <= 1; // ok, busy
|
||||
|
||||
// CMD1: SEND_OP_COND
|
||||
'h41: reply <= 0; // ok, not busy
|
||||
|
||||
// CMD8: SEND_IF_COND (V2 only)
|
||||
'h48: begin
|
||||
reply <= 1; // ok, busy
|
||||
|
||||
reply0 <= 'h00;
|
||||
reply1 <= 'h00;
|
||||
reply2 <= 'h01;
|
||||
reply3 <= 'hAA;
|
||||
reply_len <= 4;
|
||||
end
|
||||
|
||||
// CMD9: SEND_CSD
|
||||
'h49: reply <= 0; // ok
|
||||
|
||||
// CMD10: SEND_CID
|
||||
'h4a: reply <= 0; // ok
|
||||
|
||||
// CMD12: STOP_TRANSMISSION
|
||||
'h4c: reply <= 0; // ok
|
||||
|
||||
// CMD13: SEND_STATUS
|
||||
'h4d: begin
|
||||
reply <= 'h00; // ok
|
||||
reply0 <='h00;
|
||||
reply_len <= 1;
|
||||
end
|
||||
|
||||
// CMD16: SET_BLOCKLEN
|
||||
'h50: begin
|
||||
// we only support a block size of 512
|
||||
if(new_lba == 512) reply <= 0; // ok
|
||||
else reply <= 'h40; // parmeter error
|
||||
end
|
||||
|
||||
// CMD17: READ_SINGLE_BLOCK
|
||||
'h51: reply <= 0; // ok
|
||||
|
||||
// CMD18: READ_MULTIPLE
|
||||
'h52: reply <= 0; // ok
|
||||
// ACMD23: SET_WR_BLK_ERASE_COUNT
|
||||
'h57: reply <= 0; //ok
|
||||
|
||||
// CMD24: WRITE_BLOCK
|
||||
'h58,
|
||||
// CMD25: WRITE_MULTIPLE
|
||||
'h59: begin
|
||||
reply <= 0; // ok
|
||||
write_state <= WR_STATE_EXP_DTOKEN; // expect data token
|
||||
rx_finish <=0;
|
||||
lba <= new_lba;
|
||||
end
|
||||
|
||||
// ACMD41: APP_SEND_OP_COND
|
||||
'h69: if(cmd55) reply <= 0; // ok, not busy
|
||||
|
||||
// CMD55: APP_COND
|
||||
'h77: reply <= 1; // ok, busy
|
||||
|
||||
// CMD58: READ_OCR
|
||||
'h7a: begin
|
||||
reply <= 0; // ok
|
||||
|
||||
reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card
|
||||
reply1 <= OCR[23:16];
|
||||
reply2 <= OCR[15:8];
|
||||
reply3 <= OCR[7:0];
|
||||
reply_len <= 4;
|
||||
end
|
||||
|
||||
// CMD59: CRC_ON_OFF
|
||||
'h7b: reply <= 0; // ok
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------- handle write -----------
|
||||
case(write_state)
|
||||
// do nothing in idle state
|
||||
WR_STATE_IDLE: ;
|
||||
|
||||
// waiting for data token
|
||||
WR_STATE_EXP_DTOKEN: begin
|
||||
buffer_ptr <= 0;
|
||||
if(cmd == 'h58) begin
|
||||
if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA;
|
||||
end
|
||||
else begin
|
||||
if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA;
|
||||
if({sbuf,mosi} == 8'hfd) begin
|
||||
write_state <= WR_STATE_IDLE;
|
||||
rx_finish <= 1;
|
||||
end
|
||||
// send data token
|
||||
RD_STATE_SEND_TOKEN: begin
|
||||
miso <= DATA_TOKEN[~bit_cnt -:SZ];
|
||||
if(last_bit) begin
|
||||
read_state <= RD_STATE_SEND_DATA; // next: send data
|
||||
buffer_ptr <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer 512 bytes
|
||||
WR_STATE_RECV_DATA: begin
|
||||
// push one byte into local buffer
|
||||
buffer_wr <= 1;
|
||||
buffer_din <= {sbuf, mosi};
|
||||
// send data
|
||||
RD_STATE_SEND_DATA: begin
|
||||
|
||||
// all bytes written?
|
||||
if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
|
||||
miso <= (cmd == 9) ? CSD[{buffer_ptr[3:0],~bit_cnt} -:SZ] : (cmd == 10) ? CID[{buffer_ptr[3:0],~bit_cnt} -:SZ] : buffer_dout[~bit_cnt -:SZ];
|
||||
|
||||
if(last_bit) begin
|
||||
|
||||
// sent 512 sector data bytes?
|
||||
if(cmd == 17 && &buffer_ptr) read_state <= RD_STATE_IDLE;
|
||||
else if(cmd == 18 && &buffer_ptr) begin
|
||||
read_state <= RD_STATE_WAIT_M;
|
||||
wait_m_cnt <= 0;
|
||||
end
|
||||
|
||||
// sent 16 cid/csd data bytes?
|
||||
else if((cmd == 9 || cmd == 10) && &buffer_ptr[3:0]) read_state <= RD_STATE_IDLE;
|
||||
|
||||
// not done yet -> trigger read of next data byte
|
||||
else buffer_ptr <= buffer_ptr + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer 1st crc byte
|
||||
WR_STATE_RECV_CRC0:
|
||||
write_state <= WR_STATE_RECV_CRC1;
|
||||
RD_STATE_WAIT_M: begin
|
||||
if(last_bit) begin
|
||||
wait_m_cnt <= wait_m_cnt + 1'd1;
|
||||
if(&wait_m_cnt) begin
|
||||
spi_buf <= spi_buf + 1'd1;
|
||||
read_state <= RD_STATE_WAIT_IO;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// transfer 2nd crc byte
|
||||
WR_STATE_RECV_CRC1:
|
||||
write_state <= WR_STATE_SEND_DRESP;
|
||||
// ------------------ write support ----------------------
|
||||
// send write data response
|
||||
if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt -:SZ];
|
||||
|
||||
// send data response
|
||||
WR_STATE_SEND_DRESP: begin
|
||||
write_state <= WR_STATE_BUSY;
|
||||
io_ack <= 0;
|
||||
sd_wr <= 1;
|
||||
// busy after write until the io controller sends ack
|
||||
if(write_state == WR_STATE_BUSY) miso <= 0;
|
||||
end
|
||||
else if(~old_sck & sck) begin
|
||||
|
||||
sbuf[6:0] <= {sbuf[5:0],mosi[0]};
|
||||
bit_cnt <= bit_cnt + SZ[2:0];
|
||||
|
||||
if(last_bit) begin
|
||||
// finished reading one byte
|
||||
// byte counter runs against 15 byte boundary
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
|
||||
|
||||
// byte_cnt > 6 -> complete command received
|
||||
// first byte of valid command is 01xxxxxx
|
||||
// don't accept new commands once a write or read command has been accepted
|
||||
if(byte_cnt > 5 &&
|
||||
((write_state == WR_STATE_IDLE && read_state == RD_STATE_IDLE && ibuf[7:6] == 1) ||
|
||||
(read_state != RD_STATE_IDLE && ibuf == 8'h4c))) begin
|
||||
byte_cnt <= 0;
|
||||
cmd <= ibuf[5:0];
|
||||
cmd55 <= (cmd == 55); // set cmd55 flag if previous command was 55
|
||||
if(ibuf[5:0] == 12) read_state <= RD_STATE_IDLE;
|
||||
end
|
||||
|
||||
// wait for io controller to accept data
|
||||
WR_STATE_BUSY:
|
||||
if(io_ack) begin
|
||||
if(cmd == 'h59) begin
|
||||
write_state <= WR_STATE_EXP_DTOKEN;
|
||||
lba <= lba + 1;
|
||||
// parse additional command bytes
|
||||
if(byte_cnt == 0) arg[31:24] <= ibuf;
|
||||
if(byte_cnt == 1) arg[23:16] <= ibuf;
|
||||
if(byte_cnt == 2) arg[15:8] <= ibuf;
|
||||
if(byte_cnt == 3) arg[7:0] <= ibuf;
|
||||
|
||||
// last byte (crc) received, evaluate
|
||||
if(byte_cnt == 4) begin
|
||||
|
||||
// default:
|
||||
reply <= 40'h04FFFFFFFF; // illegal command
|
||||
|
||||
case(cmd)
|
||||
// CMD0: GO_IDLE_STATE
|
||||
0: reply[39:32] <= 1; // ok, busy
|
||||
|
||||
// CMD1: SEND_OP_COND
|
||||
1: reply[39:32] <= 0;
|
||||
|
||||
// CMD8: SEND_IF_COND (V2 only)
|
||||
8: reply <= 40'h01000001AA; // ok, busy
|
||||
|
||||
// CMD9: SEND_CSD
|
||||
9,
|
||||
// CMD10: SEND_CID
|
||||
10: begin
|
||||
reply[39:32] <= 0;
|
||||
read_state <= RD_STATE_START;
|
||||
end
|
||||
|
||||
// CMD12: STOP_TRANSMISSION
|
||||
12: reply[39:32] <= 0;
|
||||
|
||||
// CMD13: SEND_STATUS
|
||||
13: reply[39:24] <= 16'h0000;
|
||||
|
||||
// CMD16: SET_BLOCKLEN
|
||||
16: reply[39:32] <= (arg == 512) ? 8'h00 : 8'h40; // we only support a block size of 512
|
||||
|
||||
// CMD17: READ_SINGLE_BLOCK
|
||||
17,
|
||||
// CMD18: READ_MULTIPLE
|
||||
18: begin
|
||||
reply[39:32] <= 0;
|
||||
read_state <= RD_STATE_START;
|
||||
spi_buf <= 0;
|
||||
sd_buf <= 0;
|
||||
sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]};
|
||||
end
|
||||
|
||||
// ACMD23: SET_WR_BLK_ERASE_COUNT
|
||||
23: reply[39:32] <= 0;
|
||||
|
||||
// CMD24: WRITE_BLOCK
|
||||
24,
|
||||
// CMD25: WRITE_MULTIPLE
|
||||
25: begin
|
||||
reply[39:32] <= 0;
|
||||
write_state <= WR_STATE_EXP_DTOKEN; // expect data token
|
||||
spi_buf <= 0;
|
||||
sd_buf <= 0;
|
||||
sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]};
|
||||
end
|
||||
|
||||
// ACMD41: APP_SEND_OP_COND
|
||||
41: if(cmd55) reply[39:32] <= 0; // ok, not busy
|
||||
|
||||
// CMD55: APP_COND
|
||||
55: reply[39:32] <= 1; // ok, busy
|
||||
|
||||
// CMD58: READ_OCR
|
||||
58: reply <= { 8'h00, 1'b1, csd_sdhc, 30'd0 }; // bit 30 = 1 -> high capacity card
|
||||
|
||||
// CMD59: CRC_ON_OFF
|
||||
59: reply[39:32] <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------- handle write -----------
|
||||
case(write_state)
|
||||
// do nothing in idle state
|
||||
WR_STATE_IDLE: ;
|
||||
|
||||
// waiting for data token
|
||||
WR_STATE_EXP_DTOKEN: begin
|
||||
buffer_ptr <= 0;
|
||||
if(cmd == 24) begin
|
||||
if(ibuf == DATA_TOKEN) write_state <= WR_STATE_RECV_DATA;
|
||||
end
|
||||
else begin
|
||||
write_state <= WR_STATE_IDLE;
|
||||
rx_finish <= 1;
|
||||
if(ibuf == DATA_TOKEN_CMD25) write_state <= WR_STATE_RECV_DATA;
|
||||
if(ibuf == STOP_TRAN) write_state <= WR_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// wait for first 0 bit until start counting bits
|
||||
if(!synced && !mosi) begin
|
||||
synced <= 1;
|
||||
bit_cnt <= 1; // byte assembly prepare for next time loop
|
||||
sbuf <= 7'b1111110; // byte assembly prepare for next time loop
|
||||
rx_finish<= 0;
|
||||
end else if (synced && tx_finish && rx_finish ) begin
|
||||
synced <= 0;
|
||||
bit_cnt <= 0;
|
||||
rx_finish<= 0;
|
||||
|
||||
// transfer 512 bytes
|
||||
WR_STATE_RECV_DATA: begin
|
||||
// push one byte into local buffer
|
||||
buffer_wr <= 1;
|
||||
buffer_din <= ibuf;
|
||||
|
||||
// all bytes written?
|
||||
if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
|
||||
end
|
||||
|
||||
// transfer 1st crc byte
|
||||
WR_STATE_RECV_CRC0:
|
||||
write_state <= WR_STATE_RECV_CRC1;
|
||||
|
||||
// transfer 2nd crc byte
|
||||
WR_STATE_RECV_CRC1:
|
||||
write_state <= WR_STATE_SEND_DRESP;
|
||||
|
||||
// send data response
|
||||
WR_STATE_SEND_DRESP:
|
||||
write_state <= WR_STATE_BUSY;
|
||||
|
||||
// wait for io controller to accept data
|
||||
WR_STATE_BUSY:
|
||||
if(spi_buf == sd_buf) write_state <= (cmd == 25) ? WR_STATE_EXP_DTOKEN : WR_STATE_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module sdbuf #(parameter WIDE)
|
||||
(
|
||||
input clock_a,
|
||||
input [AW:0] address_a,
|
||||
input [DW:0] data_a,
|
||||
input wren_a,
|
||||
output reg [DW:0] q_a,
|
||||
|
||||
input clock_b,
|
||||
input [8:0] address_b,
|
||||
input [7:0] data_b,
|
||||
input wren_b,
|
||||
output reg [7:0] q_b
|
||||
);
|
||||
|
||||
localparam AW = WIDE ? 7 : 8;
|
||||
localparam DW = WIDE ? 15 : 7;
|
||||
|
||||
always@(posedge clock_a) begin
|
||||
if(wren_a) begin
|
||||
ram[address_a] <= data_a;
|
||||
q_a <= data_a;
|
||||
end
|
||||
else begin
|
||||
q_a <= ram[address_a];
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if(WIDE) begin
|
||||
reg [1:0][7:0] ram[1<<8];
|
||||
always@(posedge clock_b) begin
|
||||
if(wren_b) begin
|
||||
ram[address_b[8:1]][address_b[0]] <= data_b;
|
||||
q_b <= data_b;
|
||||
end
|
||||
else begin
|
||||
q_b <= ram[address_b[8:1]][address_b[0]];
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
reg [7:0] ram[1<<9];
|
||||
always@(posedge clock_b) begin
|
||||
if(wren_b) begin
|
||||
ram[address_b] <= data_b;
|
||||
q_b <= data_b;
|
||||
end
|
||||
else begin
|
||||
q_b <= ram[address_b];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
136
sys/shadowmask.sv
Normal file
136
sys/shadowmask.sv
Normal file
@@ -0,0 +1,136 @@
|
||||
module shadowmask
|
||||
(
|
||||
input clk,
|
||||
input clk_sys,
|
||||
|
||||
input cmd_wr,
|
||||
input [15:0] cmd_in,
|
||||
|
||||
input [23:0] din,
|
||||
input hs_in,vs_in,
|
||||
input de_in,
|
||||
input brd_in,
|
||||
input enable,
|
||||
|
||||
output reg [23:0] dout,
|
||||
output reg hs_out,vs_out,
|
||||
output reg de_out
|
||||
);
|
||||
|
||||
|
||||
reg [4:0] hmax;
|
||||
reg [4:0] vmax;
|
||||
reg [7:0] mask_idx;
|
||||
reg mask_2x;
|
||||
reg mask_rotate;
|
||||
reg mask_enable;
|
||||
reg [10:0] mask_lut[256];
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [4:0] hcount;
|
||||
reg [4:0] vcount;
|
||||
reg [3:0] hindex;
|
||||
reg [3:0] vindex;
|
||||
reg [4:0] hmax2;
|
||||
reg [4:0] vmax2;
|
||||
reg [11:0] pcnt,pde;
|
||||
reg old_hs, old_vs, old_brd;
|
||||
reg next_v;
|
||||
|
||||
old_hs <= hs_in;
|
||||
old_vs <= vs_in;
|
||||
old_brd<= brd_in;
|
||||
|
||||
// hcount and vcount counts pixel rows and columns
|
||||
// hindex and vindex half the value of the counters for double size patterns
|
||||
// hindex2, vindex2 swap the h and v counters for drawing rotated masks
|
||||
hindex <= mask_2x ? hcount[4:1] : hcount[3:0];
|
||||
vindex <= mask_2x ? vcount[4:1] : vcount[3:0];
|
||||
mask_idx <= mask_rotate ? {hindex,vindex} : {vindex,hindex};
|
||||
|
||||
// hmax and vmax store these sizes
|
||||
// hmax2 and vmax2 swap the values to handle rotation
|
||||
hmax2 <= ((mask_rotate ? vmax : hmax) << mask_2x) | mask_2x;
|
||||
vmax2 <= ((mask_rotate ? hmax : vmax) << mask_2x) | mask_2x;
|
||||
|
||||
pcnt <= pcnt+1'd1;
|
||||
if(old_brd && ~brd_in) pde <= pcnt-4'd3;
|
||||
|
||||
hcount <= hcount+1'b1;
|
||||
if(hcount == hmax2 || pde == pcnt) hcount <= 0;
|
||||
|
||||
if(~old_brd && brd_in) next_v <= 1;
|
||||
if(old_vs && ~vs_in) vcount <= 0;
|
||||
if(old_hs && ~hs_in) begin
|
||||
vcount <= vcount + next_v;
|
||||
next_v <= 0;
|
||||
pcnt <= 0;
|
||||
if (vcount == vmax2) vcount <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [4:0] r_mul, g_mul, b_mul; // 1.4 fixed point multipliers
|
||||
always @(posedge clk) begin
|
||||
reg [10:0] lut;
|
||||
|
||||
lut <= mask_lut[mask_idx];
|
||||
|
||||
r_mul <= 5'b10000; g_mul <= 5'b10000; b_mul <= 5'b10000; // default 100% to all channels
|
||||
if (mask_enable) begin
|
||||
r_mul <= lut[10] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
|
||||
g_mul <= lut[9] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
|
||||
b_mul <= lut[8] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [11:0] vid;
|
||||
reg [7:0] r1, g1, b1;
|
||||
reg [7:0] r2, g2, b2;
|
||||
reg [7:0] r3_x, g3_x, b3_x; // 6.25% + 12.5%
|
||||
reg [8:0] r3_y, g3_y, b3_y; // 25% + 50% + 100%
|
||||
reg [8:0] r4, g4, b4;
|
||||
|
||||
// C1 - data input
|
||||
{r1,g1,b1} <= din;
|
||||
vid <= {vid[8:0],vs_in, hs_in, de_in};
|
||||
|
||||
// C2 - relax timings
|
||||
{r2,g2,b2} <= {r1,g1,b1};
|
||||
|
||||
// C3 - perform multiplications
|
||||
r3_x <= ({4{r_mul[0]}} & r2[7:4]) + ({8{r_mul[1]}} & r2[7:3]);
|
||||
r3_y <= ({6{r_mul[2]}} & r2[7:2]) + ({7{r_mul[3]}} & r2[7:1]) + ({9{r_mul[4]}} & r2[7:0]);
|
||||
g3_x <= ({4{g_mul[0]}} & g2[7:4]) + ({8{g_mul[1]}} & g2[7:3]);
|
||||
g3_y <= ({6{g_mul[2]}} & g2[7:2]) + ({7{g_mul[3]}} & g2[7:1]) + ({9{g_mul[4]}} & g2[7:0]);
|
||||
b3_x <= ({4{b_mul[0]}} & b2[7:4]) + ({8{b_mul[1]}} & b2[7:3]);
|
||||
b3_y <= ({6{b_mul[2]}} & b2[7:2]) + ({7{b_mul[3]}} & b2[7:1]) + ({9{b_mul[4]}} & b2[7:0]);
|
||||
|
||||
// C4 - combine results
|
||||
r4 <= r3_x + r3_y;
|
||||
g4 <= g3_x + g3_y;
|
||||
b4 <= b3_x + b3_y;
|
||||
|
||||
// C5 - clamp and output
|
||||
dout <= {{8{r4[8]}} | r4[7:0], {8{g4[8]}} | g4[7:0], {8{b4[8]}} | b4[7:0]};
|
||||
{vs_out,hs_out,de_out} <= vid[11:9];
|
||||
end
|
||||
|
||||
// clock in mask commands
|
||||
always @(posedge clk_sys) begin
|
||||
reg m_enable;
|
||||
reg [7:0] idx;
|
||||
|
||||
if (cmd_wr) begin
|
||||
case(cmd_in[15:13])
|
||||
3'b000: begin {m_enable, mask_rotate, mask_2x} <= cmd_in[3:1]; idx <= 0; end
|
||||
3'b001: vmax <= cmd_in[3:0];
|
||||
3'b010: hmax <= cmd_in[3:0];
|
||||
3'b011: begin mask_lut[idx] <= cmd_in[10:0]; idx <= idx + 1'd1; end
|
||||
endcase
|
||||
end
|
||||
|
||||
mask_enable <= m_enable & enable;
|
||||
end
|
||||
|
||||
endmodule
|
||||
38
sys/spdif.v
38
sys/spdif.v
@@ -67,6 +67,8 @@ reg spdif_out_q;
|
||||
|
||||
reg [5:0] parity_count_q;
|
||||
|
||||
reg channel_status_bit_q;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Subframe Counter
|
||||
//-----------------------------------------------------------------
|
||||
@@ -142,19 +144,20 @@ assign subframe_w[28] = 1'b0; // Valid
|
||||
assign subframe_w[29] = 1'b0;
|
||||
|
||||
// Timeslots 30 = Channel status bit
|
||||
assign subframe_w[30] = 1'b0;
|
||||
assign subframe_w[30] = channel_status_bit_q ; //was constant 1'b0 enabling copy-bit;
|
||||
|
||||
// Timeslots 31 = Even Parity bit (31:4)
|
||||
assign subframe_w[31] = 1'b0;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Preamble
|
||||
// Preamble and Channel status bit
|
||||
//-----------------------------------------------------------------
|
||||
localparam PREAMBLE_Z = 8'b00010111;
|
||||
localparam PREAMBLE_Y = 8'b00100111;
|
||||
localparam PREAMBLE_X = 8'b01000111;
|
||||
localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block
|
||||
localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data
|
||||
localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block
|
||||
|
||||
reg [7:0] preamble_r;
|
||||
reg channel_status_bit_r;
|
||||
|
||||
always @ *
|
||||
begin
|
||||
@@ -168,13 +171,30 @@ begin
|
||||
// Left Channel (but not start of block)?
|
||||
else
|
||||
preamble_r = PREAMBLE_X; // X(M)
|
||||
|
||||
if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted
|
||||
channel_status_bit_r = 1'b1;
|
||||
else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media
|
||||
channel_status_bit_r = 1'b1;
|
||||
else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r)
|
||||
channel_status_bit_r = 1'b1;
|
||||
else
|
||||
channel_status_bit_r = 1'b0; // everything else defaults to 0
|
||||
end
|
||||
|
||||
always @ (posedge rst_i or posedge clk_i )
|
||||
if (rst_i == 1'b1)
|
||||
preamble_q <= 8'h00;
|
||||
else if (load_subframe_q)
|
||||
preamble_q <= preamble_r;
|
||||
begin
|
||||
if (rst_i == 1'b1)
|
||||
begin
|
||||
preamble_q <= 8'h00;
|
||||
channel_status_bit_q <= 1'b0;
|
||||
end
|
||||
else if (load_subframe_q)
|
||||
begin
|
||||
preamble_q <= preamble_r;
|
||||
channel_status_bit_q <= channel_status_bit_r;
|
||||
end
|
||||
end
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Parity Counter
|
||||
|
||||
@@ -3,12 +3,16 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
|
||||
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
|
||||
@@ -20,9 +24,11 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ]
|
||||
|
||||
@@ -218,6 +218,7 @@ set_location_assignment PIN_W20 -to SW[3]
|
||||
|
||||
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
|
||||
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
|
||||
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c
|
||||
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
|
||||
|
||||
|
||||
@@ -1,9 +1,10 @@
|
||||
# Specify root clocks
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
|
||||
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
|
||||
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
|
||||
create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
@@ -14,6 +15,7 @@ set_clock_groups -exclusive \
|
||||
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
|
||||
-group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \
|
||||
-group [get_clocks { spi_sck}] \
|
||||
-group [get_clocks { hdmi_sck}] \
|
||||
-group [get_clocks { *|h2f_user0_clk}] \
|
||||
-group [get_clocks { FPGA_CLK1_50 }] \
|
||||
-group [get_clocks { FPGA_CLK2_50 }] \
|
||||
@@ -21,29 +23,30 @@ set_clock_groups -exclusive \
|
||||
|
||||
set_false_path -from [get_ports {KEY*}]
|
||||
set_false_path -from [get_ports {BTN_*}]
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
|
||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
set_false_path -to {cfg[*]}
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
|
||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
set_false_path -to {cfg[*]}
|
||||
set_false_path -from {cfg[*]}
|
||||
set_false_path -from {VSET[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {width[*] height[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {hdmi_width[*] hdmi_height[*]}
|
||||
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||
set_false_path -to {*_osd|v_cnt*}
|
||||
set_false_path -to {*_osd|v_osd_start*}
|
||||
set_false_path -to {*_osd|v_info_start*}
|
||||
set_false_path -to {*_osd|h_osd_start*}
|
||||
|
||||
set_false_path -to {*_osd|v_cnt*}
|
||||
set_false_path -to {*_osd|v_osd_start*}
|
||||
set_false_path -to {*_osd|v_info_start*}
|
||||
set_false_path -to {*_osd|h_osd_start*}
|
||||
set_false_path -from {*_osd|v_osd_start*}
|
||||
set_false_path -from {*_osd|v_info_start*}
|
||||
set_false_path -from {*_osd|h_osd_start*}
|
||||
set_false_path -from {*_osd|rot*}
|
||||
set_false_path -from {*_osd|dsp_width*}
|
||||
set_false_path -to {*_osd|half}
|
||||
set_false_path -to {*_osd|half}
|
||||
|
||||
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
|
||||
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
|
||||
@@ -51,4 +54,18 @@ set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*]
|
||||
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
|
||||
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {aflt_* acx* acy* areset*}
|
||||
set_false_path -from {aflt_* acx* acy* areset* arc*}
|
||||
set_false_path -from {vs_line*}
|
||||
|
||||
set_false_path -from {ascal|o_ihsize*}
|
||||
set_false_path -from {ascal|o_ivsize*}
|
||||
set_false_path -from {ascal|o_format*}
|
||||
set_false_path -from {ascal|o_hdown}
|
||||
set_false_path -from {ascal|o_vdown}
|
||||
set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax*}
|
||||
set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*}
|
||||
set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
|
||||
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
|
||||
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
|
||||
|
||||
set_false_path -from {mcp23009|sd_cd}
|
||||
|
||||
479
sys/sys_top.v
479
sys/sys_top.v
@@ -19,18 +19,6 @@
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
`ifndef ARCADE_SYS
|
||||
`define USE_DDRAM
|
||||
`define USE_SDRAM
|
||||
`endif
|
||||
|
||||
`ifndef USE_DDRAM
|
||||
`ifdef USE_FB
|
||||
`define USE_DDRAM
|
||||
`endif
|
||||
`endif
|
||||
|
||||
|
||||
module sys_top
|
||||
(
|
||||
/////////// CLOCK //////////
|
||||
@@ -68,7 +56,7 @@ module sys_top
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE,
|
||||
|
||||
`ifdef DUAL_SDRAM
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
////////// SDR #2 //////////
|
||||
output [12:0] SDRAM2_A,
|
||||
inout [15:0] SDRAM2_DQ,
|
||||
@@ -139,20 +127,14 @@ module sys_top
|
||||
////////////////////// Secondary SD ///////////////////////////////////
|
||||
wire SD_CS, SD_CLK, SD_MOSI;
|
||||
|
||||
`ifdef ARCADE_SYS
|
||||
assign SD_CS = 1'bZ;
|
||||
assign SD_CLK = 1'bZ;
|
||||
assign SD_MOSI = 1'bZ;
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire sd_miso = SW[3] | SDIO_DAT[0];
|
||||
`else
|
||||
`ifndef DUAL_SDRAM
|
||||
wire sd_miso = SW[3] | SDIO_DAT[0];
|
||||
`else
|
||||
wire sd_miso = 1;
|
||||
`endif
|
||||
wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO;
|
||||
wire sd_miso = 1;
|
||||
`endif
|
||||
wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO;
|
||||
|
||||
`ifndef DUAL_SDRAM
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
assign SDIO_DAT[2:1]= 2'bZZ;
|
||||
assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS;
|
||||
assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK;
|
||||
@@ -175,7 +157,7 @@ wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
|
||||
wire led_u = ~led_user;
|
||||
wire led_locked;
|
||||
|
||||
`ifndef DUAL_SDRAM
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0;
|
||||
assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0;
|
||||
assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0;
|
||||
@@ -185,7 +167,7 @@ wire led_locked;
|
||||
assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
|
||||
|
||||
wire btn_r, btn_o, btn_u;
|
||||
`ifdef DUAL_SDRAM
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
assign {btn_r,btn_o,btn_u} = {mcp_btn[1],mcp_btn[2],mcp_btn[0]};
|
||||
`else
|
||||
assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]};
|
||||
@@ -233,7 +215,7 @@ end
|
||||
wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout};
|
||||
wire [31:0] gp_out;
|
||||
|
||||
wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future.
|
||||
wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future.
|
||||
wire io_wait;
|
||||
wire io_wide;
|
||||
wire [15:0] io_dout;
|
||||
@@ -243,7 +225,7 @@ wire io_ss0 = gp_outr[18];
|
||||
wire io_ss1 = gp_outr[19];
|
||||
wire io_ss2 = gp_outr[20];
|
||||
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
||||
`endif
|
||||
|
||||
@@ -268,7 +250,7 @@ always @(posedge clk_sys) begin
|
||||
gp_outd <= gp_out;
|
||||
end
|
||||
|
||||
`ifdef DUAL_SDRAM
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
wire [7:0] core_type = 'hA8; // generic core, dual SDRAM.
|
||||
`else
|
||||
wire [7:0] core_type = 'hA4; // generic core.
|
||||
@@ -287,10 +269,10 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
|
||||
reg [15:0] cfg;
|
||||
|
||||
reg cfg_set = 0;
|
||||
wire vga_fb = cfg[12];
|
||||
wire vga_fb = cfg[12] | vga_force_scaler;
|
||||
wire [1:0] hdmi_limited = {cfg[11],cfg[8]};
|
||||
|
||||
`ifdef DEBUG_NOHDMI
|
||||
`ifdef MISTER_DEBUG_NOHDMI
|
||||
wire direct_video = 1;
|
||||
`else
|
||||
wire direct_video = cfg[10];
|
||||
@@ -301,22 +283,23 @@ wire audio_96k = cfg[6];
|
||||
wire csync_en = cfg[3];
|
||||
wire ypbpr_en = cfg[5];
|
||||
wire io_osd_vga = io_ss1 & ~io_ss2;
|
||||
`ifndef DUAL_SDRAM
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire sog = cfg[9];
|
||||
wire vga_scaler = cfg[2];
|
||||
wire vga_scaler = cfg[2] | vga_force_scaler;
|
||||
`endif
|
||||
|
||||
reg cfg_custom_t = 0;
|
||||
reg [5:0] cfg_custom_p1;
|
||||
reg [31:0] cfg_custom_p2;
|
||||
|
||||
reg [4:0] vol_att = 0;
|
||||
reg [4:0] vol_att;
|
||||
initial vol_att = 5'b11111;
|
||||
|
||||
reg [6:0] coef_addr;
|
||||
reg [8:0] coef_addr;
|
||||
reg [8:0] coef_data;
|
||||
reg coef_wr = 0;
|
||||
|
||||
wire [7:0] ARX, ARY;
|
||||
wire[12:0] ARX, ARY;
|
||||
reg [11:0] VSET = 0, HSET = 0;
|
||||
reg FREESCALE = 0;
|
||||
reg [2:0] scaler_flt;
|
||||
@@ -337,6 +320,10 @@ reg [23:0] acy0 = -24'd6216759;
|
||||
reg [23:0] acy1 = 24'd6143386;
|
||||
reg [23:0] acy2 = -24'd2023767;
|
||||
reg areset = 0;
|
||||
reg [12:0] arc1x = 0;
|
||||
reg [12:0] arc1y = 0;
|
||||
reg [12:0] arc2x = 0;
|
||||
reg [12:0] arc2y = 0;
|
||||
|
||||
always@(posedge clk_sys) begin
|
||||
reg [7:0] cmd;
|
||||
@@ -349,6 +336,10 @@ always@(posedge clk_sys) begin
|
||||
old_strobe <= io_strobe;
|
||||
coef_wr <= 0;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
shadowmask_wr <= 0;
|
||||
`endif
|
||||
|
||||
if(~io_uio) begin
|
||||
has_cmd <= 0;
|
||||
cmd <= 0;
|
||||
@@ -376,6 +367,7 @@ always@(posedge clk_sys) begin
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cmd == 1) begin
|
||||
cfg <= io_din;
|
||||
cfg_set <= 1;
|
||||
@@ -383,7 +375,6 @@ always@(posedge clk_sys) begin
|
||||
end
|
||||
if(cmd == 'h20) begin
|
||||
cfg_set <= 0;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt<8) begin
|
||||
case(cnt[2:0])
|
||||
0: if(WIDTH != io_din[11:0]) WIDTH <= io_din[11:0];
|
||||
@@ -395,7 +386,7 @@ always@(posedge clk_sys) begin
|
||||
6: if(VS != io_din[11:0]) VS <= io_din[11:0];
|
||||
7: if(VBP != io_din[11:0]) VBP <= io_din[11:0];
|
||||
endcase
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
if(cnt == 1) begin
|
||||
cfg_custom_p1 <= 0;
|
||||
cfg_custom_p2 <= 0;
|
||||
@@ -415,7 +406,6 @@ always@(posedge clk_sys) begin
|
||||
end
|
||||
end
|
||||
if(cmd == 'h2F) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt[3:0])
|
||||
0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]};
|
||||
1: LFB_BASE[15:0] <= io_din[15:0];
|
||||
@@ -426,17 +416,20 @@ always@(posedge clk_sys) begin
|
||||
6: LFB_HMAX <= io_din[11:0];
|
||||
7: LFB_VMIN <= io_din[11:0];
|
||||
8: LFB_VMAX <= io_din[11:0];
|
||||
9: LFB_STRIDE <= io_din[13:0];
|
||||
endcase
|
||||
end
|
||||
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
|
||||
if(cmd == 'h26) vol_att <= io_din[4:0];
|
||||
if(cmd == 'h27) VSET <= io_din[11:0];
|
||||
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
|
||||
if(cmd == 'h2A) begin
|
||||
if(cnt[0]) {coef_wr,coef_data} <= {1'b1,io_din[8:0]};
|
||||
else coef_addr <= io_din[8:0];
|
||||
end
|
||||
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
|
||||
if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
|
||||
if(cmd == 'h38) vs_line <= io_din[11:0];
|
||||
if(cmd == 'h39) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt[3:0])
|
||||
0: acx_att <= io_din[4:0];
|
||||
1: aflt_rate[15:0] <= io_din;
|
||||
@@ -455,6 +448,17 @@ always@(posedge clk_sys) begin
|
||||
14: acy2[23:16] <= io_din[7:0];
|
||||
endcase
|
||||
end
|
||||
if(cmd == 'h3A) begin
|
||||
case(cnt[3:0])
|
||||
0: arc1x <= io_din[12:0];
|
||||
1: arc1y <= io_din[12:0];
|
||||
2: arc2x <= io_din[12:0];
|
||||
3: arc2y <= io_din[12:0];
|
||||
endcase
|
||||
end
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
if(cmd == 'h3E) {shadowmask_wr,shadowmask_data} <= {1'b1, io_din};
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
@@ -467,9 +471,7 @@ end
|
||||
|
||||
cyclonev_hps_interface_peripheral_uart uart
|
||||
(
|
||||
.ri(0)
|
||||
`ifndef ARCADE_SYS
|
||||
,
|
||||
.ri(0),
|
||||
.dsr(uart_dsr),
|
||||
.dcd(uart_dsr),
|
||||
.dtr(uart_dtr),
|
||||
@@ -478,7 +480,6 @@ cyclonev_hps_interface_peripheral_uart uart
|
||||
.rts(uart_rts),
|
||||
.rxd(uart_rxd),
|
||||
.txd(uart_txd)
|
||||
`endif
|
||||
);
|
||||
|
||||
wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
|
||||
@@ -533,7 +534,6 @@ sysmem_lite sysmem
|
||||
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
|
||||
.reset_hps_cold_req(btn_r),
|
||||
|
||||
`ifdef USE_DDRAM
|
||||
//64-bit DDR3 RAM access
|
||||
.ram1_clk(ram_clk),
|
||||
.ram1_address(ram_address),
|
||||
@@ -545,7 +545,6 @@ sysmem_lite sysmem
|
||||
.ram1_writedata(ram_writedata),
|
||||
.ram1_byteenable(ram_byteenable),
|
||||
.ram1_write(ram_write),
|
||||
`endif
|
||||
|
||||
//64-bit DDR3 RAM access
|
||||
.ram2_clk(clk_audio),
|
||||
@@ -626,17 +625,23 @@ wire [15:0] vbuf_byteenable;
|
||||
wire vbuf_write;
|
||||
|
||||
wire [23:0] hdmi_data;
|
||||
wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl;
|
||||
wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd;
|
||||
wire freeze;
|
||||
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire clk_hdmi = hdmi_clk_out;
|
||||
|
||||
ascal
|
||||
#(
|
||||
.RAMBASE(32'h20000000),
|
||||
`ifndef USE_FB
|
||||
`ifndef MISTER_FB
|
||||
.PALETTE2("false"),
|
||||
`else
|
||||
`ifndef MISTER_FB_PALETTE
|
||||
.PALETTE2("false"),
|
||||
`endif
|
||||
`endif
|
||||
.FRAC(6),
|
||||
.N_DW(128),
|
||||
.N_AW(28)
|
||||
)
|
||||
@@ -644,7 +649,7 @@ ascal
|
||||
(
|
||||
.reset_na (~reset_req),
|
||||
.run (1),
|
||||
.freeze (0),
|
||||
.freeze (freeze),
|
||||
|
||||
.i_clk (clk_ihdmi),
|
||||
.i_ce (ce_hpix),
|
||||
@@ -670,6 +675,7 @@ ascal
|
||||
.o_vs (hdmi_vs),
|
||||
.o_de (hdmi_de),
|
||||
.o_vbl (hdmi_vbl),
|
||||
.o_brd (hdmi_brd),
|
||||
.o_lltune (lltune),
|
||||
.htotal (WIDTH + HFP + HBP + HS),
|
||||
.hsstart (WIDTH + HFP),
|
||||
@@ -695,13 +701,15 @@ ascal
|
||||
.pal1_a (pal_a),
|
||||
.pal1_wr (pal_wr),
|
||||
|
||||
`ifdef USE_FB
|
||||
.pal2_clk (fb_pal_clk),
|
||||
.pal2_dw (fb_pal_d),
|
||||
.pal2_dr (fb_pal_q),
|
||||
.pal2_a (fb_pal_a),
|
||||
.pal2_wr (fb_pal_wr),
|
||||
.pal_n (fb_en),
|
||||
`ifdef MISTER_FB
|
||||
`ifdef MISTER_FB_PALETTE
|
||||
.pal2_clk (fb_pal_clk),
|
||||
.pal2_dw (fb_pal_d),
|
||||
.pal2_dr (fb_pal_q),
|
||||
.pal2_a (fb_pal_a),
|
||||
.pal2_wr (fb_pal_wr),
|
||||
.pal_n (fb_en),
|
||||
`endif
|
||||
`endif
|
||||
|
||||
.o_fb_ena (FB_EN),
|
||||
@@ -734,6 +742,7 @@ reg [11:0] LFB_HMAX = 0;
|
||||
reg [11:0] LFB_VMIN = 0;
|
||||
reg [11:0] LFB_VMAX = 0;
|
||||
reg [31:0] LFB_BASE = 0;
|
||||
reg [13:0] LFB_STRIDE = 0;
|
||||
|
||||
reg FB_EN = 0;
|
||||
reg [5:0] FB_FMT = 0;
|
||||
@@ -749,7 +758,7 @@ always @(posedge clk_sys) begin
|
||||
FB_WIDTH <= LFB_WIDTH;
|
||||
FB_HEIGHT <= LFB_HEIGHT;
|
||||
FB_BASE <= LFB_BASE;
|
||||
FB_STRIDE <= 0;
|
||||
FB_STRIDE <= LFB_STRIDE;
|
||||
end
|
||||
else begin
|
||||
FB_FMT <= fb_fmt;
|
||||
@@ -760,59 +769,131 @@ always @(posedge clk_sys) begin
|
||||
end
|
||||
end
|
||||
|
||||
`ifdef USE_FB
|
||||
`ifdef MISTER_FB
|
||||
reg fb_vbl;
|
||||
always @(posedge clk_vid) fb_vbl <= hdmi_vbl;
|
||||
`endif
|
||||
|
||||
reg ar_md_start;
|
||||
wire ar_md_busy;
|
||||
reg [11:0] ar_md_mul1, ar_md_mul2, ar_md_div;
|
||||
wire [11:0] ar_md_res;
|
||||
|
||||
sys_umuldiv #(12,12,12) ar_muldiv
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.start(ar_md_start),
|
||||
.busy(ar_md_busy),
|
||||
|
||||
.mul1(ar_md_mul1),
|
||||
.mul2(ar_md_mul2),
|
||||
.div(ar_md_div),
|
||||
.result(ar_md_res)
|
||||
);
|
||||
|
||||
reg [11:0] hmin;
|
||||
reg [11:0] hmax;
|
||||
reg [11:0] vmin;
|
||||
reg [11:0] vmax;
|
||||
reg [11:0] hdmi_height;
|
||||
reg [11:0] hdmi_width;
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
reg [31:0] wcalc;
|
||||
reg [31:0] hcalc;
|
||||
reg [11:0] hmini,hmaxi,vmini,vmaxi;
|
||||
reg [11:0] wcalc,videow,arx;
|
||||
reg [11:0] hcalc,videoh,ary;
|
||||
reg [2:0] state;
|
||||
reg [11:0] videow;
|
||||
reg [11:0] videoh;
|
||||
reg [11:0] height;
|
||||
reg [11:0] width;
|
||||
reg xy;
|
||||
|
||||
height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
|
||||
width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH;
|
||||
hdmi_height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
|
||||
hdmi_width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH;
|
||||
|
||||
if(!ARY) begin
|
||||
if(ARX == 1) begin
|
||||
arx <= arc1x[11:0];
|
||||
ary <= arc1y[11:0];
|
||||
xy <= arc1x[12] | arc1y[12];
|
||||
end
|
||||
else if(ARX == 2) begin
|
||||
arx <= arc2x[11:0];
|
||||
ary <= arc2y[11:0];
|
||||
xy <= arc2x[12] | arc2y[12];
|
||||
end
|
||||
else begin
|
||||
arx <= 0;
|
||||
ary <= 0;
|
||||
xy <= 0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
arx <= ARX[11:0];
|
||||
ary <= ARY[11:0];
|
||||
xy <= ARX[12] | ARY[12];
|
||||
end
|
||||
|
||||
ar_md_start <= 0;
|
||||
state <= state + 1'd1;
|
||||
case(state)
|
||||
0: if(LFB_EN) begin
|
||||
hmin <= LFB_HMIN;
|
||||
vmin <= LFB_VMIN;
|
||||
hmax <= LFB_HMAX;
|
||||
vmax <= LFB_VMAX;
|
||||
state<= 0;
|
||||
hmini <= LFB_HMIN;
|
||||
vmini <= LFB_VMIN;
|
||||
hmaxi <= LFB_HMAX;
|
||||
vmaxi <= LFB_VMAX;
|
||||
state <= 0;
|
||||
end
|
||||
else if(ARX && ARY && !FREESCALE) begin
|
||||
wcalc <= (height*ARX)/ARY;
|
||||
hcalc <= (width*ARY)/ARX;
|
||||
else if(FREESCALE || !arx || !ary) begin
|
||||
wcalc <= hdmi_width;
|
||||
hcalc <= hdmi_height;
|
||||
state <= 6;
|
||||
end
|
||||
else begin
|
||||
wcalc <= width;
|
||||
hcalc <= height;
|
||||
else if(xy) begin
|
||||
wcalc <= arx;
|
||||
hcalc <= ary;
|
||||
state <= 6;
|
||||
end
|
||||
|
||||
1: begin
|
||||
ar_md_mul1 <= hdmi_height;
|
||||
ar_md_mul2 <= arx;
|
||||
ar_md_div <= ary;
|
||||
ar_md_start<= 1;
|
||||
end
|
||||
2: begin
|
||||
wcalc <= ar_md_res;
|
||||
if(ar_md_start | ar_md_busy) state <= 2;
|
||||
end
|
||||
|
||||
3: begin
|
||||
ar_md_mul1 <= hdmi_width;
|
||||
ar_md_mul2 <= ary;
|
||||
ar_md_div <= arx;
|
||||
ar_md_start<= 1;
|
||||
end
|
||||
4: begin
|
||||
hcalc <= ar_md_res;
|
||||
if(ar_md_start | ar_md_busy) state <= 4;
|
||||
end
|
||||
|
||||
6: begin
|
||||
videow <= (wcalc > width) ? width : wcalc[11:0];
|
||||
videoh <= (hcalc > height) ? height : hcalc[11:0];
|
||||
videow <= (wcalc > hdmi_width) ? hdmi_width : wcalc[11:0];
|
||||
videoh <= (hcalc > hdmi_height) ? hdmi_height : hcalc[11:0];
|
||||
end
|
||||
|
||||
7: begin
|
||||
hmin <= ((WIDTH - videow)>>1);
|
||||
hmax <= ((WIDTH - videow)>>1) + videow - 1'd1;
|
||||
vmin <= ((HEIGHT - videoh)>>1);
|
||||
vmax <= ((HEIGHT - videoh)>>1) + videoh - 1'd1;
|
||||
hmini <= ((WIDTH - videow)>>1);
|
||||
hmaxi <= ((WIDTH - videow)>>1) + videow - 1'd1;
|
||||
vmini <= ((HEIGHT - videoh)>>1);
|
||||
vmaxi <= ((HEIGHT - videoh)>>1) + videoh - 1'd1;
|
||||
end
|
||||
endcase
|
||||
|
||||
hmin <= hmini;
|
||||
hmax <= hmaxi;
|
||||
vmin <= vmini;
|
||||
vmax <= vmaxi;
|
||||
end
|
||||
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire [15:0] lltune;
|
||||
pll_hdmi_adj pll_hdmi_adj
|
||||
(
|
||||
@@ -855,7 +936,7 @@ end
|
||||
|
||||
|
||||
///////////////////////// HDMI output /////////////////////////////////
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire hdmi_clk_out;
|
||||
pll_hdmi pll_hdmi
|
||||
(
|
||||
@@ -887,7 +968,7 @@ reg adj_write;
|
||||
reg [5:0] adj_address;
|
||||
reg [31:0] adj_data;
|
||||
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
pll_cfg pll_cfg
|
||||
(
|
||||
.mgmt_clk(FPGA_CLK1_50),
|
||||
@@ -964,35 +1045,56 @@ hdmi_config hdmi_config
|
||||
.ypbpr(ypbpr_en & direct_video)
|
||||
);
|
||||
|
||||
`ifndef DEBUG_NOHDMI
|
||||
wire [23:0] hdmi_data_sl;
|
||||
wire hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl;
|
||||
assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ;
|
||||
assign HDMI_I2C_SDA = hdmi_sda_en ? 1'b0 : 1'bZ;
|
||||
|
||||
`ifdef USE_FB
|
||||
wire hdmi_scl_en, hdmi_sda_en;
|
||||
cyclonev_hps_interface_peripheral_i2c hdmi_i2c
|
||||
(
|
||||
.out_clk(hdmi_scl_en),
|
||||
.scl(HDMI_I2C_SCL),
|
||||
.out_data(hdmi_sda_en),
|
||||
.sda(HDMI_I2C_SDA)
|
||||
);
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
|
||||
`ifdef MISTER_FB
|
||||
reg dis_output;
|
||||
always @(posedge clk_hdmi) begin
|
||||
reg dis;
|
||||
dis <= fb_force_blank;
|
||||
dis <= fb_force_blank & ~LFB_EN;
|
||||
dis_output <= dis;
|
||||
end
|
||||
`else
|
||||
wire dis_output = 0;
|
||||
`endif
|
||||
|
||||
scanlines #(1) HDMI_scanlines
|
||||
wire [23:0] hdmi_data_mask;
|
||||
wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
|
||||
|
||||
reg [15:0] shadowmask_data;
|
||||
reg shadowmask_wr = 0;
|
||||
|
||||
shadowmask HDMI_shadowmask
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.cmd_wr(shadowmask_wr),
|
||||
.cmd_in(shadowmask_data),
|
||||
|
||||
.scanlines(scanlines),
|
||||
.din(dis_output ? 24'd0 : hdmi_data),
|
||||
.hs_in(hdmi_hs),
|
||||
.vs_in(hdmi_vs),
|
||||
.de_in(hdmi_de),
|
||||
|
||||
.dout(hdmi_data_sl),
|
||||
.hs_out(hdmi_hs_sl),
|
||||
.vs_out(hdmi_vs_sl),
|
||||
.de_out(hdmi_de_sl)
|
||||
.brd_in(hdmi_brd),
|
||||
.enable(~LFB_EN),
|
||||
|
||||
.dout(hdmi_data_mask),
|
||||
.hs_out(hdmi_hs_mask),
|
||||
.vs_out(hdmi_vs_mask),
|
||||
.de_out(hdmi_de_mask)
|
||||
);
|
||||
|
||||
wire [23:0] hdmi_data_osd;
|
||||
@@ -1007,19 +1109,15 @@ osd hdmi_osd
|
||||
.io_din(io_din),
|
||||
|
||||
.clk_video(clk_hdmi),
|
||||
.din(hdmi_data_sl),
|
||||
.hs_in(hdmi_hs_sl),
|
||||
.vs_in(hdmi_vs_sl),
|
||||
.de_in(hdmi_de_sl),
|
||||
.din(hdmi_data_mask),
|
||||
.hs_in(hdmi_hs_mask),
|
||||
.vs_in(hdmi_vs_mask),
|
||||
.de_in(hdmi_de_mask),
|
||||
|
||||
.dout(hdmi_data_osd),
|
||||
.hs_out(hdmi_hs_osd),
|
||||
.vs_out(hdmi_vs_osd),
|
||||
.de_out(hdmi_de_osd)
|
||||
`ifndef ARCADE_SYS
|
||||
,
|
||||
.osd_status(osd_status)
|
||||
`endif
|
||||
);
|
||||
`endif
|
||||
|
||||
@@ -1068,7 +1166,7 @@ always @(posedge clk_vid) begin
|
||||
end
|
||||
|
||||
wire hdmi_tx_clk;
|
||||
`ifndef DEBUG_NOHDMI
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
cyclonev_clkselect hdmi_clk_sw
|
||||
(
|
||||
.clkselect({1'b1, ~vga_fb & direct_video}),
|
||||
@@ -1158,6 +1256,7 @@ osd vga_osd
|
||||
.io_osd(io_osd_vga),
|
||||
.io_strobe(io_strobe),
|
||||
.io_din(io_din),
|
||||
.osd_status(osd_status),
|
||||
|
||||
.clk_video(clk_vid),
|
||||
.din(vga_data_sl),
|
||||
@@ -1173,25 +1272,46 @@ osd vga_osd
|
||||
wire vga_cs_osd;
|
||||
csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||
|
||||
`ifndef DUAL_SDRAM
|
||||
wire [23:0] vga_o;
|
||||
vga_out vga_out
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire [23:0] vgas_o;
|
||||
wire vgas_hs, vgas_vs, vgas_cs;
|
||||
vga_out vga_scaler_out
|
||||
(
|
||||
.ypbpr_full(0),
|
||||
.clk(clk_hdmi),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.dout(vga_o),
|
||||
.din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd)
|
||||
.hsync(hdmi_hs_osd),
|
||||
.vsync(hdmi_vs_osd),
|
||||
.csync(hdmi_cs_osd),
|
||||
.dout(vgas_o),
|
||||
.din({24{hdmi_de_osd}} & hdmi_data_osd),
|
||||
.hsync_o(vgas_hs),
|
||||
.vsync_o(vgas_vs),
|
||||
.csync_o(vgas_cs)
|
||||
);
|
||||
|
||||
wire vs1 = (vga_fb | vga_scaler) ? hdmi_vs_osd : vga_vs_osd;
|
||||
wire hs1 = (vga_fb | vga_scaler) ? hdmi_hs_osd : vga_hs_osd;
|
||||
wire cs1 = (vga_fb | vga_scaler) ? hdmi_cs_osd : vga_cs_osd;
|
||||
wire [23:0] vga_o;
|
||||
wire vga_hs, vga_vs, vga_cs;
|
||||
vga_out vga_out
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.dout(vga_o),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(vga_hs),
|
||||
.vsync_o(vga_vs),
|
||||
.csync_o(vga_cs)
|
||||
);
|
||||
|
||||
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vs1;
|
||||
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~cs1 : ~hs1;
|
||||
assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[23:18];
|
||||
assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[15:10];
|
||||
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
|
||||
wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs;
|
||||
|
||||
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ~vgas_vs : ~vga_vs) | csync_en;
|
||||
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : (vga_fb | vga_scaler) ? (csync_en ? ~vgas_cs : ~vgas_hs) : (csync_en ? ~vga_cs : ~vga_hs);
|
||||
assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : vga_o[23:18];
|
||||
assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : vga_o[15:10];
|
||||
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : vga_o[7:2] ;
|
||||
`endif
|
||||
|
||||
reg video_sync = 0;
|
||||
@@ -1223,7 +1343,7 @@ end
|
||||
|
||||
assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;
|
||||
|
||||
`ifndef DUAL_SDRAM
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire analog_l, analog_r;
|
||||
|
||||
assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif;
|
||||
@@ -1270,7 +1390,7 @@ audio_out audio_out
|
||||
.i2s_bclk(HDMI_SCLK),
|
||||
.i2s_lrclk(HDMI_LRCLK),
|
||||
.i2s_data(HDMI_I2S),
|
||||
`ifndef DUAL_SDRAM
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
.dac_l(analog_l),
|
||||
.dac_r(analog_r),
|
||||
`endif
|
||||
@@ -1335,19 +1455,18 @@ wire [7:0] r_out, g_out, b_out, hr_out, hg_out, hb_out;
|
||||
wire vs_fix, hs_fix, de_emu, vs_emu, hs_emu, f1;
|
||||
wire hvs_fix, hhs_fix, hde_emu;
|
||||
wire clk_vid, ce_pix, clk_ihdmi, ce_hpix;
|
||||
wire vga_force_scaler;
|
||||
|
||||
`ifdef USE_DDRAM
|
||||
wire ram_clk;
|
||||
wire [28:0] ram_address;
|
||||
wire [7:0] ram_burstcount;
|
||||
wire ram_waitrequest;
|
||||
wire [63:0] ram_readdata;
|
||||
wire ram_readdatavalid;
|
||||
wire ram_read;
|
||||
wire [63:0] ram_writedata;
|
||||
wire [7:0] ram_byteenable;
|
||||
wire ram_write;
|
||||
`endif
|
||||
wire ram_clk;
|
||||
wire [28:0] ram_address;
|
||||
wire [7:0] ram_burstcount;
|
||||
wire ram_waitrequest;
|
||||
wire [63:0] ram_readdata;
|
||||
wire ram_readdatavalid;
|
||||
wire ram_read;
|
||||
wire [63:0] ram_writedata;
|
||||
wire [7:0] ram_byteenable;
|
||||
wire ram_write;
|
||||
|
||||
wire led_user;
|
||||
wire [1:0] led_power;
|
||||
@@ -1359,32 +1478,23 @@ sync_fix sync_h(clk_vid, hs_emu, hs_fix);
|
||||
|
||||
wire [6:0] user_out, user_in;
|
||||
|
||||
`ifndef USE_SDRAM
|
||||
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39'bZ};
|
||||
`endif
|
||||
|
||||
assign clk_ihdmi= clk_vid;
|
||||
assign ce_hpix = ce_pix;
|
||||
assign hr_out = r_out;
|
||||
assign hg_out = g_out;
|
||||
assign hb_out = b_out;
|
||||
assign hhs_fix = hs_fix;
|
||||
assign hvs_fix = vs_fix;
|
||||
assign hde_emu = de_emu;
|
||||
assign hr_out = vga_data_sl[23:16];
|
||||
assign hg_out = vga_data_sl[15:8];
|
||||
assign hb_out = vga_data_sl[7:0];
|
||||
assign hhs_fix = vga_hs_sl;
|
||||
assign hvs_fix = vga_vs_sl;
|
||||
assign hde_emu = vga_de_sl;
|
||||
|
||||
`ifdef ARCADE_SYS
|
||||
assign audio_mix = 0;
|
||||
assign {ADC_SCK, ADC_SDI, ADC_CONVST} = 0;
|
||||
assign btn = 0;
|
||||
`else
|
||||
wire uart_dtr;
|
||||
wire uart_dsr;
|
||||
wire uart_cts;
|
||||
wire uart_rts;
|
||||
wire uart_rxd;
|
||||
wire uart_txd;
|
||||
wire osd_status;
|
||||
`endif
|
||||
wire uart_dtr;
|
||||
wire uart_dsr;
|
||||
wire uart_cts;
|
||||
wire uart_rts;
|
||||
wire uart_rxd;
|
||||
wire uart_txd;
|
||||
|
||||
wire osd_status;
|
||||
|
||||
wire fb_en;
|
||||
wire [4:0] fb_fmt;
|
||||
@@ -1393,13 +1503,16 @@ wire [11:0] fb_height;
|
||||
wire [31:0] fb_base;
|
||||
wire [13:0] fb_stride;
|
||||
|
||||
`ifdef USE_FB
|
||||
wire fb_pal_clk;
|
||||
wire [7:0] fb_pal_a;
|
||||
wire [23:0] fb_pal_d;
|
||||
wire [23:0] fb_pal_q;
|
||||
wire fb_pal_wr;
|
||||
wire fb_force_blank;
|
||||
|
||||
`ifdef MISTER_FB
|
||||
`ifdef MISTER_FB_PALETTE
|
||||
wire fb_pal_clk;
|
||||
wire [7:0] fb_pal_a;
|
||||
wire [23:0] fb_pal_d;
|
||||
wire [23:0] fb_pal_q;
|
||||
wire fb_pal_wr;
|
||||
`endif
|
||||
wire fb_force_blank;
|
||||
`else
|
||||
assign fb_en = 0;
|
||||
assign fb_fmt = 0;
|
||||
@@ -1413,7 +1526,10 @@ emu emu
|
||||
(
|
||||
.CLK_50M(FPGA_CLK2_50),
|
||||
.RESET(reset),
|
||||
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_ihdmi, ce_hpix, hde_emu, hhs_fix, hvs_fix, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
|
||||
.HPS_BUS({scanlines,f1, HDMI_TX_VS,
|
||||
clk_100m, clk_ihdmi,
|
||||
ce_hpix, hde_emu, hhs_fix, hvs_fix,
|
||||
io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
|
||||
|
||||
.VGA_R(r_out),
|
||||
.VGA_G(g_out),
|
||||
@@ -1422,6 +1538,11 @@ emu emu
|
||||
.VGA_VS(vs_emu),
|
||||
.VGA_DE(de_emu),
|
||||
.VGA_F1(f1),
|
||||
.VGA_SCALER(vga_force_scaler),
|
||||
|
||||
.HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width),
|
||||
.HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height),
|
||||
.HDMI_FREEZE(freeze),
|
||||
|
||||
.CLK_VIDEO(clk_vid),
|
||||
.CE_PIXEL(ce_pix),
|
||||
@@ -1429,7 +1550,7 @@ emu emu
|
||||
.VIDEO_ARX(ARX),
|
||||
.VIDEO_ARY(ARY),
|
||||
|
||||
`ifdef USE_FB
|
||||
`ifdef MISTER_FB
|
||||
.FB_EN(fb_en),
|
||||
.FB_FORMAT(fb_fmt),
|
||||
.FB_WIDTH(fb_width),
|
||||
@@ -1440,11 +1561,14 @@ emu emu
|
||||
.FB_LL(lowlat),
|
||||
.FB_FORCE_BLANK(fb_force_blank),
|
||||
|
||||
`ifdef MISTER_FB_PALETTE
|
||||
.FB_PAL_CLK (fb_pal_clk),
|
||||
.FB_PAL_ADDR(fb_pal_a),
|
||||
.FB_PAL_DOUT(fb_pal_d),
|
||||
.FB_PAL_DIN (fb_pal_q),
|
||||
.FB_PAL_WR (fb_pal_wr),
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
.LED_USER(led_user),
|
||||
@@ -1455,13 +1579,10 @@ emu emu
|
||||
.AUDIO_L(audio_l),
|
||||
.AUDIO_R(audio_r),
|
||||
.AUDIO_S(audio_s),
|
||||
|
||||
`ifndef ARCADE_SYS
|
||||
.AUDIO_MIX(audio_mix),
|
||||
.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
|
||||
`endif
|
||||
|
||||
`ifdef USE_DDRAM
|
||||
.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
|
||||
|
||||
.DDRAM_CLK(ram_clk),
|
||||
.DDRAM_ADDR(ram_address),
|
||||
.DDRAM_BURSTCNT(ram_burstcount),
|
||||
@@ -1472,9 +1593,7 @@ emu emu
|
||||
.DDRAM_DIN(ram_writedata),
|
||||
.DDRAM_BE(ram_byteenable),
|
||||
.DDRAM_WE(ram_write),
|
||||
`endif
|
||||
|
||||
`ifdef USE_SDRAM
|
||||
.SDRAM_DQ(SDRAM_DQ),
|
||||
.SDRAM_A(SDRAM_A),
|
||||
.SDRAM_DQML(SDRAM_DQML),
|
||||
@@ -1486,9 +1605,8 @@ emu emu
|
||||
.SDRAM_nCAS(SDRAM_nCAS),
|
||||
.SDRAM_CLK(SDRAM_CLK),
|
||||
.SDRAM_CKE(SDRAM_CKE),
|
||||
`endif
|
||||
|
||||
`ifdef DUAL_SDRAM
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
.SDRAM2_DQ(SDRAM2_DQ),
|
||||
.SDRAM2_A(SDRAM2_A),
|
||||
.SDRAM2_BA(SDRAM2_BA),
|
||||
@@ -1500,14 +1618,14 @@ emu emu
|
||||
.SDRAM2_EN(SW[3]),
|
||||
`endif
|
||||
|
||||
`ifndef ARCADE_SYS
|
||||
.BUTTONS(btn),
|
||||
.OSD_STATUS(osd_status),
|
||||
|
||||
.SD_SCK(SD_CLK),
|
||||
.SD_MOSI(SD_MOSI),
|
||||
.SD_MISO(SD_MISO),
|
||||
.SD_CS(SD_CS),
|
||||
`ifdef DUAL_SDRAM
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
.SD_CD(mcp_sdcd),
|
||||
`else
|
||||
.SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))),
|
||||
@@ -1519,7 +1637,6 @@ emu emu
|
||||
.UART_TXD(uart_rxd),
|
||||
.UART_DTR(uart_dsr),
|
||||
.UART_DSR(uart_dtr),
|
||||
`endif
|
||||
|
||||
.USER_OUT(user_out),
|
||||
.USER_IN(user_in)
|
||||
|
||||
195
sys/sysmem.sv
195
sys/sysmem.sv
@@ -44,41 +44,182 @@ module sysmem_lite
|
||||
|
||||
assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// f2sdram_safe_terminator_ram1 ////
|
||||
////////////////////////////////////////////////////////
|
||||
wire [28:0] f2h_ram1_address;
|
||||
wire [7:0] f2h_ram1_burstcount;
|
||||
wire f2h_ram1_waitrequest;
|
||||
wire [63:0] f2h_ram1_readdata;
|
||||
wire f2h_ram1_readdatavalid;
|
||||
wire f2h_ram1_read;
|
||||
wire [63:0] f2h_ram1_writedata;
|
||||
wire [7:0] f2h_ram1_byteenable;
|
||||
wire f2h_ram1_write;
|
||||
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_0 = 1'b1;
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_1 = 1'b1;
|
||||
always @(posedge ram1_clk) begin
|
||||
ram1_reset_0 <= reset_out;
|
||||
ram1_reset_1 <= ram1_reset_0;
|
||||
end
|
||||
|
||||
f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram1
|
||||
(
|
||||
.clk (ram1_clk),
|
||||
.rst_req_sync (ram1_reset_1),
|
||||
|
||||
.waitrequest_slave (ram1_waitrequest),
|
||||
.burstcount_slave (ram1_burstcount),
|
||||
.address_slave (ram1_address),
|
||||
.readdata_slave (ram1_readdata),
|
||||
.readdatavalid_slave (ram1_readdatavalid),
|
||||
.read_slave (ram1_read),
|
||||
.writedata_slave (ram1_writedata),
|
||||
.byteenable_slave (ram1_byteenable),
|
||||
.write_slave (ram1_write),
|
||||
|
||||
.waitrequest_master (f2h_ram1_waitrequest),
|
||||
.burstcount_master (f2h_ram1_burstcount),
|
||||
.address_master (f2h_ram1_address),
|
||||
.readdata_master (f2h_ram1_readdata),
|
||||
.readdatavalid_master (f2h_ram1_readdatavalid),
|
||||
.read_master (f2h_ram1_read),
|
||||
.writedata_master (f2h_ram1_writedata),
|
||||
.byteenable_master (f2h_ram1_byteenable),
|
||||
.write_master (f2h_ram1_write)
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// f2sdram_safe_terminator_ram2 ////
|
||||
////////////////////////////////////////////////////////
|
||||
wire [28:0] f2h_ram2_address;
|
||||
wire [7:0] f2h_ram2_burstcount;
|
||||
wire f2h_ram2_waitrequest;
|
||||
wire [63:0] f2h_ram2_readdata;
|
||||
wire f2h_ram2_readdatavalid;
|
||||
wire f2h_ram2_read;
|
||||
wire [63:0] f2h_ram2_writedata;
|
||||
wire [7:0] f2h_ram2_byteenable;
|
||||
wire f2h_ram2_write;
|
||||
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_0 = 1'b1;
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_1 = 1'b1;
|
||||
always @(posedge ram2_clk) begin
|
||||
ram2_reset_0 <= reset_out;
|
||||
ram2_reset_1 <= ram2_reset_0;
|
||||
end
|
||||
|
||||
f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram2
|
||||
(
|
||||
.clk (ram2_clk),
|
||||
.rst_req_sync (ram2_reset_1),
|
||||
|
||||
.waitrequest_slave (ram2_waitrequest),
|
||||
.burstcount_slave (ram2_burstcount),
|
||||
.address_slave (ram2_address),
|
||||
.readdata_slave (ram2_readdata),
|
||||
.readdatavalid_slave (ram2_readdatavalid),
|
||||
.read_slave (ram2_read),
|
||||
.writedata_slave (ram2_writedata),
|
||||
.byteenable_slave (ram2_byteenable),
|
||||
.write_slave (ram2_write),
|
||||
|
||||
.waitrequest_master (f2h_ram2_waitrequest),
|
||||
.burstcount_master (f2h_ram2_burstcount),
|
||||
.address_master (f2h_ram2_address),
|
||||
.readdata_master (f2h_ram2_readdata),
|
||||
.readdatavalid_master (f2h_ram2_readdatavalid),
|
||||
.read_master (f2h_ram2_read),
|
||||
.writedata_master (f2h_ram2_writedata),
|
||||
.byteenable_master (f2h_ram2_byteenable),
|
||||
.write_master (f2h_ram2_write)
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// f2sdram_safe_terminator_vbuf ////
|
||||
////////////////////////////////////////////////////////
|
||||
wire [27:0] f2h_vbuf_address;
|
||||
wire [7:0] f2h_vbuf_burstcount;
|
||||
wire f2h_vbuf_waitrequest;
|
||||
wire [127:0] f2h_vbuf_readdata;
|
||||
wire f2h_vbuf_readdatavalid;
|
||||
wire f2h_vbuf_read;
|
||||
wire [127:0] f2h_vbuf_writedata;
|
||||
wire [15:0] f2h_vbuf_byteenable;
|
||||
wire f2h_vbuf_write;
|
||||
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_0 = 1'b1;
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_1 = 1'b1;
|
||||
always @(posedge vbuf_clk) begin
|
||||
vbuf_reset_0 <= reset_out;
|
||||
vbuf_reset_1 <= vbuf_reset_0;
|
||||
end
|
||||
|
||||
f2sdram_safe_terminator #(128, 8) f2sdram_safe_terminator_vbuf
|
||||
(
|
||||
.clk (vbuf_clk),
|
||||
.rst_req_sync (vbuf_reset_1),
|
||||
|
||||
.waitrequest_slave (vbuf_waitrequest),
|
||||
.burstcount_slave (vbuf_burstcount),
|
||||
.address_slave (vbuf_address),
|
||||
.readdata_slave (vbuf_readdata),
|
||||
.readdatavalid_slave (vbuf_readdatavalid),
|
||||
.read_slave (vbuf_read),
|
||||
.writedata_slave (vbuf_writedata),
|
||||
.byteenable_slave (vbuf_byteenable),
|
||||
.write_slave (vbuf_write),
|
||||
|
||||
.waitrequest_master (f2h_vbuf_waitrequest),
|
||||
.burstcount_master (f2h_vbuf_burstcount),
|
||||
.address_master (f2h_vbuf_address),
|
||||
.readdata_master (f2h_vbuf_readdata),
|
||||
.readdatavalid_master (f2h_vbuf_readdatavalid),
|
||||
.read_master (f2h_vbuf_read),
|
||||
.writedata_master (f2h_vbuf_writedata),
|
||||
.byteenable_master (f2h_vbuf_byteenable),
|
||||
.write_master (f2h_vbuf_write)
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// HPS <> FPGA interfaces ////
|
||||
////////////////////////////////////////////////////////
|
||||
sysmem_HPS_fpga_interfaces fpga_interfaces (
|
||||
.f2h_cold_rst_req_n (~reset_hps_cold_req),
|
||||
.f2h_warm_rst_req_n (~reset_hps_warm_req),
|
||||
.h2f_user0_clk (clock),
|
||||
.h2f_rst_n (hps_h2f_reset_n),
|
||||
.f2h_sdram0_clk (vbuf_clk),
|
||||
.f2h_sdram0_ADDRESS (vbuf_address),
|
||||
.f2h_sdram0_BURSTCOUNT (vbuf_burstcount),
|
||||
.f2h_sdram0_WAITREQUEST (vbuf_waitrequest),
|
||||
.f2h_sdram0_READDATA (vbuf_readdata),
|
||||
.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
|
||||
.f2h_sdram0_READ (vbuf_read),
|
||||
.f2h_sdram0_WRITEDATA (vbuf_writedata),
|
||||
.f2h_sdram0_BYTEENABLE (vbuf_byteenable),
|
||||
.f2h_sdram0_WRITE (vbuf_write),
|
||||
.f2h_sdram0_ADDRESS (f2h_vbuf_address),
|
||||
.f2h_sdram0_BURSTCOUNT (f2h_vbuf_burstcount),
|
||||
.f2h_sdram0_WAITREQUEST (f2h_vbuf_waitrequest),
|
||||
.f2h_sdram0_READDATA (f2h_vbuf_readdata),
|
||||
.f2h_sdram0_READDATAVALID (f2h_vbuf_readdatavalid),
|
||||
.f2h_sdram0_READ (f2h_vbuf_read),
|
||||
.f2h_sdram0_WRITEDATA (f2h_vbuf_writedata),
|
||||
.f2h_sdram0_BYTEENABLE (f2h_vbuf_byteenable),
|
||||
.f2h_sdram0_WRITE (f2h_vbuf_write),
|
||||
.f2h_sdram1_clk (ram1_clk),
|
||||
.f2h_sdram1_ADDRESS (ram1_address),
|
||||
.f2h_sdram1_BURSTCOUNT (ram1_burstcount),
|
||||
.f2h_sdram1_WAITREQUEST (ram1_waitrequest),
|
||||
.f2h_sdram1_READDATA (ram1_readdata),
|
||||
.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
|
||||
.f2h_sdram1_READ (ram1_read),
|
||||
.f2h_sdram1_WRITEDATA (ram1_writedata),
|
||||
.f2h_sdram1_BYTEENABLE (ram1_byteenable),
|
||||
.f2h_sdram1_WRITE (ram1_write),
|
||||
.f2h_sdram1_ADDRESS (f2h_ram1_address),
|
||||
.f2h_sdram1_BURSTCOUNT (f2h_ram1_burstcount),
|
||||
.f2h_sdram1_WAITREQUEST (f2h_ram1_waitrequest),
|
||||
.f2h_sdram1_READDATA (f2h_ram1_readdata),
|
||||
.f2h_sdram1_READDATAVALID (f2h_ram1_readdatavalid),
|
||||
.f2h_sdram1_READ (f2h_ram1_read),
|
||||
.f2h_sdram1_WRITEDATA (f2h_ram1_writedata),
|
||||
.f2h_sdram1_BYTEENABLE (f2h_ram1_byteenable),
|
||||
.f2h_sdram1_WRITE (f2h_ram1_write),
|
||||
.f2h_sdram2_clk (ram2_clk),
|
||||
.f2h_sdram2_ADDRESS (ram2_address),
|
||||
.f2h_sdram2_BURSTCOUNT (ram2_burstcount),
|
||||
.f2h_sdram2_WAITREQUEST (ram2_waitrequest),
|
||||
.f2h_sdram2_READDATA (ram2_readdata),
|
||||
.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
|
||||
.f2h_sdram2_READ (ram2_read),
|
||||
.f2h_sdram2_WRITEDATA (ram2_writedata),
|
||||
.f2h_sdram2_BYTEENABLE (ram2_byteenable),
|
||||
.f2h_sdram2_WRITE (ram2_write)
|
||||
.f2h_sdram2_ADDRESS (f2h_ram2_address),
|
||||
.f2h_sdram2_BURSTCOUNT (f2h_ram2_burstcount),
|
||||
.f2h_sdram2_WAITREQUEST (f2h_ram2_waitrequest),
|
||||
.f2h_sdram2_READDATA (f2h_ram2_readdata),
|
||||
.f2h_sdram2_READDATAVALID (f2h_ram2_readdatavalid),
|
||||
.f2h_sdram2_READ (f2h_ram2_read),
|
||||
.f2h_sdram2_WRITEDATA (f2h_ram2_writedata),
|
||||
.f2h_sdram2_BYTEENABLE (f2h_ram2_byteenable),
|
||||
.f2h_sdram2_WRITE (f2h_ram2_write)
|
||||
);
|
||||
|
||||
wire hps_h2f_reset_n;
|
||||
|
||||
@@ -1,44 +1,20 @@
|
||||
|
||||
module vga_out
|
||||
(
|
||||
input ypbpr_full,
|
||||
input clk,
|
||||
input ypbpr_en,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout
|
||||
);
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
|
||||
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
|
||||
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
|
||||
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
|
||||
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
|
||||
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
|
||||
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
|
||||
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
|
||||
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
|
||||
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
|
||||
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
|
||||
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
|
||||
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
|
||||
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
|
||||
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
|
||||
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
|
||||
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
|
||||
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
|
||||
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
|
||||
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
|
||||
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
|
||||
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
|
||||
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
|
||||
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
|
||||
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
|
||||
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
|
||||
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
|
||||
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
|
||||
6'd63
|
||||
};
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
);
|
||||
|
||||
wire [5:0] red = din[23:18];
|
||||
wire [5:0] green = din[15:10];
|
||||
@@ -49,17 +25,44 @@ wire [5:0] blue = din[7:2];
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
reg [7:0] y, pb, pr;
|
||||
reg [23:0] rgb;
|
||||
always @(posedge clk) begin
|
||||
reg [18:0] y_1r, pb_1r, pr_1r;
|
||||
reg [18:0] y_1g, pb_1g, pr_1g;
|
||||
reg [18:0] y_1b, pb_1b, pr_1b;
|
||||
reg [18:0] y_2, pb_2, pr_2;
|
||||
reg [23:0] din1, din2;
|
||||
reg hsync2, vsync2, csync2;
|
||||
reg hsync1, vsync1, csync1;
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0});
|
||||
pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0});
|
||||
pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0});
|
||||
|
||||
assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
|
||||
assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8];
|
||||
assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
|
||||
y_1g <= {green, 9'd0} + {green, 2'd0};
|
||||
pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0};
|
||||
pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0};
|
||||
|
||||
y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0};
|
||||
pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0};
|
||||
pr_1b <= {blue, 6'd0} + {blue, 3'd0};
|
||||
|
||||
y_2 <= y_1r + y_1g + y_1b;
|
||||
pb_2 <= pb_1r - pb_1g + pb_1b;
|
||||
pr_2 <= pr_1r - pr_1g - pr_1b;
|
||||
|
||||
y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
|
||||
pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
|
||||
pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
|
||||
|
||||
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
||||
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
||||
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
||||
|
||||
rgb <= din2; din2 <= din1; din1 <= din;
|
||||
end
|
||||
|
||||
assign dout = ypbpr_en ? {pr, y, pb} : rgb;
|
||||
|
||||
endmodule
|
||||
|
||||
278
sys/video_freak.sv
Normal file
278
sys/video_freak.sv
Normal file
@@ -0,0 +1,278 @@
|
||||
//
|
||||
//
|
||||
// Video crop
|
||||
// Copyright (c) 2020 Grabulosaure, (c) 2021 Alexey Melnikov
|
||||
//
|
||||
// Integer scaling
|
||||
// Copyright (c) 2021 Alexey Melnikov
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module video_freak
|
||||
(
|
||||
input CLK_VIDEO,
|
||||
input CE_PIXEL,
|
||||
input VGA_VS,
|
||||
input [11:0] HDMI_WIDTH,
|
||||
input [11:0] HDMI_HEIGHT,
|
||||
output VGA_DE,
|
||||
output reg [12:0] VIDEO_ARX,
|
||||
output reg [12:0] VIDEO_ARY,
|
||||
|
||||
input VGA_DE_IN,
|
||||
input [11:0] ARX,
|
||||
input [11:0] ARY,
|
||||
input [11:0] CROP_SIZE,
|
||||
input [4:0] CROP_OFF, // -16...+15
|
||||
input [2:0] SCALE //0 - normal, 1 - V-integer, 2 - HV-Integer-, 3 - HV-Integer+, 4 - HV-Integer
|
||||
);
|
||||
|
||||
reg mul_start;
|
||||
wire mul_run;
|
||||
reg [11:0] mul_arg1, mul_arg2;
|
||||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
reg vde;
|
||||
reg [11:0] arxo,aryo;
|
||||
reg [11:0] vsize;
|
||||
reg [11:0] hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_de, old_vs,ovde;
|
||||
reg [11:0] vtot,vcpt,vcrop,voff;
|
||||
reg [11:0] hcpt;
|
||||
reg [11:0] vadj;
|
||||
reg [23:0] ARXG,ARYG;
|
||||
reg [11:0] arx,ary;
|
||||
reg [1:0] vcalc;
|
||||
|
||||
if (CE_PIXEL) begin
|
||||
old_de <= VGA_DE_IN;
|
||||
old_vs <= VGA_VS;
|
||||
if (VGA_VS & ~old_vs) begin
|
||||
vcpt <= 0;
|
||||
vtot <= vcpt;
|
||||
vcalc <= 1;
|
||||
vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE;
|
||||
end
|
||||
|
||||
if (VGA_DE_IN) hcpt <= hcpt + 1'd1;
|
||||
if (~VGA_DE_IN & old_de) begin
|
||||
vcpt <= vcpt + 1'd1;
|
||||
if(!vcpt) hsize <= hcpt;
|
||||
hcpt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
arx <= ARX;
|
||||
ary <= ARY;
|
||||
|
||||
vsize <= vcrop ? vcrop : vtot;
|
||||
|
||||
mul_start <= 0;
|
||||
|
||||
if(!vcrop || !ary || !arx) begin
|
||||
arxo <= arx;
|
||||
aryo <= ary;
|
||||
end
|
||||
else if (vcalc) begin
|
||||
if(~mul_start & ~mul_run) begin
|
||||
vcalc <= vcalc + 1'd1;
|
||||
case(vcalc)
|
||||
1: begin
|
||||
mul_arg1 <= arx;
|
||||
mul_arg2 <= vtot;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
2: begin
|
||||
ARXG <= mul_res;
|
||||
mul_arg1 <= ary;
|
||||
mul_arg2 <= vcrop;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
3: begin
|
||||
ARYG <= mul_res;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else if (ARXG[23] | ARYG[23]) begin
|
||||
arxo <= ARXG[23:12];
|
||||
aryo <= ARYG[23:12];
|
||||
end
|
||||
else begin
|
||||
ARXG <= ARXG << 1;
|
||||
ARYG <= ARYG << 1;
|
||||
end
|
||||
|
||||
vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0};
|
||||
voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1];
|
||||
ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;
|
||||
vde <= ovde;
|
||||
end
|
||||
|
||||
assign VGA_DE = vde & VGA_DE_IN;
|
||||
|
||||
video_scale_int scale
|
||||
(
|
||||
.CLK_VIDEO(CLK_VIDEO),
|
||||
.HDMI_WIDTH(HDMI_WIDTH),
|
||||
.HDMI_HEIGHT(HDMI_HEIGHT),
|
||||
.SCALE(SCALE),
|
||||
.hsize(hsize),
|
||||
.vsize(vsize),
|
||||
.arx_i(arxo),
|
||||
.ary_i(aryo),
|
||||
.arx_o(VIDEO_ARX),
|
||||
.ary_o(VIDEO_ARY)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module video_scale_int
|
||||
(
|
||||
input CLK_VIDEO,
|
||||
|
||||
input [11:0] HDMI_WIDTH,
|
||||
input [11:0] HDMI_HEIGHT,
|
||||
|
||||
input [2:0] SCALE,
|
||||
|
||||
input [11:0] hsize,
|
||||
input [11:0] vsize,
|
||||
|
||||
input [11:0] arx_i,
|
||||
input [11:0] ary_i,
|
||||
|
||||
output reg [12:0] arx_o,
|
||||
output reg [12:0] ary_o
|
||||
);
|
||||
|
||||
reg div_start;
|
||||
wire div_run;
|
||||
reg [23:0] div_num;
|
||||
reg [11:0] div_den;
|
||||
wire [23:0] div_res;
|
||||
sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res);
|
||||
|
||||
reg mul_start;
|
||||
wire mul_run;
|
||||
reg [11:0] mul_arg1, mul_arg2;
|
||||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
wire [11:0] wideres = mul_res[11:0] + hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [11:0] oheight,wres;
|
||||
reg [12:0] arxf,aryf;
|
||||
reg [3:0] cnt;
|
||||
reg narrow;
|
||||
|
||||
div_start <= 0;
|
||||
mul_start <= 0;
|
||||
|
||||
if (!SCALE || (!ary_i && arx_i)) begin
|
||||
arxf <= arx_i;
|
||||
aryf <= ary_i;
|
||||
end
|
||||
else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
0: begin
|
||||
div_num <= HDMI_HEIGHT;
|
||||
div_den <= vsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
1: if(!div_res[11:0]) begin
|
||||
// screen resolution is lower than video resolution.
|
||||
// Integer scaling is impossible.
|
||||
arxf <= arx_i;
|
||||
aryf <= ary_i;
|
||||
cnt <= 0;
|
||||
end
|
||||
else begin
|
||||
mul_arg1 <= vsize;
|
||||
mul_arg2 <= div_res[11:0];
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
2: begin
|
||||
oheight <= mul_res[11:0];
|
||||
if(!ary_i) begin
|
||||
cnt <= 8;
|
||||
end
|
||||
end
|
||||
|
||||
3: begin
|
||||
mul_arg1 <= mul_res[11:0];
|
||||
mul_arg2 <= arx_i;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
4: begin
|
||||
div_num <= mul_res;
|
||||
div_den <= ary_i;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
5: begin
|
||||
div_num <= div_res;
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
6: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
7: if(mul_res <= HDMI_WIDTH) begin
|
||||
cnt <= 10;
|
||||
end
|
||||
|
||||
8: begin
|
||||
div_num <= HDMI_WIDTH;
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
9: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
10: begin
|
||||
narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
|
||||
wres <= wideres;
|
||||
end
|
||||
|
||||
11: begin
|
||||
case(SCALE)
|
||||
2: arxf <= {1'b1, mul_res[11:0]};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
|
||||
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
|
||||
default: arxf <= {1'b1, div_num[11:0]};
|
||||
endcase
|
||||
aryf <= {1'b1, oheight};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
arx_o <= arxf;
|
||||
ary_o <= aryf;
|
||||
end
|
||||
|
||||
endmodule
|
||||
143
sys/video_freezer.sv
Normal file
143
sys/video_freezer.sv
Normal file
@@ -0,0 +1,143 @@
|
||||
//
|
||||
// video freeze with sync
|
||||
// (C) Alexey Melnikov
|
||||
//
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
|
||||
module video_freezer
|
||||
(
|
||||
input clk,
|
||||
|
||||
output sync,
|
||||
input freeze,
|
||||
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input hbl_in,
|
||||
input vbl_in,
|
||||
|
||||
output hs_out,
|
||||
output vs_out,
|
||||
output hbl_out,
|
||||
output vbl_out
|
||||
);
|
||||
|
||||
sync_lock #(33) vs_lock
|
||||
(
|
||||
.clk(clk),
|
||||
.sync_in(vs_in),
|
||||
.sync_out(vs_out),
|
||||
.de_in(vbl_in),
|
||||
.de_out(vbl_out),
|
||||
.freeze(freeze)
|
||||
);
|
||||
|
||||
wire sync_pt;
|
||||
sync_lock #(21) hs_lock
|
||||
(
|
||||
.clk(clk),
|
||||
.sync_in(hs_in),
|
||||
.sync_out(hs_out),
|
||||
.de_in(hbl_in),
|
||||
.de_out(hbl_out),
|
||||
.freeze(freeze),
|
||||
.sync_pt(sync_pt)
|
||||
);
|
||||
|
||||
reg sync_o;
|
||||
always @(posedge clk) begin
|
||||
reg old_hs, old_vs;
|
||||
reg vs_sync;
|
||||
|
||||
old_vs <= vs_out;
|
||||
|
||||
if(~old_vs & vs_out) vs_sync <= 1;
|
||||
if(sync_pt & vs_sync) begin
|
||||
vs_sync <= 0;
|
||||
sync_o <= ~sync_o;
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = sync_o;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module sync_lock #(parameter WIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input sync_in,
|
||||
input de_in,
|
||||
|
||||
output sync_out,
|
||||
output de_out,
|
||||
|
||||
input freeze,
|
||||
output sync_pt,
|
||||
output valid
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] f_len, s_len, de_start, de_end;
|
||||
reg sync_valid;
|
||||
|
||||
reg old_sync;
|
||||
always @(posedge clk) old_sync <= sync_in;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [WIDTH-1:0] cnti;
|
||||
reg f_valid;
|
||||
reg old_de;
|
||||
|
||||
cnti <= cnti + 1'd1;
|
||||
if(~old_sync & sync_in) begin
|
||||
if(sync_valid) f_len <= cnti;
|
||||
f_valid <= 1;
|
||||
sync_valid <= f_valid;
|
||||
cnti <= 0;
|
||||
end
|
||||
|
||||
if(old_sync & ~sync_in & sync_valid) s_len <= cnti;
|
||||
|
||||
old_de <= de_in;
|
||||
if(~old_de & de_in & sync_valid) de_start <= cnti;
|
||||
if(old_de & ~de_in & sync_valid) de_end <= cnti;
|
||||
|
||||
if(freeze) {f_valid, sync_valid} <= 0;
|
||||
end
|
||||
|
||||
reg sync_o, de_o, sync_o_pre;
|
||||
always @(posedge clk) begin
|
||||
reg [WIDTH-1:0] cnto;
|
||||
|
||||
cnto <= cnto + 1'd1;
|
||||
if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2'd2;
|
||||
if(cnto == f_len) cnto <= 0;
|
||||
|
||||
sync_o_pre <= (cnto == (s_len>>1)); // middle in sync
|
||||
if(cnto == f_len) sync_o <= 1;
|
||||
if(cnto == s_len) sync_o <= 0;
|
||||
if(cnto == de_start) de_o <= 1;
|
||||
if(cnto == de_end) de_o <= 0;
|
||||
end
|
||||
|
||||
assign sync_out = freeze ? sync_o : sync_in;
|
||||
assign valid = sync_valid;
|
||||
assign sync_pt = sync_o_pre;
|
||||
assign de_out = freeze ? de_o : de_in;
|
||||
|
||||
endmodule
|
||||
@@ -1,6 +1,6 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
// Copyright (c) 2017,2021 Alexey Melnikov
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
@@ -10,13 +10,8 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels
|
||||
// Usually it's length from HSync to HSync.
|
||||
// May be less if line_start is used.
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels when HBlank = 0;
|
||||
// HALF_DEPTH: If =1 then color dept is 4 bits per component
|
||||
// For half depth 8 bits monochrome is available with
|
||||
// mono signal enabled and color = {G, R}
|
||||
//
|
||||
// altera message_off 10720
|
||||
// altera message_off 12161
|
||||
@@ -28,38 +23,33 @@ module video_mixer
|
||||
parameter GAMMA = 0
|
||||
)
|
||||
(
|
||||
// video clock
|
||||
// it should be multiple by (ce_pix*4).
|
||||
input clk_vid,
|
||||
input CLK_VIDEO, // should be multiple by (ce_pix*4)
|
||||
output reg CE_PIXEL, // output pixel clock enable
|
||||
|
||||
// Pixel clock or clock_enable (both are accepted).
|
||||
input ce_pix,
|
||||
output ce_pix_out,
|
||||
input ce_pix, // input pixel clock or clock_enable
|
||||
|
||||
input scandoubler,
|
||||
input hq2x, // high quality 2x scaling
|
||||
|
||||
// scanlines (00-none 01-25% 10-50% 11-75%)
|
||||
input [1:0] scanlines,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
inout [21:0] gamma_bus,
|
||||
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Monochrome mode (for HALF_DEPTH only)
|
||||
input mono,
|
||||
|
||||
inout [21:0] gamma_bus,
|
||||
|
||||
// Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
input HBlank,
|
||||
input VBlank,
|
||||
|
||||
// Freeze engine
|
||||
// HDMI: displays last frame
|
||||
// VGA: black screen with HSync and VSync
|
||||
input HDMI_FREEZE,
|
||||
output freeze_sync,
|
||||
|
||||
// video output signals
|
||||
output reg [7:0] VGA_R,
|
||||
output reg [7:0] VGA_G,
|
||||
@@ -73,19 +63,43 @@ localparam DWIDTH = HALF_DEPTH ? 3 : 7;
|
||||
localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
|
||||
localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
|
||||
|
||||
wire frz_hs, frz_vs;
|
||||
wire frz_hbl, frz_vbl;
|
||||
video_freezer freezer
|
||||
(
|
||||
.clk(CLK_VIDEO),
|
||||
.freeze(HDMI_FREEZE),
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.hbl_in(HBlank),
|
||||
.vbl_in(VBlank),
|
||||
.sync(freeze_sync),
|
||||
.hs_out(frz_hs),
|
||||
.vs_out(frz_vs),
|
||||
.hbl_out(frz_hbl),
|
||||
.vbl_out(frz_vbl)
|
||||
);
|
||||
|
||||
reg frz;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg frz1;
|
||||
|
||||
frz1 <= HDMI_FREEZE;
|
||||
frz <= frz1;
|
||||
end
|
||||
|
||||
generate
|
||||
if(GAMMA && HALF_DEPTH) begin
|
||||
wire [7:0] R_in = mono ? {G,R} : {R,R};
|
||||
wire [7:0] G_in = mono ? {G,R} : {G,G};
|
||||
wire [7:0] B_in = mono ? {G,R} : {B,B};
|
||||
wire [7:0] R_in = frz ? 8'd0 : {R,R};
|
||||
wire [7:0] G_in = frz ? 8'd0 : {G,G};
|
||||
wire [7:0] B_in = frz ? 8'd0 : {B,B};
|
||||
end else begin
|
||||
wire [DWIDTH:0] R_in = R;
|
||||
wire [DWIDTH:0] G_in = G;
|
||||
wire [DWIDTH:0] B_in = B;
|
||||
wire [DWIDTH:0] R_in = frz ? 1'd0 : R;
|
||||
wire [DWIDTH:0] G_in = frz ? 1'd0 : G;
|
||||
wire [DWIDTH:0] B_in = frz ? 1'd0 : B;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
wire hs_g, vs_g;
|
||||
wire hb_g, vb_g;
|
||||
wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
|
||||
@@ -95,7 +109,7 @@ generate
|
||||
assign gamma_bus[21] = 1;
|
||||
gamma_corr gamma(
|
||||
.clk_sys(gamma_bus[20]),
|
||||
.clk_vid(clk_vid),
|
||||
.clk_vid(CLK_VIDEO),
|
||||
.ce_pix(ce_pix),
|
||||
|
||||
.gamma_en(gamma_bus[19]),
|
||||
@@ -103,10 +117,10 @@ generate
|
||||
.gamma_wr_addr(gamma_bus[17:8]),
|
||||
.gamma_value(gamma_bus[7:0]),
|
||||
|
||||
.HSync(HSync),
|
||||
.VSync(VSync),
|
||||
.HBlank(HBlank),
|
||||
.VBlank(VBlank),
|
||||
.HSync(frz_hs),
|
||||
.VSync(frz_vs),
|
||||
.HBlank(frz_hbl),
|
||||
.VBlank(frz_vbl),
|
||||
.RGB_in({R_in,G_in,B_in}),
|
||||
|
||||
.HSync_out(hs_g),
|
||||
@@ -118,11 +132,10 @@ generate
|
||||
end else begin
|
||||
assign gamma_bus[21] = 0;
|
||||
assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
|
||||
assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank};
|
||||
assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
wire [DWIDTH_SD:0] R_sd;
|
||||
wire [DWIDTH_SD:0] G_sd;
|
||||
wire [DWIDTH_SD:0] B_sd;
|
||||
@@ -130,7 +143,10 @@ wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd
|
||||
(
|
||||
.*,
|
||||
.clk_vid(CLK_VIDEO),
|
||||
.hq2x(hq2x),
|
||||
|
||||
.ce_pix(ce_pix),
|
||||
.hs_in(hs_g),
|
||||
.vs_in(vs_g),
|
||||
.hb_in(hb_g),
|
||||
@@ -149,90 +165,55 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma);
|
||||
wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma);
|
||||
wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma);
|
||||
wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma);
|
||||
wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma);
|
||||
wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma);
|
||||
|
||||
generate
|
||||
if(!GAMMA && HALF_DEPTH) begin
|
||||
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
|
||||
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
|
||||
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
|
||||
end else begin
|
||||
wire [7:0] r = rt;
|
||||
wire [7:0] g = gt;
|
||||
wire [7:0] b = bt;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoubler ? hs_sd : hs_g);
|
||||
wire vs = (scandoubler ? vs_sd : vs_g);
|
||||
|
||||
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
|
||||
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_vid) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs;
|
||||
old_vs <= vs;
|
||||
|
||||
if(old_hs && ~hs) scanline <= ~scanline;
|
||||
if(old_vs && ~vs) scanline <= 0;
|
||||
end
|
||||
|
||||
wire hde = scandoubler ? ~hb_sd : ~hb_g;
|
||||
wire vde = scandoubler ? ~vb_sd : ~vb_g;
|
||||
|
||||
reg [7:0] v_r,v_g,v_b;
|
||||
reg v_vs,v_hs,v_de;
|
||||
always @(posedge clk_vid) begin
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [7:0] r,g,b;
|
||||
reg hde,vde,hs,vs, old_vs;
|
||||
reg old_hde;
|
||||
reg old_ce;
|
||||
reg ce_osc, fs_osc;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
ce_osc <= ce_osc | (old_ce ^ ce_pix);
|
||||
|
||||
if(ce_pix_out) begin
|
||||
case(scanlines & {scanline, scanline})
|
||||
1: begin // reduce 25% = 1/2 + 1/4
|
||||
v_r <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
|
||||
v_g <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
|
||||
v_b <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
|
||||
end
|
||||
old_vs <= vs;
|
||||
if(~old_vs & vs) begin
|
||||
fs_osc <= ce_osc;
|
||||
ce_osc <= 0;
|
||||
end
|
||||
|
||||
2: begin // reduce 50% = 1/2
|
||||
v_r <= {1'b0, r[7:1]};
|
||||
v_g <= {1'b0, g[7:1]};
|
||||
v_b <= {1'b0, b[7:1]};
|
||||
end
|
||||
CE_PIXEL <= scandoubler ? ce_pix_sd : fs_osc ? (~old_ce & ce_pix) : ce_pix;
|
||||
|
||||
3: begin // reduce 75% = 1/4
|
||||
v_r <= {2'b00, r[7:2]};
|
||||
v_g <= {2'b00, g[7:2]};
|
||||
v_b <= {2'b00, b[7:2]};
|
||||
end
|
||||
if(!GAMMA && HALF_DEPTH) begin
|
||||
r <= {rt,rt};
|
||||
g <= {gt,gt};
|
||||
b <= {bt,bt};
|
||||
end
|
||||
else begin
|
||||
r <= rt;
|
||||
g <= gt;
|
||||
b <= bt;
|
||||
end
|
||||
|
||||
default: begin
|
||||
v_r <= r;
|
||||
v_g <= g;
|
||||
v_b <= b;
|
||||
end
|
||||
endcase
|
||||
hde <= scandoubler ? ~hb_sd : ~hb_g;
|
||||
vde <= scandoubler ? ~vb_sd : ~vb_g;
|
||||
vs <= scandoubler ? vs_sd : vs_g;
|
||||
hs <= scandoubler ? hs_sd : hs_g;
|
||||
|
||||
v_vs <= vs;
|
||||
v_hs <= hs;
|
||||
if(CE_PIXEL) begin
|
||||
VGA_R <= r;
|
||||
VGA_G <= g;
|
||||
VGA_B <= b;
|
||||
|
||||
VGA_VS <= vs;
|
||||
VGA_HS <= hs;
|
||||
|
||||
old_hde <= hde;
|
||||
if(~old_hde && hde) v_de <= vde;
|
||||
if(old_hde && ~hde) v_de <= 0;
|
||||
if(old_hde ^ hde) VGA_DE <= vde & hde;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_vid) if(ce_pix_out) begin
|
||||
VGA_R <= v_r;
|
||||
VGA_G <= v_g;
|
||||
VGA_B <= v_b;
|
||||
VGA_HS <= v_hs;
|
||||
VGA_VS <= v_vs;
|
||||
VGA_DE <= v_de;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user