diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ec8ccc9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,15 @@ +db +incremental_db +output_files +build_id.v +c5_pin_model_dump.txt +jtag.cdf +*.zip +*.bak +/*.qws +greybox_tmp/cbx_args.txt +*/greybox_tmp/cbx_args.txt +.idea +output_files +incremental_db + diff --git a/AcornAtom.qsf b/AcornAtom.qsf index c3aff6c..c682eee 100644 --- a/AcornAtom.qsf +++ b/AcornAtom.qsf @@ -13,7 +13,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition" set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files @@ -37,6 +37,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name MUX_RESTRUCTURE ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON @@ -49,13 +50,15 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM set_global_assignment -name SEED 1 -#set_global_assignment -name VERILOG_MACRO "ARCADE_SYS=1" -#set_global_assignment -name VERILOG_MACRO "USE_FB=1" -#set_global_assignment -name VERILOG_MACRO "USE_SDRAM=1" -#set_global_assignment -name VERILOG_MACRO "USE_DDRAM=1" +#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1" + +#enable it only if 8bit indexed mode is used in core +#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1" + +#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1" #do not enable DEBUG_NOHDMI in release! -#set_global_assignment -name VERILOG_MACRO "DEBUG_NOHDMI=1" +#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1" source sys/sys.tcl source sys/sys_analog.tcl diff --git a/AcornAtom.sv b/AcornAtom.sv index f3ab7ba..3583217 100644 --- a/AcornAtom.sv +++ b/AcornAtom.sv @@ -17,6 +17,7 @@ // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. //============================================================================ + module emu ( //Master input clock @@ -27,7 +28,7 @@ module emu input RESET, //Must be passed to hps_io module - inout [45:0] HPS_BUS, + inout [47:0] HPS_BUS, //Base video clock. Usually equals to CLK_SYS. output CLK_VIDEO, @@ -37,8 +38,9 @@ module emu output CE_PIXEL, //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - output [7:0] VIDEO_ARX, - output [7:0] VIDEO_ARY, + //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. + output [12:0] VIDEO_ARX, + output [12:0] VIDEO_ARY, output [7:0] VGA_R, output [7:0] VGA_G, @@ -46,8 +48,42 @@ module emu output VGA_HS, output VGA_VS, output VGA_DE, // = ~(VBlank | HBlank) - output VGA_F1, - output [1:0] VGA_SL, + output VGA_F1, + output [1:0] VGA_SL, + output VGA_SCALER, // Force VGA scaler + + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + output HDMI_FREEZE, + +`ifdef MISTER_FB + // Use framebuffer in DDRAM (USE_FB=1 in qsf) + // FB_FORMAT: + // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp + // [3] : 0=16bits 565 1=16bits 1555 + // [4] : 0=RGB 1=BGR (for 16/24/32 modes) + // + // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) + output FB_EN, + output [4:0] FB_FORMAT, + output [11:0] FB_WIDTH, + output [11:0] FB_HEIGHT, + output [31:0] FB_BASE, + output [13:0] FB_STRIDE, + input FB_VBL, + input FB_LL, + output FB_FORCE_BLANK, + +`ifdef MISTER_FB_PALETTE + // Palette control for 8bit modes. + // Ignored for other video modes. + output FB_PAL_CLK, + output [7:0] FB_PAL_ADDR, + output [23:0] FB_PAL_DOUT, + input [23:0] FB_PAL_DIN, + output FB_PAL_WR, +`endif +`endif output LED_USER, // 1 - ON, 0 - OFF. @@ -62,16 +98,16 @@ module emu // b[0]: osd button output [1:0] BUTTONS, - input CLK_AUDIO, //24.576 MHz + input CLK_AUDIO, // 24.576 MHz output [15:0] AUDIO_L, output [15:0] AUDIO_R, output AUDIO_S, // 1 - signed audio samples, 0 - unsigned output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - - //ADC - inout [3:0] ADC_BUS, - // SD-SPI + //ADC + inout [3:0] ADC_BUS, + + //SD-SPI output SD_SCK, output SD_MOSI, input SD_MISO, @@ -102,24 +138,38 @@ module emu output SDRAM_nCS, output SDRAM_nCAS, output SDRAM_nRAS, - output SDRAM_nWE, - - input UART_CTS, - output UART_RTS, - input UART_RXD, - output UART_TXD, - output UART_DTR, - input UART_DSR, - - // Open-drain User port. - // 0 - D+/RX - // 1 - D-/TX - // 2..5 - USR1..USR4 - // Set USER_OUT to 1 to read from USER_IN. - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input OSD_STATUS + output SDRAM_nWE, + +`ifdef MISTER_DUAL_SDRAM + //Secondary SDRAM + //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 + input SDRAM2_EN, + output SDRAM2_CLK, + output [12:0] SDRAM2_A, + output [1:0] SDRAM2_BA, + inout [15:0] SDRAM2_DQ, + output SDRAM2_nCS, + output SDRAM2_nCAS, + output SDRAM2_nRAS, + output SDRAM2_nWE, +`endif + + input UART_CTS, + output UART_RTS, + input UART_RXD, + output UART_TXD, + output UART_DTR, + input UART_DSR, + + // Open-drain User port. + // 0 - D+/RX + // 1 - D-/TX + // 2..6 - USR2..USR6 + // Set USER_OUT to 1 to read from USER_IN. + input [6:0] USER_IN, + output [6:0] USER_OUT, + + input OSD_STATUS ); assign ADC_BUS = 'Z; @@ -134,10 +184,14 @@ assign LED_DISK = {1'b1,~vsd_sel & sd_act}; assign LED_POWER = 0; assign BUTTONS = 0; -assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; -assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; +assign VGA_SCALER = 0; +assign HDMI_FREEZE = 0; + +wire [1:0] ar = status[12:11]; + +assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1); +assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0; -wire [1:0] scale = status[3:2]; `include "build_id.v" parameter CONF_STR = { @@ -145,8 +199,8 @@ parameter CONF_STR = { "-;", "S,VHD;", "-;", - "O1,Aspect ratio,4:3,16:9;", - "O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "OBC,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];", + "O13,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;", "-;", "O45,Audio,Atom,SID,TAPE,off;", "O67,Keyboard,UK,US,orig,game;", @@ -160,23 +214,48 @@ parameter CONF_STR = { }; ///////////////// CLOCKS //////////////////////// - -wire clk_sys; +wire clk_main = clk_sys; +wire clk_sys = clk_32; +//wire clk_100; wire clk_16; wire clk_32; -wire clk_25; +//wire clk_25; +wire clk_42; wire pll_locked; pll pll ( .refclk(CLK_50M), .rst(0), - .outclk_0(clk_sys), - .outclk_1(clk_16), - .outclk_2(clk_25), - .outclk_3(clk_32) + .outclk_0(clk_42), + .outclk_1(clk_32), + .outclk_2(clk_16) + ); +reg clk_14M318_ena ; +reg [1:0] count; + + +always @(posedge clk_42) +begin + if (reset) + count<=0; + else + begin + clk_14M318_ena <= 0; + if (count == 'd2) + begin + clk_14M318_ena <= 1; + count <= 0; + end + else + begin + count<=count+1; + end + end +end + ///////////////// HPS /////////////////////////// @@ -197,35 +276,35 @@ wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; wire forced_scandoubler; wire [21:0] gamma_bus; +wire direct_video; -wire [31:0] sd_lba; +wire [31:0] sd_lba[1]; wire sd_rd; wire sd_wr; wire sd_ack; wire [8:0] sd_buff_addr; wire [7:0] sd_buff_dout; -wire [7:0] sd_buff_din; +wire [7:0] sd_buff_din[1]; wire sd_buff_wr; wire img_mounted; wire img_readonly; wire [63:0] img_size; -wire sd_ack_conf; wire [64:0] RTC; wire ps2_clk,ps2_data; -hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io +hps_io #(.CONF_STR(CONF_STR)) hps_io ( .clk_sys(clk_sys), .HPS_BUS(HPS_BUS), - .conf_str(CONF_STR), .buttons(buttons), .status(status), .forced_scandoubler(forced_scandoubler), .gamma_bus(gamma_bus), + .direct_video(direct_video), .RTC(RTC), @@ -240,13 +319,13 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io .ioctl_addr(ioctl_addr), .ioctl_dout(ioctl_dout), - .uart_mode(16'b000_11111_000_11111), + //.uart_mode(16'b000_11111_000_11111), .sd_lba(sd_lba), .sd_rd(sd_rd), .sd_wr(sd_wr), .sd_ack(sd_ack), - .sd_ack_conf(sd_ack_conf), + .sd_buff_addr(sd_buff_addr), .sd_buff_dout(sd_buff_dout), .sd_buff_din(sd_buff_din), @@ -257,8 +336,8 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io .joystick_0(joy1), .joystick_1(joy2), - .joystick_analog_0({joy1_y,joy1_x}), - .joystick_analog_1({joy2_y,joy2_x}) + .joystick_l_analog_0({joy1_y,joy1_x}), + .joystick_l_analog_1({joy2_y,joy2_x}) ); ///////////////// RESET ///////////////////////// @@ -327,7 +406,7 @@ wire [7:0] mem_din,mem_dout; spram #(8, 18, 196608, "roms/ATOM192k.mif") rom ( - .clock(clk_sys), + .clock(clk_main), .address(mem_addr), .data(mem_din), .wren(mem_we), @@ -340,14 +419,19 @@ spram #(8, 18, 196608, "roms/ATOM192k.mif") rom wire charset = status[8]; wire tape_out; - +wire pixel_clock; AtomFpga_Core AcornAtom ( // clocks - .clk_vga(clk_25), - .clk_main(clk_32), + + .clk_vid(clk_42), + .clk_vid_en(clk_14M318_ena), + .clk_main(clk_main), .clk_dac(clk_sys), - .clk_avr(clk_16), + //.clk_avr(clk_16), + .clk_avr(clk_main), + + .pixel_clock(pixel_clock), // Keyboard .ps2_key(ps2_key), @@ -435,42 +519,41 @@ assign AUDIO_R = status[5:4] == 2'b00 ? {{16{a_audio}}} : status[5:4] == 2'b01 ? assign AUDIO_MIX = 0; assign AUDIO_S = 1'b0; -wire hs, vs, hblank, vblank, ce_pix, clk_sel; +wire hs, vs, hblank, vblank, clk_sel; wire [1:0] r,g,b; -assign CLK_VIDEO = clk_25; -video_mixer #(640, 0) mixer -( - .clk_vid(CLK_VIDEO), - - .ce_pix(1'b1), - .ce_pix_out(CE_PIXEL), +assign CLK_VIDEO = clk_42;// clk_25; +wire freeze_sync; + + + +video_mixer #(.GAMMA(1)) video_mixer +( + .*, + + .CLK_VIDEO(CLK_VIDEO), + .ce_pix(pixel_clock), + + .hq2x(scale==1), - .hq2x(scale == 1), - .scanlines(0), - .scandoubler(scale), .R({r[1],r[1],r[1],r[0],r[0],r[0],r}), .G({g[1],g[1],g[1],g[0],g[0],g[0],g}), .B({b[1],b[1],b[1],b[0],b[0],b[0],b}), - .mono(0), - - .HSync(~hs), - .VSync(~vs), - .HBlank(hblank), - .VBlank(vblank), - - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .VGA_DE(VGA_DE) + .HSync(~hs), + .VSync(~vs), + .HBlank(hblank), + .VBlank(vblank) ); + + assign VGA_F1 = 0; -assign VGA_SL = scale ? scale - 1'd1 : 2'd0; +wire [2:0] scale = status[3:1]; +wire [2:0] sl = scale ? scale - 1'd1 : 3'd0; +wire scandoubler = (scale || forced_scandoubler); +assign VGA_SL = sl[1:0]; ////////////////// SD /////////////////// @@ -487,6 +570,9 @@ sd_card #(0) sd_card ( .*, + .sd_lba(sd_lba[0]), + .sd_buff_din(sd_buff_din[0]), + .clk_spi(clk_sys), .sdhc(1), .sck(sdclk), diff --git a/pll.xml b/pll.xml new file mode 100644 index 0000000..b01c3e3 --- /dev/null +++ b/pll.xml @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/rtl/AtomFpga_Core.vhd b/rtl/AtomFpga_Core.vhd index 05d01cb..b8d6222 100644 --- a/rtl/AtomFpga_Core.vhd +++ b/rtl/AtomFpga_Core.vhd @@ -22,10 +22,12 @@ use ieee.numeric_std.all; entity AtomFpga_Core is port ( -- Clocking - clk_vga : in std_logic; -- nominally 25.175MHz VGA clock + clk_vid : in std_logic; -- nominally 25.175MHz VGA clock + clk_vid_en : in std_logic; -- nominally 25.175MHz VGA clock clk_main : in std_logic; -- clock for the main system clk_dac : in std_logic; -- fast clock for the 1-bit DAC clk_avr : in std_logic; -- clock for the AtoMMC AVR + pixel_clock : out std_logic; -- Keyboard/mouse ps2_key : in std_logic_vector (10 downto 0); @@ -257,7 +259,7 @@ architecture BEHAVIORAL of AtomFpga_Core is signal clk_sid_1MHz : std_logic; - + signal reset_vid : std_logic; -------------------------------------------------------------------- -- here it begin :) @@ -329,7 +331,13 @@ begin not_cpu_R_W_n <= not cpu_R_W_n; -- reset logic - RSTn <= key_break and ext_reset_n; + process (clk_main) + begin + if rising_edge(clk_main) then + RSTn <= key_break and ext_reset_n; + reset_vid <=not ext_reset_n; + end if; + end process; reset <= not RSTn; -- process(clk_main) -- begin @@ -346,24 +354,16 @@ begin video_ram_we <= not_cpu_R_W_n and vid_cs; - - process (clk_vga) - begin - if rising_edge(clk_vga) then - clock_vga_en <= not clock_vga_en; - end if; - end process; - -- Motorola MC6847 -- Original version: https://svn.pacedev.net/repos/pace/sw/src/component/video/mc6847.vhd -- Updated by AlanD for his Atom FPGA: http://stardot.org.uk/forums/viewtopic.php?f=3&t=6313 -- A further few bugs fixed by myself Inst_mc6847 : entity work.mc6847 port map ( - clk => clk_vga, - clk_ena => clock_vga_en, - reset => not ext_reset_n, + clk => clk_vid, + clk_ena => clk_vid_en, + reset => reset_vid, da0 => open, videoaddr => vid_addr, dd => vid_data, @@ -388,7 +388,8 @@ begin cvbs => open, black_backgnd => BLACK_BACKGND, char_a => char_a, - char_d_o => char_d_o + char_d_o => char_d_o, + pixel_clock => pixel_clock ); -- 8Kx8 Dual port video RAM @@ -401,7 +402,7 @@ begin addra => cpu_addr(12 downto 0), dina => cpu_dout, douta => vid_dout, - clkb => clk_vga, + clkb => clk_vid, web => '0', addrb => vid_addr, dinb => (others => '0'), @@ -412,7 +413,7 @@ begin ---- ram for char generator charrom_inst : entity work.CharRom port map( - CLK => clk_vga, + CLK => clk_vid, ADDR => char_a, DATA => char_do ); @@ -420,7 +421,7 @@ begin ---- ram for xtra char generator charromx_inst : entity work.CharRomx port map( - CLK => clk_vga, + CLK => clk_vid, ADDR => char_a, DATA => charx_do ); @@ -488,9 +489,9 @@ begin vga_blank <= (vga_vblank or vga_hblank); -- Making this a synchronous process should improve the timing -- and potentially make the pixels more defined - process (clk_vga) + process (clk_vid) begin - if rising_edge(clk_vga) then + if rising_edge(clk_vid) then if vga_blank = '1' then physical_colour <= (others => '0'); else diff --git a/rtl/MC6847/mc6847.vhd b/rtl/MC6847/mc6847.vhd index c3bb015..a0d9da5 100644 --- a/rtl/MC6847/mc6847.vhd +++ b/rtl/MC6847/mc6847.vhd @@ -7,7 +7,7 @@ entity mc6847 is generic ( T1_VARIANT : boolean := false; - CVBS_NOT_VGA : boolean := false); + CVBS_NOT_VGA : boolean := true); port ( clk : in std_logic; @@ -37,7 +37,8 @@ entity mc6847 is cvbs : out std_logic_vector(7 downto 0); black_backgnd : in std_logic; char_a : out std_logic_vector(11 downto 0); - char_d_o : in std_logic_vector(7 downto 0) + char_d_o : in std_logic_vector(7 downto 0); + pixel_clock : out std_logic ); end mc6847; @@ -67,14 +68,25 @@ architecture SYN of mc6847 is -- constant H_RIGHT_BORDER : integer := H_VIDEO + 54;---3; -- tweak to get to 60hz exactly -- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER; - constant H_FRONT_PORCH : integer := 8; - constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48; - constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24; - constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6 - constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16; - constant H_VIDEO : integer := H_LEFT_BORDER + 256; - constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- " - constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER; + + + constant H_FRONT_PORCH : integer := 11-1+1; + constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 35+2; + constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 34+1+2; -- AJS + constant H_LEFT_BORDER : integer := H_BACK_PORCH + 61+1+3 ; -- adjust for hblank de-assert @sys_count=6 + constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16 +8; + constant H_VIDEO : integer := H_LEFT_BORDER + 256; + constant H_RIGHT_BORDER : integer := H_VIDEO + 61+1-3; -- " + constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER; + +-- constant H_FRONT_PORCH : integer := 8; +-- constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48; +-- constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24; +-- constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6 +-- constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16; +-- constant H_VIDEO : integer := H_LEFT_BORDER + 256; +-- constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- " +-- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER; constant V2_FRONT_PORCH : integer := 2; constant V2_VERTICAL_SYNC : integer := V2_FRONT_PORCH + 2; @@ -93,6 +105,7 @@ architecture SYN of mc6847 is signal inv_s : std_logic; -- VGA signals + signal vga_clk_ena : std_logic; signal vga_hsync : std_logic; signal vga_vsync : std_logic; signal vga_hblank : std_logic; @@ -213,6 +226,7 @@ begin cvbs_clk_ena <= toggle; toggle := not toggle; end if; + vga_clk_ena <= clk_ena; end if; end process PROC_CLOCKS; @@ -229,7 +243,7 @@ begin vga_vsync <= '1'; vga_hblank <= '0'; - elsif rising_edge (clk) and clk_ena = '1' then + elsif rising_edge (clk) and vga_clk_ena = '1' then -- start hsync when cvbs comes out of vblank if vga_vblank_r = '1' and vga_vblank = '0' then @@ -273,7 +287,7 @@ begin end if; end process; - -- generate horizontal timing for CVBS + -- generate horizontal timing f or CVBS -- generate line buffer address for writing CVBS char_d_o PROC_CVBS : process (clk, reset) variable h_count : integer range 0 to H_TOTAL_PER_LINE; @@ -387,9 +401,9 @@ begin active_h_count := (others => '0'); elsif h_count = H_LEFT_BORDER then cvbs_hblank <= '0'; - active_h_start <= '1'; elsif h_count = H_VIDEO then cvbs_hblank <= '1'; + active_h_start <= '1'; active_h_count := active_h_count + 1; elsif h_count = H_RIGHT_BORDER then null; @@ -421,15 +435,15 @@ begin cvbs_hblank_r := cvbs_hblank; if an_g_s = '0' then - lookup(4 downto 0) <= active_h_count(7 downto 3) + 1; + lookup(4 downto 0) <= active_h_count(7 downto 3); videoaddr <= videoaddr_base(12 downto 5) & lookup(4 downto 0); else case gm is --lookupaddr when "000" | "001" | "011" | "101" => - lookup(3 downto 0) <= active_h_count(7 downto 4) + 1; + lookup(3 downto 0) <= active_h_count(7 downto 4); videoaddr <= videoaddr_base(12 downto 4) & lookup(3 downto 0); when "010" | "100" | "110" | "111" => - lookup(4 downto 0) <= active_h_count(7 downto 3) + 1; + lookup(4 downto 0) <= active_h_count(7 downto 3); videoaddr <= videoaddr_base(12 downto 5) & lookup(4 downto 0); when others => null; @@ -615,7 +629,8 @@ begin if CVBS_NOT_VGA then if cvbs_clk_ena = '1' then if cvbs_hblank = '0' and cvbs_vblank = '0' then - map_palette (vga_char_d_o, r, g, b); + --map_palette (vga_char_d_o, r, g, b); + map_palette (pixel_char_d_o,r,g,b); else r := (others => '0'); g := (others => '0'); @@ -670,11 +685,13 @@ begin vsync <= cvbs_vsync; hblank <= cvbs_hblank; vblank <= cvbs_vblank; + pixel_clock<=cvbs_clk_ena; else hsync <= vga_hsync; vsync <= vga_vsync; hblank <= not vga_hborder; vblank <= not cvbs_vborder; + pixel_clock<=vga_clk_ena; end if; end process PROC_OUTPUT; diff --git a/rtl/T65/T65.vhd b/rtl/T65/T65.vhd index b9fa335..991236f 100644 --- a/rtl/T65/T65.vhd +++ b/rtl/T65/T65.vhd @@ -1,6 +1,10 @@ -- **** -- T65(b) core. In an effort to merge and maintain bug fixes .... -- +-- Ver 315 SzGy April 2020 +-- Reduced the IRQ detection delay when RDY is not asserted (NMI?) +-- Undocumented opcodes behavior change during not RDY and page boundary crossing (VICE tests - cpu/sha, cpu/shs, cpu/shxy) +-- -- Ver 313 WoS January 2015 -- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in -- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D @@ -130,6 +134,8 @@ library IEEE; entity T65 is port( Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + BCD_en : in std_logic := '1'; -- '0' => 2A03/2A07, '1' => others + Res_n : in std_logic; Enable : in std_logic; Clk : in std_logic; @@ -152,7 +158,8 @@ entity T65 is DO : out std_logic_vector(7 downto 0); -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB) Regs : out std_logic_vector(63 downto 0); - DEBUG : out T_t65_dbg + DEBUG : out T_t65_dbg; + NMI_ack : out std_logic ); end T65; @@ -175,7 +182,10 @@ architecture rtl of T65 is signal IR : std_logic_vector(7 downto 0); signal MCycle : std_logic_vector(2 downto 0); + signal DO_r : std_logic_vector(7 downto 0); + signal Mode_r : std_logic_vector(1 downto 0); + signal BCD_en_r : std_logic; signal ALU_Op_r : T_ALU_Op; signal Write_Data_r : T_Write_Data; signal Set_Addr_To_r : T_Set_Addr_To; @@ -208,6 +218,7 @@ architecture rtl of T65 is signal Write_Data : T_Write_Data; signal Jump : std_logic_vector(1 downto 0); signal BAAdd : std_logic_vector(1 downto 0); + signal BAQuirk : std_logic_vector(1 downto 0); signal BreakAtNA : std_logic; signal ADAdd : std_logic; signal AddY : std_logic; @@ -230,12 +241,15 @@ architecture rtl of T65 is signal Res_n_i : std_logic; signal Res_n_d : std_logic; + signal rdy_mod : std_logic; -- RDY signal turned off during the instruction signal really_rdy : std_logic; signal WRn_i : std_logic; signal NMI_entered : std_logic; begin + NMI_ack <= NMIAct; + -- gate Rdy with read/write to make an "OK, it's really OK to stop the processor really_rdy <= Rdy or not(WRn_i); Sync <= '1' when MCycle = "000" else '0'; @@ -265,6 +279,7 @@ begin IR => IR, MCycle => MCycle, P => P, + Rdy_mod => rdy_mod, --outputs LCycle => LCycle, ALU_Op => ALU_Op, @@ -273,6 +288,7 @@ begin Write_Data => Write_Data, Jump => Jump, BAAdd => BAAdd, + BAQuirk => BAQuirk, BreakAtNA => BreakAtNA, ADAdd => ADAdd, AddY => AddY, @@ -296,6 +312,7 @@ begin alu : entity work.T65_ALU port map( Mode => Mode_r, + BCD_en => BCD_en_r, Op => ALU_Op_r, BusA => BusA_r, BusB => BusB, @@ -327,6 +344,7 @@ begin DBR <= (others => '0'); Mode_r <= (others => '0'); + BCD_en_r <= '1'; ALU_Op_r <= ALU_OP_BIT; Write_Data_r <= Write_Data_DL; Set_Addr_To_r <= Set_Addr_To_PBR; @@ -338,6 +356,13 @@ begin elsif Clk'event and Clk = '1' then if (Enable = '1') then + -- some instructions behavior changed by the Rdy line. Detect this at the correct cycles. + if MCycle = "000" then + rdy_mod <= '0'; + elsif ((MCycle = "011" and IR /= x"93") or (MCycle = "100" and IR = x"93")) and Rdy = '0' then + rdy_mod <= '1'; + end if; + if (really_rdy = '1') then WRn_i <= not Write or RstCycle; @@ -349,6 +374,7 @@ begin if MCycle = "000" then Mode_r <= Mode; + BCD_en_r <= BCD_en; if IRQCycle = '0' and NMICycle = '0' then PC <= PC + 1; @@ -376,7 +402,7 @@ begin if Inc_S = '1' then S <= S + 1; end if; - if Dec_S = '1' and RstCycle = '0' then + if Dec_S = '1' and (RstCycle = '0' or Mode="00") then -- 6502 only? S <= S - 1; end if; @@ -463,9 +489,6 @@ begin --This should happen after P has been pushed to stack tmpP(Flag_I) := '1'; end if; - if SO_n_o = '1' and SO_n = '0' then - tmpP(Flag_V) := '1'; - end if; if RstCycle = '1' then tmpP(Flag_I) := '1'; tmpP(Flag_D) := '0'; @@ -474,16 +497,24 @@ begin P<=tmpP;--new way - SO_n_o <= SO_n; - if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works... - IRQ_n_o <= IRQ_n; - end if; + end if; + + -- detect irq even if not rdy + if IR(4 downto 0)/="10000" or Jump/="01" or really_rdy = '0' then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works... + IRQ_n_o <= IRQ_n; end if; -- detect nmi even if not rdy if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works... NMI_n_o <= NMI_n; end if; end if; + -- act immediately on SO pin change + -- The signal is sampled on the trailing edge of phi1 and must be externally synchronized (from datasheet) + SO_n_o <= SO_n; + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + end if; end process; @@ -505,8 +536,8 @@ begin DL <= (others => '0'); elsif Clk'event and Clk = '1' then if (Enable = '1') then - NMI_entered <= '0'; if (really_rdy = '1') then + NMI_entered <= '0'; BusA_r <= BusA; BusB <= DI; @@ -526,7 +557,13 @@ begin when "11" => -- BA Adj if BAL(8) = '1' then - BAH <= std_logic_vector(unsigned(BAH) + 1); + -- Handle quirks with some undocumented opcodes crossing page boundary + case BAQuirk is + when "00" => BAH <= std_logic_vector(unsigned(BAH) + 1); -- no quirk + when "01" => BAH <= std_logic_vector(unsigned(BAH) + 1) and DO_r; + when "10" => BAH <= DO_r; + when others => null; + end case; end if; when others => end case; @@ -604,8 +641,10 @@ begin -- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does. PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P; + DO <= DO_r; + with Write_Data_r select - DO <= + DO_r <= DL when Write_Data_DL, ABC(7 downto 0) when Write_Data_ABC, X(7 downto 0) when Write_Data_X, diff --git a/rtl/T65/T65_ALU.vhd b/rtl/T65/T65_ALU.vhd index c076ab0..a3613ba 100644 --- a/rtl/T65/T65_ALU.vhd +++ b/rtl/T65/T65_ALU.vhd @@ -57,6 +57,7 @@ use work.T65_Pack.all; entity T65_ALU is port( Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + BCD_en : in std_logic; Op : in T_ALU_OP; BusA : in std_logic_vector(7 downto 0); BusB : in std_logic_vector(7 downto 0); @@ -83,7 +84,7 @@ architecture rtl of T65_ALU is begin - process (P_In, BusA, BusB) + process (P_In, BusA, BusB, BCD_en) variable AL : unsigned(6 downto 0); variable AH : unsigned(6 downto 0); variable C : std_logic; @@ -102,7 +103,7 @@ begin ADC_Z <= '0'; end if; - if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then AL(6 downto 1) := AL(6 downto 1) + 6; end if; @@ -116,7 +117,7 @@ begin if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on - if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then AH(6 downto 1) := AH(6 downto 1) + 6; end if; @@ -125,7 +126,7 @@ begin ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); end process; - process (Op, P_In, BusA, BusB) + process (Op, P_In, BusA, BusB, BCD_en) variable AL : unsigned(6 downto 0); variable AH : unsigned(5 downto 0); variable C : std_logic; @@ -165,7 +166,7 @@ begin SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); - if P_In(Flag_D) = '1' then + if P_In(Flag_D) = '1' and BCD_en = '1' then if AL(5) = '1' then AL(5 downto 1) := AL(5 downto 1) - 6; end if; @@ -180,16 +181,16 @@ begin process (Op, P_In, BusA, BusB, ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, - SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q, - SBX_Q) + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q, + SBX_Q, BCD_en) variable Q_t : std_logic_vector(7 downto 0); variable Q2_t : std_logic_vector(7 downto 0); begin -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC P_Out <= P_In; - Q_t := BusA; - Q2_t := BusA; + Q_t := BusA; + Q2_t := BusA; case Op is when ALU_OP_OR=> Q_t := BusA or BusB; @@ -226,7 +227,7 @@ begin Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1)); P_Out(Flag_V) <= Q_t(5) xor Q_t(6); Q2_t := Q_t; - if P_In(Flag_D)='1' then + if P_In(Flag_D)='1' and BCD_en = '1' then if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6"); end if; diff --git a/rtl/T65/T65_MCode.vhd b/rtl/T65/T65_MCode.vhd index 867e0b8..a0500df 100644 --- a/rtl/T65/T65_MCode.vhd +++ b/rtl/T65/T65_MCode.vhd @@ -61,6 +61,7 @@ entity T65_MCode is IR : in std_logic_vector(7 downto 0); MCycle : in T_Lcycle; P : in std_logic_vector(7 downto 0); + Rdy_mod : in std_logic; LCycle : out T_Lcycle; ALU_Op : out T_ALU_Op; Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX @@ -68,6 +69,7 @@ entity T65_MCode is Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BAQuirk : out std_logic_vector(1 downto 0); -- None,And,Copy BreakAtNA : out std_logic; ADAdd : out std_logic; AddY : out std_logic; @@ -106,7 +108,7 @@ begin not P(Flag_Z) when "110", P(Flag_Z) when others; - process (IR, MCycle, P, Branch, Mode) + process (IR, MCycle, P, Branch, Mode, Rdy_mod) begin lCycle <= Cycle_1; Set_BusA_To <= Set_BusA_To_ABC; @@ -114,6 +116,7 @@ begin Write_Data <= Write_Data_DL; Jump <= (others => '0'); BAAdd <= "00"; + BAQuirk <= "00"; BreakAtNA <= '0'; ADAdd <= '0'; PCAdd <= '0'; @@ -140,14 +143,22 @@ begin when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C Set_BusA_To <= Set_BusA_To_Y; if IR(4 downto 2)="111" then -- SYA ($9C) - Write_Data <= Write_Data_YB; + if Rdy_mod = '0' then + Write_Data <= Write_Data_YB; + else + Write_Data <= Write_Data_Y; + end if; else Write_Data <= Write_Data_Y; end if; when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E Set_BusA_To <= Set_BusA_To_X; if IR(4 downto 2)="111" then -- SXA ($9E) - Write_Data <= Write_Data_XB; + if Rdy_mod = '0' then + Write_Data <= Write_Data_XB; + else + Write_Data <= Write_Data_X; + end if; else Write_Data <= Write_Data_X; end if; @@ -159,7 +170,11 @@ begin Set_BusA_To <= Set_BusA_To_ABC; end if; if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B) - Write_Data <= Write_Data_AXB; + if Rdy_mod = '0' then + Write_Data <= Write_Data_AXB; + else + Write_Data <= Write_Data_AX; + end if; else Write_Data <= Write_Data_AX; end if; @@ -843,6 +858,9 @@ begin BAAdd <= "11"; -- BA Adj if IR(7 downto 5) = "100" then Write <= '1'; + if IR(3 downto 0) = x"3" then + BAQuirk <= "10"; -- COPY + end if; elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests) BreakAtNA <= '1'; end if; @@ -956,6 +974,9 @@ begin BAAdd <= "11"; -- BA adj if IR(7 downto 5) = "100" then--99/9b Write <= '1'; + if IR(3 downto 0) = x"B" then + BAQuirk <= "01"; -- AND + end if; elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests) BreakAtNA <= '1'; end if; @@ -1045,8 +1066,13 @@ begin Set_Addr_To <= Set_Addr_To_BA; when Cycle_3 => BAAdd <= "11"; -- BA adj - if IR(7 downto 5) = "100" then -- ($9E,$9F) + if IR(7 downto 5) = "100" then -- ($9C,$9D,$9E,$9F) Write <= '1'; + case IR(1 downto 0) is + when "00"|"10" => BAQuirk <= "01"; -- AND + when "11" => BAQuirk <= "10"; -- COPY + when others => null; + end case; else BreakAtNA <= '1'; end if; diff --git a/rtl/T65/T65_Pack.vhd b/rtl/T65/T65_Pack.vhd index f56c343..3adb40b 100644 --- a/rtl/T65/T65_Pack.vhd +++ b/rtl/T65/T65_Pack.vhd @@ -177,4 +177,4 @@ package body T65_Pack is end case; end CycleNext; -end T65_Pack; +end T65_Pack; \ No newline at end of file diff --git a/rtl/T65/t65.qip b/rtl/T65/t65.qip new file mode 100644 index 0000000..b165455 --- /dev/null +++ b/rtl/T65/t65.qip @@ -0,0 +1,4 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_Pack.vhd ] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_ALU.vhd ] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_MCode.vhd ] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65.vhd ] diff --git a/rtl/pll.bsf b/rtl/pll.bsf new file mode 100644 index 0000000..3190e94 --- /dev/null +++ b/rtl/pll.bsf @@ -0,0 +1,104 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 224) + (text "pll" (rect 74 -1 81 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 208 20 220)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) + (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) + (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 48 112)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 112 72)(line_width 1)) + ) + (port + (pt 160 112) + (output) + (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) + (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) + (line (pt 160 112)(pt 112 112)(line_width 1)) + ) + (port + (pt 160 152) + (output) + (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) + (line (pt 160 152)(pt 112 152)(line_width 1)) + ) + (port + (pt 160 192) + (output) + (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) + (text "locked" (rect 127 181 163 192)(font "Arial" (font_size 8))) + (line (pt 160 192)(pt 112 192)(line_width 1)) + ) + (drawing + (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) + (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) + (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) + (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) + (text "locked" (rect 113 163 262 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 82 187 200 384)(font "Arial" (color 0 0 0))) + (text " altera_pll " (rect 118 208 308 426)(font "Arial" )) + (line (pt 48 32)(pt 112 32)(line_width 1)) + (line (pt 112 32)(pt 112 208)(line_width 1)) + (line (pt 48 208)(pt 112 208)(line_width 1)) + (line (pt 48 32)(pt 48 208)(line_width 1)) + (line (pt 49 52)(pt 49 76)(line_width 1)) + (line (pt 50 52)(pt 50 76)(line_width 1)) + (line (pt 49 92)(pt 49 116)(line_width 1)) + (line (pt 50 92)(pt 50 116)(line_width 1)) + (line (pt 111 52)(pt 111 76)(line_width 1)) + (line (pt 110 52)(pt 110 76)(line_width 1)) + (line (pt 111 92)(pt 111 116)(line_width 1)) + (line (pt 110 92)(pt 110 116)(line_width 1)) + (line (pt 111 132)(pt 111 156)(line_width 1)) + (line (pt 110 132)(pt 110 156)(line_width 1)) + (line (pt 111 172)(pt 111 196)(line_width 1)) + (line (pt 110 172)(pt 110 196)(line_width 1)) + (line (pt 0 0)(pt 160 0)(line_width 1)) + (line (pt 160 0)(pt 160 224)(line_width 1)) + (line (pt 0 224)(pt 160 224)(line_width 1)) + (line (pt 0 0)(pt 0 224)(line_width 1)) + ) +) diff --git a/rtl/pll.cmp b/rtl/pll.cmp new file mode 100644 index 0000000..c906603 --- /dev/null +++ b/rtl/pll.cmp @@ -0,0 +1,11 @@ + component pll is + port ( + refclk : in std_logic := 'X'; -- clk + rst : in std_logic := 'X'; -- reset + outclk_0 : out std_logic; -- clk + outclk_1 : out std_logic; -- clk + outclk_2 : out std_logic; -- clk + locked : out std_logic -- export + ); + end component pll; + diff --git a/rtl/pll.ppf b/rtl/pll.ppf new file mode 100644 index 0000000..9e00f78 --- /dev/null +++ b/rtl/pll.ppf @@ -0,0 +1,15 @@ + + + + + + + + + + + diff --git a/rtl/pll.qip b/rtl/pll.qip index 4228ebf..363f585 100644 --- a/rtl/pll.qip +++ b/rtl/pll.qip @@ -1,5 +1,5 @@ set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0" set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" @@ -11,19 +11,18 @@ set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NA set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" @@ -36,17 +35,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NDIuOTU0::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjIw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" @@ -54,11 +53,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MzAw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" @@ -66,11 +65,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MzI=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NTkw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" @@ -80,9 +79,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTY=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MzAw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" @@ -90,11 +89,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::NDIuOTU0::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTg5::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MjIw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" @@ -257,16 +256,16 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NDIuOTU0NTQ1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MzEuNTAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MjUuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTYuMDE2OTQ5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MzIuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" @@ -318,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw4LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjUsMjUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTYsMTYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTMsMTIsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxLDIwLDQwMDAsODAwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OTUsOTQsNSw1LGZhbHNlLGZhbHNlLHRydWUsZmFsc2UsMTEsMTEsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTUsMTUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMzAsMjksMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxLDIwLDEyMDAwLDk0NS4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" @@ -334,5 +333,5 @@ set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qi set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"] set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" diff --git a/rtl/pll.sip b/rtl/pll.sip new file mode 100644 index 0000000..2b9d2f1 --- /dev/null +++ b/rtl/pll.sip @@ -0,0 +1,6 @@ +set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_pll" -name SPD_FILE [file join $::quartus(sip_path) "pll.spd"] + +set_global_assignment -library "lib_pll" -name MISC_FILE [file join $::quartus(sip_path) "pll_sim/pll.vo"] diff --git a/rtl/pll.spd b/rtl/pll.spd new file mode 100644 index 0000000..f0bef84 --- /dev/null +++ b/rtl/pll.spd @@ -0,0 +1,6 @@ + + + + + + diff --git a/rtl/pll.v b/rtl/pll.v index 17c89be..6ec3b9d 100644 --- a/rtl/pll.v +++ b/rtl/pll.v @@ -1,8 +1,8 @@ -// megafunction wizard: %Altera PLL v17.1% +// megafunction wizard: %Altera PLL v17.0% // GENERATION: XML // pll.v -// Generated using ACDS version 17.1 593 +// Generated using ACDS version 17.0 602 `timescale 1 ps / 1 ps module pll ( @@ -11,7 +11,6 @@ module pll ( output wire outclk_0, // outclk0.clk output wire outclk_1, // outclk1.clk output wire outclk_2, // outclk2.clk - output wire outclk_3, // outclk3.clk output wire locked // locked.export ); @@ -21,7 +20,6 @@ module pll ( .outclk_0 (outclk_0), // outclk0.clk .outclk_1 (outclk_1), // outclk1.clk .outclk_2 (outclk_2), // outclk2.clk - .outclk_3 (outclk_3), // outclk3.clk .locked (locked) // locked.export ); @@ -32,7 +30,7 @@ endmodule // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // ************************************************************ -// Copyright (C) 1991-2020 Altera Corporation +// Copyright (C) 1991-2022 Altera Corporation // Any megafunction design, and related net list (encrypted or decrypted), // support information, device programming or simulation file, and any other // associated documentation or information provided by Altera or a partner @@ -52,11 +50,11 @@ endmodule // their respective licensors. No other licenses, including any licenses // needed under any third party's intellectual property, are provided herein. //--> -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -67,12 +65,12 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -81,7 +79,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -90,7 +88,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -108,7 +106,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/rtl/pll/pll_0002.v b/rtl/pll/pll_0002.v index 22a5da7..540474d 100644 --- a/rtl/pll/pll_0002.v +++ b/rtl/pll/pll_0002.v @@ -16,9 +16,6 @@ module pll_0002( // interface 'outclk2' output wire outclk_2, - // interface 'outclk3' - output wire outclk_3, - // interface 'locked' output wire locked ); @@ -27,17 +24,17 @@ module pll_0002( .fractional_vco_multiplier("false"), .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), - .number_of_clocks(4), - .output_clock_frequency0("100.000000 MHz"), + .number_of_clocks(3), + .output_clock_frequency0("42.954545 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), - .output_clock_frequency1("16.000000 MHz"), + .output_clock_frequency1("31.500000 MHz"), .phase_shift1("0 ps"), .duty_cycle1(50), - .output_clock_frequency2("25.000000 MHz"), + .output_clock_frequency2("16.016949 MHz"), .phase_shift2("0 ps"), .duty_cycle2(50), - .output_clock_frequency3("32.000000 MHz"), + .output_clock_frequency3("0 MHz"), .phase_shift3("0 ps"), .duty_cycle3(50), .output_clock_frequency4("0 MHz"), @@ -86,7 +83,7 @@ module pll_0002( .pll_subtype("General") ) altera_pll_i ( .rst (rst), - .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), + .outclk ({outclk_2, outclk_1, outclk_0}), .locked (locked), .fboutclk ( ), .fbclk (1'b0), diff --git a/rtl/pll_sim.f b/rtl/pll_sim.f new file mode 100644 index 0000000..8c0e05b --- /dev/null +++ b/rtl/pll_sim.f @@ -0,0 +1 @@ +pll_sim/pll.vo diff --git a/rtl/pll_sim/aldec/rivierapro_setup.tcl b/rtl/pll_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..e7fcd77 --- /dev/null +++ b/rtl/pll_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,278 @@ + +# (C) 2001-2022 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 17.0 602 win32 2022.01.09.09:43:02 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# pll +# +# Altera recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Altera simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR