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Updates for the tranZPUter SW v2.2 on the MZ800

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This commit is contained in:
Philip Smart
2021-03-07 23:31:30 +00:00
parent 27cb6fc79e
commit f72a4e6be6
23 changed files with 8449 additions and 609 deletions
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31
CPLD/SW/build/tranZPUterSW.qsf
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@@ -56,13 +56,18 @@ set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
# Z80 Address Bus
# ===============
set_location_assignment PIN_108 -to Z80_HI_ADDR[18]
set_location_assignment PIN_32 -to Z80_HI_ADDR[23]
set_location_assignment PIN_42 -to Z80_HI_ADDR[22]
set_location_assignment PIN_44 -to Z80_HI_ADDR[21]
set_location_assignment PIN_40 -to Z80_HI_ADDR[20]
set_location_assignment PIN_39 -to Z80_HI_ADDR[19]
set_location_assignment PIN_107 -to Z80_HI_ADDR[18]
set_location_assignment PIN_102 -to Z80_HI_ADDR[17]
set_location_assignment PIN_107 -to Z80_HI_ADDR[16]
set_location_assignment PIN_110 -to Z80_HI_ADDR[15]
set_location_assignment PIN_111 -to Z80_HI_ADDR[14]
set_location_assignment PIN_112 -to Z80_HI_ADDR[13]
set_location_assignment PIN_114 -to Z80_HI_ADDR[12]
set_location_assignment PIN_108 -to Z80_HI_ADDR[16]
set_location_assignment PIN_110 -to Z80_RA_ADDR[15]
set_location_assignment PIN_111 -to Z80_RA_ADDR[14]
set_location_assignment PIN_112 -to Z80_RA_ADDR[13]
set_location_assignment PIN_114 -to Z80_RA_ADDR[12]
set_location_assignment PIN_106 -to Z80_ADDR[15]
set_location_assignment PIN_103 -to Z80_ADDR[14]
set_location_assignment PIN_98 -to Z80_ADDR[13]
@@ -118,17 +123,17 @@ set_location_assignment PIN_65 -to SVCREQn
# ============
set_location_assignment PIN_41 -to CTL_WAITn
set_location_assignment PIN_38 -to CTL_RFSHn
set_location_assignment PIN_31 -to CTL_CLKSLCT
set_location_assignment PIN_55 -to CTL_MBSEL
set_location_assignment PIN_54 -to CTL_HALTn
set_location_assignment PIN_128 -to CTLCLK
set_location_assignment PIN_45 -to CTL_M1n
set_location_assignment PIN_55 -to CTL_BUSACKn
set_location_assignment PIN_31 -to CTL_BUSACKn
set_location_assignment PIN_70 -to CTL_BUSRQn
set_location_assignment PIN_32 -to Z80_MEM[4]
set_location_assignment PIN_42 -to Z80_MEM[3]
set_location_assignment PIN_44 -to Z80_MEM[2]
set_location_assignment PIN_40 -to Z80_MEM[1]
set_location_assignment PIN_39 -to Z80_MEM[0]
#set_location_assignment PIN_32 -to Z80_MEM[4]
#set_location_assignment PIN_42 -to Z80_MEM[3]
#set_location_assignment PIN_44 -to Z80_MEM[2]
#set_location_assignment PIN_40 -to Z80_MEM[1]
#set_location_assignment PIN_39 -to Z80_MEM[0]
# Z80 Control signals.
# ====================

90
CPLD/SW/build/tranZPUterSW_constraints.sdc
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@@ -75,36 +75,15 @@ create_clock -name {INCLK} -period 62.500 -waveform { 0.000 31.250 } [ get_po
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}]
@@ -118,7 +97,7 @@ set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_CLKSLCT}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}]
@@ -133,47 +112,12 @@ set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS
#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[12]}]
#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VADDR[13]}]
#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {OUTDATA[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {OUTDATA[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {OUTDATA[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {OUTDATA[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {OUTDATA[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[4]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[5]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[6]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[7]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[8]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[9]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[10]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[14]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[14]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[0]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[1]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[2]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[3]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MEM[4]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}]
@@ -208,12 +152,14 @@ set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For both configurations.
set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[4]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[3]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[2]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[1]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[0]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
# For the video module interconnect clock.
set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {INCLK}]

959
CPLD/SW/tranZPUterSW.vhd
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File diff suppressed because it is too large Load Diff

153
CPLD/SW/tranZPUterSW_Toplevel.vhd
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@@ -11,6 +11,7 @@
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- <ar 2021 - Synchronize with SW700 development in order to progress MZ800 adaptation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
@@ -36,56 +37,56 @@ use altera.altera_syn_attributes.all;
entity tranZPUterSW is
port (
-- Z80 Address and Data.
Z80_HI_ADDR : out std_logic_vector(18 downto 12);
Z80_ADDR : inout std_logic_vector(15 downto 0);
Z80_DATA : inout std_logic_vector(7 downto 0);
Z80_HI_ADDR : inout std_logic_vector(23 downto 16); -- Hi address. These are the upper bank bits allowing 512K of address space. They are directly set by the K64F when accessing RAM or FPGA and set by the FPGA according to memory mode.
Z80_RA_ADDR : out std_logic_vector(15 downto 12); -- Row address - RAM is subdivided into 4K blocks which can be remapped as needed. This is required for the MZ80B emulation where memory changes location according to mode.
Z80_ADDR : inout std_logic_vector(15 downto 0);
Z80_DATA : inout std_logic_vector(7 downto 0);
-- Z80 Control signals.
Z80_BUSRQn : out std_logic;
Z80_BUSACKn : in std_logic;
Z80_INTn : inout std_logic;
Z80_IORQn : in std_logic;
Z80_MREQn : inout std_logic;
Z80_NMIn : inout std_logic;
Z80_RDn : in std_logic;
Z80_WRn : in std_logic;
Z80_RESETn : in std_logic;
Z80_HALTn : in std_logic;
Z80_WAITn : out std_logic;
Z80_M1n : in std_logic;
Z80_RFSHn : in std_logic;
Z80_CLK : out std_logic;
Z80_BUSRQn : out std_logic;
Z80_BUSACKn : in std_logic;
Z80_INTn : inout std_logic;
Z80_IORQn : in std_logic;
Z80_MREQn : inout std_logic;
Z80_NMIn : inout std_logic;
Z80_RDn : in std_logic;
Z80_WRn : in std_logic;
Z80_RESETn : in std_logic;
Z80_HALTn : in std_logic;
Z80_WAITn : out std_logic;
Z80_M1n : in std_logic;
Z80_RFSHn : in std_logic;
Z80_CLK : out std_logic;
-- K64F control signals.
CTL_BUSACKn : in std_logic;
CTL_BUSRQn : in std_logic;
CTL_HALTn : out std_logic;
CTL_M1n : out std_logic;
CTL_RFSHn : out std_logic;
CTL_WAITn : in std_logic;
SVCREQn : out std_logic;
Z80_MEM : out std_logic_vector(4 downto 0);
CTL_MBSEL : in std_logic; -- Select mainboard, 1 = mainboard, 0 = tranzputer bus.
CTL_BUSRQn : in std_logic;
CTL_BUSACKn : out std_logic; -- Combined BUSACK signal to the K64F
CTL_HALTn : out std_logic;
CTL_M1n : out std_logic;
CTL_RFSHn : out std_logic;
CTL_WAITn : in std_logic;
SVCREQn : out std_logic;
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn : out std_logic;
SYS_BUSRQn : in std_logic;
SYS_WAITn : in std_logic;
SYS_WRn : out std_logic;
SYS_RDn : out std_logic;
SYS_BUSACKn : out std_logic;
SYS_BUSRQn : in std_logic;
SYS_WAITn : in std_logic;
SYS_WRn : out std_logic;
SYS_RDn : out std_logic;
-- RAM control.
RAM_CSn : out std_logic;
RAM_OEn : out std_logic;
RAM_WEn : out std_logic;
RAM_CSn : out std_logic;
RAM_OEn : out std_logic;
RAM_WEn : out std_logic;
-- Graphics Board I/O and Memory Select.
INCLK : in std_logic;
OUTDATA : out std_logic_vector(3 downto 0);
INCLK : in std_logic;
OUTDATA : out std_logic_vector(3 downto 0);
-- Clocks, system and K64F generated.
SYSCLK : in std_logic;
CTLCLK : in std_logic;
CTL_CLKSLCT : out std_logic
SYSCLK : in std_logic;
CTLCLK : in std_logic
);
END entity;
@@ -99,56 +100,56 @@ begin
--)
port map
(
Z80_HI_ADDR => Z80_HI_ADDR,
Z80_ADDR => Z80_ADDR,
Z80_DATA => Z80_DATA,
Z80_HI_ADDR => Z80_HI_ADDR,
Z80_RA_ADDR => Z80_RA_ADDR,
Z80_ADDR => Z80_ADDR,
Z80_DATA => Z80_DATA,
-- Z80 Control signals.
Z80_BUSRQn => Z80_BUSRQn,
Z80_BUSACKn => Z80_BUSACKn,
Z80_INTn => Z80_INTn,
Z80_IORQn => Z80_IORQn,
Z80_MREQn => Z80_MREQn,
Z80_NMIn => Z80_NMIn,
Z80_RDn => Z80_RDn,
Z80_WRn => Z80_WRn,
Z80_RESETn => Z80_RESETn,
Z80_HALTn => Z80_HALTn,
Z80_WAITn => Z80_WAITn,
Z80_M1n => Z80_M1n,
Z80_RFSHn => Z80_RFSHn,
Z80_CLK => Z80_CLK,
Z80_BUSRQn => Z80_BUSRQn,
Z80_BUSACKn => Z80_BUSACKn,
Z80_INTn => Z80_INTn,
Z80_IORQn => Z80_IORQn,
Z80_MREQn => Z80_MREQn,
Z80_NMIn => Z80_NMIn,
Z80_RDn => Z80_RDn,
Z80_WRn => Z80_WRn,
Z80_RESETn => Z80_RESETn,
Z80_HALTn => Z80_HALTn,
Z80_WAITn => Z80_WAITn,
Z80_M1n => Z80_M1n,
Z80_RFSHn => Z80_RFSHn,
Z80_CLK => Z80_CLK,
-- K64F control signals.
CTL_BUSACKn => CTL_BUSACKn,
CTL_BUSRQn => CTL_BUSRQn,
CTL_HALTn => CTL_HALTn,
CTL_M1n => CTL_M1n,
CTL_RFSHn => CTL_RFSHn,
CTL_WAITn => CTL_WAITn,
SVCREQn => SVCREQn,
Z80_MEM => Z80_MEM,
CTL_MBSEL => CTL_MBSEL,
CTL_BUSRQn => CTL_BUSRQn,
CTL_BUSACKn => CTL_BUSACKn,
CTL_HALTn => CTL_HALTn,
CTL_M1n => CTL_M1n,
CTL_RFSHn => CTL_RFSHn,
CTL_WAITn => CTL_WAITn,
SVCREQn => SVCREQn,
-- Mainboard signals which are blended with K64F signals to activate corresponding Z80 functionality.
SYS_BUSACKn => SYS_BUSACKn,
SYS_BUSRQn => SYS_BUSRQn,
SYS_WAITn => SYS_WAITn,
SYS_WRn => SYS_WRn,
SYS_RDn => SYS_RDn,
SYS_BUSACKn => SYS_BUSACKn,
SYS_BUSRQn => SYS_BUSRQn,
SYS_WAITn => SYS_WAITn,
SYS_WRn => SYS_WRn,
SYS_RDn => SYS_RDn,
-- RAM control.
RAM_CSn => RAM_CSn,
RAM_OEn => RAM_OEn,
RAM_WEn => RAM_WEn,
RAM_CSn => RAM_CSn,
RAM_OEn => RAM_OEn,
RAM_WEn => RAM_WEn,
-- Graphics Board I/O and Memory Select.
INCLK => INCLK,
OUTDATA => OUTDATA,
INCLK => INCLK,
OUTDATA => OUTDATA,
-- Clocks, system and K64F generated.
SYSCLK => SYSCLK,
CTLCLK => CTLCLK,
CTL_CLKSLCT => CTL_CLKSLCT
SYSCLK => SYSCLK,
CTLCLK => CTLCLK
);
end architecture;

52
CPLD/SW/tranZPUterSW_pkg.vhd
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@@ -5,12 +5,13 @@
-- Author(s): Philip Smart
-- Description: tranZPUter SW CPLD configuration file.
--
-- This module contains parameters for the CPLD in v2.1 of the tranZPUterSW project.
-- This module contains parameters for the CPLD in v2.1 - v2.2 of the tranZPUterSW project.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Mar 2021 - Updated to enable better compatibility with the Sharp MZ-800.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
@@ -68,12 +69,15 @@ package tranZPUterSW_pkg is
constant TZMM_CPM : integer := 06; -- CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_CPM2 : integer := 07; -- CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
-- Special case for 0000:003F (interrupt vectors) which resides in block 4, F3FE:F3FF & F7FE:F7FF (floppy disk paging vectors) which resides on the mainboard.
constant TZMM_ORIGMON : integer := 08; -- Original monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_COMPAT : integer := 08; -- Compatibility monitor mode, monitor ROM on mainboard, RAM on tranZPUter in Block 0 1000-CFFF.
constant TZMM_MZ700_0 : integer := 10; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
constant TZMM_MZ700_1 : integer := 11; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_2 : integer := 12; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
constant TZMM_MZ700_3 : integer := 13; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_MZ700_4 : integer := 14; -- MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
constant TZMM_FPGA : integer := 21; -- Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked.
constant TZMM_TZPUM : integer := 22; -- Everything in on mainboard, no access to tranZPUter memory.
constant TZMM_TZPU : integer := 23; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
constant TZMM_TZPU0 : integer := 24; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
constant TZMM_TZPU1 : integer := 25; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
constant TZMM_TZPU2 : integer := 26; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
@@ -83,11 +87,14 @@ package tranZPUterSW_pkg is
constant TZMM_TZPU6 : integer := 30; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
constant TZMM_TZPU7 : integer := 31; -- Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
------------------------------------------------------------
-- Configurable parameters.
------------------------------------------------------------
-- Target hardware.
constant CPLD_HOST_HW : integer := MODE_MZ80A;
constant CPLD_HOST_HW : integer := MODE_MZ800;
--constant CPLD_HOST_HW : integer := MODE_MZ80A;
-- Target video hardware.
constant CPLD_HAS_FPGA_VIDEO : std_logic := '1';
@@ -95,7 +102,7 @@ package tranZPUterSW_pkg is
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
-- Clock source for the secondary clock. If a K64F is installed the enable it otherwise use the onboard oscillator.
-- Clock source for the secondary clock. If a K64F is installed then enable it otherwise use the onboard oscillator.
--
constant USE_K64F_CTL_CLOCK : integer := 1;
@@ -111,6 +118,17 @@ package tranZPUterSW_pkg is
-- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
function clockTicks(period : in integer; clock : in integer) return integer;
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural;
------------------------------------------------------------
-- Records
------------------------------------------------------------
@@ -167,4 +185,30 @@ package body tranZPUterSW_pkg is
end if;
end function;
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
-- Function to return the value of a bit as an integer for array indexing etc.
function bit_to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
end package body;

133
CPLD/SW700/v1.2/tranZPUterSW700.vhd
View File

@@ -34,6 +34,9 @@
-- as there are a lot of pin and logic differences. The tranZPUter SW is still
-- under development so didnt make sense to share the same files and make
-- them conditional.
-- Mar 2021 - Better control of the external Asyn BUSRQ/BUSACK was needed, bringing in
-- the async K64F CTL_BUSRQ into the Z80 clocked domain and adjustment of
-- mux lines.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
@@ -82,7 +85,7 @@ entity cpld512 is
Z80_CLK : out std_logic;
-- K64F control signals.
CTL_BUSACKn : in std_logic;
CTL_BUSACKn : out std_logic;
CTL_BUSRQn : in std_logic;
CTL_HALTn : out std_logic;
CTL_M1n : out std_logic;
@@ -191,6 +194,8 @@ architecture rtl of cpld512 is
--
signal DISABLE_BUSn : std_logic; -- Signal to disable access to the mainboard (= 0) via the SYS_BUSACKn signal which tri-states the mainboard logic.
signal SYS_BUSACKni : std_logic := '0'; -- Signal to hold the current state of the SYS_BUSACKn signal used to activate/tri-state the mainboard logic.
signal CTL_BUSACKni : std_logic; -- Buffered BUSACK signal to the K64F to indicate it has control of the bus.
signal CTL_BUSRQni : std_logic; --
-- CPU Frequency select logic based on Flip Flops and gates.
signal SCK_CTLSELn : std_logic;
@@ -267,6 +272,13 @@ begin
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
--*[6:5] - R/W - Mainboard/CPU clock.
-- 000 = Sharp MZ80A 2MHz System Clock.
-- 001 = Sharp MZ80B 4MHz System Clock.
-- 010 = Sharp MZ700 3.54MHz System Clock.
-- 011 -111 = Reserved, defaults to 2MHz System Clock.
-- [7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
-- * = SW v2.2 MZ-80A version only, not used in other CPLD versions.
--
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPLD_CFGn, Z80_ADDR, Z80_DATA )
begin
@@ -275,7 +287,7 @@ begin
MODE_CPLD_SWITCH <= '0';
CPLD_CFG_DATA <= "00000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
elsif(Z80_CLKi'event and Z80_CLKi = '1') then
elsif(rising_edge(Z80_CLKi)) then
-- Write to config register.
if(CS_CPLD_CFGn = '0' and Z80_WRn = '0') then
@@ -293,7 +305,6 @@ begin
end if;
end process;
-- Memory mode latch. This latch stores the current memory mode (or Bank Paging Scheme) according to the running software.
--
MEMORYMODE: process( Z80_CLKi, Z80_RESETn, CS_MEM_CFGn, Z80_IORQn, Z80_WRn, Z80_ADDR, Z80_DATA )
@@ -581,14 +592,14 @@ begin
-- is not available, use the onboard oscillator.
--
CTLCLKSRC: if USE_K64F_CTL_CLOCK = 1 generate
CTLCLKi <= CTLCLK;
CTLCLKi <= CTLCLK;
else generate
process(Z80_RESETn, CTLCLK)
variable FREQDIVCTR : unsigned(3 downto 0);
begin
if Z80_RESETn = '0' then
FREQDIVCTR := (others => '0');
CTLCLKi <= '0';
CTLCLKi <= '0';
elsif CTLCLK'event and CTLCLK = '1' then
@@ -607,27 +618,27 @@ begin
-- high until the falling edge of the clock being switched into.
FFCLK1: process( SYSCLK, Z80_RESETn ) begin
if Z80_RESETn = '0' then
SYSCLK_Q <= '0';
SYSCLK_Q <= '0';
-- If the system clock goes active high, process the inputs and set the D-type output.
elsif( rising_edge(SYSCLK) ) then
if ((DISABLE_BUSn = '1' or MB_BUSRQn = '0' or SCK_CTLSELn = '1') and CTLCLK_Q = '1') then
SYSCLK_Q <= '0';
SYSCLK_Q <= '0';
else
SYSCLK_Q <= '1';
SYSCLK_Q <= '1';
end if;
end if;
end process;
FFCLK2: process( CTLCLKi, Z80_RESETn ) begin
if Z80_RESETn = '0' then
CTLCLK_Q <= '1';
CTLCLK_Q <= '1';
-- If the control clock goes active high, process the inputs and set the D-type output.
elsif( rising_edge(CTLCLKi) ) then
if ((DISABLE_BUSn = '0' and SCK_CTLSELn = '0') and SYSCLK_Q = '1') then
CTLCLK_Q <= '0';
CTLCLK_Q <= '0';
else
CTLCLK_Q <= '1';
CTLCLK_Q <= '1';
end if;
end if;
end process;
@@ -752,6 +763,9 @@ begin
-- 12 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
-- 13 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
-- 14 - MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
-- *21 - Access the FPGA memory by passing through the full 24bit Z80 address, typically from the K64F.
-- *22 - Access to the host mainboard 64K address space only.
-- *23 - Access all memory and IO on the tranZPUter board with the K64F addressing the full 512K RAM.
-- 24 - All memory and IO are on the tranZPUter board, 64K block 0 selected.
-- 25 - All memory and IO are on the tranZPUter board, 64K block 1 selected.
-- 26 - All memory and IO are on the tranZPUter board, 64K block 2 selected.
@@ -760,6 +774,8 @@ begin
-- 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected.
-- 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected.
-- 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected.
--
-- * = Only on SW-700 v1.3
MEMORYMGMT: process(Z80_ADDR, Z80_WRn, Z80_RDn, Z80_IORQn, Z80_MREQn, Z80_M1n, MEM_MODE_LATCH, SYS_BUSACKni, CS_VIDEOn, CS_VIDEO_IOn, CS_IO_DXXn, CS_IO_EXXn, CS_IO_FXXn, MODE_CPLD_MB_VIDEOn)
begin
@@ -1175,6 +1191,15 @@ begin
RAM_OEni <= '1';
end if;
-- Set 21 - Access the FPGA memory by passing through the full 24bit Z80 address, typically from the K64F.
when TZMM_FPGA =>
-- Set 22 - Access to the host mainboard 64K address space.
when TZMM_TZPUM =>
-- Set 23 - Access all memory and IO on the tranZPUter board with the K64F addressing the full 512K RAM.
when TZMM_TZPU =>
-- Set 24 - All memory and IO are on the tranZPUter board, 64K block 0 selected.
when TZMM_TZPU0 =>
DISABLE_BUSn <= '0';
@@ -1289,6 +1314,26 @@ begin
end if;
end process;
-- A process to bring the external K64F control signals into this domain. The K64F can request the bus asynchronously so it is important the system state is known before
-- passing the request onto the internal processes.
--
SIGNALSYNC: process( Z80_CLKi, Z80_RESETn, CTL_BUSRQn )
begin
if(Z80_RESETn = '0') then
CTL_BUSRQni <= '1';
elsif rising_edge(Z80_CLKi) then
-- When a Bus request comes in, ensure that the state is idle before passing it on as this signal is used to enable/disable or mux control other signals.
if CTL_BUSRQn = '0' then
CTL_BUSRQni <= '0';
end if;
if CTL_BUSRQn = '1' then
CTL_BUSRQni <= '1';
end if;
end if;
end process;
-- Latch output so the K64F can determine current status.
Z80_MEM <= MEM_MODE_LATCH(4 downto 0);
@@ -1298,7 +1343,6 @@ begin
CTL_CLKSLCT <= SYSCLK_Q;
Z80_CLK <= Z80_CLKi;
-- Wait states, added by the mainboard video circuitry, FPGA video circuitry or the K64F.
Z80_WAITn <= '0' when SYS_WAITn = '0' or CTL_WAITn = '0' or (VWAITn = '0' and MODE_CPLD_VIDEO_WAIT = '1') or MB_WAITn = '0'
else '1';
@@ -1314,12 +1358,17 @@ begin
-- Bus control logic.
SYS_BUSACKni <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else
'0' when DISABLE_BUSn = '0' or (KEY_SUBSTITUTE = '1' and Z80_MREQn = '0') or (Z80_BUSACKn = '0' and CTL_BUSACKn = '0')
'0' when DISABLE_BUSn = '0' or (KEY_SUBSTITUTE = '1' and Z80_MREQn = '0') or (Z80_BUSACKn = '0' and CTL_BUSACKni = '0')
else '1';
SYS_BUSACKn <= SYS_BUSACKni;
Z80_BUSRQn <= '0' when SYS_BUSRQn = '0' or CTL_BUSRQn = '0' or MB_BUSRQn = '0'
Z80_BUSRQn <= '0' when SYS_BUSRQn = '0' or CTL_BUSRQni = '0' or MB_BUSRQn = '0'
else '1';
-- Acknowlegde to the K64F it has bus control.
CTL_BUSACKni <= '0' when CTL_BUSRQni = '0' and Z80_BUSACKn = '0'
else '1';
CTL_BUSACKn <= CTL_BUSACKni;
-- Register read values.
CLK_STATUS_DATA <= "0000000" & SYSCLK_Q;
MEM_MODE_DATA <= "000" & MEM_MODE_LATCH(4 downto 0);
@@ -1364,7 +1413,7 @@ begin
else
MEM_MODE_DATA when CS_MEM_CFGn = '0' and Z80_RDn = '0' -- Read the memory mode latch.
else
(others => 'Z') when Z80_BUSACKn = '0' and CTL_BUSACKn = '0' -- Tristate bus when Z80 tristated and the K64F is requesting all devices to tristate.
(others => 'Z') when Z80_BUSACKn = '0' and CTL_BUSACKni = '0' -- Tristate bus when Z80 tristated and the K64F is requesting all devices to tristate.
-- else
-- KEY_DATA when MB_BUSRQn = '1' and Z80_BUSACKn = '1' and KEY_SUBSTITUTE = '1' and Z80_MREQn = '0' -- Read mapped keyboard data.
-- else
@@ -1377,48 +1426,48 @@ begin
--
-- Address Bus Multiplexing.
--
Z80_ADDR <= MB_ADDR when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
Z80_ADDR <= MB_ADDR when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else
(others => 'Z');
Z80_WRn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_WRITE_STROBE = '1') -- and (write1 or write2...) signals active here
Z80_WRn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_WRITE_STROBE = '1') -- and (write1 or write2...) signals active here
else
'1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
'1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else 'Z';
Z80_RDn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_READ_KEYS = '1') -- and (read1 or read2...) signals active here
Z80_RDn <= '0' when MB_MREQn = '0' and Z80_BUSACKn = '0' and (MB_READ_KEYS = '1') -- and (read1 or read2...) signals active here
else
'1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
'1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else 'Z';
Z80_MREQn <= MB_MREQn when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
Z80_MREQn <= MB_MREQn when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else 'Z';
Z80_INTn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
Z80_INTn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else 'Z';
Z80_NMIn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
Z80_NMIn <= '1' when Z80_BUSACKn = '0' and MB_BUSRQn = '0'
else 'Z';
-- The tranZPUter SW board adds upgrades for the Z80 processor and host. These upgrades are controlled through an IO port which
-- in v1.0 - v1.1 was either at 0x2-=0x2f, 0x60-0x6f, 0xA0-0xAf, 0xF0-0xFF, the default being 0x60. This logic mimcs the 74HCT138 and
-- FlashRAM decoder which produces the I/O port select signals.
--
CS_IO_6XXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "0110"
CS_IO_6XXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "0110"
else '1';
CS_MEM_CFGn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "000" -- IO 60
CS_MEM_CFGn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "000" -- IO 60
else '1';
CS_SCK_CTLCLKn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "001" -- IO 62
CS_SCK_CTLCLKn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "001" -- IO 62
else '1';
CS_SCK_SYSCLKn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "010" -- IO 64
CS_SCK_SYSCLKn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "010" -- IO 64
else '1';
CS_SCK_RDn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "011" -- IO 66
CS_SCK_RDn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "011" -- IO 66
else '1';
SVCREQn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "100" -- IO 68
SVCREQn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 1) = "100" -- IO 68
else '1';
CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 0) = "1110" -- IO 6E
CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 0) = "1110" -- IO 6E
else '1';
CS_CPLD_INFOn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 0) = "1111" -- IO 6F
CS_CPLD_INFOn <= '0' when CS_IO_6XXn = '0' and Z80_ADDR(3 downto 0) = "1111" -- IO 6F
else '1';
-- Assign the RAM select signals to their external pins.
@@ -1429,21 +1478,21 @@ begin
else '1';
-- I/O Control signals to read and update the current video parameters, mainly used for setting FPGA access.
CS_IO_DXXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "1101"
CS_IO_DXXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "1101"
else '1';
-- I/O Control signals, mainly used for mirroring of the video module registers.
CS_IO_EXXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "1110"
CS_IO_EXXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "1110"
else '1';
CS_IO_FXXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "1111"
CS_IO_FXXn <= '0' when Z80_IORQn = '0' and Z80_M1n = '1' and Z80_ADDR(7 downto 4) = "1111"
else '1';
-- 0xF8 set the video mode. [2:0] = mode, 000 = MZ80A, 001 = MZ-700, 010 = MZ-80B, 011 = MZ-800, 111 = Pixel graphics.
CS_FB_VMn <= '0' when CS_IO_FXXn = '0' and Z80_ADDR(3 downto 0) = "1000"
CS_FB_VMn <= '0' when CS_IO_FXXn = '0' and Z80_ADDR(3 downto 0) = "1000"
else '1';
-- 0xFD set the Video memory page in block C000:FFFF bit 0, set the CGROM upload access in bit 7.
CS_FB_PAGEn <= '0' when CS_IO_FXXn = '0' and Z80_ADDR(3 downto 0) = "1101"
CS_FB_PAGEn <= '0' when CS_IO_FXXn = '0' and Z80_ADDR(3 downto 0) = "1101"
else '1';
-- MZ80B/MZ2000 I/O Registers E0-EB,
CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and Z80_ADDR(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1'
CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and Z80_ADDR(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1'
else '1';
@@ -1498,24 +1547,24 @@ begin
-- Mainboard WAIT State Generator S-R latch 4.
-- NB: V2.1 design doesnt need the wait state generator as the mapping is done in hardware.
--
--MBWAITGEN: process(SYSCLK, Z80_ADDR, Z80_M1n, CTL_BUSRQn, MEM_MODE_LATCH, Z80_IORQn)
--MBWAITGEN: process(SYSCLK, Z80_ADDR, Z80_M1n, CTL_BUSRQni, MEM_MODE_LATCH, Z80_IORQn)
-- variable tmp : std_logic;
-- variable iowait : std_logic;
--begin
--
-- -- IO Wait select active when an IO operation is made in range 0xE0-0xFF.
-- if (Z80_ADDR(7 downto 5) = "111" and Z80_M1n = '1' and CTL_BUSRQn = '1' and MEM_MODE_LATCH(5) = '1' and Z80_IORQn = '0') then
-- if (Z80_ADDR(7 downto 5) = "111" and Z80_M1n = '1' and CTL_BUSRQni = '1' and MEM_MODE_LATCH(5) = '1' and Z80_IORQn = '0') then
-- iowait := '0';
-- else
-- iowait := '1';
-- end if;
--
-- if(SYSCLK='1' and SYSCLK'event) then
-- if((CTL_BUSRQn = '1' and Z80_RESETn = '1') and iowait = '1') then
-- if((CTL_BUSRQni = '1' and Z80_RESETn = '1') and iowait = '1') then
-- tmp := tmp;
-- elsif((CTL_BUSRQn = '0' or Z80_RESETn = '0') and iowait = '0') then
-- elsif((CTL_BUSRQni = '0' or Z80_RESETn = '0') and iowait = '0') then
-- tmp := 'Z';
-- elsif((CTL_BUSRQn = '0' or Z80_RESETn = '0') and iowait = '1') then
-- elsif((CTL_BUSRQni = '0' or Z80_RESETn = '0') and iowait = '1') then
-- tmp := '1';
-- else
-- tmp := '0';

2
CPLD/SW700/v1.2/tranZPUterSW700_Toplevel.vhd
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@@ -61,7 +61,7 @@ entity tranZPUterSW700 is
Z80_CLK : out std_logic;
-- K64F control signals.
CTL_BUSACKn : in std_logic;
CTL_BUSACKn : out std_logic;
CTL_BUSRQn : in std_logic;
CTL_HALTn : out std_logic;
CTL_M1n : out std_logic;

2
CPLD/SW700/v1.3/build/tranZPUterSW700_constraints.sdc
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@@ -276,7 +276,7 @@ set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For both configurations.
#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}

12
CPLD/SW700/v1.3/tranZPUterSW700.vhd
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@@ -239,7 +239,7 @@ architecture rtl of cpld512 is
signal CPLD_RFSHn : std_logic; --
signal CPLD_HALTn : std_logic; --
signal CTL_BUSRQni : std_logic; --
signal CTL_BUSACKni : std_logic; --
signal CTL_BUSACKni : std_logic; -- Buffered BUSACK signal to the K64F to indicate it has control of the bus.
signal CTL_BUSGRANTn : std_logic; --
-- RAM select and write signals.
@@ -289,10 +289,16 @@ begin
-- 111 = MZ-2000
-- [3] - R/W - Mainboard Video - 0 = Enable, 1 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
-- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
--*[4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
-- [6:5] - R/W - Mainboard/CPU clock.
-- 000 = Sharp MZ80A 2MHz System Clock.
-- 001 = Sharp MZ80B 4MHz System Clock.
-- 010 = Sharp MZ700 3.54MHz System Clock.
-- 011 -111 = Reserved, defaults to 2MHz System Clock.
-- [7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
-- * = SW v2.2 MZ80A only, not used in other CPLD versions.
--
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPU_CFGn, CS_CPLD_CFGn, CPLD_ADDR, CPLD_DATA_IN, CPLD_CFG_DATA, CPU_CFG_DATA )
begin
@@ -632,6 +638,8 @@ begin
-- 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected.
-- 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected.
-- 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected.
--
-- * = Only on SW-700 v1.3
MEMORYMGMT: process(CPLD_ADDR, CPLD_WRn, CPLD_RDn, CPLD_IORQn, CPLD_MREQn, CPLD_M1n, Z80_HI_ADDR, VZ80_HI_ADDR, MEM_MODE_LATCH, SYS_BUSACKni, CS_VIDEOn, CS_VIDEO_IOn, CS_IO_DXXn, CS_IO_EXXn, CS_IO_FXXn, CS_CPU_CFGn, CS_CPU_INFOn, MODE_CPLD_MB_VIDEOn)
begin

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software/asm/MZ800_1Z_013B.asm Normal file
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software/asm/MZ800_9Z_504M.asm Normal file
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software/asm/MZ800_IOCS.asm Normal file
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software/roms/9Z_504M.ROM Normal file
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software/roms/MZ800_1Z_013B.ORI Normal file
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software/roms/MZ800_1Z_013B.rom Normal file
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software/roms/MZ800_9Z_504M.ORI Normal file
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software/roms/MZ800_9Z_504M.rom Normal file
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software/roms/MZ800_CGROM.ORI Normal file
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software/roms/MZ800_CGROM_JP.ORI Normal file
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software/roms/MZ800_IOCS.ORI Normal file
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software/roms/MZ800_IOCS.rom Normal file
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software/roms/MZ800_IPL.rom Normal file
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6
software/tools/assemble_roms.sh
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@@ -12,6 +12,7 @@
## Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
##
## History: August 2018 - Initial script written.
## March 2021 - Added MZ-800 IPL
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
@@ -32,7 +33,7 @@ ROOTDIR=../../tranZPUter
TOOLDIR=${ROOTDIR}/software/tools
JARDIR=${ROOTDIR}/software/tools
ASM=glass-0.5.jar
BUILDROMLIST="MZ80AFI monitor_SA1510 monitor_80c_SA1510 monitor_1Z-013A monitor_80c_1Z-013A monitor_1Z-013A-KM monitor_80c_1Z-013A-KM MZ80B_IPL"
BUILDROMLIST="MZ800_1Z_013B MZ800_9Z_504M MZ800_IOCS MZ80AFI monitor_SA1510 monitor_80c_SA1510 monitor_1Z-013A monitor_80c_1Z-013A monitor_1Z-013A-KM monitor_80c_1Z-013A-KM MZ80B_IPL"
#BUILDMZFLIST="hi-ramcheck sharpmz-test"
BUILDMZFLIST="BASIC sharpmz-test"
ASMDIR=${ROOTDIR}/software/asm
@@ -65,3 +66,6 @@ do
fi
fi
done
# Manual tinkering to build the MZ800 Rom.
cat ${ROMDIR}/MZ800_1Z_013B.rom ${ROMDIR}/MZ800_CGROM.ORI ${ROMDIR}/MZ800_9Z_504M.rom ${ROMDIR}/MZ800_IOCS.rom > ${ROMDIR}/MZ800_IPL.rom