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Updates for SW-700 board

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This commit is contained in:
Philip Smart
2020-11-08 00:17:59 +00:00
parent 78707b355d
commit dad7e2a110
19 changed files with 248 additions and 171 deletions
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20
CPLD/SW/tranZPUterSW.vhd
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@@ -187,7 +187,7 @@ architecture rtl of cpld512 is
signal MODE_VIDEO_MZ80C : std_logic := '0'; -- The machine is running in MZ80C mode.
signal MODE_VIDEO_MZ1200 : std_logic := '0'; -- The machine is running in MZ1200 mode.
signal MODE_VIDEO_MZ2000 : std_logic := '0'; -- The machine is running in MZ2000 mode.
signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable.
signal GRAM_PAGE_ENABLE : std_logic; -- Graphics mode page enable.
signal MZ80B_VRAM_HI_ADDR : std_logic; -- Video RAM located at D000:FFFF when high.
signal MZ80B_VRAM_LO_ADDR : std_logic; -- Video RAM located at 5000:7FFF when high.
signal CS_FB_VMn : std_logic; -- Chip Select for the Video Mode register.
@@ -685,7 +685,7 @@ begin
MODE_VIDEO_MZ80C <= '0';
MODE_VIDEO_MZ1200 <= '0';
MODE_VIDEO_MZ2000 <= '0';
GRAM_PAGE_ENABLE <= "00";
GRAM_PAGE_ENABLE <= '0';
MZ80B_VRAM_HI_ADDR <= '0';
MZ80B_VRAM_LO_ADDR <= '0';
@@ -725,9 +725,9 @@ begin
end case;
end if;
-- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' then
GRAM_PAGE_ENABLE <= Z80_DATA(1 downto 0);
-- memory page register. [0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 00 = Off, 1 = Enabled. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and Z80_WRn = '0' then
GRAM_PAGE_ENABLE <= Z80_DATA(0);
end if;
-- MZ80B Z80 PIO.
@@ -779,7 +779,7 @@ begin
-- 29 - All memory and IO are on the tranZPUter board, 64K block 5 selected.
-- 30 - All memory and IO are on the tranZPUter board, 64K block 6 selected.
-- 31 - All memory and IO are on the tranZPUter board, 64K block 7 selected.
MEMORYMGMT: process(Z80_ADDR, Z80_WRn, Z80_RDn, Z80_IORQn, Z80_MREQn, Z80_M1n, MEM_MODE_LATCH, SYS_BUSACKni, CS_VIDEOn, CS_VIDEO_IOn, CS_IO_DXXn, CS_IO_EXXn, CS_IO_FXXn, CS_CPLD_CFGn, CS_CPLD_INFOn)
MEMORYMGMT: process(Z80_ADDR, Z80_WRn, Z80_RDn, Z80_IORQn, Z80_MREQn, Z80_M1n, MEM_MODE_LATCH, SYS_BUSACKni, CS_VIDEOn, CS_VIDEO_IOn, CS_IO_DXXn, CS_IO_EXXn, CS_IO_FXXn, CS_CPLD_CFGn, CS_CPLD_INFOn, MODE_CPLD_MB_VIDEOn)
begin
-- Memory action according to the configured memory mode. Not synchronous as we need to detect and act on address or signals long before a rising edge.
@@ -1438,16 +1438,16 @@ begin
-- Select for video based on the memory being accessed, the mode and control signals.
-- Standard access to VRAM/ARAM. Video memory based IO registers in region E000:E2FF are enabled so that the FPGA can set its internal mirrored values but FPGA to block read operations as it will affect mainboard reads from keyboard etc.
CS_VIDEOn <= '0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '0' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) < X"E300"
CS_VIDEOn <= '0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '0' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) < X"E300"
else
-- Graphics RAM enabled, range C000:FFFF is mapped to graphics RAM.
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE /= "00" and unsigned(Z80_ADDR(15 downto 0)) >= X"C000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"C000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
else
-- MZ80B Graphics RAM enabled, range E000:FFFF is mapped to graphics RAMI + II and D000:DFFF to standard video.
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
else
-- MZ80B Graphics RAM enabled, range 6000:7FFF is mapped to graphics RAMI + II and 5000:5FFF to standard video.
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"5000" and unsigned(Z80_ADDR(15 downto 0)) <= X"7FFF"
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"5000" and unsigned(Z80_ADDR(15 downto 0)) <= X"7FFF"
else '1';
-- Read from memory and IO devices within the FPGA.

4
CPLD/SW700/build/tranZPUterSW700.qsf
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@@ -121,6 +121,7 @@ set_location_assignment PIN_1 -to VZ80_RDn
set_location_assignment PIN_2 -to VZ80_WRn
set_location_assignment PIN_5 -to VZ80_IORQn
set_location_assignment PIN_6 -to VZ80_CLK
set_location_assignment PIN_8 -to VWAITn
# RAM control
# ===========
@@ -175,7 +176,6 @@ set_location_assignment PIN_49 -to SYS_BUSACKn
# Mainboard control signals.
# ==========================
set_location_assignment PIN_7 -to V_CSYNC
set_location_assignment PIN_8 -to V_CVIDEO
set_location_assignment PIN_9 -to V_HSYNC
set_location_assignment PIN_10 -to V_VSYNC
set_location_assignment PIN_11 -to V_G
@@ -183,7 +183,7 @@ set_location_assignment PIN_12 -to V_B
set_location_assignment PIN_14 -to V_R
set_location_assignment PIN_15 -to V_COLR
set_location_assignment PIN_34 -to CSYNC_IN
set_location_assignment PIN_31 -to CVIDEO_IN
#set_location_assignment PIN_31 -to CVIDEO_IN
set_location_assignment PIN_29 -to HSYNC_IN
set_location_assignment PIN_26 -to VSYNC_IN
set_location_assignment PIN_23 -to G_IN

6
CPLD/SW700/build/tranZPUterSW700_constraints.sdc
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@@ -110,12 +110,13 @@ set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VWAITn}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}]
#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}]
set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VDATA[0]}]
@@ -215,7 +216,6 @@ set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_G
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_B}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_COLR}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_CVIDEO}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_HSYNC}]
set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {V_VSYNC}]
@@ -247,7 +247,7 @@ set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
# For both configurations.
set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[4]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[3]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[2]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}

57
CPLD/SW700/tranZPUterSW700.vhd
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@@ -107,11 +107,11 @@ entity cpld512 is
VZ80_IORQn : out std_logic;
VZ80_RDn : out std_logic;
VZ80_WRn : out std_logic;
VWAITn : in std_logic; -- Wait signal from asserted when Video RAM is busy.
VZ80_CLK : out std_logic;
-- Graphics signal in/out.
V_CSYNC : out std_logic;
V_CVIDEO : out std_logic;
V_HSYNC : out std_logic;
V_VSYNC : out std_logic;
V_G : out std_logic;
@@ -119,7 +119,7 @@ entity cpld512 is
V_R : out std_logic;
V_COLR : out std_logic;
CSYNC_IN : in std_logic;
CVIDEO_IN : in std_logic;
--CVIDEO_IN : in std_logic;
HSYNC_IN : in std_logic;
VSYNC_IN : in std_logic;
G_IN : in std_logic;
@@ -163,6 +163,7 @@ architecture rtl of cpld512 is
signal MODE_CPLD_MZ2000 : std_logic;
signal MODE_CPLD_SWITCH : std_logic;
signal MODE_CPLD_MB_VIDEOn : std_logic; -- Mainboard video, 0 = enabled, 1 = disabled.
signal MODE_CPLD_VIDEO_WAIT : std_logic; -- FPGA video display period wait flag, 1 = enabled, 0 = disabled.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0); -- CPLD Configuration register.
signal CPLD_INFO_DATA : std_logic_vector(7 downto 0); -- CPLD status value.
@@ -208,7 +209,7 @@ architecture rtl of cpld512 is
signal MODE_VIDEO_MZ80C : std_logic := '0'; -- The machine is running in MZ80C mode.
signal MODE_VIDEO_MZ1200 : std_logic := '0'; -- The machine is running in MZ1200 mode.
signal MODE_VIDEO_MZ2000 : std_logic := '0'; -- The machine is running in MZ2000 mode.
signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable.
signal GRAM_PAGE_ENABLE : std_logic; -- Graphics mode page enable.
signal MZ80B_VRAM_HI_ADDR : std_logic; -- Video RAM located at D000:FFFF when high.
signal MZ80B_VRAM_LO_ADDR : std_logic; -- Video RAM located at 5000:7FFF when high.
signal CS_FB_VMn : std_logic; -- Chip Select for the Video Mode register.
@@ -250,24 +251,27 @@ begin
-- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
-- by host software such as RFS.
--
-- [2:0] - Mode/emulated machine.
-- 000 = MZ-80K
-- 001 = MZ-80C
-- 010 = MZ-1200
-- 011 = MZ-80A
-- 100 = MZ-700
-- 101 = MZ-800
-- 110 = MZ-80B
-- 111 = MZ-2000
-- [3] - Mainboard Video - 1 = Enable, 0 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
-- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
-- [2:0] - R/W - Mode/emulated machine.
-- 000 = MZ-80K
-- 001 = MZ-80C
-- 010 = MZ-1200
-- 011 = MZ-80A
-- 100 = MZ-700
-- 101 = MZ-800
-- 110 = MZ-80B
-- 111 = MZ-2000
-- [3] - R/W - Mainboard Video - 0 = Enable, 1 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
-- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
--
MACHINEMODE: process( Z80_CLKi, Z80_RESETn, CS_CPLD_CFGn, CS_CPLD_INFOn, Z80_ADDR, Z80_DATA )
begin
if(Z80_RESETn = '0') then
MODE_CPLD_SWITCH <= '0';
CPLD_CFG_DATA <= "00000100"; -- Default to Sharp MZ700.
CPLD_CFG_DATA <= "00000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
elsif(Z80_CLKi'event and Z80_CLKi = '1') then
@@ -660,7 +664,7 @@ begin
MODE_VIDEO_MZ80C <= '0';
MODE_VIDEO_MZ1200 <= '0';
MODE_VIDEO_MZ2000 <= '0';
GRAM_PAGE_ENABLE <= "00";
GRAM_PAGE_ENABLE <= '0';
MZ80B_VRAM_HI_ADDR <= '0';
MZ80B_VRAM_LO_ADDR <= '0';
@@ -700,9 +704,9 @@ begin
end case;
end if;
-- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' then
GRAM_PAGE_ENABLE <= Z80_DATA(1 downto 0);
-- memory page register. [1:0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = Off, 1 = Enabled. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and Z80_WRn = '0' then
GRAM_PAGE_ENABLE <= Z80_DATA(0);
end if;
-- MZ80B Z80 PIO.
@@ -1293,8 +1297,8 @@ begin
Z80_CLK <= Z80_CLKi;
-- Wait states, added by the video circuitry or the K64F.
Z80_WAITn <= '0' when SYS_WAITn = '0' or CTL_WAITn = '0' or MB_WAITn = '0'
-- Wait states, added by the mainboard video circuitry, FPGA video circuitry or the K64F.
Z80_WAITn <= '0' when SYS_WAITn = '0' or CTL_WAITn = '0' or (VWAITn = '0' and MODE_CPLD_VIDEO_WAIT = '1') or MB_WAITn = '0'
else '1';
-- Z80 signals passed to the mainboard, if the K64F has control of the bus then the Z80 signals are disabled as they are not tri-stated during a BUSRQ state.
@@ -1321,16 +1325,16 @@ begin
-- Select for video based on the memory being accessed, the mode and control signals.
-- Standard access to VRAM/ARAM.
CS_VIDEOn <= '0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '0' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) < X"E000"
CS_VIDEOn <= '0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '0' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) < X"E000"
else
-- Graphics RAM enabled, range C000:FFFF is mapped to graphics RAM.
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE /= "00" and unsigned(Z80_ADDR(15 downto 0)) >= X"C000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"C000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
else
-- MZ80B Graphics RAM enabled, range E000:FFFF is mapped to graphics RAMI + II and D000:DFFF to standard video.
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"D000" and unsigned(Z80_ADDR(15 downto 0)) <= X"FFFF"
else
-- MZ80B Graphics RAM enabled, range 6000:7FFF is mapped to graphics RAMI + II and 5000:5FFF to standard video.
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"5000" and unsigned(Z80_ADDR(15 downto 0)) <= X"7FFF"
'0' when MODE_CPLD_MB_VIDEOn = '1' and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1' and unsigned(Z80_ADDR(15 downto 0)) >= X"5000" and unsigned(Z80_ADDR(15 downto 0)) <= X"7FFF"
else '1';
-- Read from memory and IO devices within the FPGA.
@@ -1434,6 +1438,8 @@ begin
CS_80B_PIOn <= '0' when CS_IO_EXXn = '0' and Z80_ADDR(3 downto 2) = "10" and MODE_VIDEO_MZ80B = '1'
else '1';
-- Set the video wait state generator, 0 = disabled, 1 = enabled.
MODE_CPLD_VIDEO_WAIT <= CPLD_CFG_DATA(4);
-- Set the mainboard video state, 0 = enabled, 1 = disabled.
MODE_CPLD_MB_VIDEOn <= CPLD_CFG_DATA(3);
-- Set CPLD mode flag according to value given in config 2:0
@@ -1456,7 +1462,6 @@ begin
-- Graphics signal in/out.
V_CSYNC <= CSYNC_IN;
V_CVIDEO <= CVIDEO_IN;
V_HSYNC <= HSYNC_IN;
V_VSYNC <= VSYNC_IN;
V_G <= G_IN;

8
CPLD/SW700/tranZPUterSW700_Toplevel.vhd
View File

@@ -87,10 +87,10 @@ entity tranZPUterSW700 is
VZ80_RDn : out std_logic;
VZ80_WRn : out std_logic;
VZ80_CLK : out std_logic;
VWAITn : in std_logic; -- Wait signal from asserted when Video RAM is busy.
-- Graphics signal in/out.
V_CSYNC : out std_logic;
V_CVIDEO : out std_logic;
V_HSYNC : out std_logic;
V_VSYNC : out std_logic;
V_G : out std_logic;
@@ -98,7 +98,7 @@ entity tranZPUterSW700 is
V_R : out std_logic;
V_COLR : out std_logic;
CSYNC_IN : in std_logic;
CVIDEO_IN : in std_logic;
--CVIDEO_IN : in std_logic;
HSYNC_IN : in std_logic;
VSYNC_IN : in std_logic;
G_IN : in std_logic;
@@ -169,11 +169,11 @@ begin
VZ80_IORQn => VZ80_IORQn,
VZ80_RDn => VZ80_RDn,
VZ80_WRn => VZ80_WRn,
VWAITn => VWAITn, -- Wait signal from asserted when Video RAM is busy.
VZ80_CLK => VZ80_CLK,
-- Graphics signal in/out.
V_CSYNC => V_CSYNC,
V_CVIDEO => V_CVIDEO,
V_HSYNC => V_HSYNC,
V_VSYNC => V_VSYNC,
V_G => V_G,
@@ -181,7 +181,7 @@ begin
V_R => V_R,
V_COLR => V_COLR,
CSYNC_IN => CSYNC_IN,
CVIDEO_IN => CVIDEO_IN,
--CVIDEO_IN => CVIDEO_IN,
HSYNC_IN => HSYNC_IN,
VSYNC_IN => VSYNC_IN,
G_IN => G_IN,

135
FPGA/SW700/VideoController700.vhd
View File

@@ -87,6 +87,7 @@ entity VideoController is
VZ80_IORQn : in std_logic; -- Z80 IORQ.
VZ80_RDn : in std_logic; -- Z80 RDn.
VZ80_WRn : in std_logic; -- Z80 WRn.
VWAITn : out std_logic; -- WAIT signal to CPU when accessing video RAM when busy.
-- VGA & Composite output signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
@@ -103,7 +104,6 @@ entity VideoController is
-- RGB & Composite input signals.
V_CSYNC : in std_logic; -- Composite sync from mainboard.
V_CVIDEO : in std_logic; -- Comnposite video from mainboard.
V_HSYNCn : in std_logic; -- Horizontal sync (negative) from mainboard.
V_VSYNCn : in std_logic; -- Vertical sync (negative) from mainboard.
V_COLR : in std_logic; -- Composite and RF base frequency from mainboard.
@@ -290,7 +290,7 @@ architecture rtl of VideoController is
signal GRAM_OPT_WRITE : std_logic; -- Graphics write to GRAMI (0) or GRAMII (1) for MZ80B/MZ2000
signal GRAM_OPT_OUT1 : std_logic; -- Graphics enable GRAMI output to display
signal GRAM_OPT_OUT2 : std_logic; -- Graphics enable GRAMII output to display
signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable.
signal GRAM_PAGE_ENABLE : std_logic; -- Graphics mode page enable.
signal VIDEO_MODE_REG : std_logic_vector(7 downto 0); -- Programmable mode register to control video mode.
signal PAGE_MODE_REG : std_logic_vector(7 downto 0); -- Current value of the Page register.
signal PALETTE_REG : std_logic_vector(7 downto 0); -- Palette register to apply mapping to the digital RGB output.
@@ -733,7 +733,7 @@ begin
-- Every time we reach the end of the visible display area we enable copying of the VRAM and GRAM into the
-- display framebuffer, ready for the next frame display. This starts to occur a fixed set of rows after
-- they have been displayed, initially only during the hblank period of a row, but the during the full row
-- they have been displayed, initially only during the hblank period of a row, but during the full row
-- in the vblank period.
--
if V_COUNT = 0 then
@@ -1698,12 +1698,12 @@ begin
-- 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
--
-- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF5->.
-- 0xF8=<val> sets the mode of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
-- 0xF8=<val> sets the mode of the Video Module. [2:0] - 000 = MZ-80K, 001 = MZ-80C, 010 = MZ-1200, 011 = MZ--80A, 100 = MZ-700, 101 = MZ-800, 110 = MZ-80B, 111 = MZ-2000. [3] = 0 - 40 col, 1 - 80 col, [4] = 0 - mono, 1 - colour.
-- 0xF9=<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
-- 0xFA=<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- 0xFB=<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- 0xFC=<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- 0xFD=<val> memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
-- 0xFD=<val> memory page register. [0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = off, 1 = GRAM enabled. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
--
CTRLREGISTERS: process( VRESETn, IF_CLK, CGROM_PAGE, GRAM_PAGE_ENABLE, VIDEOMODE, MZ80B_VRAM_HI_ADDR, MZ80B_VRAM_LO_ADDR )
begin
@@ -1734,7 +1734,7 @@ begin
MODE_CPLD_SWITCH <= '0';
VIDEO_MODE_REG <= "00000000";
VGAMODE <= "00";
GRAM_PAGE_ENABLE <= "00";
GRAM_PAGE_ENABLE <= '0';
CGROM_PAGE <= '0';
DISPLAY_VGATE <= '0';
VIDEOMODE_RESET_TIMER <= to_unsigned(2, VIDEOMODE_RESET_TIMER'length); --(others => '0') & '1';
@@ -1987,9 +1987,9 @@ begin
GRAM_OPT_OUT2 <= VDATA(2);
end if;
-- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
-- memory page register. [0] switches in 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = off, 1 = GRAM paged in. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then
GRAM_PAGE_ENABLE <= VDATA(1 downto 0);
GRAM_PAGE_ENABLE <= VDATA(0);
CGROM_PAGE <= VDATA(7);
end if;
@@ -2134,8 +2134,8 @@ begin
end if;
-- Non-registered signal vectors for readback.
-- Page register: [7] = CGROM Page setting, [6:1] = Current video mode, [1:0] = GRAM Page setting.
PAGE_MODE_REG <= CGROM_PAGE & std_logic_vector(to_unsigned(VIDEOMODE, 5)) & GRAM_PAGE_ENABLE;
-- Page register: [7] = CGROM Page setting, [6:2] = Current video mode, [0] = GRAM enabled setting.
PAGE_MODE_REG <= CGROM_PAGE & std_logic_vector(to_unsigned(VIDEOMODE, 5)) & '0' & GRAM_PAGE_ENABLE;
-- MZ80B Graphics RAM is enabled whenever one of the two control lines goes active.
GRAM_MZ80B_ENABLE <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR;
@@ -2153,17 +2153,17 @@ begin
else '1';
CS_DARAMn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "011"
else '1';
CS_EXXXn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "100" and GRAM_PAGE_ENABLE = "00" and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
CS_EXXXn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "100" and GRAM_PAGE_ENABLE = '0' and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
else '1';
-- MZ80B Graphics RAM enabled, range E000:FFFF is mapped to graphics RAMI + II and D000:DFFF to standard video.
CS_GRAMn <= '0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"D000" and unsigned(VADDR(15 downto 0)) <= X"FFFF" and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1'
CS_GRAMn <= '0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"D000" and unsigned(VADDR(15 downto 0)) <= X"FFFF" and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1'
else
-- MZ80B Graphics RAM enabled, range 6000:7FFF is mapped to graphics RAMI + II and 5000:5FFF to standard video.
'0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"5000" and unsigned(VADDR(15 downto 0)) <= X"7FFF" and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1'
'0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"5000" and unsigned(VADDR(15 downto 0)) <= X"7FFF" and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1'
else '1';
-- Graphics RAM enabled, range C000:FFFF is mapped to graphics RAM.
CS_FBRAMn <= '0' when VZ80_IORQn = '1' and VADDR(15 downto 14) = "11" and GRAM_PAGE_ENABLE /= "00"
else '0';
CS_FBRAMn <= '0' when VZ80_IORQn = '1' and VADDR(15 downto 14) = "11" and GRAM_PAGE_ENABLE = '1'
else '1';
CS_IO_6XXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "0110"
else '1';
CS_IO_DXXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "1101"
@@ -2258,17 +2258,17 @@ begin
-- Data for CPU to read, dependent on what is being accessed.
VDATA <= VRAM_VIDEO_DATA when VZ80_RDn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0'
else
GRAM_DO_R when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "01" and GRAM_MODE_REG(1 downto 0) = "00" -- For direct framebuffer access, C000:FFFF is assigned to the framebuffer during a read if the GRAM_PAGE_ENABLE register is not 0.
GRAM_DO_R when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_MODE_REG(1 downto 0) = "00" -- For direct framebuffer access, C000:FFFF is assigned to the framebuffer during a read if the GRAM_PAGE_ENABLE register is not 0.
else
GRAM_DO_B when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "10" and GRAM_MODE_REG(1 downto 0) = "01"
GRAM_DO_B when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_MODE_REG(1 downto 0) = "01"
else
GRAM_DO_G when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "11" and GRAM_MODE_REG(1 downto 0) = "10"
GRAM_DO_G when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_MODE_REG(1 downto 0) = "10"
else
GRAM_DO_GI when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '0' -- For MZ80B GRAM I memory read - lower 8K of red framebuffer.
GRAM_DO_GI when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '0' -- For MZ80B GRAM I memory read - lower 8K of red framebuffer.
else
GRAM_DO_GII when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '1' -- For MZ80B GRAM II memory read - lower 8K of blue framebuffer.
GRAM_DO_GII when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '1' -- For MZ80B GRAM II memory read - lower 8K of blue framebuffer.
else
VIDEO_MODE_REG when VZ80_RDn = '0' and CS_FB_VMn = '0'
V_BLANKi & H_BLANKi & VIDEO_MODE_REG(5 downto 0)when VZ80_RDn = '0' and CS_FB_VMn = '0'
else
GRAM_MODE_REG when VZ80_RDn = '0' and CS_FB_CTLn = '0'
else
@@ -2360,6 +2360,11 @@ begin
else
(others=>'Z');
-- Wait state generation, when the GRAM Frame Buffer is being written to and the CPU is attempting to write, pause the CPU.
VWAITn <= '0' when V_BLANKi = '1' and CS_FBRAMn = '0'
else '1';
-- VRAM mux between the CPU signals and the GPU. GPU takes priority.
--
VRAM_ADDR <= VRAM_GPU_ADDR(11 downto 0) when VRAM_GPU_ENABLE = '1'
@@ -2370,7 +2375,7 @@ begin
VDATA;
VRAM_WEN <= '1' when VRAM_GPU_WEN = '1'
else
'1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0' and GRAM_PAGE_ENABLE = "00"
'1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0' and GRAM_PAGE_ENABLE = '0'
else '0';
VRAM_VIDEO_DATA <= VRAM_DO;
@@ -2393,7 +2398,7 @@ begin
else (others => '1');
CG_ADDR <= CGRAM_ADDR(11 downto 0) when CGRAM_WEn = '0'
else XFER_CGROM_ADDR;
CGROM_WEN <= '1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' and GRAM_PAGE_ENABLE = "00"
CGROM_WEN <= '1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' and GRAM_PAGE_ENABLE = '0'
else '0';
@@ -2434,23 +2439,17 @@ begin
GRAM_DO_G <= GRAM_DO_GIII;
GWEN_R <= '1' when GWEN_GPU_R = '1'
else
'1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "01" and GRAM_MODE_REG(3 downto 2) = "00"
else
'1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11"
'1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and (GRAM_MODE_REG(3 downto 2) = "00" or GRAM_MODE_REG(3 downto 2) = "11")
else
'0';
GWEN_B <= '1' when GWEN_GPU_B = '1'
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "11" and GRAM_MODE_REG(3 downto 2) = "10"
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11"
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and (GRAM_MODE_REG(3 downto 2) = "10" or GRAM_MODE_REG(3 downto 2) = "11")
else
'0';
GWEN_G <= '1' when GWEN_GPU_G = '1'
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "10" and GRAM_MODE_REG(3 downto 2) = "01"
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11"
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and (GRAM_MODE_REG(3 downto 2) = "01" or GRAM_MODE_REG(3 downto 2) = "11")
else
'0';
@@ -2562,6 +2561,64 @@ begin
-- VGA_VS <= not V_SYNCni;
-- end if;
-- end if;
-- end process;
--
-- process(SYS_CLK)
-- begin
-- if rising_edge(SYS_CLK) then
-- if MODE_CPLD_MB_VIDEOn = '1' then
-- if H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0') then
-- VGA_R(3 downto 0) <= FB_PALETTE_R(3 downto 0);
-- VGA_G(3 downto 0) <= FB_PALETTE_G(3 downto 0);
-- VGA_B(3 downto 0) <= FB_PALETTE_B(3 downto 0);
-- else
-- VGA_R(3 downto 0) <= (others => '0');
-- VGA_G(3 downto 0) <= (others => '0');
-- VGA_B(3 downto 0) <= (others => '0');
-- end if;
--
-- if FB_PALETTE_R(4) = '0' then
-- VGA_R_COMPOSITE <= '0';
-- else
-- VGA_R_COMPOSITE <= 'Z';
-- end if;
--
-- if FB_PALETTE_G(4) = '0' then
-- VGA_G_COMPOSITE <= '0';
-- else
-- VGA_G_COMPOSITE <= 'Z';
-- end if;
--
-- if FB_PALETTE_B(4) = '0' then
-- VGA_B_COMPOSITE <= '0';
-- else
-- VGA_B_COMPOSITE <= 'Z';
-- end if;
--
-- if H_POLARITY(0) = '0' then
-- HSYNC_OUTn <= H_SYNCni;
-- else
-- HSYNC_OUTn <= not H_SYNCni;
-- end if;
--
-- if V_POLARITY(0) = '0' then
-- VSYNC_OUTn <= V_SYNCni;
-- else
-- VSYNC_OUTn <= not V_SYNCni;
-- end if;
--
-- elsif MODE_CPLD_MB_VIDEOn = '0' then
-- VGA_R_COMPOSITE <= V_R;
-- VGA_G_COMPOSITE <= V_G;
-- VGA_B_COMPOSITE <= V_B;
-- VGA_R <= (others => V_R);
-- VGA_G <= (others => V_G);
-- VGA_B <= (others => V_B);
-- HSYNC_OUTn <= V_HSYNCn; -- Horizontal sync (negative) from mainboard.
-- VSYNC_OUTn <= V_VSYNCn; -- Vertical sync (negative) from mainboard.
-- end if;
-- end if;
--
-- end process;
@@ -2585,29 +2642,29 @@ begin
MODE_CPLD_MZ2000 <= '1' when to_integer(unsigned(CPLD_CFG_DATA(2 downto 0))) = MODE_MZ2000
else '0';
VGA_R(3 downto 0) <= FB_PALETTE_R(3 downto 0) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0')
VGA_R(3 downto 0) <= FB_PALETTE_R(3 downto 0) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0')
else
(others => V_R) when MODE_CPLD_MB_VIDEOn = '0'
else (others => '0');
VGA_R_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0'
VGA_R_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_R = '1'
else
'0' when MODE_CPLD_MB_VIDEOn = '0' and FB_PALETTE_R(4) = '1'
'0' when MODE_CPLD_MB_VIDEOn = '1' and FB_PALETTE_R(4) = '0'
else 'Z';
VGA_G(3 downto 0) <= FB_PALETTE_G(3 downto 0) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0')
else
(others => V_G) when MODE_CPLD_MB_VIDEOn = '0'
else (others => '0');
VGA_G_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0'
VGA_G_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_G = '1'
else
'0' when MODE_CPLD_MB_VIDEOn = '0' and FB_PALETTE_G(4) = '1'
'0' when MODE_CPLD_MB_VIDEOn = '1' and FB_PALETTE_G(4) = '0'
else 'Z';
VGA_B(3 downto 0) <= FB_PALETTE_B(3 downto 0) when MODE_CPLD_MB_VIDEOn = '1' and H_BLANKi='0' and V_BLANKi = '0' and ((DISPLAY_VGATE = '0' and MODE_VIDEO_MZ80B = '1') or MODE_VIDEO_MZ80B = '0')
else
(others => V_B) when MODE_CPLD_MB_VIDEOn = '0'
else (others => '0');
VGA_B_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0'
VGA_B_COMPOSITE <= '1' when MODE_CPLD_MB_VIDEOn = '0' and V_B = '1'
else
'0' when MODE_CPLD_MB_VIDEOn = '0' and FB_PALETTE_B(4) = '1'
'0' when MODE_CPLD_MB_VIDEOn = '1' and FB_PALETTE_B(4) = '0'
else 'Z';
HSYNC_OUTn <= H_SYNCni when MODE_CPLD_MB_VIDEOn = '1' and H_POLARITY(0) = '0'
else

4
FPGA/SW700/VideoController700_Toplevel.vhd
View File

@@ -59,6 +59,7 @@ entity VideoController700 is
VZ80_IORQn : in std_logic; -- Z80 IORQ.
VZ80_RDn : in std_logic; -- Z80 RDn.
VZ80_WRn : in std_logic; -- Z80 WRn.
VWAITn : out std_logic; -- WAIT signal to CPU when accessing video RAM when busy.
-- VGA & Composite output signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
@@ -75,7 +76,6 @@ entity VideoController700 is
-- RGB & Composite input signals.
V_CSYNC : in std_logic; -- Composite sync from mainboard.
V_CVIDEO : in std_logic; -- Comnposite video from mainboard.
V_HSYNCn : in std_logic; -- Horizontal sync (negative) from mainboard.
V_VSYNCn : in std_logic; -- Vertical sync (negative) from mainboard.
V_COLR : in std_logic; -- Composite and RF base frequency from mainboard.
@@ -158,6 +158,7 @@ begin
VZ80_IORQn => VZ80_IORQn, -- Z80 IORQ.
VZ80_RDn => VZ80_RDn, -- Z80 RDn.
VZ80_WRn => VZ80_WRn, -- Z80 WRn.
VWAITn => VWAITn, -- WAIT signal to CPU when accessing video RAM when busy.
-- VGA & Composite output signals.
VGA_R => VGA_R, -- 16 level Red output.
@@ -174,7 +175,6 @@ begin
-- RGB & Composite input signals.
V_CSYNC => V_CSYNC, -- Composite sync from mainboard.
V_CVIDEO => V_CVIDEO, -- Comnposite video from mainboard.
V_HSYNCn => V_HSYNCn, -- Horizontal sync (negative) from mainboard.
V_VSYNCn => V_VSYNCn, -- Vertical sync (negative) from mainboard.
V_COLR => V_COLR, -- Composite and RF base frequency from mainboard.

117
FPGA/SW700/build/VideoController700.qsf
View File

@@ -142,28 +142,29 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VDATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[7]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[6]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[5]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[4]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[3]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[2]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[1]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VDATA[0]
# Video control signals.
# ======================
set_location_assignment PIN_100 -to VZ80_RDn
set_location_assignment PIN_99 -to VZ80_WRn
set_location_assignment PIN_98 -to VZ80_IORQn
set_location_assignment PIN_85 -to VWAITn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn
# Composite video signals input.
# ==============================
set_location_assignment PIN_86 -to V_CSYNC
set_location_assignment PIN_85 -to V_CVIDEO
set_location_assignment PIN_83 -to V_HSYNCn
set_location_assignment PIN_80 -to V_VSYNCn
set_location_assignment PIN_79 -to V_G
@@ -171,21 +172,19 @@ set_location_assignment PIN_77 -to V_B
set_location_assignment PIN_76 -to V_R
set_location_assignment PIN_72 -to V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_CVIDEO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to V_COLR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_CSYNC
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_CVIDEO
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_HSYNCn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_VSYNCn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_G
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_B
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_COLR
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_CSYNC
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_HSYNCn
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_VSYNCn
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_G
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_B
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_R
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
@@ -209,46 +208,46 @@ set_location_assignment PIN_59 -to VGA_B[1]
set_location_assignment PIN_58 -to VGA_B[2]
set_location_assignment PIN_51 -to VGA_B[3]
set_location_assignment PIN_50 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_B_COMPOSITE
# Reserved.
# =========
@@ -293,5 +292,17 @@ set_global_assignment -name SDC_FILE VideoController700_constraints.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
FPGA/SW700/build/output_files/VideoController700.jic
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schematics/tranZPUter-SW-700_Schematic_v1_2a.pdf Normal file
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schematics/tranZPUter-SW-700_Schematic_v1_3.pdf Normal file
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software/MZF/CPM223.MZF
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software/MZF/sharpmz-test.MZF
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4
software/asm/include/CPM_Definitions.asm
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@@ -34,8 +34,8 @@
; Features.
;-----------------------------------------------
BUILD_VIDEOMODULE EQU 1 ; Build for the Video Module v2 board (=1) otherwise build for the 80Char Colour Board v1.0
BUILD_MZ80A EQU 1 ; Build for the Sharp MZ-80A base hardware.
BUILD_MZ700 EQU 0 ; Build for the Sharp MZ-700 base hardware.
BUILD_MZ80A EQU 0 ; Build for the Sharp MZ-80A base hardware.
BUILD_MZ700 EQU 1 ; Build for the Sharp MZ-700 base hardware.
;-----------------------------------------------
; Entry/compilation start points.

58
software/asm/sharpmz-test.asm
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@@ -4,7 +4,7 @@
;- Created: October 2018
;- Author(s): Philip Smart
;- Description: Sharp MZ series tester utility.
;- This assembly language program is written to aid in testing components
;- This assembly language program is a quick coding to aid in testing components
;- of the SharpMZ Series FPGA emulation and more recently the tranZPUter
;- and video module offshoots. It is a rough and ready program just to aid
;- exercising of hardware changes to verify they work and are reliable.
@@ -91,7 +91,7 @@ VMGRMODE EQU 0F9H ; Video
VMREDMASK EQU 0FAH ; Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
VMGREENMASK EQU 0FBH ; Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
VMBLUEMASK EQU 0FCH ; Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
VMPAGE EQU 0FDH ; Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
VMPAGE EQU 0FDH ; Video Module memory page register. [0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = Off, 1 = GRAM page, as specified by VM Graphics mode register is paged in. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
;-----------------------------------------------
; GPU commands.
@@ -324,7 +324,7 @@ BUFER: DS virtual 81 ; GET L
; [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
GRAMINIT: OUT (VMGRMODE),A ; Set provided graphics mode.
LD A,C ; Switch graphics page into C000:FFFF memory bank
LD A,1 ; Switch graphics page into C000:FFFF memory bank
OUT (VMPAGE),A
GRAM0: LD HL,GRAMSTART ; Start of graphics page.
LD BC,GRAMEND - GRAMSTART ; Size of graphics page (16KB).
@@ -342,7 +342,7 @@ GRAM1: LD A,000h ; Clear memory.
; Graphics Test. Needs to be in memory before C000-FFFF
;
GRAMTEST: OUT (VMGRMODE),A
LD A,C ; Switch graphics page into C000:FFFF memory bank
LD A,1 ; Switch graphics page into C000:FFFF memory bank
OUT (VMPAGE),A
LD D, 1 ; Number of iterations.
LD E,080h
@@ -355,16 +355,17 @@ GRAMTST1: LD A,E
LD A,B
OR C
JR NZ,GRAMTST1
SRL E
RR E
JR NZ,GRAMTST0
JR C,GRAMTST0
;JR C,GRAMTST0
DEC D
JR NZ,GRAMTST0
LD A,0 ; Revert to normal memory.
OUT (VMPAGE),A
RET
;
GRAMTEST2: OUT (VMGRMODE),A
LD A,C ; Switch graphics page into C000:FFFF memory bank
LD A,1 ; Switch graphics page into C000:FFFF memory bank
OUT (VMPAGE),A
LD E,0FFH
GRAMTST4: LD HL,GRAMSTART
@@ -388,21 +389,24 @@ GRAMTST5: LD A,E
; 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect),
; 1/0 = Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
;
GRAPHICS: LD A,010h
LD C,1 ; Red page.
GRAPHICS1: LD B, 128
GRAPH0: PUSH BC
LD A,010h ; Red page read/write.
CALL GRAMTEST
LD A,015h
LD C,2 ; Green page.
LD A,015h ; Green page read/write.
CALL GRAMTEST
LD A,01Ah
LD C,3 ; Blue page.
LD A,01Ah ; Blue page.
CALL GRAMTEST
LD A, 0FFH ; Run through the filter mask.
POP BC
DJNZ GRAPH0
JP GETL1
GRAPHICS2: LD A, 0FFH ; Run through the filter mask.
OUT (VMREDMASK),A
OUT (VMGREENMASK),A
OUT (VMBLUEMASK),A
GRAPH1: LD A, 01Ch ; Set graphics mode to Indirect Page write.
LD C,1 ; Any page set active for indirect write, 0 - disable.
CALL GRAMTEST2
IN A,(VMREDMASK)
DEC A
@@ -513,18 +517,15 @@ INITGRPH: LD DE,MSG_INITGR
CALL LETNL
LD A,0FFh ; Set Red filter.
OUT (VMREDMASK),A
LD A,000h ; Set Green filter.
LD A,0FFh ; Set Green filter.
OUT (VMGREENMASK),A
LD A,000h ; Set Blue filter.
LD A,0FFh ; Set Blue filter.
OUT (VMBLUEMASK),A
LD A,000h ; Enable graphics output and character display output. Initialise Red page.
LD C,1 ; Red page.
LD A,010h ; Enable graphics output and character display output. Initialise Red page.
CALL GRAMINIT
LD A,005h ; Initialise Green page.
LD C,3 ; Green page.
LD A,015h ; Initialise Green page.
CALL GRAMINIT
LD A,00Ah ; Initialise Blue page.
LD C,2 ; Blue page.
LD A,01Ah ; Initialise Blue page.
CALL GRAMINIT
LD A, 0ECh ; Set graphics mode to Indirect Page write, disable graphics output.
OUT (VMGRMODE),A
@@ -603,9 +604,12 @@ CMDTABLE:
DB 000H | 000H | 000H | 004H
DB "HELP"
DW HELP
DB 000H | 000H | 000H | 004H
DB "GRPH"
DW GRAPHICS
DB 000H | 000H | 000H | 005H
DB "GRPH1"
DW GRAPHICS1
DB 000H | 000H | 000H | 005H
DB "GRPH2"
DW GRAPHICS2
DB 000H | 000H | 000H | 004H
DB "GPU1"
DW GPU1
@@ -2470,7 +2474,7 @@ GPUENDX: DW 00000H
GPUENDY: DW 00000H
MSG_HELP1: DB "GRPH = TEST GRAPHICS", 0Dh, 00h
MSG_HELP1: DB "GRPH[1-2]= TEST GRAPHICS", 0Dh, 00h
MSG_HELP2: DB "GPU[1-2] = TEST GPU", 0Dh, 00h
MSG_HELP3: DB "PAL = TEST PALETTE", 0Dh, 00h
MSG_HELP4: DB "MEMTEST = TEST MEMORY", 0Dh, 00h

2
software/mif/PALETTE_B.mif
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@@ -4,7 +4,7 @@ ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0000: 00 1F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;

2
software/mif/PALETTE_G.mif
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@@ -4,7 +4,7 @@ ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0000: 00 1F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;

2
software/mif/PALETTE_R.mif
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@@ -4,7 +4,7 @@ ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 0F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0000: 00 1F 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0010: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;
0020: 00 00 00 01 00 02 00 03 00 04 00 05 00 06 00 07;
0030: 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F;

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software/roms/CPM223.BIN
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