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v2.1 first cut

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This commit is contained in:
Philip Smart
2020-07-24 12:25:29 +01:00
parent c53cf37acb
commit 7f70c1e744
17 changed files with 938 additions and 331 deletions
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11
.gitignore vendored
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@@ -114,3 +114,14 @@ software/CPM/1M44/RAW/CPM_1M44_RFS_1.RAW
software/CPM/1M44/RAW/CPM_1M44_RFS_2.RAW
software/CPM/SDC16M/
software/CPM/cpm3/on2
CPLD/build/db/
CPLD/build/incremental_db/
CPLD/build/output_files/
CPLD/build/simulation/
CPLD/mz80b/
CPLD/tranZPUterSW.sav2
schematics/tranZPUter-SW/
schematics/tranZPUter/
software/asm/.cbiosII.asm.swo
software/roms/SA1510.orig

48
CPLD/EPM7160/tranZPUterSW EPM7160.qsf Normal file
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@@ -0,0 +1,48 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 08:50:12 July 04, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# tranZPUterSW EPM7160_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY "tranZPUterSW EPM7160"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:50:12 JULY 04, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

0
CPLD/build/tranZPUterSW_EPM7160.qpf → CPLD/EPM7160/tranZPUterSW_EPM7160.qpf
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0
CPLD/build/tranZPUterSW_EPM7160.qsf → CPLD/EPM7160/tranZPUterSW_EPM7160.qsf
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0
CPLD/tranZPUterSW_EPM7160.vhd → CPLD/EPM7160/tranZPUterSW_EPM7160.vhd
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0
CPLD/tranZPUterSW_Toplevel_EPM7160.vhd → CPLD/EPM7160/tranZPUterSW_Toplevel_EPM7160.vhd
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0
CPLD/build/tranZPUterSW_constraints_EPM7160.sdc → CPLD/EPM7160/tranZPUterSW_constraints_EPM7160.sdc
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0
CPLD/tranZPUterSW_pkg_EPM7160.vhd → CPLD/EPM7160/tranZPUterSW_pkg_EPM7160.vhd
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28
CPLD/build/tranZPUterSW.qsf
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@@ -45,7 +45,7 @@ set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
@@ -59,6 +59,7 @@ set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
set_location_assignment PIN_108 -to Z80_HI_ADDR[18]
set_location_assignment PIN_102 -to Z80_HI_ADDR[17]
set_location_assignment PIN_107 -to Z80_HI_ADDR[16]
set_location_assignment PIN_110 -to Z80_HI_ADDR[15]
set_location_assignment PIN_106 -to Z80_ADDR[15]
set_location_assignment PIN_103 -to Z80_ADDR[14]
set_location_assignment PIN_98 -to Z80_ADDR[13]
@@ -122,17 +123,17 @@ set_location_assignment PIN_42 -to Z80_MEM[3]
set_location_assignment PIN_44 -to Z80_MEM[2]
set_location_assignment PIN_40 -to Z80_MEM[1]
set_location_assignment PIN_39 -to Z80_MEM[0]
set_location_assignment PIN_36 -to TBA[0]
set_location_assignment PIN_35 -to TBA[1]
set_location_assignment PIN_30 -to TBA[2]
set_location_assignment PIN_29 -to TBA[3]
set_location_assignment PIN_28 -to TBA[4]
set_location_assignment PIN_27 -to TBA[5]
set_location_assignment PIN_26 -to TBA[6]
set_location_assignment PIN_25 -to TBA[7]
set_location_assignment PIN_23 -to TBA[8]
set_location_assignment PIN_22 -to TBA[9]
set_location_assignment PIN_21 -to TBA[10]
set_location_assignment PIN_36 -to CFG_MZ80A
set_location_assignment PIN_35 -to CFG_MZ700
set_location_assignment PIN_30 -to TBA[0]
set_location_assignment PIN_29 -to TBA[1]
set_location_assignment PIN_28 -to TBA[2]
set_location_assignment PIN_27 -to TBA[3]
set_location_assignment PIN_26 -to TBA[4]
set_location_assignment PIN_25 -to TBA[5]
set_location_assignment PIN_23 -to TBA[6]
set_location_assignment PIN_22 -to TBA[7]
set_location_assignment PIN_21 -to TBA[8]
# Z80 Control signals.
# ====================
@@ -163,3 +164,6 @@ set_global_assignment -name VHDL_FILE ../tranZPUterSW_pkg.vhd
set_global_assignment -name VHDL_FILE ../tranZPUterSW.vhd
set_global_assignment -name SDC_FILE tranZPUterSW_constraints.sdc
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF

177
CPLD/build/tranZPUterSW_constraints.sdc
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@@ -39,7 +39,8 @@ set_time_format -unit ns -decimal_places 3
#**************************************************************
create_clock -name {SYSCLK} -period 500.000 -waveform { 0.000 250.000 } [get_ports { SYSCLK }]
create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
#create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
#**************************************************************
@@ -64,88 +65,110 @@ create_clock -name {CTLCLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {CTLCLK}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {CTL_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {SYSCLK}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {SYS_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {SYS_WAITn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_HALTn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_M1n}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_RDn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_RESETn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_RFSHn}]
set_input_delay -add_delay -clock [get_clocks {CTLCLK}] 1.000 [get_ports {Z80_WRn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CFG_MZ80A}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CFG_MZ700}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {CTL_WAITn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {SYS_BUSRQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {SYS_WAITn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[0]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[1]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[2]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[3]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[4]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[5]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[6]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[7]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[8]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[9]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[10]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[11]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[12]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[13]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[14]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_ADDR[15]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_BUSACKn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[0]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[1]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[2]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[3]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[4]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[5]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[6]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_DATA[7]}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_HALTn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_M1n}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RESETn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RFSHn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_WRn}]
set_input_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_RDn}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {CTL_CLKSLCT}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {CTL_HALTn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {CTL_M1n}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {CTL_RFSHn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {ENIOWAIT}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {RAM_CSn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {RAM_OEn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {RAM_WEn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {SVCREQn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {SYSREQn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {SYS_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {TZ_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_BUSRQn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_MEM[0]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_MEM[1]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_MEM[2]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_MEM[3]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_MEM[4]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {VADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {VADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {VADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_CLKSLCT}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_HALTn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_M1n}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {CTL_RFSHn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {ENIOWAIT}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_CSn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_OEn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {RAM_WEn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SVCREQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SYSREQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {SYS_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {TZ_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {VMEM_CSn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_BUSRQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 1.000 [get_ports {Z80_CLK}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[0]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[1]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[2]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[3]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[4]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[5]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[6]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_DATA[7]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[0]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[1]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[2]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[3]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[4]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[5]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[6]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[7]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[8]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[9]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[10]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[11]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[12]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[13]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[14]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[15]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[16]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[17]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_HI_ADDR[18]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[0]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[1]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[2]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[3]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MEM[4]}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_WAITn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_INTn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_WRn}]
set_output_delay -add_delay -clock [get_clocks {Z80_CLK}] 5.000 [get_ports {Z80_RDn}]
#**************************************************************
# Set Clock Groups

917
CPLD/tranZPUterSW.vhd
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File diff suppressed because it is too large Load Diff

44
CPLD/tranZPUterSW_Toplevel.vhd
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@@ -36,21 +36,21 @@ use altera.altera_syn_attributes.all;
entity tranZPUterSW is
port (
-- Z80 Address and Data.
Z80_HI_ADDR : out std_logic_vector(18 downto 16);
Z80_ADDR : in std_logic_vector(15 downto 0);
Z80_HI_ADDR : out std_logic_vector(18 downto 15);
Z80_ADDR : inout std_logic_vector(15 downto 0);
Z80_DATA : inout std_logic_vector(7 downto 0);
VADDR : out std_logic_vector(13 downto 11);
-- Z80 Control signals.
Z80_BUSRQn : out std_logic;
Z80_BUSACKn : in std_logic;
Z80_INTn : in std_logic;
Z80_INTn : inout std_logic;
Z80_IORQn : in std_logic;
Z80_MREQn : in std_logic;
Z80_NMIn : in std_logic;
Z80_RDn : in std_logic;
Z80_WRn : in std_logic;
Z80_RESETn : in std_logic;
Z80_MREQn : inout std_logic;
Z80_NMIn : inout std_logic;
Z80_RDn : inout std_logic;
Z80_WRn : inout std_logic;
Z80_RESETn : in std_logic; -- NB. The CPLD inverts the GCLRn pin, so active negative on the mainboard, active positive inside the CPLD.
Z80_HALTn : in std_logic;
Z80_WAITn : out std_logic;
Z80_M1n : in std_logic;
@@ -88,8 +88,12 @@ entity tranZPUterSW is
CTLCLK : in std_logic;
CTL_CLKSLCT : out std_logic;
-- Mode signals.
CFG_MZ80A : in std_logic;
CFG_MZ700 : in std_logic;
-- Reserved.
TBA : in std_logic_vector(10 downto 0)
TBA : in std_logic_vector(8 downto 0)
-- JTAG / ISP
--TCK : in std_logic;
@@ -101,24 +105,6 @@ END entity;
architecture rtl of tranZPUterSW is
--signal reset : std_logic;
--signal sysclk : std_logic;
--signal memclk : std_logic;
--signal pll_locked : std_logic;
--signal ps2m_clk_in : std_logic;
--signal ps2m_clk_out : std_logic;
--signal ps2m_dat_in : std_logic;
--signal ps2m_dat_out : std_logic;
--signal ps2k_clk_in : std_logic;
--signal ps2k_clk_out : std_logic;
--signal ps2k_dat_in : std_logic;
--signal ps2k_dat_out : std_logic;
--alias PS2_MDAT : std_logic is GPIO_1(19);
--alias PS2_MCLK : std_logic is GPIO_1(18);
begin
cpldl512Toplevel : entity work.cpld512
@@ -179,6 +165,10 @@ begin
CTLCLK => CTLCLK,
CTL_CLKSLCT => CTL_CLKSLCT,
-- Mode signals.
CFG_MZ80A => CFG_MZ80A,
CFG_MZ700 => CFG_MZ700,
-- Reserved.
TBA => TBA
);

2
CPLD/tranZPUterSW_pkg.vhd
View File

@@ -59,6 +59,8 @@ package tranZPUterSW_pkg is
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- Version of hdl.
constant CPLD_VERSION : integer := 1;
------------------------------------------------------------
-- Records

BIN
software/MZF/CPM223.MZF
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Binary file not shown.

38
software/asm/include/CPM_Definitions.asm
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@@ -253,26 +253,26 @@ SVCREQ EQU 068H ; I/O P
TZMM_ENIOWAIT EQU 020H ; Memory management IO Wait State enable - insert a wait state when an IO operation to E0-FF is executed.
TZMM_ORIG EQU 000H ; Original Sharp MZ80A mode, no tranZPUter features are selected except the I/O control registers (default: 0x60-063).
TZMM_BOOT EQU 001H ; Original mode but E800-EFFF is mapped to tranZPUter RAM so TZFS can be booted.
TZMM_TZFS EQU 002H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
TZMM_TZFS2 EQU 003H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
TZMM_TZFS3 EQU 004H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
TZMM_TZFS4 EQU 005H + TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
TZMM_CPM EQU 006H + TZMM_ENIOWAIT ; CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_CPM2 EQU 007H + TZMM_ENIOWAIT ; CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
TZMM_TZFS EQU 002H ; TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-FFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected.
TZMM_TZFS2 EQU 003H ; TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 1.
TZMM_TZFS3 EQU 004H ; TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 2.
TZMM_TZFS4 EQU 005H ; TZMM_ENIOWAIT ; TZFS main memory configuration. all memory is in tranZPUter RAM, E800-EFFF is used by TZFS, SA1510 is at 0000-1000 and RAM is 1000-CFFF, 64K Block 0 selected, F000-FFFF is in 64K Block 3.
TZMM_CPM EQU 006H ; TZMM_ENIOWAIT ; CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_CPM2 EQU 007H ; TZMM_ENIOWAIT ; CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
; Special case for 0000:003F (interrupt vectors) which resides in block 4, F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_MZ700_0 EQU 00AH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
TZMM_MZ700_1 EQU 00BH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_2 EQU 00CH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_3 EQU 00DH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_MZ700_4 EQU 00EH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_TZPU0 EQU 018H + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
TZMM_TZPU1 EQU 019H + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
TZMM_TZPU2 EQU 01AH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
TZMM_TZPU3 EQU 01BH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
TZMM_TZPU4 EQU 01CH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
TZMM_TZPU5 EQU 01DH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
TZMM_TZPU6 EQU 01EH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
TZMM_TZPU7 EQU 01FH + TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
TZMM_MZ700_0 EQU 00AH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
TZMM_MZ700_1 EQU 00BH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_2 EQU 00CH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_3 EQU 00DH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_MZ700_4 EQU 00EH ; TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
TZMM_TZPU0 EQU 018H ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected.
TZMM_TZPU1 EQU 019H ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected.
TZMM_TZPU2 EQU 01AH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected.
TZMM_TZPU3 EQU 01BH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected.
TZMM_TZPU4 EQU 01CH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected.
TZMM_TZPU5 EQU 01DH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected.
TZMM_TZPU6 EQU 01EH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected.
TZMM_TZPU7 EQU 01FH ; TZMM_ENIOWAIT ; Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected.
;-----------------------------------------------
; TZ File System Header (MZF)

4
software/asm/include/TZFS_Definitions.asm
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@@ -190,6 +190,9 @@ SETXMHZ EQU 062H ; Selec
SET2MHZ EQU 064H ; Select the system 2MHz clock frequency.
CLKSELRD EQU 066H ; Read clock selected setting, 0 = 2MHz, 1 = XMHz
SVCREQ EQU 068H ; I/O Processor service request.
CPLDCFG EQU 06EH ; Version 2.1 CPLD configuration register.
CPLDSTATUS EQU 06EH ; Version 2.1 CPLD status register.
CPLDINFO EQU 06FH ; Version 2.1 CPLD version information register.
;-----------------------------------------------
; tranZPUter SW Memory Management modes
@@ -204,6 +207,7 @@ TZMM_TZFS4 EQU 005H + TZMM_ENIOWAIT ; TZFS
TZMM_CPM EQU 006H + TZMM_ENIOWAIT ; CPM main memory configuration, all memory on the tranZPUter board, 64K block 4 selected. Special case for F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_CPM2 EQU 007H + TZMM_ENIOWAIT ; CPM main memory configuration, F000-FFFF are on the tranZPUter board in block 4, 0040-CFFF and E800-EFFF are in block 5, mainboard for D000-DFFF (video), E000-E800 (Memory control) selected.
; Special case for 0000:003F (interrupt vectors) which resides in block 4, F3C0:F3FF & F7C0:F7FF (floppy disk paging vectors) which resides on the mainboard.
TZMM_COMPAT EQU 008H + TZMM_ENIOWAIT ; Original mode but with main DRAM in Bank 0 to allow bootstrapping of programs from other machines such as the MZ700.
TZMM_MZ700_0 EQU 00AH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the mainboard.
TZMM_MZ700_1 EQU 00BH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.
TZMM_MZ700_2 EQU 00CH + TZMM_ENIOWAIT ; MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is on the tranZPUter in block 6.

BIN
software/roms/CPM223.BIN
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Binary file not shown.