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Philip Smart
2019-10-25 20:11:42 +01:00
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## Foreword
This document is a work in progress.
## Overview
The Sharp MZ80A is based on the Z80 CPU running at 2MHz. It is vintage and under powered compared with modern computers (or Raspberry Pi). Besides being part of history, it has a software base that is useful from time to time and still has followers. A software Emulator could be written but this is an alternative, provide an upgrade than can power the machine with multiple different CPU's (in FPGA, ie. ZPU, 68000 etc) and also power it with a Z80 running upto 128MHz. This can be done by bus mastering where the original CPU is put into tri-state and the FPGA takes control of the bus.
Besides providing more powerful and alternative CPU's and memory, the FPGA can act as a Floppy Drive, Hard Drive etc using the connected SD Card and provide a menu system by overlaying the video memory when invoked.
This design is still in its infancy, many features have been tested and the schematic/pcb made, it is just a matter of the VHDL and software to be further developed.
## tranZPUter v1.0
#####
![alt text](https://github.com/pdsmart/MZ80A_RFS/blob/master/docs/IMG_9630.jpg)
![alt text](https://github.com/pdsmart/MZ80A_RFS/blob/master/docs/IMG_9631.jpg)
![alt text](https://github.com/pdsmart/MZ80A_RFS/blob/master/docs/IMG_9636.jpg)
![alt text](https://github.com/pdsmart/MZ80A_RFS/blob/master/docs/IMG_9637.jpg)
![alt text](https://github.com/pdsmart/MZ80A_RFS/blob/master/docs/IMG_9681.jpg)
## Credits
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice.
## Licenses
This design, hardware and software, is licensed under th GNU Public Licence v3.

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--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Clock_12to100
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone II" variation_name="Clock_12to100" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_12to100.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.ppf"]

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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clock_12to100.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Clock_12to100 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clock_12to100;
ARCHITECTURE SYN OF clock_12to100 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 50,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 83333,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=Clock_12to100",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_12to100.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

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--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Clock_25to100
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

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build/Clock_25to100.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone II" variation_name="Clock_25to100" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

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build/Clock_25to100.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_25to100.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.ppf"]

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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clock_25to100.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Clock_25to100 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clock_25to100;
ARCHITECTURE SYN OF clock_25to100 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 40000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=Clock_25to100",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_25to100.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

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build/Clock_50to100.BAK.vhd Normal file
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@@ -0,0 +1,397 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clock_50to100.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Clock_50to100 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clock_50to100;
ARCHITECTURE SYN OF clock_50to100 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "-2000",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

25
build/Clock_50to100.cmp Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component Clock_50to100
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

209
build/Clock_50to100.cnx Normal file
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@@ -0,0 +1,209 @@
VERSION: WM1.0
MODULE: altpll
PRIVATE: ACTIVECLK_CHECK STRING "0"
PRIVATE: BANDWIDTH STRING "1.000"
PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
PRIVATE: BANDWIDTH_PRESET STRING "Low"
PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
PRIVATE: CLKLOSS_CHECK STRING "0"
PRIVATE: CLKSWITCH_CHECK STRING "1"
PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
PRIVATE: CREATE_INCLK1_CHECK STRING "0"
PRIVATE: CUR_DEDICATED_CLK STRING "c0"
PRIVATE: CUR_FBIN_CLK STRING "c0"
PRIVATE: DEVICE_SPEED_GRADE STRING "7"
PRIVATE: DIV_FACTOR0 NUMERIC "1"
PRIVATE: DIV_FACTOR1 NUMERIC "1"
PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
PRIVATE: GLOCKED_MODE_CHECK STRING "0"
PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
PRIVATE: LONG_SCAN_RADIO STRING "1"
PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
PRIVATE: MIRROR_CLK0 STRING "0"
PRIVATE: MIRROR_CLK1 STRING "0"
PRIVATE: MULT_FACTOR0 NUMERIC "1"
PRIVATE: MULT_FACTOR1 NUMERIC "1"
PRIVATE: NORMAL_MODE_RADIO STRING "1"
PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
PRIVATE: PLL_ARESET_CHECK STRING "1"
PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
PRIVATE: PLL_ENA_CHECK STRING "0"
PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
PRIVATE: PLL_PFDENA_CHECK STRING "0"
PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
PRIVATE: SACN_INPUTS_CHECK STRING "0"
PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
PRIVATE: SHORT_SCAN_RADIO STRING "0"
PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
PRIVATE: SPREAD_FREQ STRING "50.000"
PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
PRIVATE: SPREAD_PERCENT STRING "0.500"
PRIVATE: SPREAD_USE STRING "0"
PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
PRIVATE: STICKY_CLK0 STRING "1"
PRIVATE: STICKY_CLK1 STRING "1"
PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
PRIVATE: USE_CLK0 STRING "1"
PRIVATE: USE_CLK1 STRING "1"
PRIVATE: USE_CLKENA0 STRING "0"
PRIVATE: USE_CLKENA1 STRING "0"
PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
PRIVATE: ZERO_DELAY_RADIO STRING "0"
LIBRARY: altera_mf altera_mf.altera_mf_components.all
CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
CONSTANT: CLK1_PHASE_SHIFT STRING "0"
CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
CONSTANT: LPM_TYPE STRING "altpll"
CONSTANT: OPERATION_MODE STRING "NORMAL"
CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
CONSTANT: PORT_ARESET STRING "PORT_USED"
CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
CONSTANT: PORT_INCLK0 STRING "PORT_USED"
CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
CONSTANT: PORT_LOCKED STRING "PORT_USED"
CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
CONSTANT: PORT_clk0 STRING "PORT_USED"
CONSTANT: PORT_clk1 STRING "PORT_USED"
CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
USED_PORT: areset 0 0 0 0 INPUT GND "areset"
USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
CONNECT: @areset 0 0 0 0 areset 0 0 0 0
CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
CONNECT: c0 0 0 0 0 @clk 0 0 1 0
CONNECT: c1 0 0 0 0 @clk 0 0 1 1
CONNECT: locked 0 0 0 0 @locked 0 0 0 0
GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
LIB_FILE: altera_mf
LICENSE_ID: "DEVICE_FAMILY_Cyclone 10 LP" 10915102B3011615119A
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 10915102A3011615119A
LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 10915102T3011615119M
LICENSE_ID: "DEVICE_FAMILY_MAX V" 10915102H3011615119A
LICENSE_ID: "DEVICE_FAMILY_Arria II GX" 10915102P3011615119S
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 10915102B3011615119A
LICENSE_ID: "DEVICE_FAMILY_MAX II" 10915102N3011615119S
LICENSE_ID: "DEVICE_FAMILY_MAX 10" 10915102N3011615119S
LICENSE_ID: "FEATURE_STRATIXGX_DPA" 10915102V3011615119C
LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 10915102T3011615119M
SUPPORTED_DEVICE_FAMILY: "Cyclone 10 LP"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
SUPPORTED_DEVICE_FAMILY: "Arria II GX"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
SUPPORTED_DEVICE_FAMILY: "MAX 10"
SUPPORTED_DEVICE_FAMILY: "Cyclone II"
WIZARD_TITLE: "ALTPLL"
QUARTUS_VERSION: "Version 17.0"
QUARTUS_SVERSION: "17.0.2 Build 602 07/19/2017 SJ Lite Edition:07/19/2017"
QUARTUS_BUILD_DATE: "07/19/2017"
ALTERA_COPYRIGHT: "Copyright (C) 2017 Intel Corporation. All rights reserved."
HELP_MENU_ITEM: FALSE "IUG$altpll Megafunction User Guide$http://www.altera.com/literature/ug/ug_altpll.pdf"
HELP_MENU_ITEM: FALSE "IUG$General-Purpose PLLs in Stratix (GX) Devices$http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf"
HELP_MENU_ITEM: FALSE "IUG$PLLs in Stratix II Devices$http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf"
HELP_MENU_ITEM: FALSE "IUG$Clock Networks and PLLs in Stratix III Devices$http://www.altera.com/literature/hb/stx3/stx3_siii51006.pdf "
HELP_MENU_ITEM: FALSE "IUG$PLLs in Cyclone II Devices$http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf"

7
build/Clock_50to100.cnxerr Normal file
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@@ -0,0 +1,7 @@
*******************************************
** CNX File Error Log **
*******************************************
Line 0: WM1.0
No valid wizard signature (generation mode ) found

12
build/Clock_50to100.ppf Normal file
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@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone II" variation_name="Clock_50to100" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

5
build/Clock_50to100.qip Normal file
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@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_50to100.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.ppf"]

397
build/Clock_50to100.vhd Normal file
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@@ -0,0 +1,397 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clock_50to100.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Clock_50to100 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clock_50to100;
ARCHITECTURE SYN OF clock_50to100 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

132
build/Makefile Normal file
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@@ -0,0 +1,132 @@
#########################################################################################################
##
## Name: Makefile
## Created: June 2019
## Author(s): Philip Smart
## Description: tranZPUter Makefile
## This script builds the tranZPUter fpga test images.
##
## Credits:
## Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
##
## History: September 2019 - Initial script written.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
ROOT = ../
ZPUROOT = ../../zpu/
# Build utilites
QUARTUS_SH = quartus_sh
QUARTUS_CPF = quartus_cpf
TEE = tee
ECHO = echo
MV = mv
GREP = grep
RM = rm
CC = CC $(CINCLUDES)
AR = ar
LD = ld
# Build flags
SH_FLAGS = --flow compile
CPF_FLAGS = -c -o bitstream_compression=on
MSG_FILTER = "Error\|success"
# MSG_FILTER = "Info\|Warning\|Error\|success"
# MSG_FILTER = "Info\|Warning\|Error\|success"
# MSG_FILTER = "Info\|Warning\|Error\|success"
SOC = $(ZPUROOT)/zpu_soc.vhd $(ROOT)/zpu_soc_pkg.vhd
ZPU_EVO = $(ZPUROOT)/cpu/zpu_core_evo.vhd $(ZPUROOT)/cpu/zpu_pkg.vhd
.PHONY: all
all: tranZPUter_SMALL tranZPUter_MEDIUM tranZPUter_FLEX tranZPUter_EVO tranZPUter_EVO_MINIMAL
tranZPUter: tranZPUter_SMALL tranZPUter_MEDIUM tranZPUter_FLEX tranZPUter_EVO tranZPUter_EVO_MINIMAL
SMALL: tranZPUter_SMALL
MEDIUM: tranZPUter_MEDIUM
FLEX: tranZPUter_FLEX
EVO: tranZPUter_EVO
EVO_MINIMAL: tranZPUter_EVO_MINIMAL
tranZPUter_SMALL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' |\
sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 0/g' |\
sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 0/g' |\
sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 0/g' |\
sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 0/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
$(QUARTUS_SH) $(SH_FLAGS) tranZPUter.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
$(MV) output_files/tranZPUter.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
tranZPUter_MEDIUM:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 0/g' |\
sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' |\
sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 0/g' |\
sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 0/g' |\
sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 0/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) tranZPUter.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) output_files/tranZPUter.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
tranZPUter_FLEX:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 0/g' |\
sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 0/g' |\
sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' |\
sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 0/g' |\
sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 0/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) tranZPUter.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) output_files/tranZPUter.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
tranZPUter_EVO:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 0/g' |\
sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 0/g' |\
sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 0/g' |\
sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' |\
sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 0/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) tranZPUter.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) output_files/tranZPUter.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
tranZPUter_EVO_MINIMAL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 0/g' |\
sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 0/g' |\
sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 0/g' |\
sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 0/g' |\
sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) tranZPUter.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) output_files/tranZPUter.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
clean:
@$(ECHO) "Removing all temporary files..."
@$(RM) -fr c5_pin_model_dump.txt ./db tranZPUter.asm.rpt tranZPUter.done tranZPUter.fit.rpt tranZPUter.fit.smsg tranZPUter.fit.summary tranZPUter.flow.rpt tranZPUter.jdi tranZPUter.map.rpt tranZPUter.map.smsg tranZPUter.map.summary tranZPUter.pin tranZPUter.rbf tranZPUter.sld tranZPUter.sof tranZPUter.sta.rpt tranZPUter.sta.summary ./incremental_db qmegawiz_errors_log.txt tranZPUter.pof tranZPUter*.log tranZPUter*.rbf tranZPUter*.sof tranZPUter*.sta.smsg
@$(RM) -fr output_files

4
build/clean.sh Executable file
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@@ -0,0 +1,4 @@
#!/bin/bash
rm -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt
rm -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof

162
build/constraints.sdc Normal file
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## Generated SDC file "hello_led.out.sdc"
## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
## DATE "Fri Jul 06 23:05:47 2012"
##
## DEVICE "EP3C25Q240C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
create_generated_clock -name sysclk -source [get_pins {mypll|altpll_component|pll|clk[0]}]
create_generated_clock -name sd1clk_pin -source [get_pins {mypll|altpll_component|pll|clk[1]}] [get_ports {DRAM_CLK}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty;
#**************************************************************
# Set Input Delay
#**************************************************************
#set_input_delay -clock sd1clk_pin -max 5.8 [get_ports DRAM_DQ*]
#set_input_delay -clock sd1clk_pin -min 3.2 [get_ports DRAM_DQ*]
# Delays for async signals - not necessary, but might as well avoid
# having unconstrained ports in the design
set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
#set_input_delay -clock sysclk -min 0.5 [get_ports {SD_DAT}]
#set_input_delay -clock sysclk -max 0.5 [get_ports {SD_DAT}]
#set_input_delay -clock sysclk -min 0.5 [get_ports {GPIO*}]
#set_input_delay -clock sysclk -max 0.5 [get_ports {GPIO*}]
#set_input_delay -clock sysclk -min 0.5 [get_ports {PS2_*}]
#set_input_delay -clock sysclk -max 0.5 [get_ports {PS2_*}]
#**************************************************************
# Set Output Delay
#**************************************************************
#set_output_delay -clock sd1clk_pin -max 1.5 [get_ports DRAM_*]
#set_output_delay -clock sd1clk_pin -min -0.8 [get_ports DRAM_*]
#set_output_delay -clock sd1clk_pin -max 0.5 [get_ports DRAM_CLK]
#set_output_delay -clock sd1clk_pin -min 0.5 [get_ports DRAM_CLK]
# Delays for async signals - not necessary, but might as well avoid
# having unconstrained ports in the design
set_output_delay -clock sysclk -min 0.0 [get_ports UART_TXD]
set_output_delay -clock sysclk -max 0.5 [get_ports UART_TXD]
#set_output_delay -clock sysclk -min 0.5 [get_ports {SD_DAT3}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {SD_DAT3}]
#set_output_delay -clock sysclk -min 0.5 [get_ports {SD_CLK}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {SD_CLK}]
#set_output_delay -clock sysclk -min 0.5 [get_ports {SD_CMD}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {SD_CMD}]
#set_output_delay -clock sysclk -min 0.5 [get_ports {VGA_*}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {VGA_*}]
set_output_delay -clock sysclk -min 0.5 [get_ports {LED*}]
set_output_delay -clock sysclk -max 0.5 [get_ports {LED*}]
#set_output_delay -clock sysclk -min 0.5 [get_ports {HEX*}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {HEX*}]
#set_output_delay -clock sysclk -min 0.5 [get_ports {GPIO*}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {GPIO*}]
#set_output_delay -clock sysclk -min 0.5 [get_ports {PS2_*}]
#set_output_delay -clock sysclk -max 0.5 [get_ports {PS2_*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from {KEY*} -to {*}
set_false_path -from {SW*} -to {*}
#**************************************************************
# Set Multicycle Path
#**************************************************************
#set_multicycle_path -from [get_clocks {mypll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sd2clk_pin}] -setup -end 2
#set_multicycle_path -from [get_clocks {mypll2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sd2clk_pin}] -setup -end 2
set_multicycle_path -from [get_clocks {sd1clk_pin}] -to [get_clocks {mypll|altpll_component|pll|clk[0]}] -setup -end 2
# set_multicycle_path -from {VirtualToplevel:myVirtualToplevel|*:myrom|*} -to {VirtualToplevel:myVirtualToplevel|zpu_core:zpu|*} -setup -end 2
# set_multicycle_path -from {VirtualToplevel:myVirtualToplevel|*:myrom|*} -to {VirtualToplevel:myVirtualToplevel|zpu_core:zpu|*} -hold -end 2
# The result from the hardware multiplier isn't used for two clocks, so we set a multicycle for that.
set_multicycle_path -through [get_nets {*zpu|Mult0*}] -setup -end 2
set_multicycle_path -through [get_nets {*zpu|Mult0*}] -hold -end 2
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

126
build/tranZPUter.out.sdc Normal file
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@@ -0,0 +1,126 @@
## Generated SDC file "tranZPUter.out.sdc"
## Copyright (C) 2017 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
## DATE "Tue Sep 17 13:54:17 2019"
##
## DEVICE "10CL025YU256C8G"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}]
create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_keepers {USER_BTN*}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

23
build/tranZPUter.qpf Normal file
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@@ -0,0 +1,23 @@
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "5.0"
DATE = "23:35:58 September 01, 2005"
# Revisions
PROJECT_REVISION = "tranZPUter"

506
build/tranZPUter.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 11:51:50 November 03, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# cyc1000_nios_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:51:50 NOVEMBER 03, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone 10 LP"
set_global_assignment -name TOP_LEVEL_ENTITY tranZPUter
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE 10CL025YU256C8G
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
# Assembler Assignments
# =====================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
#============================================================
# UART (PIO_01, PIO_02, PIO_05, PIO_06)
#============================================================
set_location_assignment PIN_D15 -to UART_RX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
set_location_assignment PIN_F13 -to UART_TX_0
set_location_assignment PIN_F15 -to UART_TX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
set_location_assignment PIN_C15 -to UART_RX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
#============================================================
# SD CARD (PIO_03, PIO_04, PIO_07, PIO_08)
#============================================================
set_location_assignment PIN_D16 -to SDCARD_MISO[0]
set_location_assignment PIN_C16 -to SDCARD_MOSI[0]
set_location_assignment PIN_F16 -to SDCARD_CLK[0]
set_location_assignment PIN_B16 -to SDCARD_CS[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_M2 -to CLOCK_12M
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_12M
set_location_assignment PIN_E15 -to CLK_X
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_X
#============================================================
# LED
#============================================================
set_location_assignment PIN_N3 -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_N5 -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_location_assignment PIN_R4 -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_location_assignment PIN_T2 -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_location_assignment PIN_R3 -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_location_assignment PIN_T3 -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_location_assignment PIN_T4 -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_location_assignment PIN_M6 -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
#============================================================
# SDRAM
#============================================================
# Data bus
set_location_assignment PIN_B10 -to DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[0]
set_location_assignment PIN_A10 -to DQ[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[1]
set_location_assignment PIN_B11 -to DQ[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[2]
set_location_assignment PIN_A11 -to DQ[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[3]
set_location_assignment PIN_A12 -to DQ[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[4]
set_location_assignment PIN_D9 -to DQ[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[5]
set_location_assignment PIN_B12 -to DQ[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[6]
set_location_assignment PIN_C9 -to DQ[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[7]
set_location_assignment PIN_D11 -to DQ[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[8]
set_location_assignment PIN_E11 -to DQ[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[9]
set_location_assignment PIN_A15 -to DQ[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[10]
set_location_assignment PIN_E9 -to DQ[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[11]
set_location_assignment PIN_D14 -to DQ[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[12]
set_location_assignment PIN_F9 -to DQ[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[13]
set_location_assignment PIN_C14 -to DQ[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[14]
set_location_assignment PIN_A14 -to DQ[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[15]
# Address Bus
set_location_assignment PIN_A3 -to A[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[0]
set_location_assignment PIN_B5 -to A[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[1]
set_location_assignment PIN_B4 -to A[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[2]
set_location_assignment PIN_B3 -to A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[3]
set_location_assignment PIN_C3 -to A[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[4]
set_location_assignment PIN_D3 -to A[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[5]
set_location_assignment PIN_E6 -to A[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[6]
set_location_assignment PIN_E7 -to A[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[7]
set_location_assignment PIN_D6 -to A[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[8]
set_location_assignment PIN_D8 -to A[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[9]
set_location_assignment PIN_A5 -to A[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[10]
set_location_assignment PIN_E8 -to A[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[11]
set_location_assignment PIN_A2 -to A[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[12]
set_location_assignment PIN_C6 -to A[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to A[13]
# Byte addressing
set_location_assignment PIN_A4 -to BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BA[0]
set_location_assignment PIN_B6 -to BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BA[1]
set_location_assignment PIN_B13 -to DQM[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQM[0]
set_location_assignment PIN_D12 -to DQM[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQM[1]
# Chip control.
set_location_assignment PIN_C8 -to CAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAS
set_location_assignment PIN_B7 -to RAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAS
set_location_assignment PIN_A7 -to WE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WE
set_location_assignment PIN_A6 -to CS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CS
# Clock and enabling.
set_location_assignment PIN_F8 -to CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CKE
set_location_assignment PIN_B14 -to SDRAMCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAMCLK
#============================================================
# FT2232H
#============================================================
# ADBUS
set_location_assignment PIN_H3 -to ADBUS_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_0
set_location_assignment PIN_H4 -to ADBUS_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_1
set_location_assignment PIN_J4 -to ADBUS_2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_2
set_location_assignment PIN_J5 -to ADBUS_3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_3
set_location_assignment PIN_M8 -to ADBUS_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_4
set_location_assignment PIN_N8 -to ADBUS_7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_7
# BDBUS
set_location_assignment PIN_R7 -to BDBUS[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[0]
set_location_assignment PIN_T7 -to BDBUS[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[1]
set_location_assignment PIN_R6 -to BDBUS[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[2]
set_location_assignment PIN_T6 -to BDBUS[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[3]
set_location_assignment PIN_R5 -to BDBUS[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[4]
set_location_assignment PIN_T5 -to BDBUS[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[5]
#============================================================
# Serial Configuration Memory
#============================================================
set_location_assignment PIN_H2 -to AS_DATA0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DATA0
set_location_assignment PIN_C1 -to AS_ASDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_ASDO
set_location_assignment PIN_D2 -to AS_NCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_NCS
set_location_assignment PIN_H1 -to AS_DCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DCLK
#============================================================
# PMOD IO Header PIO0 - PIO7
#============================================================
#set_location_assignment PIN_F13 -to PIO[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[1]
#set_location_assignment PIN_F15 -to PIO[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[2]
#set_location_assignment PIN_F16 -to PIO[3]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[3]
#set_location_assignment PIN_D16 -to PIO[4]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[4]
#set_location_assignment PIN_D15 -to PIO[5]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[5]
#set_location_assignment PIN_C15 -to PIO[6]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[6]
#set_location_assignment PIN_B16 -to PIO[7]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[7]
#set_location_assignment PIN_C16 -to PIO[8]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[8]
#============================================================
# TCPU - Z80 Bus Controller
#============================================================
# JP 9 GPIO14 - GPIO22 (D6-D14)
set_location_assignment PIN_N2 -to CYC_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[15]
set_location_assignment PIN_N1 -to CYC_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[14]
set_location_assignment PIN_P2 -to CYC_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[13]
set_location_assignment PIN_J1 -to CYC_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[12]
set_location_assignment PIN_J2 -to CYC_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[11]
set_location_assignment PIN_K2 -to CYC_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[10]
set_location_assignment PIN_L2 -to CYC_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[9]
set_location_assignment PIN_P1 -to CYC_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[8]
set_location_assignment PIN_R1 -to CYC_CTL_273
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_CTL_SET_n
# JP 5 GPIO8 - GPIO13 (D0 - D5)
set_location_assignment PIN_N16 -to Z80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_CLK_n
set_location_assignment PIN_L15 -to Z80_NMI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_NMI_n
set_location_assignment PIN_L16 -to Z80_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_INT_n
set_location_assignment PIN_K15 -to CYC_WAIT_I
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_WAIT_I_n
set_location_assignment PIN_K16 -to CYC_BUSACK_I
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_BUSACK_I_n
set_location_assignment PIN_J14 -to CYC_BUSACK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_BUSACK_n
set_location_assignment PIN_K1 -to D11_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D11_R
set_location_assignment PIN_L1 -to D12_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D12_R
# JP 5 GPIO23 (AIN), GPIO24 (AIN7)
set_location_assignment PIN_T12 -to CYC_BUSRQ
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_BUSRQ_n
set_location_assignment PIN_R11 -to CYC_BUSRQ_I
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_BUSRQ_I_n
# JP 4 GPIO0 (AREF), GPIO1-7 (AIN0-6)
set_location_assignment PIN_P11 -to CYC_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[0]
set_location_assignment PIN_R12 -to CYC_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[1]
set_location_assignment PIN_T13 -to CYC_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[2]
set_location_assignment PIN_R13 -to CYC_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[3]
set_location_assignment PIN_T14 -to CYC_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[4]
set_location_assignment PIN_P14 -to CYC_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[5]
set_location_assignment PIN_R14 -to CYC_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[6]
set_location_assignment PIN_T15 -to CYC_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_D[7]
# user button rewired to JTAG jumper
set_location_assignment PIN_N6 -to CYC_CTL_CLR_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CYC_CTL_CLR_n
#============================================================
# GPIO14 - GPIO22 Header
#============================================================
#set_location_assignment PIN_N2 -to GPIO[14]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
#set_location_assignment PIN_N1 -to GPIO[15]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
#set_location_assignment PIN_P2 -to GPIO[16]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
#set_location_assignment PIN_J1 -to GPIO[17]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
#set_location_assignment PIN_J2 -to GPIO[18]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
#set_location_assignment PIN_K2 -to GPIO[19]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
#set_location_assignment PIN_L2 -to GPIO[20]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
#set_location_assignment PIN_P1 -to GPIO[21]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
#set_location_assignment PIN_R1 -to GPIO[22]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
#============================================================
# GPIO8 - GPIO13 Header
#============================================================
#set_location_assignment PIN_N16 -to GPIO[8]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
#set_location_assignment PIN_L15 -to GPIO[9]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
#set_location_assignment PIN_L16 -to GPIO[10]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
#set_location_assignment PIN_K15 -to GPIO[11]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
#set_location_assignment PIN_K16 -to GPIO[12]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
#set_location_assignment PIN_J14 -to GPIO[13]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
#set_location_assignment PIN_K1 -to D11_R
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D11_R
#set_location_assignment PIN_L1 -to D12_R
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D12_R
#============================================================
# GPIO0 - GPIO7 Header
#============================================================
#set_location_assignment PIN_T12 -to AIN
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AIN
#set_location_assignment PIN_P11 -to AREF
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AREF
#set_location_assignment PIN_R12 -to GPIO[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
#set_location_assignment PIN_T13 -to GPIO[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
#set_location_assignment PIN_R13 -to GPIO[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
#set_location_assignment PIN_T14 -to GPIO[3]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
#set_location_assignment PIN_P14 -to GPIO[4]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
#set_location_assignment PIN_R14 -to GPIO[5]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
#set_location_assignment PIN_T15 -to GPIO[6]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
#set_location_assignment PIN_R11 -to GPIO[7]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
#============================================================
# Buttons
#============================================================
#set_location_assignment PIN_N6 -to USER_BTN
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_BTN
#============================================================
# 3-Axis Accelerometer
#============================================================
set_location_assignment PIN_D1 -to SEN_CS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_CS
set_location_assignment PIN_B1 -to SEN_INT1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT1
set_location_assignment PIN_C2 -to SEN_INT2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT2
set_location_assignment PIN_G2 -to SEN_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDI
set_location_assignment PIN_G1 -to SEN_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDO
set_location_assignment PIN_F3 -to SEN_SPC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SPC
#============================================================
# Modules and Files
#============================================================
#
set_global_assignment -name VHDL_FILE tranZPUter_Toplevel.vhd
set_global_assignment -name QIP_FILE Clock_12to100.qip
set_global_assignment -name SDC_FILE tranZPUter_constraints.sdc
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_flex.vhd
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_pkg.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_flex_pkg.vhd
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_small.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_small_pkg.vhd
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_medium.vhd
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_core_evo.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_medium_pkg.vhd
set_global_assignment -name VHDL_FILE ../../zpu/cpu/zpu_uart_debug.vhd
#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
set_global_assignment -name VHDL_FILE ../../zpu/zpu_soc.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/dpram.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_brgen.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_mv_filter.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_rx.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart_tx.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/uart.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/uart/simple_uart.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/fifo/fifo.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/intr/interrupt_controller.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/spi/spi.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/SDMMC/SDCard.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/ps2/io_ps2_com.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/BRAM/BootROM.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/ioctl/ioctl.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/dualport_ram.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/TCPU/tcpu.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/I2C/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
set_global_assignment -name QIP_FILE ../../zpu/devices/WishBone/SDRAM/sdram.qip
#set_global_assignment -name VERILOG_FILE ../../zpu/cpu/qdiv.v
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Peripherals/simple_uart.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/SysRAM/SysRAM.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/DualPortRAM.vhd
#set_global_assignment -name VERILOG_FILE ../../zpu/devices/sysbus/RAM/TwoWayCache.v
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/RAM/sdram_cached.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/Toplevel_Config.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/DMACache_config.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Video/video_vga_master.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Video/video_vga_dither.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/Video/vga_controller.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/DMACache.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/DMACache_pkg.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/FIFO_Counter.vhd
#set_global_assignment -name VHDL_FILE ../../zpu/devices/sysbus/DMA/DMACacheRAM.vhd
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

3
build/tranZPUter.srf Normal file
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{ "" "" "" "*" { } { } 0 10037 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 18236 "" 0 0 "Design Software" 0 -1 0 ""}

157
build/tranZPUter_Toplevel.vhd Normal file
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.zpu_soc_pkg.all;
entity tranZPUter is
port (
-- Clock
CLOCK_12M : in std_logic;
-- LED
LED : out std_logic_vector(7 downto 0);
-- Debounced keys
-- KEY : in std_logic_vector(1 downto 0);
-- DIP switches
-- SW : in std_logic_vector(3 downto 0);
USER_BTN : in std_logic;
-- TDI : in std_logic;
-- TCK : in std_logic;
-- TCS : in std_logic;
-- TDO : out std_logic;
-- I2C_SDAT : inout std_logic;
-- I2C_SCLK : out std_logic;
-- GPIO_0 : inout std_logic_vector(33 downto 0);
-- GPIO_1 : inout std_logic_vector(33 downto 0);
-- SD Card 1
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
UART_RX_0 : in std_logic;
UART_TX_0 : out std_logic;
UART_RX_1 : in std_logic;
UART_TX_1 : out std_logic;
-- SDRAM signals
SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
SDRAM_CKE : out std_logic; -- clock enable.
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
SDRAM_CS : out std_logic; -- a single chip select
SDRAM_WE : out std_logic; -- write enable
SDRAM_RAS : out std_logic; -- row address select
SDRAM_CAS : out std_logic; -- columns address select
-- TCPU signals.
CYC_D : inout std_logic_vector(15 downto 0); -- Data bus
CYC_CTL_SET_n : out std_logic; -- Set the transceiver control signals.
CYC_CTL_RST_n : out std_logic; -- Reset the transceiver control signals.
CYC_CLK_n : in std_logic; -- Z80 Main Clock
CYC_NMI_n : in std_logic; -- Z80 NMI converted to 3.3v
CYC_INT_n : in std_logic; -- Z80 INT converted to 3.,3v
CYC_WAIT_I_n : in std_logic; -- Z80 Wait converted to 3.3v.
CYC_BUSACK_I_n : in std_logic; -- Z80 Bus Ack converted to 3.3v.
CYC_BUSACK_n : out std_logic; -- CYC sending BUS ACK
CYC_BUSRQ_n : out std_logic; -- CYC requesting Z80 bus.
CYC_BUSRQ_I_n : in std_logic -- System requesting Z80 bus.
);
END entity;
architecture rtl of tranZPUter is
signal reset : std_logic;
signal sysclk : std_logic;
signal memclk : std_logic;
signal pll_locked : std_logic;
--signal ps2m_clk_in : std_logic;
--signal ps2m_clk_out : std_logic;
--signal ps2m_dat_in : std_logic;
--signal ps2m_dat_out : std_logic;
--signal ps2k_clk_in : std_logic;
--signal ps2k_clk_out : std_logic;
--signal ps2k_dat_in : std_logic;
--signal ps2k_dat_out : std_logic;
--alias PS2_MDAT : std_logic is GPIO_1(19);
--alias PS2_MCLK : std_logic is GPIO_1(18);
begin
--I2C_SDAT <= 'Z';
--GPIO_0(33 downto 2) <= (others => 'Z');
--GPIO_1 <= (others => 'Z');
--LED <= "101010" & reset & UART_RX_0;
LED <= "00000000";
mypll : entity work.Clock_12to100
port map
(
inclk0 => CLOCK_12M,
c0 => sysclk,
c1 => memclk,
locked => pll_locked
);
--reset<=(not SW(0) xor KEY(0)) and pll_locked;
reset<=(not USER_BTN) and pll_locked;
myVirtualToplevel : entity work.zpu_soc
generic map
(
SYSCLK_FREQUENCY => SYSCLK_CYC1000_FREQ
)
port map
(
SYSCLK => sysclk,
MEMCLK => memclk,
RESET_IN => reset,
-- RS232
UART_RX_0 => UART_RX_0,
UART_TX_0 => UART_TX_0,
UART_RX_1 => UART_RX_1,
UART_TX_1 => UART_TX_1,
-- SD Card (SPI) signals
SDCARD_MISO => SDCARD_MISO,
SDCARD_MOSI => SDCARD_MOSI,
SDCARD_CLK => SDCARD_CLK,
SDCARD_CS => SDCARD_CS,
-- SDRAM signals
SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz
SDRAM_RST => reset, -- reset the sdram controller.
SDRAM_CKE => SDRAM_CKE, -- clock enable.
SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus
SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus
SDRAM_DQM => SDRAM_DQM, -- two byte masks
SDRAM_BA => SDRAM_BA, -- two banks
SDRAM_CS_n => SDRAM_CS, -- a single chip select
SDRAM_WE_n => SDRAM_WE, -- write enable
SDRAM_RAS_n => SDRAM_RAS, -- row address select
SDRAM_CAS_n => SDRAM_CAS, -- columns address select
SDRAM_READY => open, -- sd ready.
-- TCPU Bus
TCPU_DATA => CYC_D, -- Data bus
TCPU_CTL_SET_n => CYC_CTL_SET_n, -- Set the transceiver control signals.
TCPU_CTL_RST_n => CYC_CTL_RST_n, -- Reset the transceiver control signals.
TCPU_CLK_n => CYC_CLK_n, -- Z80 Main Clock
TCPU_NMI_n => CYC_NMI_n, -- Z80 NMI converted to 3.3v
TCPU_INT_n => CYC_INT_n, -- Z80 INT converted to 3.,3v
TCPU_WAIT_I_n => CYC_WAIT_I_n, -- Z80 Wait converted to 3.3v.
TCPU_BUSACK_I_n => CYC_BUSACK_I_n, -- Z80 Bus Ack converted to 3.3v.
TCPU_BUSACK_n => CYC_BUSACK_n, -- CYC sending BUS ACK
TCPU_BUSRQ_n => CYC_BUSRQ_n, -- CYC requesting Z80 bus.
TCPU_BUSRQ_I_n => CYC_BUSRQ_I_n -- System requesting Z80 bus.
);
end architecture;

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## Generated SDC file "E115_zpu.out.sdc"
## Copyright (C) 2017 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
## DATE "Sat Jun 22 23:32:00 2019"
##
## DEVICE "EP4CE115F23I7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}]
create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#derive_clock_uncertainty
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
#**************************************************************
# Set Input Delay
#**************************************************************
# Delays for async signals - not necessary, but might as well avoid
# having unconstrained ports in the design
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
#**************************************************************
# Set Output Delay
#**************************************************************
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_keepers {USER_BTN*}]
#set_false_path -from [get_keepers {SW*}]
#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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; the following is only to get the original length of 2048 bytes
ALIGN: MACRO ?boundary
DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, 0FFh
ENDM
; the following is only to get the original length of 2048 bytes
ALIGN_NOPS:MACRO ?boundary
DS ?boundary - 1 - ($ + ?boundary - 1) % ?boundary, 000h
ENDM
;
; Pads up to a certain address.
; Gives an error message if that address is already exceeded.
;
PAD: MACRO ?address
IF $ > ?address
ERROR "Alignment exceeds %s"; % ?address
ENDIF
ds ?address - $
ENDM
;
; Pads up to the next multiple of the specified address.
;
;ALIGN: MACRO ?boundary
; ds ?boundary - 1 - ($ + ?boundary - 1) % ?boundary
; ENDM
;
; Pads to ensure a section of the given size does not cross a 100H boundary.
;
ALIGN_FIT8: MACRO ?size
ds (($ + ?size - 1) >> 8) != ($ >> 8) && (100H - ($ & 0FFH)) || 0
ENDM

8
software/asm/monitor_80c_SA1510.asm Normal file
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; Configurable parameters.
COLW: EQU 80 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 1
INCLUDE "sa1510.asm"

8
software/asm/monitor_SA1510.asm Normal file
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; Configurable parameters.
COLW: EQU 40 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 0
INCLUDE "sa1510.asm"

2795
software/asm/sa1510.asm Normal file
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BIN
software/mzf/hi-ramcheck.mzf Normal file
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Binary file not shown.

BIN
software/mzf/sharpmz-test.mzf Normal file
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7
tools/ConvertToMif.sh Executable file
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#!/bin/bash
BASE=`basename $1`
echo "Converting ${BASE}.bin to Memory Initialization File ${BASE}.mif..."
srec_cat ${BASE}.bin -binary -Output ${BASE}.mif -Memory_Initialization_File

64
tools/assemble_roms.sh Executable file
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#!/bin/bash
#########################################################################################################
##
## Name: assemble_roms.sh
## Created: August 2018
## Author(s): Philip Smart
## Description: Sharp MZ series ROM assembly tool
## This script takes Sharp MZ ROMS in assembler format and compiles/assembles them
## into a ROM file using the GLASS Z80 assembler.
##
## Credits:
## Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
##
## History: August 2018 - Initial script written.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
TOOLDIR=../../tools
JARDIR=../../tools
ASM=glass.jar
BUILDROMLIST="IPL monitor_SA1510 monitor_80c_SA1510 monitor_mz-1r12 quickdisk_mz-1e05 quickdisk_mz-1e14 monitor_1Z-013A monitor_80c_1Z-013A"
BUILDMZFLIST="hi-ramcheck sharpmz-test"
ASMDIR=../software/asm
INCDIR=../software/asm/include
ROMDIR=../software/roms
MZFDIR=../software/mzf
# Go through list and build image.
#
for f in ${BUILDROMLIST} ${BUILDMZFLIST}
do
echo "Assembling: $f..."
# Assemble the source.
echo "java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMDIR}/${f}.obj ${ASMDIR}/${f}.sym"
java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMDIR}/${f}.obj ${ASMDIR}/${f}.sym -I ${INCDIR}
# On successful compile, perform post actions else go onto next build.
#
if [ $? = 0 ]
then
# The object file is binary, no need to link, copy according to build group.
if [[ ${BUILDROMLIST} = *"${f}"* ]]; then
echo "Copy ${ASMDIR}/${f}.obj to ${ROMDIR}/${f}.rom"
cp ${ASMDIR}/${f}.obj ${ROMDIR}/${f}.rom
else
echo "Copy ${ASMDIR}/${f}.obj to ${MZFDIR}/${f}.mzf"
cp ${ASMDIR}/${f}.obj ${MZFDIR}/${f}.mzf
fi
fi
done

101
tools/build_meminitfiles.sh Executable file
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#!/bin/bash
#########################################################################################################
##
## Name: build_meminitfiles.sh
## Created: August 2018
## Author(s): Philip Smart
## Description: Sharp MZ series combined rom build script.
## This script takes the necessary ROM files and builds the required combined
## rom files for the emulator and converts them to MIF format.
## Change the names below if you want this script to build combined MIF files with
## different content.
##
## Credits:
## Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
##
## History: August 2018 - Initial script written.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
ROMTOOL=../tools/romtool.pl
ROMDIR=../software/roms
MIFDIR=../software/mif
MZFDIR=../software/mzf
ASMDIR=../software/asm
${ROMTOOL} --command=KEYMAP \
--a_keymap=${ROMDIR}/key_80a.rom \
--b_keymap=${ROMDIR}/key_80b.rom \
--c_keymap=${ROMDIR}/key_80c.rom \
--k_keymap=${ROMDIR}/key_80k.rom \
--7_keymap=${ROMDIR}/key_700.rom \
--8_keymap=${ROMDIR}/key_700.rom \
--12_keymap=${ROMDIR}/key_1200.rom \
--20_keymap=${ROMDIR}/key_80b.rom \
--binout=${ROMDIR}/combined_keymap.rom \
--mifout=${MIFDIR}/combined_keymap.mif
${ROMTOOL} --command=64KRAM \
--ramchecker=${MZFDIR}/hi-ramcheck.mzf \
--a_mrom=${ROMDIR}/monitor_SA1510.rom \
--mzf=${MZFDIR}/tapecheck.mzf \
--binout=${ROMDIR}/combined_mainmemory.rom \
--mifout=${MIFDIR}/combined_mainmemory.mif
${ROMTOOL} --command=MONROM \
--a_mrom=${ROMDIR}/monitor_SA1510.rom \
--b_mrom=${ROMDIR}/IPL.rom \
--c_mrom=${ROMDIR}/NEWMON.rom \
--k_mrom=${ROMDIR}/SP1002.rom \
--7_mrom=${ROMDIR}/monitor_1Z-013A.rom \
--8_mrom=${ROMDIR}/monitor_1Z-013A.rom \
--12_mrom=${ROMDIR}/SP1002.rom \
--20_mrom=${ROMDIR}/IPL.rom \
--a_80c_mrom=${ROMDIR}/monitor_80c_SA1510.rom \
--b_80c_mrom=${ROMDIR}/IPL.rom \
--c_80c_mrom=${ROMDIR}/NEWMON.rom \
--k_80c_mrom=${ROMDIR}/SP1002.rom \
--7_80c_mrom=${ROMDIR}/monitor_80c_1Z-013A.rom \
--8_80c_mrom=${ROMDIR}/monitor_80c_1Z-013A.rom \
--12_80c_mrom=${ROMDIR}/SP1002.rom \
--20_80c_mrom=${ROMDIR}/IPL.rom \
--a_userrom=${ROMDIR}/userrom.rom \
--b_userrom=${ROMDIR}/userrom.rom \
--c_userrom=${ROMDIR}/userrom.rom \
--k_userrom=${ROMDIR}/userrom.rom \
--7_userrom=${ROMDIR}/userrom.rom \
--8_userrom=${ROMDIR}/userrom.rom \
--12_userrom=${ROMDIR}/userrom.rom \
--20_userrom=${ROMDIR}/userrom.rom \
--a_fdcrom=${ROMDIR}/fdcrom.rom \
--b_fdcrom=${ROMDIR}/fdcrom.rom \
--c_fdcrom=${ROMDIR}/fdcrom.rom \
--k_fdcrom=${ROMDIR}/fdcrom.rom \
--7_fdcrom=${ROMDIR}/fdcrom.rom \
--8_fdcrom=${ROMDIR}/fdcrom.rom \
--12_fdcrom=${ROMDIR}/fdcrom.rom \
--20_fdcrom=${ROMDIR}/fdcrom.rom \
--binout=${ROMDIR}/combined_mrom.rom \
--mifout=${MIFDIR}/combined_mrom.mif
${ROMTOOL} --command=CGROM \
--a_cgrom=${ROMDIR}/mz-80acg.rom \
--b_cgrom=${ROMDIR}/MZFONT.rom \
--c_cgrom=${ROMDIR}/MZ80K_cgrom.rom \
--k_cgrom=${ROMDIR}/MZ80K_cgrom.rom \
--7_cgrom=${ROMDIR}/MZ700_cgrom.rom \
--8_cgrom=${ROMDIR}/MZ700_cgrom.rom \
--12_cgrom=${ROMDIR}/mz-80acg.rom \
--20_cgrom=${ROMDIR}/MZFONT.rom \
--binout=${ROMDIR}/combined_cgrom.rom \
--mifout=${MIFDIR}/combined_cgrom.mif

665
tools/mzftool.pl Executable file
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@@ -0,0 +1,665 @@
#! /usr/bin/perl
#########################################################################################################
##
## Name: mzftool.pl
## Created: August 2018
## Author(s): Philip Smart
## Description: Sharp MZ series MZF (Sharp Tape File) management tool.
## This script identifies the type of MZF file and can add or delete headers as required.
## Useful for seperating MZF compilations into Basic/Pascal/Machine Code etc.
## Also useful to add headers to homegrow machine code programs.
##
## Credits:
## Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
##
## History: August 2018 - Initial script written.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
# Title and Versioning.
#
$TITLE = "MZF Tool";
$VERSION = "0.1";
$VERSIONDATE = "25.09.2018";
# Global Modules.
#
#use strict
use Getopt::Long;
use IO::File;
use File::stat;
use File::Copy;
use Time::localtime;
use POSIX qw(tmpnam);
use Env qw(KPLUSHOME3 SYBASE SYBASE_OCS DSQUERY);
use sigtrap qw(die normal-signals);
# Error return codes.
#
$ERR_BADFILENAME = 1;
$ERR_BADFILEDATA = 2;
$ERR_BADFILECREATE = 3;
$ERR_BADFUNCARGS = 4;
$ERR_BADSYSCALL = 5;
$ERR_BADCHECK = 6;
$ERR_BADENV = 7;
$ERR_SYBSERVER = 8;
$ERR_BADARGUMENTS = 9;
# Run-time constants.
#
$PROGNAME = $0;
# Run-time globals. Although in Perl you can just specify variables, keeping with most
# high-order languages it is good practise to specify non-local variables in a global header
# which aids visual variable tracking etc.
#
$dbh = 0; # Handle to a Sybase object.
$logh = 0; # Handle to open log file.
$logName = ""; # Temporary name of log file.
$logMode = "terminal"; # Default logging mode for logger.
# Configurables!!
#
$SENDMAIL = "/usr/lib/sendmail -t";
@errorMailRecipients = ( "philip.smart\@net2net.org" );
$errorMailFrom = "error\@localhost";
$errorMailSubject = "MZF Tool Errors...";
$PERL = "perl";
$PERLFLAGS = "";
##################################################################################
# GENERIC SUB-ROUTINES
##################################################################################
# Sub-routine to close the log file and email its contents to required participants.
#
sub logClose
{
# Locals.
local( $idx, $line, @mailRecipients, $mailFrom, $mailSubject, $mailHeader );
# No point closing log if one wasnt created!!
#
if($logName eq "" || $sendEmail == 0)
{
return;
}
# Back to beginning of file, to copy into email.
#
seek($logh, 0, 0);
# Build up an email to required recipients and send.
#
open(SENDMAIL, "|$SENDMAIL") or die "Cannot open $SENDMAIL: $!";
for($idx=0; $idx < @errorMailRecipients; $idx++)
{
print SENDMAIL "To: $errorMailRecipients[$idx]\n";
}
print SENDMAIL "Reply-to: $errorMailFrom\n";
print SENDMAIL "From: $errorMailFrom\n";
print SENDMAIL "Subject: $errorMailSubject\n";
print SENDMAIL "Content-type: text/plain\n\n";
while( $line = <$logh> )
{
chomp($line);
print SENDMAIL "$line\n";
}
close(SENDMAIL);
# Delete the logfile, not needed.
#
unlink($logName) or die "Couldn't unlink Error File $logName : $!";
}
# Function to write a message into a log file. The logfile is a temporary buffer, used
# to store all messages until program end. Upon completion, the buffer is emailed to required
# participants.
#
sub logWrite
{
# Get parameters, define locals.
local( $mode, $text ) = @_;
local( $date );
# Get current date and time for timestamping the log message.
#
$date = `date +'%Y.%m.%d %H:%M:%S'`;
chomp($date);
# In terminal mode (=interactive mode), always log to STDOUT.
#
if($logMode eq "terminal")
{
if(index($mode, "ND") == -1)
{
print "$date ";
}
print "$text";
if(index($mode, "NR") == -1)
{
print "\n";
}
# Die if required.
#
if (index($mode, 'die') != -1)
{
print "$date Terminating at program request.\n";
exit 1;
}
return;
}
# If the logfile hasnt been opened, open it.
#
if($logName eq "")
{
# Try new temporary filenames until we get one that doesnt already exist.
do {
$logName = tmpnam();
} until $logh = IO::File->new($logName, O_RDWR|O_CREAT|O_EXCL);
# Automatically flush out log.
$logh->autoflush(1);
# Only send email if we explicitly die.
#
$sendEmail = 0;
# Install an atexit-style handler so that when we exit or die,
# we automatically dispatch the log.
END { logClose($logh, $logName); }
}
# Print to log with date and time stamp.
#
print $logh "$date $text\n";
# Print to stdout for user view if in debug mode.
#
if($debugMode > 0)
{
print "$date $text\n";
}
# If requested, log termination message and abort program.
#
if (index($mode, 'die') != -1)
{
print $logh "$date Terminating at program request.\n";
$sendEmail = 1;
exit 1;
}
}
# Sub-routine to truncate whitespace at the front (left) of a string, returning the
# truncated string.
#
sub cutWhiteSpace
{
local( $srcString ) = @_;
local( $c, $dstString, $idx );
$dstString = "";
for($idx=0; $idx < length($srcString); $idx++)
{
# If the character is a space or tab, delete.
#
$c = substr($srcString, $idx, 1);
if(length($dstString) == 0)
{
if($c ne " " && $c ne "\t")
{
$dstString = $dstString . $c;
}
} else
{
$dstString = $dstString . $c;
}
}
return($dstString);
}
# Perl trim function to remove whitespace from the start and end of the string
#
sub trim($)
{
my $string = shift;
$string =~ s/^\s+//;
$string =~ s/\s+$//;
return $string;
}
# Left trim function to remove leading whitespace
#
sub ltrim($)
{
my $string = shift;
$string =~ s/^\s+//;
return $string;
}
# Right trim function to remove trailing whitespace
#
sub rtrim($)
{
my $string = shift;
$string =~ s/\s+$//;
return $string;
}
# Sub-routine to test if a string is empty, and if so, replace
# with an alternative string. The case of the returned string
# can be adjusted according to the $convertCase parameter.
#
sub trString
{
local( $tstString, $replaceString, $convertCase ) = @_;
local( $dstString );
$tstString=cutWhitespace($tstString);
$replaceString=cutWhitespace($replaceString);
if($tstString eq "")
{
$dstString = $replaceString;
} else
{
$dstString = $tstString;
}
# Convert to Lower Case?
#
if($convertCase == 1)
{
$dstString =~ lc($dstString);
}
# Convert to Upper Case?
#
elsif($convertCase == 2)
{
$dstString =~ uc($dstString);
}
return($dstString);
}
# Sub-routine to test if a numeric is empty, and if so, set to a
# given value.
#
sub trNumeric
{
local( $tstNumber, $replaceNumber ) = @_;
local( $dstNumber );
if(!defined($tstNumber) || $tstNumber eq "" || cutWhitespace($tstNumber) eq "")
{
$dstNumber = $replaceNumber;
} else
{
$dstNumber = $tstNumber;
}
return($dstNumber);
}
# Function to look at a string and decide wether its contents
# indicate Yes or No. If the subroutine cannot determine a Yes,
# then it defaults to No.
#
sub yesNo
{
local( $srcString ) = @_;
local( $dstString, $yesNo );
$yesNo = "N";
$dstString=lc(cutWhiteSpace($srcString));
if($dstString eq "y" || $dstString eq "yes" || $dstString eq "ye")
{
$yesNo = "Y";
}
return( $yesNo );
}
# Sub-routine to encrypt an input string, typically a password,
# using the Collateral Management Encrypt utility.
#
sub encrypt
{
local( $srcPasswd ) = @_;
local( $encPasswd );
$encPasswd="";
# Call external function to perform the encryption.
#
if($srcPasswd ne "")
{
$encPasswd=`$PROG_ENCRYPT -p $srcPasswd 2>&1`;
chomp($encPasswd);
}
return($encPasswd);
}
# Sub-routine to test if a string is empty, and if so, replace
# with an alternative string. The case of the returned string
# can be adjusted according to the $convertCase parameter.
#
sub testAndReplace
{
local( $tstString, $replaceString, $convertCase ) = @_;
local( $dstString );
#printf("Input:$tstString,$replaceString\n");
$tstString=cutWhiteSpace($tstString);
$replaceString=cutWhiteSpace($replaceString);
if($tstString eq "")
{
$dstString = $replaceString;
} else
{
$dstString = $tstString;
}
# Convert to Lower Case?
#
if($convertCase == 1)
{
$dstString =~ lc($dstString);
}
# Convert to Upper Case?
#
elsif($convertCase == 2)
{
$dstString =~ uc($dstString);
}
#printf("Output:$dstString:\n");
return($dstString);
}
# Subroutine to generate a unique name by adding 2 digits onto the end of it. A hash of existing
# names is given to compare the new value against.
#
sub getUniqueName
{
local( $cnt, $uniqueName ) = ( 0, "" );
local( $startName, $maxLen, $usedNames ) = @_;
# Go through looping, adding a unique number onto the end of the string, then looking it
# up to see if it already exists.
#
$uniqueName = substr($startName, 0, $maxLen);
while(defined($$usedNames{$uniqueName}))
{
$uniqueName = substr($uniqueName, 0, $maxLen-2) . sprintf("%02d", $cnt);
$cnt++;
if($cnt > 99)
{
logWrite("die", "Unique identifier > 99: $uniqueName");
}
}
# Return unique name.
#
return($uniqueName);
}
# Sub-routine to process command line arguments. New style POSIX argument format used.
#
sub argOptions
{
local ( $writeUsage, $msg, $exitCode ) = @_;
if( $writeUsage == 1 )
{
print STDOUT "Usage: $PROGNAME <commands> [<options>] \n";
print STDOUT " commands= --help |\n";
print STDOUT " --verbose |\n";
print STDOUT " --command=<IDENT|ADDHEADER|DELHEADER> |\n";
print STDOUT " --mzffile=<file> {IDENT|ADDHEADER|DELHEADER} |\n";
print STDOUT " --srcfile=<file> {ADDHEADER} |\n";
print STDOUT " --dstfile=<file> {DELHEADER} |\n";
print STDOUT " --filename=<name of tape file> (ADDHEADER} |\n";
print STDOUT " --loadaddr=<addr tape should load @> (ADDHEADER} |\n";
print STDOUT " --execaddr=<auto exec addr> (ADDHEADER} |\n";
print STDOUT " --tapetype=<1 byte type value> (ADDHEADER} |\n";
print STDOUT " --comment=<comment string> (ADDHEADER} |\n";
print STDOUT " options = --debug=<1=ON, 0=OFF>\n";
print STDOUT "\n";
}
if($msg ne "")
{
print STDOUT "Error: $msg\n";
}
exit( $exitCode );
}
##################################################################################
# END OF GENERIC SUB-ROUTINES
##################################################################################
##################################################################################
#
# MAIN PROGRAM
#
##################################################################################
# Locals.
#
local( $time, $date, $mzfExists, $a_mromExists, $b_mromExists, $k_mromExists, $m7_mromExists, $m8_mromExists, $m12_mromExists, $m20_mromExists,
$a_80c_mromExists, $b_80c_mromExists, $k_80c_mromExists, $m7_80c_mromExists, $m8_80c_mromExists, $m12_80c_mromExists, $m20_80c_mromExists,
$mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment);
# Get current time and date.
#
$time = `date +'%H:%M:%S'`;
$date = `date +'%d.%m.%Y'`;
chomp($time);
chomp($date);
# Sign-on.
#
print STDOUT "$TITLE (v$VERSION) \@ ${VERSIONDATE}\n\n";
# Parse arguments and put into required variables.
#
$verbose = 0;
$fileName = "";
$s_loadAddr = "";
$s_execAddr = "";
$s_tapeType = "";
$comment = "";
GetOptions( "debug=n" => \$debugMode, # Debug Mode?
"verbose" => \$verbose, # Show details?
"mzffile=s" => \$mzfFile, # MZF file.
"dstfile=s" => \$dstFile, # Destination file (for header removal).
"srcfile=s" => \$srcFile, # Source file (for header adding).
"filename=s" => \$fileName, # Filename to insert into header.
"loadaddr=s" => \$s_loadAddr, # Tape load address.
"execaddr=s" => \$s_execAddr, # Tape execution address.
"tapetype=s" => \$s_tapeType, # Tape type (ie. 01 = Machine Code).
"comment=s" => \$comment, # Tape comment string.
"command=s" => \$command, # Command to execute.
"help" => \$help, # Help required on commands/options?
);
# Help required?
#
if(defined($help))
{
argOptions(1, "");
}
# Convert number arguments from string to decimal.
#
if($s_loadAddr ne "")
{
$loadAddr = oct($s_loadAddr);
}
if($s_execAddr ne "")
{
$execAddr = oct($s_execAddr);
}
if($s_tapeType ne "")
{
$tapeType = oct($s_tapeType);
}
# Verify command.
#
if($command eq "IDENT" || $command eq "ADDHEADER" || $command eq "DELHEADER")
{
1;
}
else
{
argOptions(1, "Illegal command given on command line:$command.\n",$ERR_BADARGUMENTS);
}
# Check that the additional parameters have been provided for the ADDHEADER command.
if($command eq "ADDHEADER" && ($fileName eq "" || !defined($loadAddr) || !defined($execAddr) || !defined($tapeType)) )
{
argOptions(3, "ADDHEADER command requires the following parameters to be provided: --filename, --loadaddr, --execaddr, --tapetype\n",$ERR_BADARGUMENTS);
}
# For ident or delete header commands, we need to open and read the mzf file.
#
if(($command eq "IDENT" || $command eq "DELHEADER") && defined($mzfFile) && $mzfFile ne "")
{
# If defined, can we open it?
#
if( ! open(MZFFILE, "<".$mzfFile) )
{
argOptions(1, "Cannot open MZF file: $mzfFile.\n",$ERR_BADFILENAME);
}
@MZF = ();
binmode(MZFFILE);
local $/ = \1;
$cnt = 0;
$skip = 0;
while ( my $byte = <MZFFILE> )
{
$MZF[$cnt] = $byte;
$cnt++;
}
$MZF_SIZE = $cnt;
# Once the MZF is in memory, analyse the details and output.
#
$mzf_header = pack('a'x128, @MZF);
($mzf_type, $mzf_filename, $mzf_size, $mzf_loadaddr, $mzf_execaddr, $mzf_comment) = unpack 'c1 a17 v4 v4 v4 a104', $mzf_header;
$mzf_filename =~ s/\r|\n//g;
# Output detail if requested.
#
if($verbose)
{
printf STDOUT "File Name : %s\n", $mzf_filename;
printf STDOUT "File Type : %02x\n", $mzf_type;
printf STDOUT "File Size : %04x\n", $mzf_size;
printf STDOUT "File Load Address : %04x\n", $mzf_loadaddr;
printf STDOUT "File Exec Address : %04x\n", $mzf_execaddr;
printf STDOUT "Comment : %s\n", $mzf_comment;
}
# For the DELHEADER command, a destination needs to be provided and opened.
if($command eq "DELHEADER" && defined($dstFile) && $dstFile ne "")
{
if( ! open(DSTFILE, ">".$dstFile) )
{
argOptions(1, "Cannot open the destination file: $dstFile.\n",$ERR_BADFILENAME);
}
}
}
elsif($command eq "ADDHEADER" && defined($mzfFile) && $mzfFile ne "")
{
# If defined, can we create it?
#
if( ! open(MZFFILE, ">".$mzfFile) )
{
argOptions(1, "Cannot create MZF file: $mzfFile.\n",$ERR_BADFILENAME);
}
# For this command, a source file needs to exist and opened.
if(defined($srcFile) && $srcFile ne "")
{
if( ! open(SRCFILE, "<".$srcFile) )
{
argOptions(1, "Cannot open the source file: $srcFile.\n",$ERR_BADFILENAME);
}
@SRC = ();
binmode(SRCFILE);
local $/ = \1;
$cnt = 0;
$skip = 0;
while ( my $byte = <SRCFILE> )
{
$SRC[$cnt] = $byte;
$cnt++;
}
$SRC_SIZE = $cnt;
}
}
else
{
argOptions(2, "No MZF file given, use --mzffile=<file>.\n");
}
# Process command as necessary.
#
if($command eq "ADDHEADER")
{
# Build the header based on given information and size of src file.
$mzf_size = scalar @SRC;
$mzf_type = $tapeType; # For exit code.
$mzf_header = pack('c1 a17 v v v', $tapeType, $fileName, $mzf_size, $loadAddr, $execAddr);
$mzf_header .= pack('a104', $comment) ;
# Store in file.
print MZFFILE $mzf_header;
# Now add the source data.
foreach my $byte (@SRC) { print MZFFILE $byte; }
# All done.
close MZFFILE;
# Output detail if requested.
#
if($verbose)
{
printf STDOUT "File Name : %s\n", $fileName;
printf STDOUT "File Type : %02x\n", $tapeType;
printf STDOUT "File Size : %04x\n", $mzf_size;
printf STDOUT "File Load Address : %04x\n", $loadAddr;
printf STDOUT "File Exec Address : %04x\n", $execAddr;
printf STDOUT "Comment : %s\n", $comment;
}
}
# For delete, simply write out the tape contents less the header (first 128 bytes).
elsif($command eq "DELHEADER")
{
my $cnt = 0;
foreach my $byte (@MZF) { if($cnt++ >= 128) { print DSTFILE $byte; } }
close DSTFILE;
}
# Exit code is the type of MZF file.
exit $mzf_type;

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-- ZPU
--
-- Copyright 2004-2008 oharboe - <20>yvind Harboe - oyvind.harboe@zylin.com
-- Copyright 2018-2019 psmart - Philip Smart
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.zpu_pkg.all;
package zpu_soc_pkg is
-- Choose which CPU to instantiate depending on requirements. Warning, keep the below 5 lines exactly the same
-- or ensure you update the Makefile as they are set by the Makefile to generate zpu_soc_pkg.vhd
--
constant ZPU_SMALL : integer := 0; -- Use the SMALL CPU.
constant ZPU_MEDIUM : integer := 0; -- Use the MEDIUM CPU.
constant ZPU_FLEX : integer := 0; -- Use the FLEX CPU.
constant ZPU_EVO : integer := 0; -- Use the EVOLUTION CPU.
constant ZPU_EVO_MINIMAL : integer := 0; -- Use the Minimalist EVOLUTION CPU.
-- Frequencies for the various boards.
--
constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board
constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board
constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board
-- ID for the various ZPU models. The format is 2 bytes, MSB=<Model>, LSB=<Revision>
constant ZPU_ID_SMALL : integer := 16#0101#; -- ID for the ZPU Small in this package.
constant ZPU_ID_MEDIUM : integer := 16#0201#; -- ID for the ZPU Medium in this package.
constant ZPU_ID_FLEX : integer := 16#0301#; -- ID for the ZPU Flex in this package.
constant ZPU_ID_EVO : integer := 16#0401#; -- ID for the ZPU Evo in this package.
constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package.
-- EVO CPU specific configuration.
constant MAX_EVO_L1CACHE_BITS : integer := 5; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
constant MAX_EVO_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
constant MAX_EVO_MIN_L1CACHE_BITS : integer := 4; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_MIN_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
constant MAX_EVO_MIN_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
-- Settings for various IO devices.
--
constant MAX_RX_FIFO_BITS : integer := 8; -- Size of UART RX Fifo.
constant MAX_TX_FIFO_BITS : integer := 8; -- Size of UART TX Fifo.
constant MAX_UART_DIVISOR_BITS : integer := 16; -- Maximum number of bits for the UART clock rate generator divisor.
constant INTR_MAX : integer := 16; -- Maximum number of interrupt inputs.
constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden by top level.
-- constant SYSCLK_FREQUENCY : integer := 1000; -- System clock in MHz x 10
-- constant SYSCLK_HZ : integer := SYSCLK_FREQUENCY*100000; -- System clock in Hertz
-- constant UART_RESET_COUNT : integer := ((SYSCLK_FREQUENCY*100000)/300)*8; -- Count of system clock ticks for a UART break to be recognised as a system reset.
-- SoC specific options.
--
constant SOC_IMPL_WB : boolean := EVO_USE_WB_BUS; -- Implement the Wishbone bus and all enabled devices.
constant SOC_IMPL_WB_I2C : boolean := true; -- Implement I2C over wishbone interface.
constant SOC_IMPL_WB_SDRAM : boolean := true; -- Implement SDRAM over wishbone interface.
constant SOC_IMPL_TIMER1 : boolean := true; -- Implement Timer 1, an array of prescaled downcounter with enable.
constant SOC_TIMER1_COUNTERS : integer := 0; -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter.
constant SOC_IMPL_PS2 : boolean := true; -- Implement PS2 keyboard and mouse hardware.
constant SOC_IMPL_SPI : boolean := true; -- Implement Serial Peripheral Inteface(s).
constant SOC_IMPL_SD : boolean := true; -- Implement SD Card interface.
constant SOC_SD_DEVICES : integer := 1; -- Number of SD card channels implemented.
constant SOC_IMPL_INTRCTL : boolean := true; -- Implement the prioritised interrupt controller.
constant SOC_IMPL_IOCTL : boolean := false; -- Implement the IOCTL controller (specific to the MiSTer project).
constant SOC_IMPL_SOCCFG : boolean := true; -- Implement the SoC Configuration information registers.
constant SOC_IMPL_BRAM : boolean := true; -- Implement BRAM for the BIOS and initial Stack.
constant SOC_IMPL_RAM : boolean := false; -- Implement RAM using BRAM, typically for Application programs seperate to BIOS.
constant SOC_IMPL_DRAM : boolean := false; -- Implement Dynamic RAM and controller.
constant SOC_IMPL_INSN_BRAM : boolean := true; -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory.
constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM.
constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_MAX_ADDR_RAM_BIT : integer := 23; -- Max address bit of the System RAM.
constant SOC_ADDR_RAM_START : integer := 16777216; -- Start address of RAM.
constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words.
constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM.
constant SOC_ADDR_INSN_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_RESET_ADDR_CPU : integer := SOC_ADDR_BRAM_START; -- Initial address to start execution from after reset.
constant SOC_START_ADDR_MEM : integer := SOC_ADDR_BRAM_START; -- Start location of program memory (BRAM/ROM/RAM).
constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM).
constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region.
constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region.
constant SOC_WB_IO_START : integer := 32505856; -- Start address of IO range.
constant SOC_WB_IO_END : integer := 33554431; -- End address of IO range.
-- Ranges used throughout the SOC source.
subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned
subtype ADDR_BIT_BRAM_16BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1; -- Address range of the onboard B(lock)RAM - 2 bytes aligned
subtype ADDR_BIT_BRAM_32BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit; -- Address range of the onboard B(lock)RAM - 4 bytes aligned
subtype ADDR_BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
subtype ADDR_BIT_RAM_16BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
subtype ADDR_BIT_RAM_32BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
-- subtype ADDR_DECODE_BRAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT;-- Decode range for selection of the BRAM within the address space.
-- subtype ADDR_DECODE_RAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space.
subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
-- subtype WB_IO_DECODE_RANGE is natural range maxAddrBit-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
-- Start byte address of stack for non-EVO CPU. Point to top of BRAM or a dedicated blcck of RAM - 2*words. Once booted the stack frame can be shifted to any memory location.
-- constant spStart : std_logic_vector(maxAddrBit-1 downto 0) := std_logic_vector(to_unsigned((2**(SOC_MAX_ADDR_BRAM_BIT))-8, maxAddrBit));
-- Device options
type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
------------------------------------------------------------
-- constants
------------------------------------------------------------
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
------------------------------------------------------------
-- functions
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
------------------------------------------------------------
-- records
------------------------------------------------------------
------------------------------------------------------------
-- components
------------------------------------------------------------
component dualport_ram is
port (
clk : in std_logic;
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(ADDR_32BIT_RANGE);
memAWrite : in std_logic_vector(WORD_32BIT_RANGE);
memARead : out std_logic_vector(WORD_32BIT_RANGE);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(ADDR_32BIT_RANGE);
memBWrite : in std_logic_vector(WORD_32BIT_RANGE);
memBRead : out std_logic_vector(WORD_32BIT_RANGE)
);
end component;
component cacheL2 is
generic (
MAX_CACHE_BITS : integer := 12
);
port (
clk : in std_logic;
areset : in std_logic := '0';
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(MAX_CACHE_BITS-3 downto 0);
memAWrite : in std_logic_vector(55 downto 0);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(MAX_CACHE_BITS-3 downto 0);
memBWrite : in std_logic_vector(55 downto 0);
memARead : out std_logic_vector(55 downto 0);
memBRead : out std_logic_vector(55 downto 0)
);
end component;
component dpram
generic (
init_file : string;
widthad_a : natural;
width_a : natural;
widthad_b : natural;
width_b : natural;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
port (
clock_a : in std_logic := '1';
clocken_a : in std_logic := '1';
address_a : in std_logic_vector (widthad_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
wren_a : in std_logic := '0';
q_a : out std_logic_vector (width_a-1 downto 0);
clock_b : in std_logic;
clocken_b : in std_logic := '1';
address_b : in std_logic_vector (widthad_b-1 downto 0);
data_b : in std_logic_vector (width_b-1 downto 0);
wren_b : in std_logic := '0';
q_b : out std_logic_vector (width_b-1 downto 0)
);
end component;
component signed_divider is
port (
clk : in std_logic;
ena : in std_logic;
z : in unsigned(63 downto 0);
d : in unsigned(WORD_32BIT_RANGE);
q : out signed(63 downto 0);
s : out signed(63 downto 0)
);
end component;
component unsigned_divider is
port (
clk : in std_logic;
ena : in std_logic;
z : in unsigned(63 downto 0);
d : in unsigned(WORD_32BIT_RANGE);
q : out unsigned(WORD_32BIT_RANGE);
s : out unsigned(WORD_32BIT_RANGE);
div0 : out std_logic;
ovf : out std_logic
);
end component;
component qdiv is
port (
dividend : in signed(WORD_32BIT_RANGE);
divisor : in signed(WORD_32BIT_RANGE);
start : in std_logic;
clk : in std_logic;
quotient_out : out signed(WORD_32BIT_RANGE);
complete : out std_logic
);
end component;
component SDCard is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
);
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic := NO; -- active-high, synchronous reset.
rd_i : in std_logic := NO; -- active-high read block request.
wr_i : in std_logic := NO; -- active-high write block request.
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy performing some operation.
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
error_o : out std_logic_vector(15 downto 0) := (others => NO);
-- I/O signals to the external SD card.
cs_bo : out std_logic := HI; -- Active-low chip-select.
sclk_o : out std_logic := LO; -- Serial clock to SD card.
mosi_o : out std_logic := HI; -- Serial data output to SD card.
miso_i : in std_logic := ZERO -- Serial data input from SD card.
);
end component;
component sdram_v is
port (
-- interface to the MT48LC16M16 chip
sd_clk : in std_logic; -- sdram is accessed at 128MHz
sd_rst : in std_logic; -- reset the sdram controller.
sd_cke : out std_logic; -- clock enable.
sd_dq : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
sd_addr : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
sd_dqm : out std_logic_vector(1 downto 0); -- two byte masks
sd_ba : out std_logic_vector(1 downto 0); -- two banks
sd_cs_n : out std_logic; -- a single chip select
sd_we_n : out std_logic; -- write enable
sd_ras_n : out std_logic; -- row address select
sd_cas_n : out std_logic; -- columns address select
sd_ready : out std_logic; -- sd ready.
-- cpu/chipset interface
wb_clk : in std_logic; -- 32MHz chipset clock to which sdram state machine is synchonized
wb_dat_i : in std_logic_vector(31 downto 0); -- data input from chipset/cpu
wb_dat_o : out std_logic_vector(31 downto 0); -- data output to chipset/cpu
wb_ack : out std_logic;
wb_adr : in std_logic_vector(23 downto 0); -- lower 2 bits are ignored.
wb_sel : in std_logic_vector(3 downto 0);
wb_cti : in std_logic_vector(2 downto 0); -- cycle type.
wb_stb : in std_logic;
wb_cyc : in std_logic; -- cpu/chipset requests cycle
wb_we : in std_logic -- cpu/chipset requests write
);
end component;
end zpu_soc_pkg;
package body zpu_soc_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
end package body;

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---------------------------------------------------------------------------------------------------------
--
-- Name: zpu_soc_pkg.vhd
-- Created: January 2019
-- Author(s): Philip Smart
-- Description: ZPU System On a Chip Configuration
--
-- This module contains the System on a Chip configuration for the ZPU.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: January 2019 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.zpu_pkg.all;
package zpu_soc_pkg is
-- Choose which CPU to instantiate depending on requirements. Warning, keep the below 5 lines exactly the same
-- or ensure you update the Makefile as they are set by the Makefile to generate zpu_soc_pkg.vhd
--
constant ZPU_SMALL : integer := 0; -- Use the SMALL CPU.
constant ZPU_MEDIUM : integer := 0; -- Use the MEDIUM CPU.
constant ZPU_FLEX : integer := 0; -- Use the FLEX CPU.
constant ZPU_EVO : integer := 1; -- Use the EVOLUTION CPU.
constant ZPU_EVO_MINIMAL : integer := 0; -- Use the Minimalist EVOLUTION CPU.
-- Frequencies for the various boards.
--
constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board
constant SYSCLK_QMV_FREQ : integer := 100000000; -- QM CycloneV FPGA Board
constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board
constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board
-- ID for the various ZPU models. The format is 2 bytes, MSB=<Model>, LSB=<Revision>
constant ZPU_ID_SMALL : integer := 16#0101#; -- ID for the ZPU Small in this package.
constant ZPU_ID_MEDIUM : integer := 16#0201#; -- ID for the ZPU Medium in this package.
constant ZPU_ID_FLEX : integer := 16#0301#; -- ID for the ZPU Flex in this package.
constant ZPU_ID_EVO : integer := 16#0401#; -- ID for the ZPU Evo in this package.
constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package.
-- EVO CPU specific configuration.
constant MAX_EVO_L1CACHE_BITS : integer := 5; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
constant MAX_EVO_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
constant MAX_EVO_MIN_L1CACHE_BITS : integer := 4; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_MIN_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
constant MAX_EVO_MIN_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
-- Settings for various IO devices.
--
constant MAX_RX_FIFO_BITS : integer := 8; -- Size of UART RX Fifo.
constant MAX_TX_FIFO_BITS : integer := 8; -- Size of UART TX Fifo.
constant MAX_UART_DIVISOR_BITS : integer := 16; -- Maximum number of bits for the UART clock rate generator divisor.
constant INTR_MAX : integer := 16; -- Maximum number of interrupt inputs.
constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden by top level.
-- constant SYSCLK_FREQUENCY : integer := 1000; -- System clock in MHz x 10
-- constant SYSCLK_HZ : integer := SYSCLK_FREQUENCY*100000; -- System clock in Hertz
-- constant UART_RESET_COUNT : integer := ((SYSCLK_FREQUENCY*100000)/300)*8; -- Count of system clock ticks for a UART break to be recognised as a system reset.
-- SoC specific options.
--
constant SOC_IMPL_WB : boolean := EVO_USE_WB_BUS; -- Implement the Wishbone bus and all enabled devices.
constant SOC_IMPL_WB_I2C : boolean := true; -- Implement I2C over wishbone interface.
constant SOC_IMPL_WB_SDRAM : boolean := true; -- Implement SDRAM over wishbone interface.
constant SOC_IMPL_TIMER1 : boolean := true; -- Implement Timer 1, an array of prescaled downcounter with enable.
constant SOC_TIMER1_COUNTERS : integer := 0; -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter.
constant SOC_IMPL_PS2 : boolean := true; -- Implement PS2 keyboard and mouse hardware.
constant SOC_IMPL_SPI : boolean := true; -- Implement Serial Peripheral Inteface(s).
constant SOC_IMPL_SD : boolean := true; -- Implement SD Card interface.
constant SOC_SD_DEVICES : integer := 1; -- Number of SD card channels implemented.
constant SOC_IMPL_INTRCTL : boolean := true; -- Implement the prioritised interrupt controller.
constant SOC_IMPL_IOCTL : boolean := false; -- Implement the IOCTL controller (specific to the MiSTer project).
constant SOC_IMPL_SOCCFG : boolean := true; -- Implement the SoC Configuration information registers.
constant SOC_IMPL_BRAM : boolean := true; -- Implement BRAM for the BIOS and initial Stack.
constant SOC_IMPL_RAM : boolean := false; -- Implement RAM using BRAM, typically for Application programs seperate to BIOS.
constant SOC_IMPL_DRAM : boolean := false; -- Implement Dynamic RAM and controller.
constant SOC_IMPL_INSN_BRAM : boolean := true; -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory.
constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM.
constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_MAX_ADDR_RAM_BIT : integer := 23; -- Max address bit of the System RAM.
constant SOC_ADDR_RAM_START : integer := 16777216; -- Start address of RAM.
constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words.
constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM.
constant SOC_ADDR_INSN_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_RESET_ADDR_CPU : integer := SOC_ADDR_BRAM_START; -- Initial address to start execution from after reset.
constant SOC_START_ADDR_MEM : integer := SOC_ADDR_BRAM_START; -- Start location of program memory (BRAM/ROM/RAM).
constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM).
constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region.
constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region.
constant SOC_WB_IO_START : integer := 32505856; -- Start address of IO range.
constant SOC_WB_IO_END : integer := 33554431; -- End address of IO range.
-- Ranges used throughout the SOC source.
subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned
subtype ADDR_BIT_BRAM_16BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1; -- Address range of the onboard B(lock)RAM - 2 bytes aligned
subtype ADDR_BIT_BRAM_32BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit; -- Address range of the onboard B(lock)RAM - 4 bytes aligned
subtype ADDR_BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
subtype ADDR_BIT_RAM_16BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
subtype ADDR_BIT_RAM_32BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
-- subtype ADDR_DECODE_BRAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT;-- Decode range for selection of the BRAM within the address space.
-- subtype ADDR_DECODE_RAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space.
subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
-- subtype WB_IO_DECODE_RANGE is natural range maxAddrBit-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
-- Device options
type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
------------------------------------------------------------
-- Constants
------------------------------------------------------------
constant YES : std_logic := '1';
constant NO : std_logic := '0';
constant HI : std_logic := '1';
constant LO : std_logic := '0';
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
------------------------------------------------------------
-- Function prototypes
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
------------------------------------------------------------
-- Records
------------------------------------------------------------
------------------------------------------------------------
-- Components
------------------------------------------------------------
component dualport_ram is
port (
clk : in std_logic;
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(ADDR_32BIT_RANGE);
memAWrite : in std_logic_vector(WORD_32BIT_RANGE);
memARead : out std_logic_vector(WORD_32BIT_RANGE);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(ADDR_32BIT_RANGE);
memBWrite : in std_logic_vector(WORD_32BIT_RANGE);
memBRead : out std_logic_vector(WORD_32BIT_RANGE)
);
end component;
component dpram
generic (
init_file : string;
widthad_a : natural;
width_a : natural;
widthad_b : natural;
width_b : natural;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
port (
clock_a : in std_logic := '1';
clocken_a : in std_logic := '1';
address_a : in std_logic_vector (widthad_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
wren_a : in std_logic := '0';
q_a : out std_logic_vector (width_a-1 downto 0);
clock_b : in std_logic;
clocken_b : in std_logic := '1';
address_b : in std_logic_vector (widthad_b-1 downto 0);
data_b : in std_logic_vector (width_b-1 downto 0);
wren_b : in std_logic := '0';
q_b : out std_logic_vector (width_b-1 downto 0)
);
end component;
component SDCard is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
);
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic := NO; -- active-high, synchronous reset.
rd_i : in std_logic := NO; -- active-high read block request.
wr_i : in std_logic := NO; -- active-high write block request.
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy performing some operation.
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
error_o : out std_logic_vector(15 downto 0) := (others => NO);
-- I/O signals to the external SD card.
cs_bo : out std_logic := HI; -- Active-low chip-select.
sclk_o : out std_logic := LO; -- Serial clock to SD card.
mosi_o : out std_logic := HI; -- Serial data output to SD card.
miso_i : in std_logic := ZERO -- Serial data input from SD card.
);
end component;
end zpu_soc_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body zpu_soc_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
end package body;