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Minor tweaks

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This commit is contained in:
Philip Smart
2021-05-15 09:37:47 +01:00
parent b398b7ada3
commit 141939edd9
5 changed files with 49 additions and 51 deletions
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6
FPGA/SW700/v1.3/build/coreMZ.qpf
View File

@@ -18,17 +18,17 @@
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 00:16:19 May 09, 2021
# Date created = 15:09:30 May 14, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.1"
DATE = "00:16:19 May 09, 2021"
DATE = "15:09:30 May 14, 2021"
# Revisions
PROJECT_REVISION = "coreMZ"
PROJECT_REVISION = "coreMZ_SoftCPU"
PROJECT_REVISION = "coreMZ"
PROJECT_REVISION = "coreMZ_emuMZ"
PROJECT_REVISION = "coreMZ_E115"
PROJECT_REVISION = "coreMZ_E115_SoftCPU"

8
FPGA/SW700/v1.3/softZPU/ZPU/zpu_pkg.vhd
View File

@@ -139,10 +139,10 @@ package zpu_pkg is
RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU.
START_ADDR_MEM : integer := 0; -- Start address of program memory.
STACK_ADDR : integer := 0; -- Initial stack address on CPU start.
-- EXT_MEM_START : integer := 16#100000#; -- Start of off chip memory needing different timing to onchip resources.
-- EXT_MEM_SIZE : integer := 16#080000#; -- Size of off chip memory.
-- EXT_IO_START : integer := 16#D00000#; -- Start of off chip I/O region needing different timing to onchip resources.
-- EXT_IO_SIZE : integer := 16#200000#; -- Size of off chip I/O region.
EXT_MEM_START : integer := 16#100000#; -- Start of off chip memory needing different timing to onchip resources.
EXT_MEM_SIZE : integer := 16#080000#; -- Size of off chip memory.
EXT_IO_START : integer := 16#D00000#; -- Start of off chip I/O region needing different timing to onchip resources.
EXT_IO_SIZE : integer := 16#200000#; -- Size of off chip I/O region.
CLK_FREQ : integer := 100000000 -- Frequency of the input clock.
);
port (

40
devices/sysbus/BRAM/TZSW_DualPortBootBRAM.vhd
View File

@@ -4378,7 +4378,7 @@ architecture arch of DualPortBootBRAM is
4307 => x"78",
4308 => x"56",
4309 => x"fb",
4310 => x"8e",
4310 => x"ee",
4311 => x"ff",
4312 => x"87",
4313 => x"73",
@@ -6477,7 +6477,7 @@ architecture arch of DualPortBootBRAM is
6406 => x"f3",
6407 => x"56",
6408 => x"15",
6409 => x"87",
6409 => x"86",
6410 => x"34",
6411 => x"9c",
6412 => x"d4",
@@ -6692,7 +6692,7 @@ architecture arch of DualPortBootBRAM is
6621 => x"f3",
6622 => x"56",
6623 => x"16",
6624 => x"87",
6624 => x"86",
6625 => x"34",
6626 => x"9c",
6627 => x"d4",
@@ -22609,7 +22609,7 @@ architecture arch of DualPortBootBRAM is
4307 => x"74",
4308 => x"29",
4309 => x"39",
4310 => x"87",
4310 => x"86",
4311 => x"53",
4312 => x"34",
4313 => x"85",
@@ -22617,7 +22617,7 @@ architecture arch of DualPortBootBRAM is
4315 => x"80",
4316 => x"f4",
4317 => x"b0",
4318 => x"8e",
4318 => x"ee",
4319 => x"80",
4320 => x"76",
4321 => x"80",
@@ -24399,7 +24399,7 @@ architecture arch of DualPortBootBRAM is
6097 => x"58",
6098 => x"83",
6099 => x"f0",
6100 => x"8e",
6100 => x"ee",
6101 => x"80",
6102 => x"98",
6103 => x"c0",
@@ -40845,13 +40845,13 @@ architecture arch of DualPortBootBRAM is
4312 => x"73",
4313 => x"34",
4314 => x"81",
4315 => x"8e",
4315 => x"ee",
4316 => x"80",
4317 => x"ff",
4318 => x"87",
4318 => x"86",
4319 => x"56",
4320 => x"80",
4321 => x"8e",
4321 => x"ee",
4322 => x"8a",
4323 => x"74",
4324 => x"75",
@@ -42630,13 +42630,13 @@ architecture arch of DualPortBootBRAM is
6097 => x"55",
6098 => x"2e",
6099 => x"81",
6100 => x"87",
6100 => x"86",
6101 => x"34",
6102 => x"c0",
6103 => x"87",
6104 => x"08",
6105 => x"2e",
6106 => x"8e",
6106 => x"ee",
6107 => x"57",
6108 => x"f8",
6109 => x"14",
@@ -43010,7 +43010,7 @@ architecture arch of DualPortBootBRAM is
6477 => x"d4",
6478 => x"fe",
6479 => x"34",
6480 => x"90",
6480 => x"f0",
6481 => x"87",
6482 => x"08",
6483 => x"08",
@@ -43100,7 +43100,7 @@ architecture arch of DualPortBootBRAM is
6567 => x"d4",
6568 => x"fe",
6569 => x"34",
6570 => x"90",
6570 => x"f0",
6571 => x"87",
6572 => x"08",
6573 => x"08",
@@ -59076,13 +59076,13 @@ architecture arch of DualPortBootBRAM is
4312 => x"8a",
4313 => x"73",
4314 => x"34",
4315 => x"87",
4315 => x"86",
4316 => x"55",
4317 => x"34",
4318 => x"34",
4319 => x"98",
4320 => x"34",
4321 => x"87",
4321 => x"86",
4322 => x"54",
4323 => x"80",
4324 => x"80",
@@ -60867,7 +60867,7 @@ architecture arch of DualPortBootBRAM is
6103 => x"0c",
6104 => x"88",
6105 => x"80",
6106 => x"87",
6106 => x"86",
6107 => x"08",
6108 => x"f4",
6109 => x"81",
@@ -61171,7 +61171,7 @@ architecture arch of DualPortBootBRAM is
6407 => x"d4",
6408 => x"fe",
6409 => x"34",
6410 => x"90",
6410 => x"f0",
6411 => x"87",
6412 => x"08",
6413 => x"08",
@@ -61241,7 +61241,7 @@ architecture arch of DualPortBootBRAM is
6477 => x"f3",
6478 => x"56",
6479 => x"15",
6480 => x"87",
6480 => x"86",
6481 => x"34",
6482 => x"9c",
6483 => x"d4",
@@ -61331,7 +61331,7 @@ architecture arch of DualPortBootBRAM is
6567 => x"f3",
6568 => x"56",
6569 => x"15",
6570 => x"87",
6570 => x"86",
6571 => x"34",
6572 => x"9c",
6573 => x"d4",
@@ -61386,7 +61386,7 @@ architecture arch of DualPortBootBRAM is
6622 => x"d4",
6623 => x"fe",
6624 => x"34",
6625 => x"90",
6625 => x"f0",
6626 => x"87",
6627 => x"08",
6628 => x"08",

40
devices/sysbus/BRAM/TZSW_SinglePortBootBRAM.vhd
View File

@@ -4373,7 +4373,7 @@ architecture arch of SinglePortBootBRAM is
4307 => x"78",
4308 => x"56",
4309 => x"fb",
4310 => x"8e",
4310 => x"ee",
4311 => x"ff",
4312 => x"87",
4313 => x"73",
@@ -6472,7 +6472,7 @@ architecture arch of SinglePortBootBRAM is
6406 => x"f3",
6407 => x"56",
6408 => x"15",
6409 => x"87",
6409 => x"86",
6410 => x"34",
6411 => x"9c",
6412 => x"d4",
@@ -6687,7 +6687,7 @@ architecture arch of SinglePortBootBRAM is
6621 => x"f3",
6622 => x"56",
6623 => x"16",
6624 => x"87",
6624 => x"86",
6625 => x"34",
6626 => x"9c",
6627 => x"d4",
@@ -22604,7 +22604,7 @@ architecture arch of SinglePortBootBRAM is
4307 => x"74",
4308 => x"29",
4309 => x"39",
4310 => x"87",
4310 => x"86",
4311 => x"53",
4312 => x"34",
4313 => x"85",
@@ -22612,7 +22612,7 @@ architecture arch of SinglePortBootBRAM is
4315 => x"80",
4316 => x"f4",
4317 => x"b0",
4318 => x"8e",
4318 => x"ee",
4319 => x"80",
4320 => x"76",
4321 => x"80",
@@ -24394,7 +24394,7 @@ architecture arch of SinglePortBootBRAM is
6097 => x"58",
6098 => x"83",
6099 => x"f0",
6100 => x"8e",
6100 => x"ee",
6101 => x"80",
6102 => x"98",
6103 => x"c0",
@@ -40840,13 +40840,13 @@ architecture arch of SinglePortBootBRAM is
4312 => x"73",
4313 => x"34",
4314 => x"81",
4315 => x"8e",
4315 => x"ee",
4316 => x"80",
4317 => x"ff",
4318 => x"87",
4318 => x"86",
4319 => x"56",
4320 => x"80",
4321 => x"8e",
4321 => x"ee",
4322 => x"8a",
4323 => x"74",
4324 => x"75",
@@ -42625,13 +42625,13 @@ architecture arch of SinglePortBootBRAM is
6097 => x"55",
6098 => x"2e",
6099 => x"81",
6100 => x"87",
6100 => x"86",
6101 => x"34",
6102 => x"c0",
6103 => x"87",
6104 => x"08",
6105 => x"2e",
6106 => x"8e",
6106 => x"ee",
6107 => x"57",
6108 => x"f8",
6109 => x"14",
@@ -43005,7 +43005,7 @@ architecture arch of SinglePortBootBRAM is
6477 => x"d4",
6478 => x"fe",
6479 => x"34",
6480 => x"90",
6480 => x"f0",
6481 => x"87",
6482 => x"08",
6483 => x"08",
@@ -43095,7 +43095,7 @@ architecture arch of SinglePortBootBRAM is
6567 => x"d4",
6568 => x"fe",
6569 => x"34",
6570 => x"90",
6570 => x"f0",
6571 => x"87",
6572 => x"08",
6573 => x"08",
@@ -59071,13 +59071,13 @@ architecture arch of SinglePortBootBRAM is
4312 => x"8a",
4313 => x"73",
4314 => x"34",
4315 => x"87",
4315 => x"86",
4316 => x"55",
4317 => x"34",
4318 => x"34",
4319 => x"98",
4320 => x"34",
4321 => x"87",
4321 => x"86",
4322 => x"54",
4323 => x"80",
4324 => x"80",
@@ -60862,7 +60862,7 @@ architecture arch of SinglePortBootBRAM is
6103 => x"0c",
6104 => x"88",
6105 => x"80",
6106 => x"87",
6106 => x"86",
6107 => x"08",
6108 => x"f4",
6109 => x"81",
@@ -61166,7 +61166,7 @@ architecture arch of SinglePortBootBRAM is
6407 => x"d4",
6408 => x"fe",
6409 => x"34",
6410 => x"90",
6410 => x"f0",
6411 => x"87",
6412 => x"08",
6413 => x"08",
@@ -61236,7 +61236,7 @@ architecture arch of SinglePortBootBRAM is
6477 => x"f3",
6478 => x"56",
6479 => x"15",
6480 => x"87",
6480 => x"86",
6481 => x"34",
6482 => x"9c",
6483 => x"d4",
@@ -61326,7 +61326,7 @@ architecture arch of SinglePortBootBRAM is
6567 => x"f3",
6568 => x"56",
6569 => x"15",
6570 => x"87",
6570 => x"86",
6571 => x"34",
6572 => x"9c",
6573 => x"d4",
@@ -61381,7 +61381,7 @@ architecture arch of SinglePortBootBRAM is
6622 => x"d4",
6623 => x"fe",
6624 => x"34",
6625 => x"90",
6625 => x"f0",
6626 => x"87",
6627 => x"08",
6628 => x"08",

6
software/asm/tzfs_bank4.asm
View File

@@ -84,7 +84,7 @@ SETVMODE: IN A,(CPLDINFO) ; Get c
AND 0C7H ; Clear video mode setting.
OR L ; Add in new setting.
SET 2,A ; Set flag to indicate video mode override - ie, dont use base machine mode.
SET 1, A ; Ensure flag set so on restart the FPGA video mode is selected.
SETVMODECLR:SET 1, A ; Ensure flag set so on restart the FPGA video mode is selected.
LD (SCRNMODE),A
LD A, 016H ; Clear the screen so we start from a known position.
CALL PRNT
@@ -132,9 +132,7 @@ SETVGAMODE1:IN A,(CPLDCFG)
LD A,(SCRNMODE) ; Repeat for the screen mode variable, used when resetting or changing display settings.
AND 03FH ; Clear VGA setting.
OR L ; Add in new setting.
SET 1, A ; Ensure flag set so on restart the FPGA video mode is selected.
LD (SCRNMODE),A
RET
JP SETVMODECLR
; Method to set the VGA border colour on the external display.
SETVBORDER: IN A,(CPLDINFO) ; Get configuration of hardware.